CS8127YD8

CS8127 CHERRY | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 6

Technical content

Features

R Vdis Delay Comparator 1.25V Error Amp PULLUP VIN Sense RESET Over Voltage Shutdown 50mA VOUT n Externally Set Delay for Reset n 60V Peak Transient Capability n Internal Thermal Overload Protection n 3% Output Accuracy n Active RESET n Noise Immunity n On Chip EMC Hardening Protection Incorporated n Externally Set Current Limit Package Options 8L SO & 8L PDIP CS8127 5V Linear Controller/Driver 1VIN Sense Delay VOUT Pwr Gnd Pullup Ref Gnd RESET CS8127

Description

A Company ¨ Rev. 2/12/99 Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com

Note 1: Dependent on characteristics of external transistor. Electrical Characteristics: TA=-40ûC to +125ûC, TJ=-40ûC to +150ûC, VIN=6 to 26V, IOUT=5 to 500mA, Per Test Circuit (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Absolute Maximum Ratings Lead Temperature Soldering CS8127 CDelay x VDTC ICharge Note 2: Delay Time = = CDelay x 3.5 x 105 (Typical) n Output Stage (VOUT) Output Voltage 4.85 5.00 5.15 V Dropout Voltage I OUT = 500mA, note 1 0.1 0.6 V Supply Current IQ IOUT ² 10mA 4 8 mA IOUT ² 500mA 5 15 IOUT ² 3A, note 1 30 Line Regulation 6V ² V IN ² 26V, IOUT = 5mA 12 50 mV Load Regulation 5V ² I OUT ² 500mA, VIN = 14V 2 50 mV Ripple Rejection f = 120Hz, 7V ² V IN ² 17V, 60 70 dB IOUT = 350mA VIN Overvoltage Shutdown 32 40 V Drive Current V SENSE = 6V 50 µA VSENSE = 0V 25 250 mA n and Delay Functions Delay Charge Current, ICharge VDelay = 2V 5 10 15 µA Threshold VRTH VOUT Increasing 4.65 4.90 V OUT-0.10 V VRTL VOUT Decreasing 4.50 4.70 V OUT-0.15 V Hysteresis VRH 150 200 250 mV Delay Threshold VDTC Charge 3.25 3.50 3.75 V VDTD Discharge 2.80 3.00 3.40 V Delay Hysteresis, VDH VDTC - VDTD 200 400 800 mV Output Voltage Low 1V < V OUT < VRTL, 3k½ to VOUT 0.4 V Output V D > VDTC , VOUT >V RTH 10 µA Leakage Current Delay Capacitor (Vdis) Discharge Latched "ON", 0.2 0.5 V Discharge Voltage V OUT > VRTH Delay Time C Delay = 0.1µF, note 2 16 32 48 ms RESET RESET RESET RESET RESET

Typical Performance Characteristics (per Test Circuit) 5.02 5.01 4.99 4.98 4.97 4.96 4.95 -40 -20 0 20 40 60 80 100120 140150 JUNCTION TEMPERATURE (°C) VOUT (V) 5.00V @ 25°C IOUT=500mA 200 400 600 800 1000 1200 1400 1600 1800 2000 RESET OUTPUT CURRENT (mA) RESET OUTPUT VOLTAGE (mV) Vin = 5V 0 5 10 15 20 25 30 35 40 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00 0 123456789 1 0 VIN (V) IQ (mA) IOUT = 3A ROUT = 47W IOUT = 0.5A ROUT = 330W IQ vs. VIN RESET Voltage vs. Output CurrentTemperature Performance of VOUT 0123456789 1 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 V IN (V) VOUT (V) IOUT=0.5A IOUT= 3A 100 150 200 250 300 350 400 IOUT (Amps) DROPOUT VOLTAGE (mV) ROUT = 47W 25°C IOUT(Amps) LOAD REGULATION (mV) VIN=14V 25°C Load Regulation vs. IOUT Dropout Voltage vs. IOUT VOUT vs. VIN 6V£VIN £- 26V IOUT(Amps) LINE REGULATION (mV) 25°C VIN=14V IOUT (Amps) IQ (mA) 25°C 10 100 1K 10K 100K FREQUENCY (Hz) 1M 10M 100M 80VIN / VOUT(dB) IOUT=250mA 25°C Ripple Rejection IQ vs. IOUT Line Regulation vs. IOUT Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION CS8127 8L SO & PDIP 1V IN Unregulated supply voltage to the IC.

2 Sense Kelvin connection which allows remote sensing of output volt-

age for improved regulation.

3 Delay Timing CAP for function

4 CMOS/TTL compatible open collector output. goes low whenever VOUT drops below 6% of it's typical value.

5 Ref Gnd Ground connection

6 Pullup Internal pullup transistor for V

OUT . Also Sense pin for overvoltage shutdown.

7 Pwr Gnd Ground connection

OUT Supplies base current to PNP pass transistor or threshold volt- age to FET pass transistor. RESETRESET RESET

The CS8127 function is very precise, has hysteresis on both the and Delay comparators, a latching Delay capacitor discharge circuit, and operation down to 1V. The reset circuit output is an open collector type with ON and OFF parameters as specified. The reset output NPN transistor is controlled by the Low Voltage Inhibit and Reset Delay circuits (see Block Diagram). This circuit monitors output voltage, and when output voltage is below V RTL, causes the reset output transistor to be in the ON (saturation) state. When the output voltage is above V RTH, this circuit permits the reset output transistor to go into the OFF state if allowed by the reset Delay cir- cuit. This circuit provides a programmable (by external capaci- tor) delay on the output lead. The Delay lead pro- vides source current to the external delay capacitor only when the Low Voltage Inhibit circuit indicates that output voltage is above V RTH. Otherwise, the Delay lead sinks current to ground (used to discharge the Delay capacitor). The discharge current is latched ON when the output volt- age falls below V RTL. The Delay capacitor is fully dis- charged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a con- trolled pulse is generated following the detection of an error condition. The circuit allows the out- put transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than V DTC. RESET RESET RESET RESET Delay Circuit Low Voltage Inhibit Circuit RESET RESET CS8127 RESET VRH VOUT VRTH VRTL VRL Delay VDTC VDTD VDH TD VDIS (3) (1) (2) (2) RESET Circuit Waveform RESET Circuit Functional Description (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0V)

4.7 kW CDelay 0.022mF CO 10mF VOUT (5V) VIN RIN 220W CIN 0.022mF TIP42B ROUT 220W Gnd CS-8127 RESET RESET Test Circuit CS8127

Application Information

The CS8127 includes an over voltage shutdown circuit. Shutdown typically occurs at 36V. The CS8127 includes a thermal shutdown circuit that dis- ables the output when junction temperature exceeds approximately 180ûC. This is a self-protection feature designed to protect the CS8127. The thermal shutdown cir- cuit does not monitor the temperature of the pass transis- tor, which will probably be much hotter. To optimize ther- mal shutdown, board design should minimize the differ- ence in temperature of the CS8127 and the pass device. External Pass Device - Select a pass device that will deliv- er the desired output current, withstand the maximum expected input voltage, and dissipate the resulting power. The CS8127 is compatible with a wide variety of Bipolar and FET pass transistors. Output Capacitor - An output capacitor is required for sta- bility in most applications. Though a 10µF capacitor should be sufficient, regulator stability is dependent on the characteristics of the pass transistor. Capacitor effective series resistance (ESR) also factors in system stability. Some bench work may be required to determine the capacitor characteristics required for use in a particular application. BIAS Resistor - This resistor provides bias current for the CS8127 output stage, and prevents the pass device from ÒleakingÓ. It also speeds the turn-off of the pass device during an overvoltage transient. For proper operation over temperature, the recommended value is 560½, although it may be increased or decreased for a particular application. R OUT Resistor - This resistor controls the drive current available to the pass transistor. It also determines regula- tor start-up current and short circuit current limit. For bipolar pass transistors, it can be selected by use of the fol- lowing formulae: R OUT = x §Q1* *bQ1 = Pass transistor minimum b @ maximum output current. Typical start-up current and current limit can be calculat- ed as follows: ISTART Å + 5mA ILimit Åx § Q1 @ Current Limit For example, if the minimum input voltage is 6V, maxi- mum output current is 1Amp, and minimum transistor b @ 1Amp is 60, then R OUT can be calculated as follows: ROUT Å x 60 = 300½ IStart Å + 5mA = 18.3mA With VIN = 14V, and a pass transistor b of 40 @ current limit: ILimit Å x 40 = 1.7Amps14V Ð 1V 300½ 300½ 6V Ð 1V 1Amp VIN Ð 1V ROUT ROUT VIN(min) Ð 1V IOUT(max) External Component Selection Thermal Shutdown Overvoltage Shutdown

CS8127YD8 8 Lead SO Narrow CS8127YDR8 8 Lead SO Narrow (tape & reel)

Ordering Information

D Lead Count Metric English Max Min Max Min 8L PDIP 10.16 9.02 .400 .355 8L SO Narrow 5.00 4.80 .197 .189 Thermal Data 8 Lead 8 Lead PDIP SO Narrow RQJC typ 52 45 ûC/W RQJA typ 100 165 ûC/W Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA Rev. 2/12/99 CS8127 © 1999 Cherry Semiconductor Corporation Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Plastic DIP (N); 300 mil wide 0.39 (.015) MIN. 1.14 (.045) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. .203 (.008) .356 (.014) REF: JEDEC MS-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022) 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) D 0.25 (0.10) 0.10 (.004) 1.75 (.069) MAX 1.27 (.050) 0.40 (.016) REF: JEDEC MS-012 0.25 (.010) 0.19 (.008) Surface Mount Narrow Body (D); 150 mil wide