CS8126_09 ONSEMI | Alldatasheet
Document overview
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- PDF pages: 9
Technical content
Features
- Low Dropout V oltage (0.6 V at 0.5 A)
- 3.0% Output Accuracy
- Active RESET
- External RESET Delay for Reset
- Protection Circuitry − Reverse Battery Protection − +60 V , −50 V Peak Transient V oltage − Short Circuit Protection − Internal Thermal Overload Protection
- These are Pb−Free Devices D2PAK−7 DPS SUFFIX CASE 936AB Pin 1. V IN 2. VOUT 3. VOUT(SENSE) 4. GND 5. Delay 6. RESET 7. NC MARKING DIAGRAM *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com A = Assembly Location W = Wafer Lot Y = Year WW = Work Week G = Pb −Free Device CS 8126 AWLYWWG Device Package Shipping †
ORDERING INFORMATION
CS8126−1YDPSR7G D 2PAK−7 (Pb−Free) 750/Tape & Reel CS8126−1YDPS7G D 2PAK−7 (Pb−Free)
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Figure 1. Block Diagram
http://onsemi.com MAXIMUM RATINGS* Rating Value Unit Power Dissipation Internally Limited − Peak Transient Voltage (46 V Load Dump) −50, 60 V Output Current Internally Limited − ESD Susceptibility (Human Body Model) 4.0 kV Package Thermal Resistance: Junction−to−Case, R/C0113JC Junction−to−Ambient, R/C0113JA 2.1 10−50** °C/W °C/W Junction Temperature Range −40 to +150 °C Storage Temperature Range −55 to +150 °C Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) 260 peak 230 peak Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 10 second maximum. 2. 60 second maximum above 183 °C. *The maximum package power dissipation must be observed. **Depending on thermal properties of substrate. R /C0113JA = R/C0113JC + R/C0113CA. ELECTRICAL CHARACTERISTICS (TA = −40°C to +125°C, TJ = −40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 k/C0087 to VCC, unless otherwise noted.) Characteristic Test Conditions Min Typ Max Unit Output Stage (VOUT) Output Voltage − 4.85 5.00 5.15 V Dropout Voltage IOUT1 = 500 mA − 0.35 0.60 V Supply Current IOUT ≤ 10 mA IOUT ≤ 100 mA IOUT ≤ 500 mA 2.0 6.0 7.0 100 mA mA mA Line Regulation VIN = 6.0 to 26 V, IOUT = 50 mA − 5.0 50 mV Load Regulation IOUT = 50 to 500 mA, VIN = 14 V − 10 50 mV Ripple Rejection f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA 54 75 − dB Current Limit − 0.75 1.20 − A Overvoltage Shutdown − 32 − 40 V Maximum Line Transient VOUT ≤ 5.5 V − 95 − V Reverse Polarity Input Voltage DC VOUT ≥ −0.6 V, 10 /C0087 Load −15 −30 − V Reverse Polarity Input Voltage Transient 1.0% Duty Cycle, T < 100 ms, 10 /C0087 Load − −80 − V Thermal Shutdown Note 3 150 180 210 °C 3. Guaranteed By Design
http://onsemi.com ELECTRICAL CHARACTERISTICS (continued) (TA = −40°C to +125°C, TJ = −40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 k/C0087 to VCC, unless otherwise noted.) Characteristic UnitMaxTypMinTest Conditions RESET and Delay Functions Delay Charge Current VDelay = 2.0 V 5.0 10 15 /C0109A RESET Threshold VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) 4.65 4.50 4.90 4.70 VOUT − 0.01 VOUT − 0.15 V V RESET Hysteresis VRH = VRT(ON) − VRT(OFF) 150 200 250 mV Delay Threshold Charge, VDC(HI) Discharge, VDC(LO) 3.25 2.85 3.50 3.10 3.75 3.35 V V Delay Hysteresis − 200 400 800 mV RESET Output Voltage Low 1.0 V < VOUT < VRTL, 3.0 k/C0087 to VOUT − 0.1 0.4 V RESET Output Leakage Current VOUT > VRT(ON) − 0 10 /C0109A Delay Capacitor Discharge Voltage Discharge Latched “ON”, VOUT > VRT − 0.2 0.5 V Delay Time CDelay = 0.1 /C0109F*. Note 4 16 32 48 ms * Delay Time /C0043 CDelay /C0032VDelayThreshold Charge ICharge /C0043CDelay /C00323.2 4. Assumes Ideal Capacitor PACKAGE LEAD DESCRIPTION PACKAGE LEAD # LEAD SYMBOL FUNCTION 1 VIN Unregulated supply voltage to IC. 2 VOUT Regulated 5.0 V output. 4 GND Ground connection. 5 Delay Timing capacitor for RESET function. 6 RESET CMOS/TTL compatible output lead. RESET goes low after detection of any error in the regulated output or during power up. 3 VOUT(SENSE) Remote sensing of output voltage. 7 NC No Connection.
discharge circuit, and operates down to 1.0 V . current to ground (used to discharge the delay capacitor). when the voltage on the Delay lead is higher than VDC(H1). into account to calculate the total variation in the delay time. Figure 13. Application Diagram
- C1 is required if the regulator is far from the power source filter.
** C2 is required for stability. delay, load transient response and loop stability. manufacturers data sheet usually provides this information. however it is not necessarily the optimized solution.
http://onsemi.com Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 14) is: PD(max) /C0043/C0458VIN(max) /C0042VOUT(min)/C0459IOUT(max) /C0041VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application, and I Q is the quiescent current the regulator consumes at IOUT(max). Once the value of P D(max) is known, the maximum permissible value of R/C0113JA can be calculated: R/C0081JA /C0043150° C /C0042TA PD (2) The value of R/C0113JA can then be compared with those in the package section of the data sheet. Those packages with R/C0113JA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. Figure 14. Single Output Regulator With Key A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R /C0113JA. R/C0081JA /C0043R/C0081JC /C0041R/C0081CS /C0041R/C0081SA (3) where: R/C0113JC = the junction−to−case thermal resistance, R/C0113CS = the case−to−heatsink thermal resistance, and R/C0113SA = the heatsink−to−ambient thermal resistance. R/C0113JC appears in the package section of the data sheet. Like R/C0113JA, it is a function of package type. R /C0113CS and R/C0113SA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
http://onsemi.com PACKAGE DIMENSIONS D2PAK−7 (SHORT LEAD) DPS SUFFIX CASE 936AB−01 ISSUE B 0.539 DIM MIN MAX MIN MAX MILLIMETERSINCHES E 0.380 0.420 9.65 10.67 D 0.325 0.368 8.25 9.53 A 0.170 0.180 4.32 4.57 b 0.026 0.036 0.66 0.91 c2 0.045 0.055 1.14 1.40 e 0.050 BSC 1.27 BSC H 0.579 13.69 14.71 A1 0.000 0.010 0.00 0.25 c 0.017 0.026 0.43 0.66 E D cb e H L 0.058 0.078 1.47 1.98 M L3 0.010 BSC 0.25 BSC 0 8 °° 0 8 °° *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. RECOMMENDED NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.005 MAXIMUM PER SIDE. THESE DIMENSIONS TO BE MEASURED AT DATUM H. 4. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS E, L1, D1, AND E1. DIMENSIONS D1 AND E1 ESTABLISH A MINIMUM MOUNTING SURFACE FOR THE THERMAL PAD. A DIMENSIONS: MILLIMETERS 0.424 0.584 0.310 0.136 0.040 0.050 PITCH SOLDERING FOOTPRINT* B H L M DETAIL C SEATING PLANE GAUGE PLANE A MAM0.13 B E/2 B SEATING PLANE A A DETAIL C VIEW A−A MAM0.10 B ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. CS8126/D SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative