CS8126

CS8126 CHERRY | Alldatasheet

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5 L TO-220 7 L D2PAK

Tab (Gnd)Tab (Gnd) CS8126, -1, -2 5V , 750mA Low Dropout Linear Regulator with Delayed RESET CS8126,-1,-2

Description

The CS8126 is a low dropout, high cur- rent 5V linear regulator. It is an improved replacement for the CS8156. Improvements include higher accuracy, tighter saturation control, better supply rejection, and enhanced circuit- ry. Familiar PNP regulator features such as reverse battery protection, over- voltage shutdown, thermal shutdown, and current limit make the CS8126 suit- able for use in automotive and battery operated equipment. Additional on- chip filtering has been included to enhance rejection of high frequency transients on all external leads. An active microprocessor func- tion is included on-chip with externally programmable delay time. During power-up, or after detection of any error in the regulated output, the lead will remain in the low state for the duration of the delay. Types of errors include short circuit, low input voltage, overvoltage shut- down, thermal shutdown, or others that cause the output to become unregulat- ed. This function is independent of the input voltage and will function correct- ly with an output voltage as low as 1V. Hysteresis is included in both the reset and Delay comparators for enhanced noise immunity. A latching discharge circuit is used to discharge the Delay capacitor, even when triggered by a rel- atively short fault condition. This circuit improves upon the commonly used SCR structure by providing full capaci- tor discharge (0.2V type). Note:The CS8126 is lead compatible with the LM2925, TLE4260, L4947, LM2927, and LM2926. RESET RESET RESET Block Diagram VOUT VIN Over Voltage Shutdown Pre- Regulator Regulated Supply for Circuit Bias Bandgap Reference Thermal Shutdown Error Amp Anti-Saturation and Current Limit Charge Current Generator Latching Discharge Reset Comparator Delay Comparator Q R S VDischarge Delay Gnd RESET CS8126-1 1V IN 2V OUT

3 Gnd

4 Delay

5 RESET

2 RESET

16 Lead SOIC Wide

ÐÐÐÐÐÐRESET VOUT(SENSE) NC NC Gnd NC NC NC NC NCNC NC NC A Company ¨ Rev. 5/4/99 1V IN 2V OUT 3V OUT(SENSE)

4 Gnd

5 Delay

6 RESET

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: TA = -40ûC to +125ûC, TJ = -40ûC to +150ûC, VIN = 6 to 26V, IO=5 to 500mA, RRESET = 4.7k½ to VCC, unless otherwise noted. Absolute Maximum Ratings n Output Stage (VOUT) Output Voltage 4.85 5.00 5.15 V Dropout Voltage I OUT = 500mA 0.35 0.60 V Supply Current I OUT ² 10mA 2 7 mA IOUT ² 100mA 6 12 IOUT ² 500mA 55 100 Line Regulation V IN = 6 to 26V, IOUT = 50mA 5 50 mV Load Regulation I OUT = 50 to 500mA, VIN = 14V 10 50 mV Ripple Rejection f = 120Hz, V IN = 7 to 17V, 54 75 dB IOUT = 250mA Current Limit 0.75 1.20 A Overvoltage Shutdown 32 40 V Maximum Line Transient V OUT ² 5.5V 95 V Reverse Polarity Input V OUT ³ -0.6V, 10½ Load -15 -30 V Voltage DC Reverse Polarity Input 1% Duty Cycle, T < 100ms, -80 V Voltage Transient 10½ Load Thermal Shutdown Guaranteed by Design 150 180 210 ¡C n and Delay Functions Delay Charge Current V Delay = 2V 5 10 15 µA Threshold V OUT Increasing, VRT(ON) 4.65 4.90 V OUT - 0.01 V VOUT Decreasing, VRT(OFF) 4.50 4.70 V OUT - 0.15 V Hysteresis V RH = VRT(ON) - VRT(OFF) 150 200 250 mV Delay Threshold Charge, V DC(HI) 3.25 3.50 3.75 V Discharge, VDC(LO) 2.85 3.10 3.35 V Delay Hysteresis 200 400 800 mV Output Voltage Low 1V < V OUT < VRTL , 3k½ to VOUT 0.1 0.4 V Output Leakage V OUT > VRT(ON) 01 0 µ A Current Delay Capacitor Discharge Latched ÒONÓ, 0.2 0.5 V Discharge Voltage V OUT > VRT Delay Time C Delay = 0.1µF* (Note 1) 16 32 48 ms Delay Time = = C Delay x 3.2 x 105 (typ) Note 1: assumes ideal capacitor CDelay ´ VDelay Threshold Charge ICharge RESET RESET RESET RESET RESET CS8126, -1, -2

Typical Performance Characteristics 0.0 0.0 ICQ (mA) VIN (V) 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 RLOAD= 25W 125ûC 25ûC -40ûC 0.0 0.0 ICQ (mA) VIN (V) Room Temp. 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0 110.0 120.0 Rload = 6.67 Rload = 10 Rload = 25 Rload = NO LOAD 0.0 0.0 VOUT (V) VIN (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 RLOAD = 25W 125ûC 25ûC -40ûC VOUT vs VIN over Temperature ICQ vs. VIN over RLOADICQ vs. VIN over Temperature 0.0 0.0 VOUT (V) VIN (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Room Temp. Rload = NO LOAD Rload = 6.67 Rload = 10 VOUT vs. VIN over RLOAD Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION CS8126, -1, -2

5 Lead TO-220 7Lead 16 Lead

8126-1 8126-2 D 2PAK SOIC Wide 11 1 1 V IN Unregulated supply voltage to IC. 25 2 1 6 V OUT Regulated 5V output. 3 3 4 11 Gnd Ground connection. 4 4 5 8 Delay Timing capacitor for function. 5 2 6 6 CMOS/TTL compatible output lead. goes low after detection of any error in the regulated output or during power up. 31 4 V OUT(SENSE) Remote sensing of output voltage. 7 2, 3, 4, 5, 7, 9, NC No Connection. 10, 12, 13, 15 RESETRESET RESET

Dropout Voltage (mV) Output Current (mA) 100 200 300 400 500 600 700 800 100 200 300 400 500 600 700 800 900 25ûC -40ûC 125ûC Quiescent Current (mA) Output Current (mA) 100 100 200 300 400 500 600 700 800 VIN = 14V 125ûC 25ûC -40ûC 100 Rejection (dB) Freq. (Hz) 101 102 103 104 105 106 107 108 IOUT= 250mA COUT= 10mF, ESR = 10W COUT= 10mF, ESR = 1W COUT= 10mF, ESR = 1 & 0.1mF, ESR = 0 Ripple Rejection Quiescent Current vs. Output Current over TemperatureDropout Voltage vs. Output Current over Temperature Typical Performance Characteristics: continued -100 Line Regulation (mV) Output Current (mA) -80 -60 -40 -20 100 100 200 300 400 500 600 700 800 VIN 6-26V TEMP = 25ûC TEMP = 40ûC TEMP = 125ûC -14 Load Regulation (mV) Output Current (mA) -12 -10 100 200 300 400 500 600 700 800 TEMP = 25ûC TEMP = 125ûC VIN = 14V TEMP = -40ûC Load Regulation vs. Output Current over TemperatureLine Regulation vs. Output Current over Temperature 100 ESR (ohms) Output Current (mA) 101 102 103 101 102 103 10-4 100 10-1 10-2 10-3 COUT= 68mF COUT= 47mF COUT= 47/68mF Stable Region Output Capacitor ESR CS8126, -1, -2

The CS8126 function, has hysteresis on both the Reset and Delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1V. The circuit output is an open collector type with ON and OFF parameters as specified. The output NPN transistor is controlled by the two circuits described (see Block Diagram). Low Voltage Inhibit Circuit This circuit monitors output voltage, and when the output voltage falls below V RT(OFF), causes the output tran- sistor to be in the ON (saturation) state. When the output voltage rises above V RT(ON), this circuit permits the output transistor to go into the OFF state if allowed by the Delay circuit. RESET Delay Circuit This circuit provides a programmable (by external capaci- tor) delay on the output lead. The Delay lead pro- vides source current to the external delay capacitor only when the "Low Voltage Inhibit" circuit indicates that out- put voltage is above V RT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage falls below V RT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a controlled pulse is generated following detection of an error condition. The circuit allows the output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than V DC(H1). The Delay time for the function is calculated from the formula: Delay time = Delay time = CDelay ´ 3.2 ´ 105 If CDelay = 0.1µF, Delay time (ms) = 32ms ± 50%: i.e. 16ms to 48ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. C Delay ´ VDelay Threshold ICharge RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET Circuit Waveform VRH VOUT VRT(ON) VRT(OFF) VRL Delay VDC(HI) VDC(LO) VDH tDelay VDIS (3) (1) (2) (2) RESET (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0V) Circuit Description CS8126, -1, -2

C1* 100nF VIN Delay Gnd RESET VOUT CS8126 C2** 10mF to 100mF RRST 4.7kW Delay 0.1mF The output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause insta- bility. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low tem- peratures (-25¡C to -40¡C), both the value and ESR of the capacitor will vary considerably. The capacitor manufac- turers data sheet usually provides this information. The value for the output capacitor C 2 shown in the test and applications circuit should work for most applica- tions, however it is not necessarily the optimized solution. To determine an acceptable value for C 2 for a particular application, start with a tantalum capacitor of the recom- mended value and work towards a less expensive alterna- tive part. Step 1: Place the completed circuit with a tantalum capac- itor of the recommended value in an environmental cham- ber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscil- lations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage condi- tions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capaci- tor will usually cost less and occupy less board space. If the output oscillates within the range of expected operat- ing conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Remove the unit from the environmental chamber and heat the IC with a heat gun. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regula- tor performance. Most good quality aluminum electrolytic capacitors have a tolerance of +/- 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. The maximum power dissipation for a single output regu- lator (Figure 1) is: P D(max) = {VIN(max) - VOUT(min)}IOUT(max) + VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the applica- tion, and IQ is the quiescent current the regulator consumes at IOUT(max). Stability Considerations Calculating Power Dissipation in a Single Output Linear Regulator C1* is required if the regulator is far from the power source filter. C2** is required for stability CS8126, -1, -2

Application Notes: continued Once the value of PD(max) is known, the maximum permis- sible value of RQJA can be calculated: RQJA = (2) The value of RQJA can then be compared with those in the package section of the data sheet. Those packages with R QJA's less than the calculated value in equation 2 will keep the die temperature below 150¡C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R QJA. RQJA = RQJC + RQCS + RQSA (3) where: RQJC = the junctionÐtoÐcase thermal resistance, RQCS = the caseÐtoÐheatsink thermal resistance, and RQSA = the heatsinkÐtoÐambient thermal resistance. RQJC appears in the package section of the data sheet. Like RQJA, it is a function of package type. RQCS and RQSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. 150¡C - T A PD Heat Sinks VIN Smart Regulator VOUT IOUT IIN IQ Control Figure 1. Single output regulator with key performance parameters

5 Lead 7 Lead 16 Lead

Thermal Data TO-220 D 2PAK SOIC Wide RQJC typ 2.1 2.1 23 ûC/W RQJA typ 50 10-50* 105 ûC/W *Depending on thermal properties of substrate. RQJA = RQJC + RQCA. D Lead Count Metric English Max Min Max Min 16 Lead SO Wide 10.50 10.10 .413 .398 CS8126 Package Specification PACKAGE THERMAL DATAPACKAGE DIMENSIONS IN mm (INCHES) Surface Mount Wide Body (DW); 300 mil wide 1.27 (.050) BSC 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) D 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) REF: JEDEC MS-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 0.10 (.004)

5 Lead TO-220 (T) Straight

2.87 (.113) 2.62 (.103) 6.93(.273) 6.68(.263) 9.78 (.385) 10.54 (.415) 1.02(.040) 0.63(.025) 1.83(.072) 1.57(.062) 0.56 (.022) 0.36 (.014) 2.92 (.115) 2.29 (.090) 1.40 (.055) 4.06 (.160) 6.55 (.258) 5.94 (.234) 14.22 (.560) 0.76 (.030) 3.71 (.146) 3.96 (.156) 14.99 (.590) 14.22 (.560)

5 Lead TO-220 (THA) Horizontal

0.81(.032) 1.70 (.067) 6.81(.268) 1.40 (.055) 1.14 (.045) 5.84 (.230) 6.60 (.260) 6.83 (.269) 0.56 (.022) 0.36 (.014) 10.54 (.415) 9.78 (.385) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146) 1.68 (.066) TYP 14.99 (.590) 14.22 (.560) 2.77 (.109) 2.29 (.090) 2.92 (.115) 4.83 (.190) 4.06 (.160) 2.87 (.113) 2.62 (.103)

5 Lead TO-220 (TVA) Vertical

1.68 7.51 (.296) 1.78 (.070) 4.34 (.171) 0.56 (.022) 0.36 (.014) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 14.99 (.590) 14.22 (.560) 2.92 (.115) 2.29 (.090) .94 (.037) .69 (.027) 8.64 (.340) 7.87 (.310) 6.80 (.268) 10.54 (.415) 9.78 (.385) 2.87 (.113) 2.62 (.103) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146)

CS8126-1YT5 5 Lead TO-220 Straight CS8126-1YTVA5 5 Lead TO-220 Vertical CS8126-1YTHA5 5 Lead TO-220 Horizontal CS8126-2GT5 5 Lead TO-220 Straight CS8126-2GTVA5 5 Lead TO-220 Vertical CS8126-2GTHA5 5 Lead TO-220 Horizontal CS8126-1YTHE5 5 Lead TO-220 Surface Mount CS8126-1YTHER5 5 Lead TO-220 Surface Mount (tape & reel) CS8126YDPS7 7 Lead D 2PAK Short-Leaded CS8126YDPSR7 7 Lead D2PAK Short-Leaded (tape & reel) CS8126YDW16 16 Lead SOIC Wide CS8126YDWR16 16 Lead SOIC Wide (tape & reel) Rev. 5/4/99

Ordering Information

© 1999 Cherry Semiconductor Corporation Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Package Specification: continued CS8126 PACKAGE DIMENSIONS IN mm (INCHES)

5 Lead TO-220 (THE) SMD

10.3 (.405) 10.0 (.395) 3.96 (.156) 3.71 (.146) 2.87 (.113) 2.61 (.103) 14.6 (.575) 8.40 (.331) .914 (.036) .711 (.028) 1.70 (.067) 6.80 (.268) 4.44 (.175) .254 (.010) .000 (.000) B .102 (.004) MAX A 1.40 (.055) 1.14 (.045) 5° (5 Places) 14.0 (.550) 2.66 (.105) 2.56 (.101) 2.03 (.080) .254 (.010) REF Notes: 1. Dimensions exclusive of mold flash and metal burrs. 2. Footpad length measured from lead tip with ref. to datum . 3. Coplanarity .004² max. Reference plane standoff height .000Ð.010². B A

7 Lead D2PAK (DPS)* Short-Leaded

1.98 (.078) 1.47 (.058) 14.71 (.579) 13.69 (.539) 4.57 (.180) 4.31 (.170) 1.40 (.055) 1.14 (.045) 2.79 (.110) 2.54 (.100) TERMINAL 8 7.75 (.305) REF 6.50 (.256) REF 10.31 (.406) 10.05 (.396) 1.27 (.050) REF 1.68 (.066) 1.40 (.055) .254 (.010) REF0.91 (.036) 0.66 (.026) 8.53 (.336) 8.28 (.326) 0.10 (.004) 0.00 (.000) *CHERRY SEMICONDUCTOR SHORT-LEADED FOOTPRINT