CS8126 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Low Dropout V oltage (0.6 V at 0.5 A)
- 3.0% Output Accuracy
- Active RESET
- External RESET Delay for Reset
- Protection Circuitry − Reverse Battery Protection − +60 V , −50 V Peak Transient V oltage − Short Circuit Protection − Internal Thermal Overload Protection
- Pb−Free Packages are Available TO−220−5 T SUFFIX CASE 314D 1 5 TO−220−5 TVA SUFFIX CASE 314K TO−220−5 THA SUFFIX CASE 314A Pin 1. V IN 2. VOUT 3. GND 4. Delay 5. RESET TO−220−5 THE SUFFIX CASE 314J D2PAK−7 DPS SUFFIX CASE 936AB Pin 1. V IN 2. VOUT 3. VOUT(SENSE) 4. GND 5. Delay 6. RESET 7. NC See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking section on page 9 of this data sheet. DEVICE MARKING INFORMATION *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com
Figure 1. Block Diagram
http://onsemi.com MAXIMUM RATINGS* Rating Value Unit Power Dissipation Internally Limited − Peak Transient Voltage (46 V Load Dump) −50, 60 V Output Current Internally Limited − ESD Susceptibility (Human Body Model) 4.0 kV Package Thermal Resistance, TO−220−5: Junction−to−Case, R /C0113JC Junction−to−Ambient, R /C0113JA 2.1 °C/W °C/W Package Thermal Resistance, D2PAK−7: Junction−to−Case, R /C0113JC Junction−to−Ambient, R /C0113JA 2.1 10−50** °C/W °C/W Junction Temperature Range −40 to +150 °C Storage Temperature Range −55 to +150 °C Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) 260 peak 230 peak Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 10 second maximum. 2. 60 second maximum above 183 °C. *The maximum package power dissipation must be observed. **Depending on thermal properties of substrate. R/C0113JA = R/C0113JC + R/C0113CA. ELECTRICAL CHARACTERISTICS (TA = −40°C to +125°C, TJ = −40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 k/C0087 to VCC, unless otherwise noted.) Characteristic Test Conditions Min Typ Max Unit Output Stage (VOUT) Output Voltage − 4.85 5.00 5.15 V Dropout Voltage IOUT1 = 500 mA − 0.35 0.60 V Supply Current IOUT ≤ 10 mA IOUT ≤ 100 mA IOUT ≤ 500 mA 2.0 6.0 7.0 100 mA mA mA Line Regulation VIN = 6.0 to 26 V, IOUT = 50 mA − 5.0 50 mV Load Regulation IOUT = 50 to 500 mA, VIN = 14 V − 10 50 mV Ripple Rejection f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA 54 75 − dB Current Limit − 0.75 1.20 − A Overvoltage Shutdown − 32 − 40 V Maximum Line Transient VOUT ≤ 5.5 V − 95 − V Reverse Polarity Input Voltage DC VOUT ≥ −0.6 V, 10 /C0087 Load −15 −30 − V Reverse Polarity Input Voltage Transient 1.0% Duty Cycle, T < 100 ms, 10 /C0087 Load − −80 − V Thermal Shutdown Note 3 150 180 210 °C 3. Guaranteed By Design
http://onsemi.com ELECTRICAL CHARACTERISTICS (continued) (TA = −40°C to +125°C, TJ = −40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 k/C0087 to VCC, unless otherwise noted.) Characteristic UnitMaxTypMinTest Conditions RESET and Delay Functions Delay Charge Current VDelay = 2.0 V 5.0 10 15 /C0109A RESET Threshold VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) 4.65 4.50 4.90 4.70 VOUT − 0.01 VOUT − 0.15 V V RESET Hysteresis VRH = VRT(ON) − VRT(OFF) 150 200 250 mV Delay Threshold Charge, VDC(HI) Discharge, VDC(LO) 3.25 2.85 3.50 3.10 3.75 3.35 V V Delay Hysteresis − 200 400 800 mV RESET Output Voltage Low 1.0 V < VOUT < VRTL, 3.0 k/C0087 to VOUT − 0.1 0.4 V RESET Output Leakage Current VOUT > VRT(ON) − 0 10 /C0109A Delay Capacitor Discharge Voltage Discharge Latched “ON”, VOUT > VRT − 0.2 0.5 V Delay Time CDelay = 0.1 /C0109F*. Note 4 16 32 48 ms *D e l a yT i m e/C0043 CDelay /C0032VDelayThreshold Charge ICharge /C0043CDelay /C00323.2 4. Assumes Ideal Capacitor PACKAGE LEAD DESCRIPTION PACKAGE LEAD # LEAD SYMBOL FUNCTIONTO−220−5 D 2PAK−7 1 1 VIN Unregulated supply voltage to IC. 2 2 VOUT Regulated 5.0 V output. 3 4 GND Ground connection. 4 5 Delay Timing capacit or for RESET function. 5 6 RESET CMOS/TTL compatible output lead. RESET goes low after detection of any error in the regulated output or during power up. − 3 VOUT(SENSE) Remote sensing of output voltage. − 7 NC No Connection.
discharge circuit, and operates down to 1.0 V . current to ground (used to discharge the delay capacitor). when the voltage on the Delay lead is higher than VDC(H1). into account to calculate the total variation in the delay time. Figure 13. Application Diagram
- C1 is required if the regulator is far from the power source filter.
** C2 is required for stability. delay, load transient response and loop stability. manufacturers data sheet usually provides this information. however it is not necessarily the optimized solution.
http://onsemi.com Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 14) is: PD(max) /C0043/C0458VIN(max) /C0042VOUT(min)/C0459IOUT(max) /C0041VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of P D(max) is known, the maximum permissible value of R/C0113JA can be calculated: R/C0081JA /C0043150°C /C0042TA PD (2) The value of R/C0113JA can then be compared with those in the package section of the data sheet. Those packages with R /C0113JA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. Figure 14. Single Output Regulator With Key A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R/C0113JA. R/C0081JA /C0043R/C0081JC /C0041R/C0081CS /C0041R/C0081SA (3) where: R/C0113JC = the junction−to−case thermal resistance, R/C0113CS = the case−to−heatsink thermal resistance, and R/C0113SA = the heatsink−to−ambient thermal resistance. R/C0113JC appears in the package section of the data sheet. Like R/C0113JA, it is a function of package type. R /C0113CS and R/C0113SA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
http://onsemi.com Device Package Shipping† CS8126−1YT5 TO−220−5 STRAIGHT 50 Units/Rail CS8126−1YT5G TO−220−5 STRAIGHT (Pb−Free)
50 Units/Rail
CS8126−1YTVA5 TO−220−5 VERTICAL 50 Units/Rail CS8126−1YTVA5G TO−220−5 VERTICAL (Pb−Free) CS8126−1YTHA5 TO−220−5 HORIZONTAL 50 Units/Rail CS8126−1YTHA5G TO−220−5 HORIZONTAL (Pb−Free) CS8126−1YTHE5 TO−220−5 SURFACE MOUNT 50 Units/Rail CS8126−1YTHE5G TO−220−5 SURFACE MOUNT (Pb−Free) CS8126−1YTHER5 TO−220−5 SURFACE MOUNT 750 / Tape & Reel CS8126−1YTHER5G TO−220−5 SURFACE MOUNT (Pb−Free) 750 / Tape & Reel CS8126−1YDPS7 D2PAK−7 50 Units/Rail CS8126−1YDPS7G D2PAK−7 (Pb−Free) CS8126−1YDPSR7 D2PAK−7 750 / Tape & Reel CS8126−1YDPSR7G D2PAK−7 (Pb−Free) 750 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifi- cations Brochure, BRD8011/D. MARKING DIAGRAMS A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Device TO−220−5 T SUFFIX CASE 314D CS 8126 AWLYWWG TO−220−5 TVA SUFFIX CASE 314K CS 8126 AWLYWWG TO−220−5 THA SUFFIX CASE 314A CS 8126 AWLYWWG TO−220−5 THE SUFFIX CASE 314J CS 8126 AWLYWWG D2PAK−7 DPS SUFFIX CASE 936AB CS 8126 AWLYWWG
http://onsemi.com PACKAGE DIMENSIONS TO−220−5 T SUFFIX CASE 314D−04 ISSUE E −Q− 12345 U K D G A B 5 PL J H L E C MQM0.356 (0.014) T SEATING PLANE−T− DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.572 0.613 14.529 15.570 B 0.390 0.415 9.906 10.541 C 0.170 0.180 4.318 4.572 D 0.025 0.038 0.635 0.965 E 0.048 0.055 1.219 1.397 G 0.067 BSC 1.702 BSC H 0.087 0.112 2.210 2.845 J 0.015 0.025 0.381 0.635 K 0.990 1.045 25.146 26.543 L 0.320 0.365 8.128 9.271 Q 0.140 0.153 3.556 3.886 U 0.105 0.117 2.667 2.972 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. TO−220−5 TVA SUFFIX CASE 314K−01 ISSUE O K FU A B G M0.356 (0.014) Q MT J L E C R SEATING PLANE
5 PLD
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D, INCLUDING PROTRUSION, SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. 12345 −T− M W S DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.560 0.590 14.22 14.99 B 0.385 0.415 9.78 10.54 C 0.160 0.190 4.06 4.83 D 0.027 0.037 0.69 0.94 E 0.045 0.055 1.14 1.40 F 0.530 0.545 13.46 13.84 G 0.067 BSC 1.70 BSC J 0.014 0.022 0.36 0.56 K 0.785 0.800 19.94 20.32 L 0.321 0.337 8.15 8.56 M 0.063 0.078 1.60 1.98 Q 0.146 0.156 3.71 3.96 R 0.271 0.321 6.88 8.15 S 0.146 0.196 3.71 4.98 U 0.460 0.475 11.68 12.07 W 5 5 /C0095/C0095 −Q−
http://onsemi.com PACKAGE DIMENSIONS TO−220−5 THA SUFFIX CASE 314A−03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. DIM A MIN MAX MIN MAX MILLIMETERS 0.572 0.613 14.529 15.570 INCHES B 0.390 0.415 9.906 10.541 C 0.170 0.180 4.318 4.572 D 0.025 0.038 0.635 0.965 E 0.048 0.055 1.219 1.397 F 0.570 0.585 14.478 14.859 G 0.067 BSC 1.702 BSC J 0.015 0.025 0.381 0.635 K 0.730 0.745 18.542 18.923 L 0.320 0.365 8.128 9.271 Q 0.140 0.153 3.556 3.886 S 0.210 0.260 5.334 6.604 U 0.468 0.505 11.888 12.827 −T− SEATING PLANE L S E C F K J OPTIONAL CHAMFER D5X MPM0.014 (0.356) T G AU B Q −P− TO−220−5 THE SUFFIX CASE 314J−01 ISSUE O NOTES: /Em/figure1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. /Em/figure2. CONTROLLING DIMENSION: INCH. /Em/figure3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. /Em/figure4. DIMENSIONS EXCLUSIVE OF MOLD FLASH AND METAL BURRS. /Em/figure5. FOOTPAD LENGTH MEASURED FROM LEAD TIP WITH REFERENCE TO DATUM −M−. /Em/figure6. COPLANARITY 0.004" MAX. REFERENCE TO DATUM −N− STANDOFF HEIGHT 0.00 − 0.010". A U D G B TM0.356 (0.014) MQ 5 PL −Q− K F J C E −T− L 12345 DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.568 0.583 14.43 14.81 B 0.395 0.405 10.03 10.29 C 0.170 0.180 4.32 4.57 D 0.028 0.036 0.71 0.91 E 0.045 0.055 1.14 1.40 F 0.543 0.558 13.79 14.17 G 0.067 BSC 1.70 BSC J 0.014 0.022 0.36 0.56 K 0.073 0.088 1.85 2.24 L 0.324 0.339 8.23 8.61 Q 0.146 0.156 3.71 3.96 S 0.000 0.010 0.00 0.25 U 0.460 0.475 11.68 12.07 SEATING PLANE W −M− 0.102 (0.004) −N− S W 5 ° 5 °
http://onsemi.com PACKAGE DIMENSIONS D2PAK−7 (SHORT LEAD) DPS SUFFIX CASE 936AB−01 ISSUE A DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.396 0.406 10.05 10.31 B 0.326 0.336 8.28 8.53 C 0.170 0.180 4.31 4.57 D 0.026 0.036 0.66 0.91 E 0.045 0.055 1.14 1.40 G 0.050 REF 1.27 REF H 0.539 0.579 13.69 14.71 K L 0.000 0.010 0.00 0.25 M 0.100 0.110 2.54 2.79 N 0.017 0.023 0.43 0.58 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. A B K E P M ND G U VS H L C R 0.055 0.066 1.40 1.68 P 0.058 0.078 1.47 1.98 R S 0.095 0.105 2.41 2.67 U 0.256 REF 6.50 REF V 0.305 REF 7.75 REF 0 8 °° 0 8 °° TERMINAL 8 8.26 0.325 10.54 0.415 0.96 0.038 SCALE 3:1 /C0466mm inches/C0467 9.5 0.374 3.25 0.128 2.16 0.085 3.8 0.150 1.27 0.050CL CL *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 CS8126/D SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.