CS8101 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- 5.0 V ±2.0% Output
- Low 70 /C0109A Quiescent Current
- Active RESET
- ENABLE Input for ON/OFF and Active/Sleep Mode Control
- 100 mA Output Current Capability
- Fault Protection − +60 V Peak Transient V oltage − −15 V Reverse V oltage Short Circuit Thermal Overload
- Low Reverse Current (Output to Input)
- Internally Fused Leads Available in SO−20 WB Package
- Pb−Free Packages are Available TO−220 FIVE LEAD T SUFFIX CASE 314D 1 5 TO−220 FIVE LEAD TVA SUFFIX CASE 314K TO−220 FIVE LEAD THA SUFFIX CASE 314A1 See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking section on page 9 of this data sheet. DEVICE MARKING INFORMATION SO−20 WB DWF SUFFIX CASE 751D SOIC−8 D SUFFIX CASE 7511 http://onsemi.com
Figure 1. Block Diagram
http://onsemi.com MAXIMUM RATINGS* Rating Value Unit Power Dissipation Internally Limited − Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) −15, 60 V Operating DC Voltage 30 V ENABLE (Up to VIN with external resistor) 10 V Output Current Internally Limited − ESD Susceptibility (Human Body Model) 2.0 kV ESD Susceptibility (Machine Model) 200 V Operating Temperature −40 to +125 °C Junction Temperature Range −40 to +150 °C Storage Temperature Range −55 to +150 °C Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Notes 2 & 3) 260 peak 240 peak Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 10 second maximum. 2. 60 second maximum above 183 °C. 3. −5 °C / +0°C allowable conditions. *The maximum package power dissipation must be observed. ELECTRICAL CHARACTERISTICS (6.0 V ≤ VIN ≤ 26 V; IOUT = 1.0 mA; −40 ≤ TA ≤ 125, −40°C ≤ TJ ≤ 150°C, unless otherwise noted.) Characteristic Test Conditions Min Typ Max Unit Output Stage Output Voltage, VOUT 9.0 V < VIN < 16 V, 100 /C0109A ≤ IOUT ≤ 100 mA
6.0 V < VIN < 26 V, 100 /C0109A ≤ IOUT ≤ 100 mA
4.90 4.85 5.00 5.00 5.10 5.15 V V Dropout Voltage (VIN − VOUT) IOUT = 100 mA IOUT = 100 /C0109A 400 100 600 150 mV mV Load Regulation VIN = 14 V, 100 /C0109A ≤ IOUT ≤ 100 mA − 5.0 50 mV Line Regulation 6.0 < V < 26 V , IOUT = 1.0 mA − 5.0 50 mV Quiescent Current, (IQ) Active Mode IOUT = 100 /C0109A, VIN = 6.0 V IOUT = 50 mA IOUT = 100 mA 4.0 140 6.0 /C0109A mA mA Quiescent Current, (IQ) Sleep Mode VOUT = OFF, VIN = 6.0 V, VENABLE = 2.0 V − 20 50 /C0109A Ripple Rejection 7.0 ≤ VIN ≤ 17 V, IOUT = 100 mA, f = 120 Hz 60 75 − dB Current Limit − 105 200 − mA Short Circuit Output Current VOUT = 0 V 25 125 − mA Thermal Shutdown − 150 180 − °C Overvoltage Shutdown VOUT ≤ 1.0 V 30 34 38 V Reverse Current VOUT = 5.0 V, VIN = 0 V − 100 200 /C0109A
http://onsemi.com ELECTRICAL CHARACTERISTICS (continued) (6.0 V ≤ VIN ≤ 26 V; IOUT = 1.0 mA; −40 ≤ TA ≤ 125, −40°C ≤ TJ ≤ 150°C, unless otherwise noted.) Characteristic UnitMaxTypMinTest Conditions ENABLE Input (ENABLE) Threshold HIGH LOW (VOUT OFF) (VOUT ON) 0.6 1.4 1.4 2.0 V V Input Current VENABLE = 2.4 V − 30 100 /C0109A Reset Functions (RESET) RESET Threshold HIGH (VRH) LOW (VRL) VOUT Increasing VOUT Decreasing 4.525 4.500 4.75 4.70 VOUT − 0.05 VOUT − 0.075 V V RESET Hysteresis (HIGH − LOW) 25 50 100 mV Reset Output Leakage RESET = HIGH VOUT ≥ VRH − − 25 /C0109A Output Voltage Low (VRLO) Low (VRPEAK)
1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k
VOUT, Power up, Power down, RRESET = 10 k 0.1 0.6 0.4 1.0 V V PACKAGE LEAD DESCRIPTION PACKAGE LEAD # TO−220
5 LEAD
SO−20 WB SOIC−8 LEAD SYMBOL FUNCTION 1 20 1 VOUT 5.0 V, ±2.0%, 100 mA output. − − 2 VOUTSENSE Kelvin connection which allows remote sensing of output voltage for improved regulation. If remote sensing is not required, connect to V OUT. 2 1 3 ENABLE Logic level switches output off when toggled HIGH. 3 4, 5, 6, 7 14, 15, 16, 17 4 GND Ground. All GND leads must be connected to Ground. 4 10 5 RESET Active reset (accurate to VOUT ≥ 1.0 V) − 2, 3, 8, 9, 11, 12, 13, 18 6,7 NC No Connection. True no−connect (i.e. is floating) 5 19 8 VIN Input voltage.
Figure 2. CS8101 Dropout Voltage vs. Load Over Temperature circuit and thermal runaway conditions (Figure 3). Figure 3. Typical Circuit Waveforms for Output control functions: ENABLE and RESET (Figure 4). Figure 4. Circuit Waveform
1.4 V typ, the output pass transistor turns off, leaving a high
Figure 5. RC Network for RESET Delay
5.0 V to /C0109P
functions before power is removed. The logic options are summarized in Table 1. Table 1. Logic Control of CS8101 Output connected to the ignition switch.
http://onsemi.com To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 9) is: PD(max) /C0043/C0458VIN(max) /C0042VOUT(min)/C0459IOUT(max) /C0041VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of P D(max) is known, the maximum permissible value of R/C0113JA can be calculated: R/C0081JA /C0043150°C /C0042TA PD (2) The value of R/C0113JA can then be compared with those in the package section of the data sheet. Those packages with R /C0113JA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. Figure 9. Single Output Regulator With Key A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R/C0113JA. R/C0081JA /C0043R/C0081JC /C0041R/C0081CS /C0041R/C0081SA (3) where: R/C0113JC = the junction−to−case thermal resistance, R/C0113CS = the case−to−heatsink thermal resistance, and R/C0113SA = the heatsink−to−ambient thermal resistance. R/C0113JC appears in the package section of the data sheet. Like R/C0113JA, it is a function of package type. R /C0113CS and R/C0113SA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
http://onsemi.com DEVICE ORDERING INFORMATION* Device Package Shipping† CS8101YD8 SOIC−8 98 Units/Rail CS8101YD8G SOIC−8 (Pb−Free)
98 Units/Rail
CS8101YDR8 SOIC−8 2500/Tape & Reel CS8101YDR8G SOIC−8 (Pb−Free) 2500/Tape & Reel CS8101YDWF20 SO−20 WB 38 Units/Tube CS8101YDWF20G SO−20 WB (Pb−Free)
38 Units/Tube
CS8101YDWFR20 SO−20 WB 1000/Tape & Reel CS8101YDWFR20G SO−20 WB (Pb−Free) 1000/Tape & Reel CS8101YT5 TO−220 FIVE LEAD STRAIGHT 50 Units/Rail CS8101YT5G TO−220 FIVE LEAD STRAIGHT (Pb−Free)
50 Units/Rail
CS8101YTVA5 TO−220 FIVE LEAD VERTICAL 50 Units/Rail CS8101YTVA5G TO−220 FIVE LEAD VERTICAL (Pb−Free) CS8101YTHA5 TO−220 FIVE LEAD HORIZONTAL 50 Units/Rail CS8101YTHA5G TO−220 FIVE LEAD HORIZONTAL (Pb−Free) *Contact your local sales representative for D2PAK package option. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS TO−220 FIVE LEAD T SUFFIX CASE 314D CS 8101 AWLYWWG TO−220 FIVE LEAD TVA SUFFIX CASE 314K TO−220 FIVE LEAD THA SUFFIX CASE 314A SO−20 WB DWF SUFFIX CASE 751D SOIC−8 D SUFFIX CASE 751 CS 8101 AWLYWWG CS8101 AWLYYWWG CS8101 = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package /C0071 = Pb−Free Package CS810 ALYW1 /C0071 CS 8101 AWLYWWG
http://onsemi.com PACKAGE DIMENSIONS TO−220 FIVE LEAD T SUFFIX CASE 314D−04 ISSUE F −Q− 12345 U K D G A 5 PL J H L E C MQM0.356 (0.014) T SEATING PLANE−T− DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.572 0.613 14.529 15.570 B 0.390 0.415 9.906 10.541 C 0.170 0.180 4.318 4.572 D 0.025 0.038 0.635 0.965 E 0.048 0.055 1.219 1.397 G 0.067 BSC 1.702 BSC H 0.087 0.112 2.210 2.845 J 0.015 0.025 0.381 0.635 K 0.977 1.045 24.810 26.543 L 0.320 0.365 8.128 9.271 Q 0.140 0.153 3.556 3.886 U 0.105 0.117 2.667 2.972 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. B1 0.375 0.415 9.525 10.541 B DETAIL A−A B DETAIL A−A
http://onsemi.com TO−220 FIVE LEAD TVA SUFFIX CASE 314K−01 ISSUE O NOTES: /Em/figure1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. /Em/figure2. CONTROLLING DIMENSION: INCH. /Em/figure3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.560 0.590 14.22 14.99 B 0.385 0.415 9.78 10.54 C 0.160 0.190 4.06 4.83 D 0.027 0.037 0.69 0.94 E 0.045 0.055 1.14 1.40 F 0.530 0.545 13.46 13.84 G 0.067 BSC 1.70 BSC J 0.014 0.022 0.36 0.56 K 0.785 0.800 19.94 20.32 L 0.321 0.337 8.15 8.56 M 0.063 0.078 1.60 1.98 Q 0.146 0.156 3.71 3.96 S 0.146 0.196 3.71 4.98 U 0.460 0.475 11.68 12.07 W 55°° R 0.271 0.321 6.88 8.15 A U D G B TM0.356 (0.014) MQ 5 PL −Q− K F J C E −T− S L 12345 SEATING PLANE R M W TO−220 FIVE LEAD THA SUFFIX CASE 314A−03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. DIM A MIN MAX MIN MAX MILLIMETERS 0.572 0.613 14.529 15.570 INCHES B 0.390 0.415 9.906 10.541 C 0.170 0.180 4.318 4.572 D 0.025 0.038 0.635 0.965 E 0.048 0.055 1.219 1.397 F 0.570 0.585 14.478 14.859 G 0.067 BSC 1.702 BSC J 0.015 0.025 0.381 0.635 K 0.730 0.745 18.542 18.923 L 0.320 0.365 8.128 9.271 Q 0.140 0.153 3.556 3.886 S 0.210 0.260 5.334 6.604 U 0.468 0.505 11.888 12.827 −T− SEATING PLANE L S E C F K J OPTIONAL CHAMFER D5X MPM0.014 (0.356) T G AU B Q −P−
http://onsemi.com SO−20 WB DWF SUFFIX CASE 751D−05 ISSUE G B20X H10X C L 18X A1 A SEATING PLANE /C0113 h X 45/C0095 E D M0.25 MB M0.25 SA SBT e T B A DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 /C0113 0 7 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. /C0095/C0095 PACKAGE THERMAL DATA Parameter TO−220 FIVE LEAD SOIC−8 SO−20 WB Unit R/C0113JC Typical 3.3 45 9.0 °C/W R/C0113JA Typical 50 165 55 °C/W
http://onsemi.com SOIC−8 NB D SUFFIX CASE 751−07 ISSUE AG 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 /C0466mm inches/C0467SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* SEATING PLANE N J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A B S DH C 0.10 (0.004) DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −X− −Y− G MYM0.25 (0.010) −Z− YM0.25 (0.010) Z S X S M /C0095/C0095/C0095/C0095 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 CS8101/D SMART REGULATOR is a trademark of Semiconductor Components Industries, LLC. LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.