CS81

CS81 FUJITSU | Alldatasheet

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DS06-20206-5EFUJITSU SEMICONDUCTOR DATA SHEET Copyright©1999-2007 FUJITSU LIMITED All rights reserved Semicustom CMOS Standard cell CS81 Series ■ DESCRIPTION The CS81 series 0.18 µm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed and low power consumption. This series incorporates up to 40 million gates which have a gate delay time of 11 ps, resulting in both integration and speed about three times higher than conventional products. In addition, CS81 can operate at a power-supply voltage of down to 1.1 V, substantially reducing power consump- tion. ■ FEATURES

• Technology : 0.18 µm silicon-gate CMOS, 3- to 6-layer wiring capable of integrating a mixture of high- speed processes and cells on a single chip (under development)  Supply voltage : +1.8 V ± 0.15 V (normal) to +1.1 V ± 0.1 V  Junction temperature range : −40 to +125 °C  Gate delay time : t pd = 11 ps (1.8 V, inverter, F/O = 1)  Gate power consumption : P d = 5 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1)  Support for high speed (62.2 Mbps to 780 Mbps, 2.5 Gb ps to 3.125 Gbps) interface macros for transmission  Output buffer cells with noise reduction circuits  Inputs with on-chip input pull-up/pull-down resistors (33 k Ω typical) and bidirectional buffer cells  Buffer cells dedicated to crystal oscillators  Special interfaces (P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, and others. including those under development)  IP macros (CPU (FR, ARM7, ARM9), DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others. including those under development)  Capable of incorporating compiled cells (RAM/ROM/multiplier, and others.)  Configurable internal bus circuits  Advanced hardware/software co-design environment  Short-term development using a timing driven layout tool  Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time (Continued)

(Continued)  Hierarchical design environment for supporting large-scale circuits  Simulation (before layout) considering the input slew ra te and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture  Support for memory (RAM/ROM) SCAN  Support for memory (RAM) BIST  Support for boundary SCAN  Support for path delay test  A variety of package options (TQFP, HQ FP, EBGA, FBGA, TAB-BGA, FCBGA, LQFP) ■ MACRO LIBRARY (Including macros being prepared) 1. Logic cells (about 400 types) 2. IP macros 3. Special I/O interface macros  Adder  Decoder A N D - O R I n v e r t e r N o n - S C A N F l i p F l o p C l o c k B u f f e r I n v e r t e r L a t c h B u f f e r N A N D O R - A N D A N D O R - A N D I n v e r t e r N O R O R  SCAN Flip Flop  Selector E N O R B U S D r i v e r A N D - O R E O R O t h e r s CPU/DSP FR, SPARClite, ARM7, ARM9, Communications DSP, DSP for AV and others High speed interface macros 622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps Interface macro PCI, IEEE139 4, USB, IrDA, and others Multimedia processing macros JPEG, MPEG, and others Mixed signal macros ADC, DAC, OPAMP, and others Compiled macros RAM, ROM, multiplier, adder, multiplier-accumulator, and others PLL Analog PLL, digital PLL  T-LVTTL  SSTL  HSTL  P-CML  LVDS  PCI  AGP  USB  IEEE1394  SDRAM-I/F

■ COMPILED CELLS Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS81 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.) 1. Clock synchronous single-port RAM (1 address : 1 RW)  High density type/Partial write type  High speed type  Large scale partial write type 2. Clock synchronous dual-port RAM (2 addresses : 1 RW, 1 R)  High density type/Partial write type 3. Clock synchronous register file (3 addresses : 1 W, 2 R) 4. Clock synchronous register file (4 addresses : 2 W, 2 R) 5. Clock synchronous ROM (1 addresses, 1 R) 6. Clock synchronous delay line memory (2 addresses : 1 W, 1 R) Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit Column type Memory capacity Word range Bit range Unit 8 256 to 144 K 64 to 2 K 4 to 72 bit Column type Memory capacity Word range Bit range Unit 16 24.5 K to 1179 K 4 K to 16 K 6 to 72 bit Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 bit Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 bit Column type Memory capacity Word range Bit range Unit 16 256 to 512 K 128 to 4 K 2 to 128 bit Column type Memory capacity Word range Bit range Unit 8 256 to 32 K 32 to 1 K 8 to 32 bit 16 384 to 32 K 64 to 2 K 6 to 16 bit 32 512 to 32 K 128 to 4 K 4 to 8 bit

■ ABSOLUTE MAXIMUM RATINGS *1 : VSS = 0 V *2 : Internal gate part in case of single power supply or dual power supply *3 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply. *4 : DC current which continues more than 10 ms, or average DC current *5 : in case of I/O cell for clock input *6 : bps = bit per second *7 : Supply pin current for one V DD/GND pin WARNING: Semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Parameter Symbol Rating Unit Min Max Supply voltage*1 VDD −0.5 +2.5*2 V +4.0*3 Input voltage*1 VI −0.5 V Output voltage*1 VO −0.5 V Storage temperature Tst −55 +125 °C Junction temperature T j −40 +125 °C Output current*4 IO ⎯± 4m A Input signal transmitting rate R I ⎯ Clock input*5 : 200 Normal input : 100 Mbps*6 Output signal transmitting rate R O ⎯ 100 Mbps* 6 Output load capacitance C O ⎯ 3000/RO pF Supply pin current I D ⎯ *7 mA Frame Source type Maximum current [mA] Number of layerStandard source Additional source YS, YI VDDE, VDDI, VDD, VSS 68 68 4, 5 VDDE 39 39 VDDI, VDD, VSS 68 68 BV DDE, VDDI, VDD, VSS 43 30 ⎯

■ RECOMMENDED OPERATING CONDITIONS  Single power supply (VDD = +1.8 V ± 0.15 V)

• Dual power supply (VDDE = +3.3 V ± 0.3 V, VDDI = +1.8 V ± 0.15 V) (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage (1.8 V supply voltage) V DD 1.65 1.8 1.95 V “H” level input voltage (1.8 V CMOS) V IH VDD × 0.65 ⎯ VDD + 0.3 V “L” level input voltage (1.8 V CMOS) V IL −0.3 ⎯ VDD × 0.35 V Junction temperature T j −40 ⎯+ 125 °C (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage 1.8 V supply voltage V DDI 1.65 1.8 1.95 V 3.3 V supply voltage V DDE 3.0 3.3 3.6 “H” level input voltage

1.8 V CMOS

VDDI × 0.65 ⎯ VDDI + 0.3 V 3.3 V CMOS 2.0 ⎯ VDDE + 0.3 “L” level input voltage −0.3 ⎯ VDDI × 0.35 V Junction temperature T j −40 ⎯+ 125 °C (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage VDDE 3.0 3.3 3.6 V VDDI 1.0 1.1 1.2 V 1.4 1.5 1.6 V “H” level input voltage 3.3 V CMOS V IH 2.0 ⎯ VDDE + 0.3 V “L” level input voltage 3.3 V CMOS V IL −0.3 ⎯+ 0.8 V Junction temperature T j −40 ⎯+ 125 °C

 Dual power supply (VDDE = +2.5 V ± 0.2 V, VDDI = +1.8 V ± 0.15 V) WARNING: The recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. SS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage VDDE 2.3 2.5 2.7 V VDDI 1.65 1.8 1.95 V “H” level input voltage VDDI × 0.65 ⎯ VDDI + 0.3 V 2.5 V CMOS 1.7 ⎯ VDDE + 0.3 V “L” level input voltage −0.3 ⎯ VDDI × 0.35 V 2.5 V CMOS −0.3 ⎯+ 0.7 V Junction temperature T j −40 ⎯+ 125 °C (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage VDDE 2.3 2.5 2.7 V VDDI 1.0 1.1 1.2 V 1.4 1.5 1.6 V “H” level input voltage 2.5 V CMOS V IH 1.7 ⎯ VDDE + 0.3 V “L” level input voltage 2.5 V CMOS V IL −0.3 ⎯+ 0.7 V Junction temperature T j −40 ⎯+ 125 °C

■ ELECTRICAL CHARACTERISTICS 1. DC characteristics  Signal power supply : VDD = 1.8 V * : For details of YS, YI, B frame of CS81 series, contact Fujitsu.  Dual power supply : VDDE = 3.3 V, VDDI = 1.8 V *1 : For details of YS, YI, B frame of CS81 series, contact Fujitsu. *2 : Refer to the Fig.1 to 2. (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Conditions Value Unit Min Typ Max Supply Current I DDS ⎯⎯ ⎯ *m A “H” level output voltage V OH IOH = −100 µAV DD − 0.2 ⎯ VDD V “L” level output voltage V OL IOL = +100 µA0 ⎯ 0.2 V Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull up/Pull down resistance RP Pull up VIL = 0 Pull down VIH = VDD ⎯ 18 ⎯ kΩ Parameter Symbol Conditions Value Unit Min Typ Max Supply Current I DDS ⎯⎯ ⎯ *1 mA “H” level output voltage VOH4 3.3 V Output IOH = −100 µAV DDE − 0.2 ⎯ VDDE V VOH2 1.8 V Output IOH = −100 µAV DDI − 0.2 ⎯ VDDI V “L” level output voltage VOL4 3.3 V Output IOL = 100 µA0 ⎯ 0.2 V VOL2 1.8 V Output IOL = 100 µA0 ⎯ 0.2 V “H” level output V-I characteristics ⎯ 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯⎯ “L” level output V-I characteristics ⎯ 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯⎯ Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull up/Pull down resistance RP 1.8 V Pull up VIL=0 Pull down VIH=VDDI ⎯ 18 ⎯ kΩ 3.3 V Pull up VIL=0 Pull down VIH=VDDE 10 33 80

 Dual power supply : VDDE = 2.5 V, VDDI = 1.8 V / 1.5 V / 1.1 V * : For details of YS, YI, B frame of CS81 series, contact Fujitsu. Parameter Symbol Conditions Value Unit Min Typ Max Supply Current I DDS ⎯⎯ ⎯ *m A “H” level output voltage VOH3 2.5 V Output IOH = −100 µAV DDE − 0.2 ⎯ VDDE V VOH2 1.8 V Output IOH = −100 µAV DDI − 0.2 ⎯ VDDI V “L” level output voltage VOL3 2.5 V Output IOL = 100 µA0 ⎯ 0.2 V VOL2 1.8 V Output IOL = 100 µA0 ⎯ 0.2 V Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull up/Pull down resistance RP 2.5 V Pull up VIL=0 Pull down VIH=VDDE ⎯ 25 ⎯ kΩ 1.8 V Pull up VIL=0 Pull down VIH=VDDI ⎯ 18 ⎯

• V-I Characteristics −20 −40 −60 −80 −100 −120 IOH (mA) −4.0 Max Min Typ VOH−VDD (V) 100 IOL (mA) VOL (V) 0.0 Max Min Typ 1.0 2.0 3.0 4.0 −20 −40 −60 −80 −100 −120 −140 −160 IOH (mA) −4.0 Max Min Typ VOH−VDD (V) −3.0 −2.0 −1.0 0.0 160 140 120 100 IOL (mA) VOL (V) 0.0 Max Min Typ 1.0 2.0 3.0 4.0 Conditions (Fig 1, 2) Min : Process = Slow, Tj = +125 °C, VDD = 3.6 V Typ : Process = TYPICAL, Tj = +25 °C, VDD = 3.3 V Max : Process = FAST, Tj = −40 °C, VDD = 3.0 V Fig.1 V-I characteristics (3.3 V normal I/O L, M type) Fig.2 V-I characteristics (3.3 V normal I/O H, V type)

1. AC characteristics *1 : Delay time = propagation delay time, enable time, disable time *2 : “typ” is calculated based on the cell specifications. *3 : Measurement conditions. Note : tpd max is calculated according to the maximum junction temperature (Tj) . ■ INPUT/OUTPUT PIN CAPACITANCE Note : Capacitance varies according to the package and the location of the pin. ■ DESIGN METHOD SCCAD2 is the standard cell integrated design environm ent providing three major functions, enabling high- quality, large-scale system LSIs to be developed in a shorter period of time. They include: the timing driven layout function for automatic placement/routing based on timing constraints to prevent timing problems after layout, the function for shortening the development cycl e time by dividing a large-scale circuit and performing simultaneous logical/physical design of multiple circ uits, and the function for autom atically generating power/ signal wiring patterns while evaluating the supply voltage drop, signal noise, delay penalty, and crosstalk (Contact your nearest Fujitsu office for more information and availability). (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Rating Unit Min Typ Max* Delay time t pd*1 typ*2 × tmin*3 typ*2 × ttyp*3 typ*2 × tmax*3 ns Measurement condition tmin ttyp tmax (Tj = +25 °C, VDD = VI = 0 V, f = 1 MHz) Parameter Symbol Requirements Unit Input pin C IN Max 16 pF Output pin C OUT Max 16 pF I/O pin C I/O Max 16 pF

■ PACKAGES The table below lists the package types available. Consult Fujitsu for the combination of each package and the time of availability. Package Pin count Material TAB-BGA 304 352 480 560 660 720 Plastic Plastic Plastic Plastic Plastic Plastic EBGA 576 660 672 Plastic Plastic Plastic HQFP 208 240 256 304 Plastic Plastic Plastic Plastic TQFP 100 120 Plastic Plastic LQFP 144 176 208 Plastic Plastic Plastic FBGA 288 Plastic FCBGA 1089 1225 1369 1681 1849 2116 Plastic Plastic Plastic Plastic Plastic Plastic

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