CS7054 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- 200 mA Peak PWM Gate Drive Output
- Patented V oltage Compensation Circuit
- 100% Duty Cycle Capability
- 5.0 V , ± 3.0% Linear Regulator
- Low Current Sleep Mode
- Overvoltage Protection
- Overcurrent Protection of External MOSFET/IGBT
- Output Inhibit http://onsemi.com A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week DIP–14 N SUFFIX CASE 646 VCCOUTPUT CS7054 AWLYYWW PGNDGND INHFLT IADJC OSC ISENSE+R OSC ISENSE–CTL VREGNC PIN CONNECTIONS AND MARKING DIAGRAMS SO–16L DW SUFFIX CASE 751G CS7054 AWLYYWW VREGNC 1 16 ISENSE–NC ISENSE+CTL IADJR OSC INHC OSC PGNDFLT NCGND VCCOUTPUT Device Package Shipping
ORDERING INFORMATION
CS7054YN14 DIP–14 25 Units/Rail CS7054YDW16 SO–16L 46 Units/Rail CS7054YDWR16 SO–16L 1000 Tape & Reel SO–16L DIP–14
Figure 1. Application Diagram Lead Temperature Soldering Wave Solder (through hole styles only) Note 1. Reflow (SMD styles only) Note 2.
- 60 seconds max above 183°C
*The maximum package power dissipation must be observed.
http://onsemi.com ELECTRICAL CHARACTERISTICS (8.0 V < VCC < 16 V; –40°C < TA < 125°C; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit VCC Supply Operating Current Supply – – 5.0 10 mA Quiescent Current VCC = 12 V – 170 275 µA Overvoltage Shutdown – 18 19.5 21 V Overvoltage Hysteresis – 150 325 500 mV Control (CTL) Control Input Current CTL = 0 V to 5.0 V –2.0 0.1 2.0 µA Sleep Mode Threshold – 8.0 10 12 % V REG Sleep Mode Hysteresis – 50 100 150 mV Current Sense Differential Voltage Sense IADJ = 51.2% VREG and RCS1 = 51 Ω 60.5 – 79.5 mV IADJ Input Current IADJ = 0 V to 5.0 V –5.0 0.3 2.0 µA Linear Regulator Output Voltage VCC = 13.2 V 4.85 5.00 5.15 V Inhibit Inhibit Threshold – 40 50 60 % V REG Inhibit Hysteresis – 150 325 575 mV External Drive (OUTPUT) Output Frequency R OSC = 105 kΩ , COSC = 390 pF 17 20 23 kHz Voltage to Duty Cycle Conversion VCC = 13 V, CTL = 30% VREG VCC = 13 V, CTL = 70% VREG 26.3 69.5 38.5 81.5 Output Rise Time VCC = 13 V, RGATE = 6.0 Ω , CGATE = 5.0 nF – 0.25 1.0 µs Output Fall Time VCC = 13 V, RGATE = 6.0 Ω , CGATE = 5.0 nF – 0.3 1.0 µs Output Sink Current VCC = 13 V, RGATE = 6.0 Ω , CGATE = 5.0 nF – 400 – mA Output Source Current VCC = 13 V, RGATE = 6.0 Ω , CGATE = 5.0 nF – 400 – mA Output High Voltage IOUT = 1.0 mA VCC – 1.7 – – V Output Low Voltage IOUT = –1.0 mA – – 1.3 V
1 1 OUTPUT MOSFET Gate Drive. 3 3 FLT Fault time out capacitor. 4 4 C OSC Oscillator capacitor. 5 5 R OSC Oscillator resistor. 6 6 CTL Pulse width control input. 7 7, 8, 15 NC No connection. 8 9 VREG 5.0 V linear regulator. 9 10 ISENSE– Current sense minus. 10 11 ISENSE+ Current sense plus. 11 12 IADJ Current limit adjust. 13 14 PGND Power ground for on chip clamp. 14 16 VCC Positive power supply input.
5.0 V Regulator
Figure 2. Block Diagram
4.94 VREG
Figure 5. VREG vs. Temperature @ VCC = 16 V Figure 6. OUTPUT Saturation Voltage (Sourcing Figure 7. OUTPUT Voltage (Sinking Current) vs
should be changed to adjust the oscillator frequency.
10 V , the IC would change the duty cycle to 70% and hence
keep the average load voltage at 7.0 V . Figure 8. Voltage Compensation
5.0 V Linear Regulator
require an external capacitor for stability.
1000 R CS
terminals and the voltage at the IADJ lead.
37000 VI(ADJ)
http://onsemi.com leads are low impedance inputs thereby creating a good current sensing amplifier. Both leads source 50 µA while the chip is in run mode. RCS should be much less than 1000 Ω to minimize error in the ILIM equation. IADJ should be biased between 1.0 V and 4.0 V . When the current through the external MOSFET exceeds ILIM , an internal latch is set and the output pulls the gate of the MOSFET low for the remainder of the oscillator cycle (fault mode). At the start of the next cycle, the latch is reset and the IC reverts back to run mode until another fault occurs. If a number of faults occur in a given period of time, the IC “times out” and disables the MOSFET for a long period of time to let it cool off. This is accomplished by charging the C FLT capacitor each time an over current condition occurs. If a cycle goes by with no overcurrent fault occurring, an even smaller amount of charge will be removed from C FLT. If enough faults occur together, eventually CFLT will charge up to 2.4 V and the fault latch will be set. The fault latch will not be reset until the CFLT discharges to 0.6 V . This action will continue indefinitely if the fault persists. The off time and on time are set by the following: Off Time C FLT 2.4 V 0.6 V 4.5A On Time C FLT 2.4 V 0.6 V IAVG where: IAVG (295.5A DC) [4.5A (1 DC)] DC PWM Duty Cycle IAVG (300A DC) 4.5A Sleep State This device will enter into a low current mode (< 275 µA) when CTL lead is brought to less than 0.5 V . All functions are disabled in this mode, except for the regulator. Inhibit When the inhibit voltage is greater than 2.5 V the internal latch is set and the external MOSFET will be turned off for the remainder of the oscillator cycle. The latch is then reset at the start of the next cycle. Overvoltage Shutdown The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the internal latch and therefore is independent of the oscillator timing (i.e. asynchronous). There is no undervoltage lockout. The device will shutdown gracefully once it runs out of headroom. This happens at the point when VREG falls out of regulation. Reverse Battery The CS7054 will not survive a reverse battery condition. Therefore, a series diode is required between the battery and the VCC lead. Load Dump V CC is internally clamped to 30 V . It is recommended that a 51 Ω resistor, (RS) is placed in series with VCC to limit the current flow into the IC in the event of a 40 V peak transient condition. Using the CS7054 as a Frequency Converter Figure 9 shows the CS7054 configured for use as a frequency converter. In the setup shown, a 150 Hz square wave from a microprocessor is converted to a 10 kHz square wave. The duty cycle of each waveform is identical. The amplitude of the input waveform is 5.0 V , but does not need to be. The input amplitude requirement just needs to be high enough to switch the external bipolar transistor. The 10 kHz oscillator frequency is setup per the oscillator section of this data sheet. The external resistor divider composed of the 3.6 k and 6.2 k resistors supplies 5.0 V to the CTL pin when the input duty cycle is at 100%. This also makes the output waveform 100%. The RC filter (1.0 MΩ and 0.1 µF) sets up a pole at 1.6 Hz: f 1 2RC 1 21M (6.2 k)(3.6 k) 1.6 Hz In this case, the pole is 2 orders of magnitude below the input waveform. Care must be taken to provide the appropriate DC level on the control pin in addition to providing the required response time. *Note the current limit feature of the CS7054 has been defeated by grounding the I SENSE+ and the ISENSE– pins and connecting the IADJ lead to VREG .
Figure 9. Frequency Converter
http://onsemi.com PACKAGE DIMENSIONS DIP–14 N SUFFIX CASE 646–04 ISSUE M 14 8 B A F HG D K C L M SEATING PLANE DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.715 0.740 18.16 18.80 B 0.240 0.260 6.10 6.60 C 0.160 0.180 4.06 4.57 D 0.015 0.020 0.38 0.51 F 0.040 0.060 1.02 1.52 G 0.100 BSC 2.54 BSC H 0.052 0.072 1.32 1.83 J 0.008 0.012 0.20 0.30 K 0.115 0.135 2.92 3.43 L M --- 10 --- 10 N 0.020 0.040 0.51 1.02 N –T– 14 PL M0.13 (0.005) J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 0.290 0.310 7.37 7.87 SO–16L DW SUFFIX CASE 751G–03 ISSUE B D 14X B16X SEATING PLANE SAM0.25 B ST 16 9 h X 45 MBM0.25 H8X E B A e T A L C NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 0 7 PACKAGE THERMAL DATA Parameter DIP–14 SO–16L Unit R Θ JC Typical 48 23 °C/W R Θ JA Typical 85 105 °C/W
http://onsemi.com Notes
http://onsemi.com Notes
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