UC62LS4008 ETC1 | Alldatasheet

Document overview

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Technical content

-20/-25 „ Features:

  • Vcc operation voltage : 3.0V ~ 3.6V
  • Low power consumption : 20mA (Max.) operating current 2uA (Typ.) CMOS standby current
  • High Speed Access time : 25ns (Max.) at Vcc = 3.0V
  • Automatic power down when chip is deselected
  • Three state outputs and TTL compatible
  • Data retention supply voltage as low as 1.2V
  • Easy expansion with CE\\ and OE\\ options „ Description The UC62LV2008 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words b y 8 bits and oper ates from 3.0V to 3. 6V suppl y voltage. Advanced CMOS techn ology and circuit techniques provide both hi gh speed and l ow power featu res w ith a typical CMOS st andby current of 2uA and maximum access time of 25ns in 3.0V operation. Easy memory expansion is provided enable (CE \\), and active LOW output enable ( OE\\) and thre e-state output drivers. The UC62LS4008 has an automatic power down feature, reducing the po wer consumptio n significantly when chip is deselected. The UC62LS4008 is available in the JEDEC standard 32 pin 450mil Pla stic SOP, 8mmx20.0mm TSOP (type I), and 8mmx13.4 mm STSOP. „ PRODUCT FAMILY Power Consumption Speed (ns) STANDBY Operating Product Family Operating Tempature Vcc Range Package Type UC62LS4008HC TSOP-32 UC62LS4008FC SOP-32 UC62LS4008GC STSOP-32 UC62LS4008AC 0℃ ~ 70℃ 3.0V ~ 3.6V 20/25 2uA 20mA DICE UC62LS4008HI TSOP-32 UC62LS4008FI SOP-32 UC62LS4008GI STSOP-32 UC62LS4008AI -40℃ ~ 85℃ 3.0V ~ 3.6V 20/25 2uA 20mA DICE „ PIN CONFIGURATIONS A14 A12 DQ0 DQ1 DQ2 GND VCC WE A13 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4

16 DQ3

„ BLOCK DIAGRAM MEMORY ARRAY 512K X 8 Bits ROW DECODER COLUMN DECODER SENSE AMPLIFIER WRITE DRIVER I/O BUFFER ADDRESS INPUT BUFFER CONTROL BLOCK CONTROL INPUT BUFFER COL Address ROW Address CE WE OE A0 - A18 CE WE OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Reserves the right to modify document contents without notice. PAGE 1

-20/-25 „ PIN DESCRIPTION Name Type Function A0 – A18 Input Address inputs for selecting one of the 524,288 x 8 bit words in the RAM CE\\ Input CE\\ is active LOW. Chip enable must be active when data read from or write to the device. If chip enable is not active, the device is deselected and not in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. WE\\ Input The W rite en able input is active LOW and cont rols read and write oper ations. With the chip selected, when WE\\ is HIGH and OE\\ is LOW, output data will be present on the DQ pins, w hen WE\\ is LOW, the data present on the DQ pins will be written into the selected memory location. OE\\ Input The output enable input is active LOW. If the outp ut enable is active while the chip is selecte d and the write enable is inactive, data will be pr esent on the DQ pins and the y will be enabled. The DQ pins will be in the high impedance state when OE\\ is inactive. DQ0 – DQ7 I/O These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Power Supply Gnd Power Ground „ TRUTH TABLE Mode WE\\ CE\\ OE\\ I/O state Vcc Current Not Selected X H X High Z ISB,ISB1 Output Disabled H L H High Z ICC Read H L L DOUT ICC Write L L X DIN ICC „ ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER RATING UNIT VTERM Terminal Voltage with Respect to GND -0.5 to VCC+0.5 V TBIAS Temperature Under Bias -40 to 125 ℃ TSTG Storage Temperature -50 to 150 ℃ PT Power Dissipation 1 W IOUT DC Output Current 20 mA 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent da mage to the device. This is a stress rating only and functional operation of the device at th ese or an y other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. „ OPERATING RANGE RANGE AMBIENT TEMPERATURE VCC Commercial 0℃ to 70℃ 3.0V ~ 3.6V „ CAPACITANCE(1)(TA=25℃,f=1.0MHz) SYMBOL PARAMETER CONDITIONS MAX. UNIT CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VDQ 8 pF 1. This parameter is guaranteed and not 100% tested. Reserves the right to modify document contents without notice. PAGE 2

-20/-25 „ DC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃) Symbol Comment Test Condition MIN. TYP.(1) MAX. UNITS VIL Guaranteed Input Low Voltage (2) VIH Guaranteed Input High Voltage (2) VCC=3.6V 2.0 - Vcc-0.2 V IL Input Leakage Current VCC=3.6V VIN=0V to VCC - - 1 uA IOL Output Leakage Current VCC=3.6V CE\\=VIH or OE\\=VIH VIO=0V t VCC - - 1 uA VOL Output Low Voltage VCC=3.6V, IOL=2mA - - 0.4 V VOH Output High Voltage VCC=3.0V, IOH=-1mA 2.4 - - V ICC Operating Power Supply Current CE\\=VIL,IDQ=0mA, F=Fmax (3) - - 20 mA ISB1 TTL Standby Current CE\\=VIH, VIN=VIH to VIL - - 1 mA ISB2 CMOS Standby Current CE\\≧VCC-0.2V, VIN=VCC-0.2V to 0.2V - 2 10 uA 1. Typical characteristics are at TA = 25 o 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . „ DATA RETENTION CHARACTERISTICS ( TA=0℃ to 70℃) Symbol Comment Test Condition MIN. TYP. (1) MAX. UNITS VDR VCC to Data Retention CE\\≧VCC - 0.2V VIN≧VCC-0.2V or VIN≦0.2V 1.2 - - V ICCDR Data Retention Current CE\\≧VCC - 0.2V VIN≧VCC-0.2V or VIN≦0.2V - 0.1 1 uA tDR Chip Deselect to Data Retention Time 0 - - ns tR Operation Recovery Time See Retention Waveform TRC (2) - - ns 2. t RC = Read Cycle Time „ LOW VCC DATA RETENTION WAVEFORM(1) (CE\\ Controlled) Data Retention Mode VDR >= 1. 2VtCDR tR VIH VIHCE >= VCC - 0. 2V Vcc CE Reserves the right to modify document contents without notice. PAGE 3

-20/-25 „ SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) tAAtOH tOH tRC ADDRESS DOUT READ CYCLE2 (1,3,4) tCEtCLZ (5) tCHZ (5) CE DOUT READ CYCLE3 (1,4) tAA tOH tRC ADDRESS tCEtCLZ (5) tCHZ (5) CE DOUT OE tOHZ (1,5)tOE tOLZ NOTES: 1. WE\\ is high in read cycle. 2. Device is continuously selected when CE\\ = VIL 3. Address valid prior to or coincident with CE\\ transition low. 4. OE\\ = VIL. 5. Transition is measured ±500mV from steady state with CL=5pF as shown in F igure 1B. The parameter is guaranteed but not 100% tested. Reserves the right to modify document contents without notice. PAGE 5

-20/-25 „ AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=3.0V~3.6V) WRITE CYCLE UC62LS4008-20 UC62LS4008-25JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Min Typ Max Min Typ Max UNIT tAVAX tWC Write Cycle Time 20 - - 25 - - ns tE1LWH tCW Chip Select to END of Write 15 - - 15 - - ns tAVWL tAS Address Setup Time 0 - - 0 - - ns tAVWH tAW Address valid to End of Write 15 - - 15 - - ns tWLWH tWP Write Pulse Width 15 - - 15 - - ns tWHAX tWR Write Recovery Time 0 - - 0 - - ns tWLOZ tWHZ Write to Output in High Z - - 8 - - 10 ns tDVWH tDW Data to Write Time Overlap 8 - 10 - ns tWHDX tDH Data Hold Time for Write End 0 - - 0 - - ns tGHOZ tOHZ Output Disable to Output In High Z - - 8 - - 10 ns tWHQX tOW End of Write to Output Active 5 - - 5 - - ns „ SWITCHING WAVEFORMS (WRITE CYCLE) WRITECYCLE1(1) tWC ADDRESS tDH tOHZ WE DOUT OE CE tCW (11) tWP (2) tAW tAS (4,10) DIN tDW Reserves the right to modify document contents without notice. PAGE 6

-20/-25 WRITE CYCLE2(1,6) tWC ADDRESS tDH tWHZ WE DOUT CE tCW (11) tWP (2) tAW tAS DIN tDW tOH (8)(7) NOTES: 1. WE\\ must be high during address transitions. 2. The internal write time of the memory is def ined by the overlap o f CE\\ and WE\\ low . All signals must be a ctive to initiate a write and a ny one can te rminate a write by going in active. The d ata input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. T WR is measured from the earlier of CE\\ or WE\\ going high at the end of write cycle. 4. During this period, DQ pins are in the output st ate so that the input signals of oppo site phase to the outputs must not be applied. 5. If the CE\\ low tran sition occurs simultaneously with the WE\\ lo w tran sitions or af ter th e WE\\ transition, output remain in a high impedance state. 6. OE\\ is continuously low (OE\\ = VIL). 7. D OUT is the same phase of write data of this write cycle. 8. D OUT is the read data of next address. 9. If CE\\ is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE\\ going low to the end of write. Reserves the right to modify document contents without notice. PAGE 7

-20/-25 „ ORDERING INFORMATION UC62LS4008 AB -- YY A => GRADE C:COMMERCIAL; 0 ~ 70℃ I : INDUSTRIAL; -40 ~ 85℃ B => PACKAGE H :TSOP(I) F :SOP G:STSOP A:DICE YY => SPEED 20: 20ns 25: 25ns Reserves the right to modify document contents without notice. PAGE 8

-20/-25 „ PACKAGE DIMENSIONS Unit Symbol Inch mm A 0.0433±0.004 1.10±0.10 A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 c1 0.004~0.006 0.10~0.16 HD 0.528±0.008 13.40±0.20 L 0.0197+0.008 -0.004 0.5 +0.2 - 0.1 L1 0.0315±0.004 0.80±0.10 y 0.004 Max 0.1 Max „ 32 - S TS O P D "A " 1716 HD 1716 b WI T H P LAT IN G c1c SE CT IO N A- A BASE M E TAL A 12 °(2 X) "A " D E T AIL V IE W A A2A1 SEATING PL AN E A 0. 254 G AU G E PL AN E 12 °(2 X) L θ E e b SEAT IN G PLAN E "y" Reserves the right to modify document contents without notice. PAGE 9

-20/-25 Unit Symbol Inch mm A 0.0433±0.004 1.10±0.10 A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 c1 0.004~0.006 0.10~0.16 D 0.724±0.004 18.40±0.10 HD 0.787±0.008 20.00±0.20 L 0.0197+0.008 - 0.004 0.5 +0.2 - 0.1 L1 0.0315±0.004 0.80±0.10 y 0.004 Max 0.1 Max 32 - TS OP D "A" 1716 HD 1716 b WITH P LATING c1c SE CTION A -A BASE M ETAL A 12°(2X) "A" DETA IL VIEW A A2A1 SEATING PL ANE A 0.254 GAUGE PL ANE 12°(2X) L θ E 12°(2X) 12°(2X) e b SEAT ING PL AN E "y" Reserves the right to modify document contents without notice. PAGE 10

-20/-25 Unit Symbol Inch mm A 0.111±0.007 2.821±0.176 A1 0.009±0.005 0.229±0.127 A2 0.1055±0.0055 2.680±0.140 b 0.014 ~ 0.020 0.35 ~ 0.50 b1 0.014 ~ 0.018 0.35 ~ 0.46 c 0.006 ~ 0.012 0.15 ~ 0.32 c1 0.006 ~ 0.011 0.15 ~ 0.28 D 0.805±0.005 20.447±0.127 E 0.445±0.005 11.303±0.127 E1 0.555±0.012 14.097±0.305 e 0.050±0.006 1.270±0.152 L 0.033±0.010 0.834±0.25 L1 0.055±0.008 1.397±0.203 y 0.004 Max 0.1 Max SOP - 32 E 32 17 161 D e b Seating Plane "y" A2A1 A "A" A A L 10°(4X) θ DETAIL "A" (2:1) b WITH PLATING c1c SECTION A-A BASE METAL Reserves the right to modify document contents without notice. PAGE 11