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21:3 LVDS Transmitter CS5820 BLOCK DIAGRAM GENERAL DESCRIPTION Myson-Century Technology

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4020 Moorpark Avenue Suite

San Jose, CA, 95117 Tel: 408-243-8388 Fax: 408-243-3188 Sales@myson.com.tw www.myson.com.tw Rev.1.6 October 2001 page 1 of 12 Myson-Century Technology, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349 CS5820 receives three sets of 7-bit data in CMOS logic level and convert them into three low-voltage differential signaling (LVDS) serial channels. The 7- bit input data is referenced to the CKIN signal. The RF pin selects either rising or falling edge trigger of CKIN. Parallel to serial conversion is performed by a 7X internal generated clock reference using on-chip PLL using CKIN. A copy of CKIN but phase-locked to the output serial streams, CLKOUT, is also converted to the fourth LVDS channel. CS5820 offers a reliable communication media using LVDS signaling and provides low EMI dealing with wide, high-speed TTL interfaces. This is especially attractive for interfaces between GUI controller and display systems such as LCD panels for SVGA/XGA/SXGA applications. Three 7-bit serial and one clock LVDS channels. Compatible with ANSI TIA/EIA-644 LVDS stan- dard. Wide CKIN ranges from 31MHz to 68MHz. Fully integrated on-chip PLL that provides 7X CKIN serial shift clock. Pin selectable for rising or falling edge trigger. Support power-down mode. 5V/3.3V tolerant data input. Single 3.3V supply operation. CMOS low power consumption. Functional compatible with DS90C363 and SN75LVDS84. Available in 48-pin TSSOP package. PARALLEL-IN SERIAL-OUT D0-D6 7-Bit SHIFT REGISTER SHIFT/LOAD_N CLK DIN PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER SHIFT/LOAD_N DIN PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER SHIFT/LOAD_N DIN CLK CLK PHASE LOCK LOOP R/F CLK 7xCLK SHIFT/LOAD_N CONTROL LOGIC D7-D13 D14-D20 RF CKIN SHTDN EN Y0P Y0N EN Y1P Y1N EN Y2P Y2N EN CKOP CKON CS5820

CS5820Myson-Century Technology page 2 of 12 PIN CONNECTION DIAGRAM Figure-1 48-pin TSSOP VDD VSS VDD D10 VSS D11 D12 RF D13 D14 VSS D15 D16 D17 VDD D18 D19 VSS CS5820 VSS NC LVDS_VSS Y0N Y0P Y1N Y1P LVDS_VDD LVDS_VSS Y2N Y2P CKON CKOP LVDS_VSS PLL_VSS PLL-VDD PLL_VSS SHTDN CKIN D20

CS5820Myson-Century Technology page 3 of 12 PIN DESCRIPTION Name I/O Description D[0-6] I Parallel data input for Y0 LVDS channel. D[0] is LSB and D[6] is MSB. MSB is shifted out first. D[7-13] I Parallel data input for Y1 LVDS channel. D[7] is LSB and D[13] is MSB. D[14-20] I Parallel data input for Y2 LVDS channel. D[14] is LSB and D[20] is MSB. CKIN I Parallel input clock.This clock signal is used for parallel data reference. It is also used by the on-chip PLL to generate the 7X shift clock for parallel to serial conversion. RF I Rise/fall select. This pin selects the polarity of the CKIN edge for data input. RF = 1 selects CKIN rise edge, and RF = 0 selects CKIN fall edge. SHTDN I Shutdown control (low active). When SHTDN is low, the internal PLL is put into inhibit mode and all LVDS output channels are shut off. This also resets all internal registers. For normal operation, SHTDN should be set to high. Y0P , Y0N O Y0 LVDS channel output. These are differential LVDS outputs for Y0 channel corresponds to D[0-6]. Y1P , Y1N O Y1 LVDS channel output. These are differential LVDS outputs for Y1 channel corresponds to D[7-13]. Y2P , Y2N O Y2 LVDS channel output. These are differential LVDS outputs for Y2 channel corresponds to D[14-21]. CKOP , CKON O Clock LVDS channel output. These are differential LVDS output for the replica of CKIN signal. CKOP and CKON are derived from the internal phase lock loop and phase aligned with the serial data output and can be used by the LVDS receiver for reference edge. PLL_VDD P Power supply for PLL circuit. PLL_VSS P Power ground for PLL circuit. LVDS_VDD P Power supply for output buffer circuits. LVDS_VSS P Power ground for output buffer circuits. VDD P Power supply for internal circuits. VSS P Power ground for internal circuits.

CS5820Myson-Century Technology page 4 of 12 FUNCTIONAL DESCRIPTION Control logic There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are controlled by the control signal “SHTDN”. If SHTDN is high, the circuit is in the normal mode, else if low, the circuit is in the power down mode. In the power down mode, every block is off to make sure the least power consumption. 7 x CLK PLL 7 x CLK PLL, which is a phase lock loop, generates seven times clock of CKIN. The signal “RF” indicates that the input data (D0 ~ D20) is rising edge or falling edge trigger by CKIN. If RF=1, it is rigging edge trigger, else if RF=0, it is falling trigger. This seven times clock of CKIN is used by the Parallel ~ LOAD 7 Bit shift Register. 7 x CLK PLL also generate the control signal “SHIFT/LOAD ”. This signal is also used by the Parallel ~ LOAD 7 Bit Shift Register to indicate when to load data or shift data. Parallel ~ LOAD 7 Bit shift Register This block transfers 7 bits parallel data into one bit series data out. It is controlled by SHIFT/LOAD . If this control signal is low, the data are loaded into shift registers. Next, the SHIFT/LOAD turns high to shift data from shift register to output buffer seven times. One load and then seven shift. Ref: There are two properties in this block. One is that it supports reference voltage to fine the output’s common mode voltage. Another is that it generates about (4ns ~6ns) pulse width’s power on reset signal. When power on, all block would be reset by power on reset signal to make sure that the circuit would not stuck-at some situation we do not care. Output buffer There are three data output buffers and one clock output buffer. Output buffer generates differential pair output that swing is under 500 ~ 900mV, and common-mode voltage is under 1.125V ~ 1.375V.

CS5820Myson-Century Technology page 5 of 12 RECOMMENDED OPERATING CONDITIONS TIMING REQUIREMENTS Symbol Parameter Min Typ Max Unit VCC Supply voltage 3 3.3 3.6 V VIH High-level input voltage 2 - - V VIL Low-level input voltage - - 0.8 V ZL Differential load impedance 90 - 132 Ω TA Operating free-air temperature 0 - 70 °C Symbol Parameter Min Typ Max Unit tC Input clock period 14.7 32.4 ns tW Pulse duration, high-level input clock 0.4t C 0.6tC ns tt Transition time, Input signal 5 ns tsu Setup time, data, D0~D20 valid before CKIN ↓ (RF = 0) or CKIN↑(RF = 1) 3n s th Hold time, data, D0~D20 valid after CKIN ↓ (RF = 0) or CKIN↑(RF = 1) 1.5 ns

CS5820Myson-Century Technology page 6 of 12 DC CHARACTERISTICS Note: All typical values are at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition Min Typ Max Unit VIT Input threshold voltage -1 . 4- V VOD Differential steady-state output voltage magnitude RL = 100Ω 247 340 454 mV ∆ VOD Change in the steady-state differential output voltage magnitude between opposite binary states -1 0 5 0 m V VOC(SS) Steady-state common-mode output voltage 1.125 - 1.375 V VOC(PP) Peak-to-peak common-mode output voltage - 80 150 mV IIH High-level input current VIH = VCC -- 20 µA IIH-SHTDN High level input current for SHTDN pin VIH = VCC -- 10 µA IIL Low-level input current VIL = 0 -- ±10 µA IOS Short-circuit output current VO(Yn) = 0 -- ±24 mA VOD = 0 -- ±12 mA IOZ High-impedance output current VO = 0 to VCC -- ±10 µA ICC(AVG) Quiescent supply current (average) Power down SHTDN = 0 -- 2 5 0 µA Enabled, RL = 100Ω (4 places) Gray_scale pattern V CC = 3.3V, tC = 15.38ns 40 60 mA Enabled, RL = 100Ω (4 places) Worst_case pattern t C = 15.38ns 50 75 mA CI Input capacitance - 3- p F

CS5820Myson-Century Technology page 7 of 12 AC CHARACTERISTICS Symbol Parameter Condition Min Typ Max Unit t0 CKO↑ to bit 0 Tc= 15.38 ns -0.2 0 0.2 ns t1 CKO↑ to bit 1 1/7tc-0.2 - 1/7tc+0.2 ns t2 CKO↑ to bit 2 2/7tc-0.2 - 2/7tc+0.2 ns t3 CKO↑ to bit 3 3/7tc-0.2 - 3/7tc+0.2 ns t4 CKO↑ to bit 4 4/7tc-0.2 - 4/7tc+0.2 ns t5 CKO↑ to bit 5 5/7tc-0.2 - 5/7tc+0.2 ns t6 CKO↑ to bit 6 6/7tc-0.2 - 6/7tc+0.2 ns tskew Output skew -0.2 - 0.2 ns ∆tc(o) Cycle time, Output clock jitter - ±100 -p s tw Pulse duration, high-level output clock - 4/7tc -n s tt Transition time, differential output voltage (t r or tf) 260 700 1500 ps tenable Enable time, SHTDN↑ to phase lock (Yn valid) -1- m s tdisable Disable time, SHTDN↓ to off state (CKO low) - 250 - ns

CS5820Myson-Century Technology page 8 of 12 Note: Maximum value of tr, tf = 5ns Figure-2 Setup and Hold Time Definition (a) SCHEMATIC (b) WAVEFORMS Figure-3 Test Load and Voltage Definitions for LVDS Outputs /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0Dn tsutsu CKIN (RF=1) CKIN (RF=0) YP YM 49.9Ω ±1%(2 Places) CL=10pF Max (2 Places) VOC VOD 100% 80% 20% VOD(H) VOD(L) trtf VOC(PP) VOC(SS)VOC(SS)

CS5820Myson-Century Technology page 9 of 12 TEST PATTERN Figure-4 16-Grayscale Testing Pattern Waveforms Figure-5 The Worst-case Testing Pattern Waveforms Figure-6 Timing Waveform’s Definitions CKIN D0, 6, 12 D1, 7, 13 D2, 8, 14 D3, 9, 15 D18, 19, 20 D4, 5, 10, 11, 16, 17 CKIN Even Dn Odd Dn CKO /i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0Yn /i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0

CS5820Myson-Century Technology page 10 of 12 TYPICAL CHARACTERISTICS Figure-7 Enabled Time Waveforms Figure-8 Disabled Time Waveforms /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 CKIN SHTDN Yn tenable Invalid valid valid valid Note: RF=1 CKIN CKO SHTDN Note: RF=1 tdisable

CS5820Myson-Century Technology page 11 of 12 PACKAGE OUTLINE (48-pin TSSOP) Symbol Dimensions in Millimeters Dimensions in Inches MIN NOM MAX MIN NOM MAX A 1.05 - 1.20 0.04 - 0.047 A1 0.05 - 0.15 0.002 - 0.006 L 0.50 - 0.75 0.020 - 0.030 θ 0° -7 ° 0° -7 ° EE1 e b A2 A D L c b θθθθ

CS5820Myson-Century Technology page 12 of 12 APPLICATION CIRCUIT SCHEMATICS Figure-9 Using 48-pin TSSOP package +3.3V R16 33 +C3 10u CLK+ R0_2 +3.3V Hi Hs B0_0 G0_0 0.01u L2 100uH Power Adaptor G0_3 R0_0 B0_0 JP1 DC+5V G0_1 JS4 PWR Sel. C14 0.1u +3.3V ENA B0_3 A1+ G0_3 Vs CS5820 IN4 Vcc IN5 IN6 GND IN7 IN8 Vcc IN9 IN10 GND IN11 IN12 R_FB IN13 IN14 GND IN15 IN16 IN17 Vcc IN18 IN19 GND IN3 IN2 GND IN1 IN0 N/C LVDS GND OUT0- OUT0+ OUT1- OUT1+ LVDS Vcc LVDS GND OUT2- OUT2+ CLK OUT- CLK OUT+ LVDS GND PLL GND PLL Vcc PLL GND PWR DWN CLK IN IN20 JC1 DIGIT INPUT OSC G0_2 65MHz R5 10 JS2 PWR_DN from Pattern Generator LT1086-3.3/DD 3 2 GND VIN VOUT JS3 CLK Sel. Lo G0_2 Hs R0_4 R0_5 C18 0.1u R7 10 Int JS1 0.1u +C16 100u C17 0.1u A1- G0_5 ENA A0+ +C15 220u G0_0 0.01u 100uH 0.1u G0_4 Ext R0_3 R0_5 B0_2 B0_3 G0_5 A0- 0.1u R0_2 B0_4 B0_5 D_CLK +3.3V +C6 10u R0_1 A2- R0_0 Lo 0.1u R1 10k R0_1 R0_4 A2+ R15 10 B0_4 Vs R0_3 R6 10 Ext CLK_IN Hi G0_4 B0_1 R10 10k B0_2 G0_1 +3.3V B0_5 CLK- B0_1 0.1u A0- A2- A2+ A0+ A1- A1+ CLK+ CLK- JC2 LVDS Connector 13 14 13 14 R3 82 R14 50 R17 50 R9 82 A2+ A2- A0+ R13 82 C11 0.1u R12 50 A1+ R8 50 CLK+ R18 82 C10 0.1u A1- R11 50 R19 50 R2 50 C13 0.1u A0- C12 0.1u CLK- R4 50

Product Information

CS5820 specifications and overview.

Summary

21:3 LVDS Transmitter

Description

21:3 LVDS Transmitter

Source title CS5820 Datasheet(PDF) - List of Unclassifed Manufacturers

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