CS5530

CS5530 NSC | Alldatasheet

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© 2000 National Semiconductor Corporation www.national.com Geode™ CS5530 I/O Companion Multi-Function South Bridge April 2000 Geode™ CS5530 I/O Companion Multi-Function South Bridge General Description The CS5530 I/O companion is designed to work in con- junction with the GXLV and GXm series processors; all members of the National Semiconductor ® Geode™ family of products. Together the Geode processor and CS5530 provide a system-level solution well suited for the high performance needs of a host of devices such as digital set-top boxes and thin client devices. Due to the low power consumption of a GXLV processor, this solution satisfies the needs of battery powered devices such as National’s WebPAD™ system, a Geode GXLV proces- sor/CS5530 based design. Also, thermal design is eased allowing for fanless system design. The CS5530 I/O companion is a PCI-to-ISA bridge (South Bridge), ACPI-compliant chipset that provides AT/ISA style functionality. T o those familiar with PC architecture this enables a quicker understanding of the CS5530’s architecture. The device contains state-of-the-art power management that enables systems, especially battery powered systems, to significantly reduce power consump- tion. Audio is supported through PCI bus master engines which connect to an AC97 compatible codec such as the National Semiconductor LM4548. If industry standard audio is required, a combination of hardware and software called Virtual System Architecture ® (VSA™) technology is provided. The GXLV processor’s graphics/video output is connected to the CS5530. The CS5530 graphics/video support includes a PLL that generates the DOT clock for the GXLV processor (where the graphics controller is located), video acceleration hardware, gamma RAM plus three DACs for RGB output to CRT, and digital RGB that can be directly connected to TFT panels or NTSC/PAL encoders. The digital RGB output can also be connected to the National Semiconductor CS9210 Graphics Companion (a DSTN Controller) for DSTN panel support. The CS9210 is also a member of the Geode product family. Geode™ CS5530 Internal Block Diagram X-Bus ISA Bus PCI Bus USB PCI to X-Bus / X-Bus to PCI BridgePCI to USB Macro Active Decode Address Mapper Audio/Codec/MPU Interface Pwr Mgmt, Traps, Events, and Timers IDE Interface Display Interface MPEG, DOT Clock CSC and SCL RGB/FP Interface AT Compatibility Logic ISA Bus Interface AT Ports, ISA Megacells Display PCI Configuration Registers Graphics and Video from CPU X-Bus Arbiter CS5530 Support GPIOs IDE AC97 Codec Ultra DMA/33 (e.g., LM4548) Joystick / Game Port Joystick PC97317 SIO GPCS Geode™ CS9210 Graphics Companion National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode, VSA, and WebPAD are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.

www.national.com 2 Revision 4.1 Geode™ CS5530 Two bus mastering IDE controllers are included for sup- port of up to four AT A-compliant devices. A two-port Uni- versal Serial Bus (USB) provides high speed, Plug & Play expansion for a variety of consumer peripheral devices such as a keyboard, mouse, printer, and digital cameras. If additional functions are required, such as real-time clock, floppy disk, PS2 keyboard, and PS2 mouse, a SuperI/O (e.g., National PC97317) can be easily con- nected to the CS5530.

Features

/G01 Designed for use with the GXLV and GXm Geode series processors /G01 352-T erminal T ape Ball Grid Array (TBGA) package /G01 3.3V or 5.0V PCI bus compatible /G01 5.0V tolerant I/O interfaces /G01 3.3V core PCI-to-ISA Bridge /G01 PCI 2.1 compliant /G01 Supports PCI initiator-to-ISA and ISA master-to-PCI cycle translations /G01 PCI master for audio I/O and IDE controllers /G01 Subtractive agent for unclaimed transactions /G01 PCI-to-ISA interrupt mapper/translator AT Compatibility /G01 Two 8259A-equivalent interrupt controllers /G01 8254-equivalent timer /G01 Two 8237-equivalent DMA controllers /G01 Boot ROM and keyboard chip select /G01 E x t e n d e dR O Mt o1 6M B Bus Mastering IDE Controllers /G01 Two controllers with support for up to four IDE devices /G01 Independent timing for master and slave devices for both channels /G01 PCI bus master burst reads and writes /G01 Ultra DMA/33 (ATA-4) support /G01 Multiword DMA support /G01 Programmed I/O (PIO) Modes 0-4 support Power Management /G01 Intelligent system controller supports multiple power management standards: — Full ACPI and Legacy (APM) support — Directly manages all GXLV and GXm processor power states (including automatic Suspend modula- tion for optimal performance/thermal balancing) /G01 I/O traps and idle timers for peripheral power management /G01 Up to eight GPIOs for system control: — All eight are configurable as external wakeup events /G01 Dedicated inputs for keyboard and mouse wakeup events XpressAUDIO /G01 Provides "back-end" hardware support via six buffered PCI bus masters /G01 AC97 codec interface: — Specification Revision 1.3, 2.0, and 2.1 compliant interface. Note that the codec (e.g., LM4548) must have SRC (sample rate conversion) support Display Subsystem Extensions /G01 Complements the GXLV and GXm processor’s graphics and video capabilities: — Three independent line buffers for accelerating video data streams — Handles asynchronous video and graphics data streams concurrently from the processor — YUV to RGB conversion hardware — Arbitrary X & Y interpolative scaling — Color keying for graphics/video overlay /G01 V D A C s/D i s p l a yi n t e r f a c e : — Three integrated DACs — Gamma RAM: – Provides gamma correction for graphics data streams – Provides brightness/contrast correction for video data streams — Integrated DOT clock generator — Digital RGB interface drives TFT panels or standard NTSC/PAL encoders Universal Serial Bus /G01 Two independent USB interfaces: — Open Host Controller Interface (OpenHCI) specification compliant — Second generation proven core design

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1.0 Architecture Overview

The Geode CS5530 can be described as providing the functional blocks shown in Figure 1-1.  PCI bus master/slave interface  ISA bus interface  AT compatibility logic  IDE controllers  Power management -G P I O i n t e r f a c e s - Traps, Events, Timers  Joystick/Game Port interface  Virtual audio support hardware  Video display, which includes MPEG accelerator, RAMDAC, and video ports U S B c o n t r o l l e r s For CPU interface connection refer to Figure 1-5 on page 11.

1.1 PCI BUS INTERFACE

The CS5530 provides a PCI bus interface that is both a slave for PCI cycles initiated by the CPU or other PCI master devices, and a non-preemptable master for DMA transfer cycles. The chip also is a standard PCI master for the IDE controllers and audio I/O logic. The CS5530 sup- ports positive decode for configurable memory and I/O regions and implements a subtractive decode option for unclaimed PCI accesses. The CS5530 also generates address and data parity and performs parity checking. The CS5530 does not include the PCI bus arbiter, it is l o c a t e di nt h ep r o c e s s o r . Configuration registers are accessed through the PCI interface using the PCI Bus Type 1 configuration mecha- nism as described in the PCI 2.1 Specification. Figure 1-1. Internal Block Diagram X-Bus ISA Bus PCI Bus USB PCI to X-Bus / X-Bus to PCI BridgePCI to USB Macro Active Decode Address Mapper Audio/Codec/MPU Interface Pwr Mgmt, Traps, Events, and Timers IDE Interface Display Interface MPEG, DOT Clock CSC and SCL RGB/FP Interface AT Compatibility Logic ISA Bus Interface AT Ports, ISA Megacells Display PCI Configuration Registers Graphics and Video from CPU X-Bus Arbiter CS5530 Support GPIOs IDE AC97 Codec Ultra DMA/33 (e.g., LM4548) Joystick / Game Port Joystick PC97317 SIO GPCS Geode™ CS9210 Graphics Companion

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1.2 ISA BUS INTERFACE

The CS5530 provides an ISA bus interface for unclaimed memory and I/O cycles on PCI. The CS5530 is the default subtractive decoding agent and forwards all unclaimed memory and I/O cycles to the ISA interface; however, the CS5530 may be configured to ignore either I/O, memory or all unclaimed cycles (subtractive decode disabled). The CS5530 supports two modes on the ISA interface. The default mode, Limited ISA Mode, supports the full memory and I/O address range without ISA mastering. The address and data buses are multiplexed together, requiring an external latch to latch the lower 16 bits of address of the ISA cycle. The signal SA_LATCH is gener- ated when the data on the SA/SD bus is a valid address. Additionally, the upper four address bits, SA[23:20] are multiplexed on GPIO[7:4]. The second mode, ISA Master Mode, supports ISA bus masters and requires no external circuitry. When the CS5530 is placed in ISA Master Mode, a large number of pins are redefined. In this mode of operation the CS5530 cannot support TFT flat panels or TV controllers, since most of the signals used to support these functions have been redefined. This mode is required if ISA slots or ISA masters are used. ISA master cycles are only passed to the PCI bus if they access memory. I/O accesses are left to complete on the ISA bus. For further information regarding mode selection and operational details refer to Section 3.5.2.2 “Limited ISA and ISA Master Modes” on page 87.

1.3 AT COMPATIBILITY LOGIC

The CS5530 integrates:  Two 8237-equivalent DMA controllers with full 32-bit addressing  Two 8259-equivalent interrupt controllers providing 13 individually programmable external interrupts  An 8254-equivalent timer for refresh, timer, and speaker logic  NMI control and generation for PCI system errors and all parity errors  Support for standard AT keyboard controllers  Positive decode for the AT I/O register space  Reset control

1.3.1 DMA Controller

The CS5530 supports the industry standard DMA archi- tecture using two 8237-compatible DMA controllers in cascaded configuration. CS5530-supported DMA func- tions include:  Standard seven-channel DMA support  32-bit address range support via high page registers  IOCHRDY extended cycles for compatible timing transfers  ISA bus master device support using cascade mode

1.3.2 Programmable Interval Timer

The CS5530 contains an 8254-equivalent programmable interval timer. This device has three timers, each with an input frequency of 1.193 MHz.

1.3.3 Programmable Interrupt Controller

The CS5530 contains two 8259-equivalent programmable interrupt controllers, with eight interrupt request lines each, for a total of 16 interrupts. The two controllers are cascaded internally, and two of the interrupt request inputs are connected to the internal circuitry. This allows a total of 13 externally available interrupt requests. Each CS5530 IRQ signal can be individually selected as edge- or level-sensitive. The PCI interrupt signals are routed internally to the PIC IRQs.

1.4 IDE CONTROLLERS

The CS5530 integrates two PCI bus mastering, AT A-4 compatible IDE controllers. These controllers support U l t r aD M A / 3 3( e n a b l e di nM i c r o s o f tW i n d o w s9 5a n dW i n - dows NT by using a driver provided by National Semicon- ductor), Multiword DMA and Programmed I/O (PIO) modes. Two devices are supported on each controller. The data-transfer speed for each device on each control- ler can be independently programmed. This allows high- speed IDE peripherals to coexist on the same channel as lower speed devices. Faster devices must be ATA-4 com- patible.

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1.5 POWER MANAGEMENT

The CS5530 integrates advanced power management features including:  Idle timers for common system peripherals  Address trap registers for programmable address ranges for I/O or memory accesses  Up to eight programmable GPIOs  Clock throttling with automatic speedup for the CPU clock  Software CPU stop clock  Zero Volt Suspend/Resume with peripheral shadow registers  Dedicated serial bus to/from the GXLV processor providing CPU power management status T h eC S 5 5 3 0i sa nA C P I( A d v a n c e dC o n t r o la n dP o w e r Interface) compliant chipset. An ACPI compliant system is one whose underlying BIOS, device drivers, chipset and peripherals conform to revision 1.0 or newer of the ACPI specification. The “Fixed Feature” and “General Purpose” registers are virtual. They are emulated by the SMI han- dling code rather than existing in physical hardware. To the ACPI compliant operating system, the SMI-base virtu- alization is transparent; however, to eliminate unneces- sary latencies, the ACPI timer exists in physical hardware. The CS5530 V-ACPI (Virtual ACPI) solution provides the following support:  CPU States — C1, C2  Sleep States — S1, S2, S4, S4BIOS, S5  Embedded Controller (Optional) — SCI and SWI event inputs.  General Purpose Events — Fully programmable GPE0 Event Block registers.

1.5.1 GPIO Interface

Eight GPIO pins are provided for general usage in the system. GPIO[3:0] are dedicated pins and can be config- ured as inputs or outputs. GPIO[7:4] can be configured as the upper addresses of the ISA bus, SA[23:20]. All GPIOs can also be configured to generate an SMI on input edge transitions.

1.6 XPRESSAUDIO

XpressAUDIO in the CS5530 offers a combined hard- ware/software support solution to meet industry standard audio requirements. XpressAUDIO uses VSA technology along with additional hardware features to provide the necessary support for industry standard 16-bit stereo syn- thesis and OPL3 emulation. The hardware portion of the XpressAUDIO subsystem can broadly be divided into two categories. Hardware for:  Transporting streaming audio data to/from the system m e m o r ya n da nA C 9 7c o d e c .  VSA technology support.

1.6.1 AC97 Codec Interface

The CS5530 provides an AC97 Specification Revision 1.3, 2.0, and 2.1 compatible interface. Any AC97 codec which supports an independent input and output sample rate conversion interface (e.g., National Semiconductor LM4548) can be used with the CS5530. This type of codec will allow for a design which meets the require- ments for PC97 and PC98-compliant audio as defined by Microsoft Corporation. Figure 1-2 shows the codec and CS5530 signal connections. For specifics on the serial interface, refer to the appropriate codec manufacturer’s data sheet. Low latency audio I/O is accomplished by a buffered PCI bus mastering controller. Figure 1-2. AC97 Codec Signal Connections

1.6.2 VSA Technology Support Hardware

The CS5530 I/O companion incorporates the required hardware in order to support VSA technology for the cap- ture and playback of audio using an external codec. This eliminates much of the hardware traditionally associated with industry standard audio functions. XpressAUDIO software provides 16-bit compatible sound. This software is available to OEMs for incorporation into the system BIOS ROM. BITCLK PC_BEEP SDAT_I SDAT_O PC_BEEP SDATA_IN SDATA_OUT AC97 Geode™ BIT_CLK

24.576 MHz

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1.7 DISPLAY SUBSYSTEM EXTENSIONS

The CS5530 incorporates extensions to the GXLV proces- sor’s display subsystem. These include:  Video Accelerator - Buffers and formats input YUV video data from processor - 8-bit interface to the GXLV processor - X & Y scaler with bilinear filter - Color space converter (YUV to RGB)  Video Overlay Logic -C o l o r k e y - Data switch for graphics and video data G a m m a R A M - Brightness and contrast control  Display Interface - Integrated RGB Video DACs - VESA DDC2B/DPMS support - Flat panel interface Figure 1-3 shows the data path of the display subsystem extensions. Figure 1-3. Display Subsystem Extensions, 8-Bit Interface VID_DATA[7:0] 8 Input Buffer 0 (3x360x32 bit) Buffer 1 Buffer 2 Formatter Scaler Vertical Filter Horizontal Filter Color Space Converter Formatter Color Key Color Compare PIXEL[23:0] Bypass Gamma RAM

24 Video

FP_DATA 1824 Enable Gamma Correction Register Register

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1.8 CLOCK GENERATION

In a CS5530/GXLV processor-based system, the CS5530 generates only the video DOT clock (DCLK) for the CPU and the ISA clock. All other clocks are generated by an external clock chip. The ISACLK is created by dividing the PCICLK. For ISA compatibility, the ISACLK nominally runs at 8.33 MHz or less. The ISACLK dividers are programmed via F0 Index 50h[2:0]. DCLK is generated from the 14.31818 MHz input (CLK_14MHZ). A combination of a phase locked loop (PLL), linear feedback shift register (LFSR) and divisors are used to generate the desired frequencies for the DCLK. The divisors and LFSR are configurable through the F4BAR+Memory Offset 24h. For applications that do not use the GXLV processor’s video, this is an available clock for general purpose use. Figure 1-4 shows a block diagram for clock generation within the CS5530. Figure 1-4. CS5530 Clock Generation

1.9 UNIVERSAL SERIAL BUS

The CS5530 provides two complete, independent USB ports. Each port has a Data "–" and a Data "+" pin. The USB controller is a compliant Open Host Controller Interface (OpenHCI). The OpenHCI specification provides a register-level description for a host controller, as well as a common industry hardware/software interface and driv- ers (see OpenHCI Specification, Revision 1.0, for descrip- tion). DCLK DCLK PLL TVCLK CLK_14MHZ ISACLKPCICLK M U X

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1.10 PROCESSOR SUPPORT

The traditional south bridge functionality included in the CS5530 I/O companion chip has been designed to sup- port the GXLV processor. When combined with the GXLV processor, the CS5530 provides a bridge which supports a standard ISA bus and system ROM. As part of the video subsystem, the CS5530 provides MPEG video accelera- tion and a digital RGB interface, to allow direct connection to TFT LCD panels. This chip also integrates a gamma RAM and three DACs, allowing for direct connection of a CRT monitor. Figure 1-5 shows a typical system block dia- gram. For detailed information regarding processor signal con- nections refer to Section 3.1 “Processor Interface” on page 41. Figure 1-5. System Block Diagram YUV Port (Video) RGB Port PCI Interface MemoryMemory Data Bus PCI Bus Geode™ CS5530 I/O Companion Graphics Data Video Data Analog RGB Digital RGB CRT TFT Flat Panel USB (2 Ports) AC97 Codec Speakers CD ROM Audio Micro- phone GPIOs Port (Graphics) Geode™ GXLV IDE Devices SuperI/O BIOS ISA Bus Ultra DMA/33 IDE Bus Memory Serial Packet DC-DC Battery Clocks or TV NTSC/PAL Encoder Processor

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2.0 Signal Definitions

This section defines the signals and describes the exter- nal interface of the Geode CS5530. Figure 2-1 shows the pins organized by their functional groupings (internal test and electrical pins are not shown). Figure 2-1. CS5530 Signal Groups AD[31:0] C/BE[3:0]# PAR HOLD_REQ# FRAME# TRDY# STOP# LOCK# DEVSEL# REQ# GNT# SERR# INTA#-INTD# IRQ13 INTR SMI# IDE_DACK1# IDE_IORDY0 ROM Interface PCI Bus CPU Interface IDE Controller PSERIAL SUSP# SUSPA# KBROMCS# IRDY# PERR# SUSP_3V IDE_IOW1# IDE_IOW0# IDE_IOR0# IDE_IOR1# Geode™ CS5530 IDE_DATA[15:0] IDE_ADDR[2:0] IDE_RST# IDE_CS0# IDE_CS1# IDE_DREQ1 IDE_DACK0# IDE_DREQ0 IDE_IORDY1 TVCLK DCLK PCICLK ISACLK Clocks CLK_32K CLK14_MHZ Reset PCI_RST# POR# CPU_RST USBCLK D+_PORT1 D–_PORT1 D+_PORT2 D–_PORT2 USB POWER_EN OVER_CUR# SDATA_OUT SDATA_IN SYNC BIT_CLK PC_BEEP Audio Interface I/O Companion VREF EXTVREFIN PCLK IOUTG IOUTB AVSS1-5 IOUTR AVDD1-3 HSYNC_OUT HSYNC VSYNC PIXEL[23:0] FP_DATA17 (MASTER#) FP_CLK (No Function) Display: Pixel Display: CRT ENA_DISP VSYNC_OUT DDC_SCL DDC_SDA FP_HSYNC_OUT (SMEMW#) FP_CLK_EVEN (No Function) FP_VSYNC_OUT (SMEMR#) IREF FP_DISP_ENA_OUT (No Function) FP_ENA_VDD (No Function) FP_ENA_BKL (No Function) FP_HSYNC (No Function) FP_VSYNC (No Function) Analog Display: MPEG PLLDVD PLLVAA PLLRO PLLLP PLLAGS DCLKPLLAnalog Port PLLAGD PLLDGN VID_RDY VID_VAL VID_CLK VID_DATA[7:0] SA[19:16] (SA_DIR) SA_LATCH SBHE# BALE IOCHRDY ZEROWS# IOR# IOW# MEMCS16# MEMR# MEMW# AEN DRQ[7:5], [3:0] DACK#[7:5], [3:0] TC ISA Bus IRQ8# IOCS16# GPCS# GPORT_CS# (SA[23:20]) GPIO[7:4]/SA[23:20] GPIO[3:2] GPIO1/SDATA_IN2 GPIO0 Game Port/ GPIO SMEMW#/RTCCS# SMEMR#/RTCALE FP_DATA16 (SA_OE#) FP_DATA[15:0] (SA[15:0]) External RTC Display: TFT/TV Note: Pins that change function when ISA Master mode is invoked are repre- sented with the ISA Mas- ter Mode function signal name in parenthesis.

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2.1 PIN ASSIGNMENTS

The tables in this section use several common abbrevia- tions. Table 2-1 lists the mnemonics and their meanings. Figure 2-2 shows the pin assignment for the CS5530 with Tables 2-2 and 2-3 listing the pin assignments sorted by terminal number and alphabetically by signal name, respectively. In Section 2.2 “Signal Descriptions” a description of each signal within its associated functional group is provided. In the signal definitions, references to F0-F4, F1BAR, F2BAR, F3BAR, F4BAR, and PCIUSB are made. These terms relate to designated register spaces. Refer to T able 4-1 "PCI Configuration Address Register (0CF8h)" on page 138 for details regarding these register spaces and their access mechanisms. Table 2-1. Pin Type Definitions Mnemonic Definition 5VT Buffer is 5V tolerant I Input pin I/O Bidirectional pin IBUF Input buffer OO u t p u t OD Open-drain output structure that allows multiple devices to share the pin in a wired-OR configuration PU Pull-up resistor PD Pull-down resistor smt Schmitt Trigger t/s Tri-state signal VDD (PWR) Power pin VSS (GND) Ground pin # The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name, the signal is asserted when at a high volt- age level.

www.national.com 14 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530 Figure 2-2. TBGA Pin Assignment Diagram Order Number: 25420-03 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Index Corner PIX0 PIX1 PIX2 PIX7 PIX10 VCLK PIX12 PIX16 PIX19 DCLK VDAT0 VDAT5 PCLK INTA# AD0 AD7 AD9 AD12 AD10 AD15 PAR SERR# DVSL# C/BE2# AD17 AD16 ENADISP TVCLK PIX4 PIX5 VSYNC PIX8 VDVAL PIX15 PIX18 VDRDY PIX22 VDAT6 VDAT2 INTD# AD3 AD5 AD6 C/BE0# AD11 AD14 C/BE1# PERR# TRDY# IRDY# AD18 AD19 FPVSY FPHSY VDD PIX3 PIX11 HSYN PIX14 PIX17 PIX21 PIX23 VDAT3 VDAT7 VDAT1 PRST# INTC# AD2 AD4 VSS VDD AD13 VSS LOCK# FRAM# VDD AD21 AD22 FPD11 NC TEST VSS PIX6 PIX9 PIX13 VSS PIX20 VDD VDAT4 VSS VSS AD1 INTB# VSS VDD AD8 VSS VSS VDD VSS VSS GNT# AD26 C/BE3# FPHSYO FPD10 FPVSYO VSS VSS AD20 AD23 STOP# FPD9 DISENO FPD17 VDD VSS VDD AD24 AD27 FPD8 FPD5 FPD7 FPD6 VSS AD25 AD28 AD29 FPD4 FPD15 FPD16 VSS VSS VDD AD31 HDRQ# FPD3 FPD1 FPD2 ENBKL VSS AD30 REQ# PCICLK FPD14 FPD13 FPD0 VSS VSS POR# CPURST SUSP# FPD12 ENVDD CKEVEN VDD VDD SUSP3V SUSPA# PSERL FPCLK DDCSCL VSS DDCSDA PLDVD VSS PLVAA PLRO HSYNO VSYNO VSS AVDD3 PLP PLAGS PLAGD PLDGN AVSS4 AVSS5 IOUTR IOUTG VSS 14MHZ SMI# INTR IOUTB AVSS1 IREF AVSS2 IRQ13 DIOW0# DIOR1# DIOR0# VREF XVREFI AVDD2 AVSS3 VDD DDCK1# DIOW1# DDCK0# AVDD1 VDD SYNC SDATI IDED7 IDED6 IDEA0 IDEA1 SDATO BITCLK PCBEEP PWREN VSS IDED8 IDED10 DCS0# USBCLK NC OVRCUR# VSS VSS IDEA2 DRST# IDED5 D–PT1 D+PT1 NC VSS VDD IDED11 IDED9 DCS1# D–PT2 D+PT2 NC VSS VSS IDED1 IDED12 IDED4 NC NC NC VDD IDED15 IDED2 IDED13 IDED3 NC NC NC VSS VSS SA3 DCK7# DCK1# VSS VDD IOW# VSS VSS IRQ3 MCS16# VSS IRQ14 VSS VDD SA10 GPIO5 GPIO0 VSS DREQ1 IDED14 IDED0 NC NC NC SMEMR# SA5 ISACLK DCK6# DCK0# SA2 SA19 SA16 DRQ1 DRQ3 IRQ7 SLTCH VDD IRQ15 DRQ5 SA9 VSS GPTCS# GPIO4 VDD SA14 IORDY0 DREQ0 NC NC 32K KRMCS# IRQ9 SA1 DCK5# AEN SA0 DRQ2 SA18 IOR# IRQ5 IRQ8# IRQ4 IRQ10 SBHE# DRQ0 MEMR# DRQ6 SA12 SA13 GPIO6 GPIO1 SA15 IORDY1 NC NC SMEMW# SA7 SA6 SA4 DCK3# DCK2# BALE 0WS# CHRDY SA17 IRQ1 IRQ6 TC CS16# IRQ12 IRQ11 SA8 MEMW# SA11 DRQ7 GPIO7 GPIO3 GPIO2 GPCS# 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Geode™ CS5530 I/O Companion Top View Note:Signal names have been abbreviated in this figure due to space constraints. = GND terminal = PWR terminal = Multiplexed signal = Changes function in ISA Master Mode

Revision 4.1 15 www.national.com Signal Definitions(Continued) Geode™ CS5530 Table 2-2. 352 TBGA Pin Assignments - Sorted by Pin Number Pin No. Signal Name Limited ISA Mode ISA Master Mode A1 PIXEL0 A2 PIXEL1 A3 PIXEL2 A4 PIXEL7 A5 PIXEL10 A6 VID_CLK A7 PIXEL12 A8 PIXEL16 A9 PIXEL19 A10 DCLK A11 VID_DAT A0 A12 VID_DAT A5 A13 PCLK A14 INT A# A15 AD0 A16 AD7 A17 AD9 A18 AD12 A19 AD10 A20 AD15 A21 P AR A22 SERR# A23 DEVSEL# A24 C/BE2# A25 AD17 A26 AD16 B1 ENA_DISP B2 TVCLK B3 PIXEL4 B4 PIXEL5 B5 VSYNC B6 PIXEL8 B7 VID_VAL B8 PIXEL15 B9 PIXEL18 B10 VID_RDY B11 PIXEL22 B12 VID_DAT A6 B13 VID_DAT A2 B14 INTD# B15 AD3 B16 AD5 B17 AD6 B18 C/BE0# B19 AD11 B20 AD14 B21 C/BE1# B22 PERR# B23 TRDY# B24 IRDY# B25 AD18 B26 AD19 C1 FP_VSYNC No Function C2 FP_HSYNC No Function C3 VDD C4 PIXEL3 C5 PIXEL11 C6 HSYNC C7 PIXEL14 C8 PIXEL17 C9 PIXEL21 C10 PIXEL23 C11 VID_DATA3 C12 VID_DATA7 C13 VID_DATA1 C14 PCI_RST# C15 INTC# C16 AD2 C17 AD4 C18 VSS C19 VDD C20 AD13 C21 VSS C22 LOCK# C23 FRAME# C24 VDD C25 AD21 C26 AD22 D1 FP_DATA11 SA11 D2 NC D3 TEST D4 VSS D5 PIXEL6 D6 PIXEL9 D7 PIXEL13 D8 VSS D9 PIXEL20 D10 VDD D11 VID_DATA4 D12 VSS D13 VSS D14 AD1 D15 INTB# D16 VSS D17 VDD D18 AD8 D19 VSS D20 VSS D21 VDD D22 VSS D23 VSS D24 GNT# Pin No. Signal Name Limited ISA Mode ISA Master Mode D25 AD26 D26 C/BE3# E1 FP_HSYNC_OUT SMEMW# E2 FP_DATA10 SA10 E3 FP_VSYNC_OUT SMEMR# E4 VSS E23 VSS E24 AD20 E25 AD23 E26 STOP# F1 FP_DATA9 SA9 F2 FP_DISP_ENA_OUT No Function F3 FP_DATA17 MASTER# F4 VDD F23 VSS F24 VDD F25 AD24 F26 AD27 G1 FP_DATA8 SA8 G2 FP_DATA5 SA5 G3 FP_DATA7 SA7 G4 FP_DATA6 SA6 G23 VSS G24 AD25 G25 AD28 G26 AD29 H1 FP_DATA4 SA4 H2 FP_DATA15 SA15 H3 FP_DATA16 SA_OE# H4 VSS H23 VSS H24 VDD H25 AD31 H26 HOLD_REQ# J1 FP_DATA3 SA3 J2 FP_DATA1 SA1 J3 FP_DATA2 SA2 J4 FP_ENA_BKL No Function J23 VSS J24 AD30 J25 REQ# J26 PCICLK K1 FP_DATA14 SA14 K2 FP_DATA13 SA13 K3 FP_DATA0 SA0 K4 VSS K23 VSS K24 POR# K25 CPU_RST K26 SUSP# L1 FP_DATA12 SA12 Pin No. Signal Name Limited ISA Mode ISA Master Mode

www.national.com 16 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530L2 FP_ENA_VDD No Function L3 FP_CLK_EVEN No Function L4 VDD L23 VDD L24 SUSP_3V L25 SUSPA# L26 PSERIAL M1 FP_CLK No Function M2 DDC_SCL M3 VSS M4 DDC_SDA M23 PLLDVD M24 VSS M25 PLLVAA M26 PLLRO N1 HSYNC_OUT N2 VSYNC_OUT N3 VSS N4 AVDD3 (DAC) N23 PLLLP N24 PLLAGS N25 PLLAGD N26 PLLDGN P1 AVSS4 (ICAP) P2 AVSS5 (DAC) P3 IOUTR P4 IOUTG P23 VSS P24 CLK_14MHZ P25 SMI# P26 INTR R1 IOUTB R2 AVSS1 (DAC) R3 IREF R4 AVSS2 (ICAP) R23 IRQ13 R24 IDE_IOW0# R25 IDE_IOR1# R26 IDE_IOR0# T1 VREF T2 EXTVREFIN T3 AVDD2 (VREF) T4 AVSS3 (VREF) T23 VDD T24 IDE_DACK1# T25 IDE_IOW1# T26 IDE_DACK0# U1 AVDD1 (DAC) U2 VDD U3 SYNC U4 SDATA_IN Pin No. Signal Name Limited ISA Mode ISA Master Mode U23 IDE_DAT A7 U24 IDE_DAT A6 U25 IDE_ADDR0 U26 IDE_ADDR1 V1 SDATA_OUT V2 BIT_CLK V3 PC_BEEP V4 POWER_EN V23 VSS V24 IDE_DAT A8 V25 IDE_DAT A10 V26 IDE_CS0# W1 USBCLK W2 NC W3 OVER_CUR# W4 VSS W23 VSS W24 IDE_ADDR2 W25 IDE_RST# W26 IDE_DAT A5 Y1 D–_PORT1 Y2 D+_PORT1 Y3 NC Y4 VSS Y23 VDD Y24 IDE_DAT A11 Y25 IDE_DAT A9 Y26 IDE_CS1# AA1 D–_PORT2 AA2 D+_PORT2 AA3 NC AA4 VSS AA23 VSS AA24 IDE_DATA1 AA25 IDE_DAT A12 AA26 IDE_DATA4 AB1 NC AB2 NC AB3 NC AB4 VDD AB23 IDE_DAT A15 AB24 IDE_DATA2 AB25 IDE_DAT A13 AB26 IDE_DATA3 AC1 NC AC2 NC AC3 NC AC4 VSS AC5 VSS AC6 SA3/SD3 SD3 AC7 DACK7# Pin No. Signal Name Limited ISA Mode ISA Master Mode AC8 DACK1# AC9 VSS AC10 VDD AC11 IOW# AC12 VSS AC13 VSS AC14 IRQ3 AC15 MEMCS16# AC16 VSS AC17 IRQ14 AC18 VSS AC19 VDD AC20 SA10/SD10 SD10 AC21 GPIO5/SA21 SA21 AC22 GPIO0 AC23 VSS AC24 IDE_DREQ1 AC25 IDE_DAT A14 AC26 IDE_DATA0 AD1 NC AD2 NC AD3 NC AD4 SMEMR#/RTCALE AD5 SA5/SD5 SD5 AD6 ISACLK AD7 DACK6# AD8 DACK0# AD9 SA2/SD2 SD2 AD10 SA19 AD11 SA16 AD12 DRQ1 AD13 DRQ3 AD14 IRQ7 AD15 SA_LATCH SA_DIR AD16 VDD AD17 IRQ15 AD18 DRQ5 AD19 SA9/SD9 SD9 AD20 VSS AD21 GPORT_CS# AD22 GPIO4/SA20 SA20 AD23 VDD AD24 SA14/SD14 SD14 AD25 IDE_IORDY0 AD26 IDE_DREQ0 AE1 NC AE2 NC AE3 CLK_32K AE4 KBROMCS# AE5 IRQ9 AE6 SA1/SD1 SD1 Pin No. Signal Name Limited ISA Mode ISA Master Mode Table 2-2. 352 TBGA Pin Assignments - Sorted by Pin Number (Continued)

Revision 4.1 17 www.national.com Signal Definitions(Continued) Geode™ CS5530 AE7 DACK5# AE8 AEN AE9 SA0/SD0 SD0 AE10 DRQ2 AE11 SA18 AE12 IOR# AE13 IRQ5 AE14 IRQ8# AE15 IRQ4 AE16 IRQ10 AE17 SBHE# AE18 DRQ0 AE19 MEMR# AE20 DRQ6 AE21 SA12/SD12 SD12 AE22 SA13/SD13 SD13 Pin No. Signal Name Limited ISA Mode ISA Master Mode AE23 GPIO6/SA22 SD22 AE24 GPIO1/SDATA_IN2 AE25 SA15/SD15 SD15 AE26 IDE_IORDY1 AF1 NC AF2 NC AF3 SMEMW#/RTCCS# AF4 SA7/SD7 SD7 AF5 SA6/SD6 SD6 AF6 SA4/SD4 SD4 AF7 DACK3# AF8 DACK2# AF9 BALE AF10 ZEROWS# AF11 IOCHRDY AF12 SA17 Pin No. Signal Name Limited ISA Mode ISA Master Mode AF13 IRQ1 AF14 IRQ6 AF15 TC AF16 IOCS16# AF17 IRQ12 AF18 IRQ11 AF19 SA8/SD8 SD8 AF20 MEMW# AF21 SA11/SD11 SD11 AF22 DRQ7 AF23 GPIO7/SA23 SA23 AF24 GPIO3 AF25 GPIO2 AF26 GPCS# Pin No. Signal Name Limited ISA Mode ISA Master Mode Table 2-2. 352 TBGA Pin Assignments - Sorted by Pin Number (Continued)

www.national.com 18 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530 Table 2-3. 352 TBGA Pin Assignments - Sorted Alphabetically by Signal Name Signal Name Pin Type (Note 1) Buffer Type (Note 2) Pin No. Limited ISA Mode ISA Master Mode AD0 I/O, t/s, 5VT PCI A15 AD1 I/O, t/s, 5VT PCI D14 AD2 I/O, t/s, 5VT PCI C16 AD3 I/O, t/s, 5VT PCI B15 AD4 I/O, t/s, 5VT PCI C17 AD5 I/O, t/s, 5VT PCI B16 AD6 I/O, t/s, 5VT PCI B17 AD7 I/O, t/s, 5VT PCI A16 AD8 I/O, t/s, 5VT PCI D18 AD9 I/O, t/s, 5VT PCI A17 AD10 I/O, t/s, 5VT PCI A19 AD11 I/O, t/s, 5VT PCI B19 AD12 I/O, t/s, 5VT PCI A18 AD13 I/O, t/s, 5VT PCI C20 AD14 I/O, t/s, 5VT PCI B20 AD15 I/O, t/s, 5VT PCI A20 AD16 I/O, t/s, 5VT PCI A26 AD17 I/O, t/s, 5VT PCI A25 AD18 I/O, t/s, 5VT PCI B25 AD19 I/O, t/s, 5VT PCI B26 AD20 I/O, t/s, 5VT PCI E24 AD21 I/O, t/s, 5VT PCI C25 AD22 I/O, t/s, 5VT PCI C26 AD23 I/O, t/s, 5VT PCI E25 AD24 I/O, t/s, 5VT PCI F25 AD25 I/O, t/s, 5VT PCI G24 AD26 I/O, t/s, 5VT PCI D25 AD27 I/O, t/s, 5VT PCI F26 AD28 I/O, t/s, 5VT PCI G25 AD29 I/O, t/s, 5VT PCI G26 AD30 I/O, t/s, 5VT PCI J24 AD31 I/O, t/s, 5VT PCI H25 AEN O 8 mA AE8 AVDD1 (DAC) I, Analog -- U1 AVDD2 (VREF) I, Analog -- T3 AVDD3 (DAC) I, Analog -- N4 AVSS1 (DAC) I, Analog -- R2 AVSS2 (ICAP) I, Analog -- R4 AVSS3 (VREF) I, Analog -- T4 AVSS4 (ICAP) I, Analog -- P1 AVSS5 (DAC) I, Analog -- P2 BALE O8 m A A F 9 BIT_CLK I, 5VT IBUF V2 C/BE0# I/O, t/s, 5VT PCI B18 C/BE1# I/O, t/s, 5VT PCI B21 C/BE2# I/O, t/s, 5VT PCI A24 C/BE3# I/O, t/s, 5VT PCI D26 CLK_14MHZ Is m t P 2 4 CLK_32K I/O, 5VT 4 mA AE3 CPU_RST O8 m A K 2 5 DACK0# O8 m A A D 8 DACK1# O8 m A A C 8 DACK2# O8 m A A F 8 DACK3# O8 m A A F 7 DACK5# O 8 mA AE7 DACK6# O8 m A A D 7 DACK7# O8 m A A C 7 DCLK O8 m A A 1 0 DDC_SCL O 8 mA M2 DDC_SDA I/O, 5VT 8 mA M4 DEVSEL# I/O, t/s, 5VT PCI A23 D–_PORT1 I/O USB Y1 D+_PORT1 I/O USB Y2 D–_PORT2 I/O USB AA1 D+_PORT2 I/O USB AA2 DRQ0 I, 5VT IBUF AE18 DRQ1 I, 5VT IBUF AD12 DRQ2 I, 5VT IBUF AE10 DRQ3 I, 5VT IBUF AD13 DRQ5 I, 5VT IBUF AD18 DRQ6 I, 5VT IBUF AE20 DRQ7 I, 5VT IBUF AF22 ENA_DISP II B U F B 1 EXTVREFIN I, Analog -- T2 FP_CLK No Function O 8 mA M1 FP_CLK_EVEN No Function O8 m A L 3 FP_DATA0 SA0 I/O 8 mA K3 FP_DATA1 SA1 I/O 8 mA J2 FP_DATA2 SA2 I/O 8 mA J3 FP_DATA3 SA3 I/O 8 mA J1 FP_DATA4 SA4 I/O 8 mA H1 FP_DATA5 SA5 I/O 8 mA G2 FP_DATA6 SA6 I/O 8 mA G4 FP_DATA7 SA7 I/O 8 mA G3 FP_DATA8 SA8 I/O 8 mA G1 FP_DATA9 SA9 I/O 8 mA F1 FP_DATA10 SA10 I/O 8 mA E2 FP_DATA11 SA11 I/O 8 mA D1 FP_DATA12 SA12 I/O 8 mA L1 FP_DATA13 SA13 I/O 8 mA K2 FP_DATA14 SA14 I/O 8 mA K1 FP_DATA15 SA15 I/O 8 mA H2 FP_DATA16 SA_OE# O8 m A H 3 FP_DATA17 MASTER# I/O 8 mA F3 FP_DISP_ENA_OUT No Function O8 m A F 2 FP_ENA_BKL No Function O8 m A J 4 FP_ENA_VDD No Function O8 m A L 2 FP_HSYNC No Function II B U F C 2 FP_HSYNC_OUT SMEMW# O8 m A E 1 FP_VSYNC No Function II B U F C 1 FP_VSYNC_OUT SMEMR# O8 m A E 3 FRAME# I/O, t/s, 5VT PCI C23 Signal Name Pin Type (Note 1) Buffer Type (Note 2) Pin No. Limited ISA Mode ISA Master Mode

Revision 4.1 19 www.national.com Signal Definitions(Continued) Geode™ CS5530 GNT# I, 5VT PCI D24 GPCS# O4 m A A F 2 6 GPIO0 I/O, 5VT 8 mA AC22 GPIO1/SDATA_IN2 I/O, 5VT 8 mA AE24 GPIO2 I/O, 5VT 8 mA AF25 GPIO3 I/O, 5VT 8 mA AF24 GPIO4/SA20 SA20 I/O, 5VT 8 mA AD22 GPIO5/SA21 SA21 I/O, 5VT 8 mA AC21 GPIO6/SA22 SA22 I/O, 5VT 8 mA AE23 GPIO7/SA23 SA23 I/O, 5VT 8 mA AF23 GPORT_CS# O8 m A A D 2 1 HOLD_REQ# (strap pin) I/O, 5VT PCI H26 HSYNC II B U F C 6 HSYNC_OUT O1 6 m A N 1 IDE_ADDR0 O8 m A U 2 5 IDE_ADDR1 O8 m A U 2 6 IDE_ADDR2 O8 m A W 2 4 IDE_CS0# O8 m A V 2 6 IDE_CS1# O8 m A Y 2 6 IDE_DACK0# O8 m A T 2 6 IDE_DACK1# O8 m A T 2 4 IDE_DATA0 I/O, 5VT 8 mA AC26 IDE_DATA1 I/O, 5VT 8 mA AA24 IDE_DATA2 I/O, 5VT 8 mA AB24 IDE_DATA3 I/O, 5VT 8 mA AB26 IDE_DATA4 I/O, 5VT 8 mA AA26 IDE_DATA5 I/O, 5VT 8 mA W26 IDE_DATA6 I/O, 5VT 8 mA U24 IDE_DATA7 I/O, 5VT 8 mA U23 IDE_DATA8 I/O, 5VT 8 mA V24 IDE_DATA9 I/O, 5VT 8 mA Y25 IDE_DATA10 I/O, 5VT 8 mA V25 IDE_DATA11 I/O, 5VT 8 mA Y24 IDE_DATA12 I/O, 5VT 8 mA AA25 IDE_DATA13 I/O, 5VT 8 mA AB25 IDE_DATA14 I/O, 5VT 8 mA AC25 IDE_DATA15 I/O, 5VT 8 mA AB23 IDE_DREQ0 I, 5VT IBUF AD26 IDE_DREQ1 I, 5VT IBUF AC24 IDE_IOR0# O8 m A R 2 6 IDE_IOR1# O8 m A R 2 5 IDE_IORDY0 I, 5VT IBUF AD25 IDE_IORDY1 I, 5VT IBUF AE26 IDE_IOW0# O8 m A R 2 4 IDE_IOW1# O8 m A T 2 5 IDE_RST# O8 m A W 2 5 INTA# I, 5VT IBUF A14 INTB# I, 5VT IBUF D15 INTC# I, 5VT IBUF C15 INTD# I, 5VT IBUF B14 INTR (strap pin) I/O 4 mA P26 Signal Name Pin Type (Note 1) Buffer Type (Note 2) Pin No. Limited ISA Mode ISA Master Mode IOCHRDY I/O, OD, 5VT 8 mA AF11 IOCS16# I, 5VT IBUF AF16 IOR# I/O (PU), 5VT 8 mA AE12 IOUTB O, Analog R1 IOUTR O, Analog P3 IOUTG O, Analog P4 IOW# I/O (PU), 5VT 8 mA AC11 IRDY# I/O, t/s, 5VT PCI B24 IREF I, Analog R3 IRQ1 I, 5VT IBUF AF13 IRQ3 I, 5VT IBUF AC14 IRQ4 I, 5VT IBUF AE15 IRQ5 I, 5VT IBUF AE13 IRQ6 I, 5VT IBUF AF14 IRQ7 I, 5VT IBUF AD14 IRQ8# I, 5VT IBUF AE14 IRQ9 I, 5VT IBUF AE5 IRQ10 I, 5VT IBUF AE16 IRQ11 I, 5VT IBUF AF18 IRQ12 I, 5VT IBUF AF17 IRQ13 I, 5VT IBUF R23 IRQ14 I, 5VT IBUF AC17 IRQ15 I, 5VT IBUF AD17 ISACLK O1 6 m A A D 6 KBROMCS# O 4 mA AE4 LOCK# I/O, t/s, 5VT PCI C22 MEMCS16# I/O, OD, 5VT 8 mA AC15 MEMR# I/O (PU), 5VT 8 mA AE19 MEMW# I/O (PU), 5VT 8 mA AF20 NC -- -- AA3 NC -- -- AB1 NC -- -- AB2 NC -- -- AB3 NC -- -- AC1 NC -- -- AC2 NC -- -- AC3 NC -- -- AD1 NC -- -- AD2 NC -- -- AD3 NC -- -- AE1 NC -- -- AE2 NC -- -- AF1 NC -- -- AF2 NC -- -- D2 NC -- -- W2 NC -- -- Y3 OVER_CUR# I, 5VT IBUF W3 PA R I/O, t/s, 5VT PCI A21 PC_BEEP O4 m A V 3 PCICLK Is m t J 2 6 PCI_RST# O1 6 m A C 1 4 Signal Name Pin Type (Note 1) Buffer Type (Note 2) Pin No. Limited ISA Mode ISA Master Mode Table 2-3. 352 TBGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)

www.national.com 20 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530PCLK Is m t A 1 3 PERR# I/O, t/s, 5VT PCI B22 PIXEL0 II B U F A 1 PIXEL1 II B U F A 2 PIXEL2 II B U F A 3 PIXEL3 II B U F C 4 PIXEL4 II B U F B 3 PIXEL5 II B U F B 4 PIXEL6 II B U F D 5 PIXEL7 II B U F A 4 PIXEL8 II B U F B 6 PIXEL9 II B U F D 6 PIXEL10 II B U F A 5 PIXEL11 II B U F C 5 PIXEL12 II B U F A 7 PIXEL13 II B U F D 7 PIXEL14 II B U F C 7 PIXEL15 II B U F B 8 PIXEL16 II B U F A 8 PIXEL17 II B U F C 8 PIXEL18 II B U F B 9 PIXEL19 II B U F A 9 PIXEL20 II B U F D 9 PIXEL21 II B U F C 9 PIXEL22 II B U F B 1 1 PIXEL23 II B U F C 1 0 PLLAGD I, Analog -- N25 PLLAGS I, Analog -- N24 PLLDGN I, Analog -- N26 PLLDVD I, Analog -- M23 PLLLP I, Analog -- N23 PLLRO I, Analog -- M26 PLLVAA I, Analog -- M25 POR# II B U F K 2 4 POWER_EN O4 m A V 4 PSERIAL II B U F L 2 6 REQ# O, 5VT PCI J25 SA0/SD0 SD0 I/O (PU), 5VT 8 mA AE9 SA1/SD1 SD1 I/O (PU), 5VT 8 mA AE6 SA2/SD2 SD2 I/O (PU), 5VT 8 mA AD9 SA3/SD3 SD3 I/O (PU), 5VT 8 mA AC6 SA4/SD4 SD4 I/O (PU), 5VT 8 mA AF6 SA5/SD5 SD5 I/O (PU), 5VT 8 mA AD5 SA6/SD6 SD6 I/O (PU), 5VT 8 mA AF5 SA7/SD7 SD7 I/O (PU), 5VT 8 mA AF4 SA8/SD8 SD8 I/O (PU), 5VT 8 mA AF19 SA9/SD9 SD9 I/O (PU), 5VT 8 mA AD19 SA10/SD10 SD10 I/O (PU), 5VT 8 mA AC20 SA11/SD11 SD11 I/O (PU), 5VT 8 mA AF21 SA12/SD12 SD12 I/O (PU), 5VT 8 mA AE21 SA13/SD13 SD13 I/O (PU), 5VT 8 mA AE22 Signal Name Pin Type (Note 1) Buffer Type (Note 2) Pin No. Limited ISA Mode ISA Master Mode SA14/SD14 SD14 I/O (PU), 5VT 8 mA AD24 SA15/SD15 SD15 I/O (PU), 5VT 8 mA AE25 SA16 I/O (PU), 5VT 8 mA AD11 SA17 I/O (PU), 5VT 8 mA AF12 SA18 I/O (PU), 5VT 8 mA AE11 SA19 I/O (PU), 5VT 8 mA AD10 SA_LATCH SA_DIR O4 m A A D 1 5 SBHE# I/O (PU), 5VT 8 mA AE17 SDATA_IN I, 5VT IBUF U4 SDATA_OUT O4 m A V 1 SERR# I/O, OD, 5VT PCI A22 SMEMR#/RTCALE O4 m A A D 4 SMEMW#/RTCCS# O4 m A A F 3 SMI# I/O 4 mA P25 STOP# I/O, t/s, 5VT PCI E26 SUSP# O4 m A K 2 6 SUSPA# II B U F L 2 5 SUSP_3V I/O 4 mA L24 SYNC O4 m A U 3 TC O8 m A A F 1 5 TEST II B U F D 3 TRDY# I/O, t/s, 5VT PCI B23 TVCLK I, 5VT 4 mA B2 USBCLK Is m t W 1 VDD PWR -- D10 VDD PWR -- D17 VDD PWR -- AB4 VDD PWR -- AC10 VDD PWR -- AC19 VDD PWR -- AD16 VDD PWR -- AD23 VDD PWR -- C19 VDD PWR -- C24 VDD PWR -- C3 VDD PWR -- D21 VDD PWR -- F24 VDD PWR -- F4 VDD PWR -- H24 VDD PWR -- L23 VDD PWR -- L4 VDD PWR -- T23 VDD PWR -- U2 VDD PWR -- Y23 VID_CLK Is m t A 6 VID_DATA0 II B U F A 1 1 VID_DATA1 II B U F C 1 3 VID_DATA2 II B U F B 1 3 VID_DATA3 II B U F C 1 1 VID_DATA4 II B U F D 1 1 VID_DATA5 II B U F A 1 2 VID_DATA6 II B U F B 1 2 Signal Name Pin Type (Note 1) Buffer Type (Note 2) Pin No. Limited ISA Mode ISA Master Mode Table 2-3. 352 TBGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)

Revision 4.1 21 www.national.com Signal Definitions(Continued) Geode™ CS5530 Notes:1) See Table 2-1 on page 13 for pin type definitions. 2) See Table 5-6 "DC Characteristics (at Recommended Operating Conditions)" on page 228 for more informa- tion. IBUF refers to input buffer. VID_DATA7 II B U F C 1 2 VID_RDY O8 m A B 1 0 VID_VAL II B U F B 7 VREF I, Analog -- T1 VSS GND -- D12 VSS GND -- D13 VSS GND -- D16 VSS GND -- AA23 VSS GND -- AA4 VSS GND -- AC12 VSS GND -- AC13 VSS GND -- AC16 VSS GND -- AC18 VSS GND -- AC23 VSS GND -- AC4 VSS GND -- AC5 VSS GND -- AC9 VSS GND -- AD20 VSS GND -- C18 VSS GND -- C21 VSS GND -- D19 VSS GND -- D20 VSS GND -- D22 VSS GND -- D23 VSS GND -- D4 VSS GND -- D8 VSS GND -- E23 VSS GND -- E4 VSS GND -- F23 VSS GND -- G23 Signal Name Pin Type (Note 1) Buffer Type (Note 2) Pin No. Limited ISA Mode ISA Master Mode VSS GND -- H23 VSS GND -- H4 VSS GND -- J23 VSS GND -- K23 VSS GND -- K4 VSS GND -- M24 VSS GND -- M3 VSS GND -- N3 VSS GND -- P23 VSS GND -- V23 VSS GND -- W23 VSS GND -- W4 VSS GND -- Y4 VSYNC II B U F B 5 VSYNC_OUT O1 6 m A N 2 ZEROWS# I, 5VT IBUF AF10 Signal Name Pin Type (Note 1) Buffer Type (Note 2) Pin No. Limited ISA Mode ISA Master Mode Table 2-3. 352 TBGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)

www.national.com 22 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530

2.2 SIGNAL DESCRIPTIONS

2.2.1 Reset Interface

No. Type Description PCI_RST# C14 O PCI Reset PCI_RST# resets the PCI bus and is asserted while POR# is asserted, and for approximately 9 ms following the deassertion of POR#. POR# K24 I smt Power On Reset POR# is the system reset signal generated from the power supply to indi- cate that the system should be reset. CPU_RST K25 O CPU Reset CPU_RST resets the CPU and is asserted while POR# is asserted, and for approximately 9 ms following the deassertion of POR#.

2.2.2 Clock Interface

No. Type Description PCICLK J26 I PCI Clock The PCI clock is used to drive most circuitry of the CS5530. TVCLK B2 I 5VT Television Clock The TVCLK is an input from a digital NTSC/PAL converter which is option- ally re-driven back out onto the DCLK signal under software program con- trol. This is only used if interfacing to a compatible digital NTSC/PAL encoder device. DCLK A10 O DOT Clock DOT clock is generated by the CS5530 and typically connects to the pro- cessor to create the video pixel clock. The minimum frequency of DCLK is 10 MHz and the maximum is 200 MHz. ISACLK AD6 O ISA Bus Clock ISACLK is derived from PCICLK and is typically programmed for approxi- mately 8 MHz. F0 Index 50h[2:0] is used to program the ISA clock divisor. CLK_14MHZ P24 I 14.31818 MHz Clock DOT clock (DCLK) is derived from this clock. USBCLK W1 I USBCLK This input is used as the clock source for the USB. In this mode, a 48 MHz clock source input is required. CLK_32K AE3 I/O 5VT 32KHz Clock CLK_32K is a 32.768 KHz clock used to generate reset signals, as well as to maintain power management functionality. It should be active when power is applied to the CS5530. CLK_32K can be an input or an output. As an output CLK_32K is inter- nally derived from CLK_14MHZ. F0 Index 44h[5:4] are used to program this pin.

Revision 4.1 23 www.national.com Signal Definitions(Continued) Geode™ CS5530

2.2.3 CPU Interface

No. Type Description INTR P26 Strap Option Pin O CPU Interrupt Request INTR is the level output from the integrated 8259 PICs and is asserted if an unmasked interrupt request (IRQn) is sampled active. I S t r a pO p t i o nS e l e c tP i n Pin P26 is a strap option select pin. It is used to select whether the CS5530 operates in Limited ISA or ISA Master mode. ISA Limited Mode—Strap pin P26 low through a 10-kohm resistor. ISA Master Mode—Strap pin P26 high through a 10-kohm resistor. SMI# P25 I/O System Management Interrupt SMI# is a level-sensitive interrupt to the CPU that can be configured to assert on a number of different system events. After an SMI# assertion, System Management Mode (SMM) is entered, and program execution begins at the base of SMM address space. Once asserted, SMI# remains active until all SMI sources are cleared. IRQ13 R23 I 5VT IRQ13 IRQ13 is an input from the processor indicating that a floating point error was detected and that INTR should be asserted. PSERIAL L26 I Power Management Serial Interface PSERIAL is the unidirectional serial data link between the GXLV proces- sor and the CS5530. An 8-bit serial data packet carries status on power management events within the CPU. Data is clocked synchronous to the PCICLK input clock. SUSP# K26 O CPU Suspend SUSP# asserted requests that the processor enter Suspend mode and assert SUSPA# after completion. The SUSP# pin is deasserted after detecting any Speedup or Resume event. If the SUSP#/SUSPA# hand- shake is configured as a system 3 Volt Suspend, the deassertion of SUSP# is delayed to allow the system clock chip and the processor to sta- bilize. The SUSP#/SUSPA# handshake occurs as a result of a write to the Sus- pend Notebook Command Register (F0 Index AFh), or an expiration of the Suspend Modulation OFF Count Register (F0 Index 94h) when Suspend Modulation is enabled. Suspend Modulation is enabled via F0 Index 96h[0]. SUSPA# L25 I CPU Suspend Acknowledge SUSPA# is a level input from the processor. When asserted it indicates the CPU is in Suspend mode as a result of SUSP# assertion or execution of a HALT instruction.

www.national.com 24 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530SUSP_3V L24 I/O Suspend 3 Volt Active SUSP_3V can be connected to the output enable (OE) of a clock synthe- sis or buffer chip to stop the clocks to the system. SUSP_3V is asserted on any write to Suspend Notebook Command Register (F0 Index AFh) with bit 0 set in the Clock Stop Control Register (F0 Index BCh). SUSP_3V is only asserted after the SUSP#/SUSPA# handshake. As an input, SUSP_3V is sampled during power-on-reset to determine the inactive state. This allows the system designer to match the active state of SUSP_3V to the inactive state for a clock driver output enabled with a pull- up/down 10-kohm resistor. If pulled down, SUSP_3V is active high. If pulled up, SUSP_3V is active low.

2.2.3 CPU Interface (Continued)

No. Type Description

2.2.4 PCI Interface

No. Type Description AD[31:0] Refer toT able 2-3 I/O t/s 5VT PCI Address/Data AD[31:0] is a physical address during the first clock of a PCI transaction; it is the data during subsequent clocks. When the CS5530 is a PCI master, AD[31:0] are outputs during the address and write data phases, and are inputs during the read data phase of a transaction. When the CS5530 is a PCI slave, AD[31:0] are inputs during the address and write data phases, and are outputs during the read data phase of a transaction. C/BE[3:0]# D26, A24, B21, B18 I/O t/s 5VT PCI Bus Command and Byte Enables During the address phase of a PCI transaction, C/BE[3:0]# defines the bus command. During the data phase of a transaction, C/BE[3:0]# are the data byte enables. C/BE[3:0]# are outputs when the CS5530 is a PCI master and are inputs when it is a PCI slave. INT A#, INTB#, INTC#, INTD# A14, D15, C15, B14 I 5VT PCI Interrupt Pins The CS5530 provides inputs for the optional “level-sensitive” PCI inter- rupts (also known in industry terms as PIRQx#). These interrupts may be mapped to IRQs of the internal 8259s using PCI Interrupt Steering Regis- ters 1 and 2 (F0 Index 5Ch and 5Dh). The USB controller uses INTA# as its output signal. Refer to PCIUSB Index 3Dh. REQ# J25 O 5VT PCI Bus Request The CS5530 asserts REQ# in response to a DMA request or ISA master request to gain ownership of the PCI bus. The REQ# and GNT# signals a r eu s e dt oa r b i t r a t ef o rt h eP C Ib u s . REQ# should connect to the REQ0# of the GXLV processor and function as the highest-priority PCI master.

Revision 4.1 25 www.national.com Signal Definitions(Continued) Geode™ CS5530 GNT# D24 I 5VT PCI Bus Grant GNT# is asserted by an arbiter that indicates to the CS5530 that access to the PCI bus has been granted. GNT# should connect to GNT0# of the GXLV processor and function as the highest-priority PCI master. HOLD_REQ# H26 Strap Option Pin O PCI Bus Hold Request This pin’s function as HOLD_REQ# is no longer applicable. I 5VT S t r a pO p t i o nS e l e c tP i n Pin H26 is a strap option select pin. It allows selection of which address b i t sa r eu s e da st h eI D S E L . Strap pin H26 low: IDSEL = AD28 (Chipset Register Space) and AD29 (USB Register Space) Strap pin H26 high: IDSEL = AD26 (Chipset Register Space) and AD27 (USB Register Space) FRAME# C23 I/O t/s 5VT PCI Cycle Frame FRAME# is asserted to indicate the start and duration of a transaction. It is deasserted on the final data phase. FRAME# is an input when the CS5530 is a PCI slave. IRDY# B24 I/O t/s 5VT PCI Initiator Ready IRDY# is driven by the master to indicate valid data on a write transaction, or that it is ready to receive data on a read transaction. When the CS5530 is a PCI slave, IRDY# is an input that can delay the beginning of a write transaction or the completion of a read transaction. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. TRDY# B23 I/O t/s 5VT PCI Target Ready TRDY# is asserted by a PCI slave to indicate it is ready to complete the current data transfer. TRDY# is an input that indicates a PCI slave has driven valid data on a read or a PCI slave is ready to accept data from the CS5530 on a write. TRDY# is an output that indicates the CS5530 has placed valid data on AD[31:0] during a read or is ready to accept the data from a PCI master on a write. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. STOP# E26 I/O t/s 5VT PCI Stop As an input, STOP# indicates that a PCI slave wants to terminate the cur- rent transfer. The transfer will either be aborted or retried. STOP# is also used to end a burst. As an output, STOP# is asserted with TRDY# to indicate a target discon- nect, or without TRDY# to indicate a target retry. The CS5530 will assert STOP# during any cache line crossings if in single transfer DMA mode or if busy.

2.2.4 PCI Interface (Continued)

No. Type Description

www.national.com 26 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530LOCK# C22 I/O t/s 5VT PCI Lock LOCK# indicates an atomic operation that may require multiple transac- tions to complete. If the CS5530 is currently the target of a LOCKed transaction, any other PCI master request with the CS5530 as the target is forced to retry the transfer. The CS5530 does not generate LOCKed transactions. DEVSEL# A23 I/O t/s 5VT PCI Device Select DEVSEL# is asserted by a PCI slave, to indicate to a PCI master and sub- tractive decoder that it is the target of the current transaction. As an input, DEVSEL# indicates a PCI slave has responded to the current address. As an output, DEVSEL# is asserted one cycle after the assertion of FRAME# and remains asserted to the end of a transaction as the result of a positive decode. DEVSEL# is asserted four cycles after the assertion of FRAME# if DEVSEL# has not been asserted by another PCI device when the CS5530 is programmed to be the subtractive decode agent. The sub- tractive decode sample point is configured in F0 Index 41h[2:1]. Subtrac- tive decode cycles are passed to the ISA bus. PAR A21 I/O t/s 5VT PCI Parity PAR is the parity signal driven to maintain even parity across AD[31:0] and C/BE[3:0]#. The CS5530 drives PAR one clock after the address phase and one clock after each completed data phase of write transactions as a PCI master. It also drives PAR one clock after each completed data phase of read trans- actions as a PCI slave. PERR# B22 I/O t/s 5VT PCI Parity Error PERR# is pulsed by a PCI device to indicate that a parity error was detected. If a parity error was detected, PERR# is asserted by a PCI slave during a write data phase and by a PCI master during a read data phase. When the CS5530 is a PCI master, PERR# is an output during read trans- fers and an input during write transfers. When the CS5530 is a PCI slave, PERR# is an input during read transfers and an output during write trans- fers. Parity detection is enabled through F0 Index 04h[6]. An NMI is generated if I/O Port 061h[2] is set. PERR# can assert SERR# if F0 Index 41h[5] is set. SERR# A22 I/O OD 5VT PCI System Error SERR# is pulsed by a PCI device to indicate an address parity error, data parity error on a special cycle command, or other fatal system errors. SERR# is an open-drain output reporting an error condition, and an input indicating that the CS5530 should generate an NMI. As an input, SERR# is asserted for a single clock by the slave reporting the error. System error detection is enabled with F0 Index 04h[8]. An NMI is gener- ated if I/O Port 061h[2] is set. PERR# can assert SERR# if F0 Index 41h[5] is set. No. Type Description

Revision 4.1 27 www.national.com Signal Definitions(Continued) Geode™ CS5530

2.2.5 ISA Bus Interface

No. Type Description SA_LATCH/ SA_DIR AD15 O Limited ISA Mode: System Address Latch This signal is used to latch the destination address, which is multiplexed on bits [15:0] of the SA/SD bus. ISA Master Mode: System Address Direction Controls the direction of the external 5.0V tolerant transceiver on bits [15:0] of the SA bus. When low, the SA bus is driven out. When high, the SA bus is driven into the CS5530 by the external transceiver. SA_OE#/ FP_DATA16 H3 O Limited ISA Mode: Flat Panel Data Port Line 16 Refer to Section 2.2.11 “Display Interface” on page 34 for this signal’s def- inition. O ISA Master Mode: System Address Transceiver Output Enable Enables the external transceiver on bits [15:0] of the SA bus. MASTER#/ FP_DATA17 F3 O Limited ISA Mode: Flat Panel Data Port Line 17 Refer to Section 2.2.11 “Display Interface” on page 34 for this signal’s def- inition. I ISA Master Mode: Master The MASTER# input asserted indicates an ISA bus master is driving the ISA bus. SA23/GPIO7 AF23 I/O 5VT Limited ISA Mode: System Address Bus Lines 23 through 20 or General Purpose I/Os 7 through 4 These pins can function either as the upper four bits of the SA bus or as general purpose I/Os. Programming is done through F0 Index 43h, bits 6 and 2. Refer to Section 2.2.9 “Game Port and General Purpose I/O Interface” on page 32 for further details when used as GPIOs. SA22/GPIO6 AE23 SA21/GPIO5 AC21 SA20/GPIO4 AD22 ISA Master Mode: System Address Bus Lines 23 through 20 The pins function only as the four MSB (most significant bits) of the SA bus. SA[19:16] AD10, AE11, AF12, AD11 I/O PU 5VT System Address Bus Lines 19 through 16 Refer to SA[15:0] signal description. SA[15:0]/SD[15:0] Refer to Table 2-3 I/O PU 5VT Limited ISA Mode: System Address Bus / System Data Bus This bus carries both the addresses and data for all ISA cycles. Initially, the address is placed on the bus and then SA_LATCH is asserted for external latches to latch the address. At some time later, the data is put on the bus, for a read, or the bus direction is changed to an input, for a write. Pins designated as SA/SD[15:0] are internally connected to a 20-kohm pull-up resistor. ISA Master Mode: System Data Bus These pins perform only as SD[15:0] and pins FP_DATA[15:0] take on the functions of SA[15:0]. Pins designated as SA/SD[15:0] are internally connected to a 20-kohm pull-up resistor.

www.national.com 28 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530SMEMW#/ FP_HSYNC_OUT E1 O Limited ISA Mode: Flat Panel Horizontal Sync Output Refer to Section 2.2.11 “Display Interface” on page 34 for this signal’s def- inition. Note that if Limited ISA Mode of operation is selected, SMEMW# is avail- able on pin AF3 (multiplexed with RTCCS#). ISA Master Mode: System Memory Write SMEMW# is asserted for any memory write accesses below 1 MB. It enables 8-bit memory slaves to decode the memory address on SA[19:0]. SMEMR#/ FP_VSYNC_OUT E3 O Limited ISA Mode: Flat Panel Vertical Sync Output Refer to Section 2.2.11 “Display Interface” on page 34 for this signal’s def- inition. Note that if Limited ISA Mode of operation is selected, SMEMR# is avail- able on pin AD4 (multiplexed with RTCALE). ISA Master Mode: System Memory Read SMEMR# is asserted for memory read accesses below 1 MB. It enables 8-bit memory slaves to decode the memory address on SA[19:0]. SMEMW#/ RTCCS# AF3 O System Memory Write / Real-Time Clock Chip Select If Limited ISA Mode of operation has been selected, then SMEMW# can be output on this pin. SMEMW# is asserted for any memory write accesses below 1 MB. It enables 8-bit memory slaves to decode the memory address on SA[19:0]. RTCCS# is a chip select to an external real-time clock chip. This signal is activated on reads or writes to I/O Port 071h Function selection is made through F0 Index 53h[2]: 0 = SMEMW#, 1=R T C C S # . SMEMR#/ RTCALE AD4 O System Memory Read / Real-Time Clock Address Latch Enable If Limited ISA Mode of operation has been selected, then SMEMR# can be output on this pin. SMEMR# is asserted for memory read accesses below 1 MB. It enables 8-bit memory slaves to decode the memory address on SA[19:0]. RTCALE is a signal telling an external real-time clock chip to latch the address, which is on the SD bus. Function selection is made through F0 Index 53h[2]: 0 = SMEMR#, 1=R T C A L E . SBHE# AE17 I/O PU 5VT System Bus High Enable The CS5530 or ISA master asserts SBHE# to indicate that SD[15:8] will be used to transfer a byte at an odd address. SBHE# is an output during non-ISA master DMA operations. It is driven as the inversion of AD0 during 8-bit DMA cycles. It is forced low for all 16- bit DMA cycles. SBHE# is an input during ISA master operations. This pin is internally connected to a 20-kohm pull-up resistor. BALE AF9 O Buffered Address Latch Enable BALE indicates when SA[23:0] and SBHE# are valid and may be latched. For DMA transfers, BALE remains asserted until the transfer is complete.

2.2.5 ISA Bus Interface (Continued)

No. Type Description

Revision 4.1 29 www.national.com Signal Definitions(Continued) Geode™ CS5530 IOCHRDY AF11 I/O OD 5VT I/O Channel Ready IOCHRDY deasserted indicates that an ISA slave requires additional wait states. When the CS5530 is an ISA slave, IOCHRDY is an output indicating addi- tional wait states are required. ZEROWS# AF10 I 5VT Zero Wait States ZEROWS# asserted indicates that an ISA 8- or 16-bit memory slave can shorten the current cycle. The CS5530 samples this signal in the phase after BALE is asserted. If asserted, it shortens 8-bit cycles to three ISACLKs and 16-bit cycles to two ISACLKs. IOCS16# AF16 I 5VT I/O Chip Select 16 IOCS16# is asserted by 16-bit ISA I/O devices based on an asynchronous decode of SA[15:0] to indicate that SD[15:0] will be used to transfer data. Note: 8-bit ISA I/O devices only use SD[7:0]. IOR# AE12 I/O PU 5VT I/O Read IOR# is asserted to request an ISA I/O slave to drive data onto the data bus. This pin is internally connected to a 20-kohm pull-up resistor. IOW# AC11 I/O PU 5VT I/O Write IOW# is asserted to request an ISA I/O slave to accept data from the data bus. This pin is internally connected to a 20-kohm pull-up resistor. MEMCS16# AC15 I/O OD 5VT Memory Chip Select 16 MEMCS16# is asserted by 16-bit ISA memory devices based on an asyn- chronous decode of SA[23:17] to indicate that SD[15:0] will be used to transfer data. Note: 8-bit ISA memory devices only use SD[7:0]. MEMR# AE19 I/O PU 5VT Memory Read MEMR# is asserted for any memory read accesses. It enables 16-bit memory slaves to decode the memory address on SA[23:0]. This pin is internally connected to a 20-kohm pull-up resistor. MEMW# AF20 I/O PU 5VT Memory Write MEMW# is asserted for any memory write accesses. It enables 16-bit memory slaves to decode the memory address on SA[23:0]. This pin is internally connected to a 20-kohm pull-up resistor. AEN AE8 O Address Enable AEN asserted indicates that a DMA transfer is in progress, informing I/O devices to ignore the I/O cycle. [7:3], 1 Refer to Table 2-3 I 5VT ISA Bus Interrupt Request IRQ inputs indicate ISA devices or other devices requesting a CPU inter- rupt service. IRQ8# AE14 I 5VT Real-Time Clock Interrupt IRQ8# is the (active-low) interrupt that can come from the external RTC chip and indicates a date/time update has completed. No. Type Description

www.national.com 30 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530DRQ[7:5], DRQ[3:0] Refer to Table 2-3 I 5VT DMA Request - Channels [7:5], [3:0] DRQ inputs are asserted by ISA DMA devices to request a DMA transfer. The request must remain asserted until the corresponding DACK is asserted. DACK[7:5]#, DACK[3:0]# Refer to Table 2-3 O DMA Acknowledge - Channels [7:5], [3:0] DACK outputs are asserted to indicate when a DRQ is granted and the start of a DMA cycle. TC AF15 O Terminal Count TC signals the final data transfer of a DMA transfer. No. Type Description

2.2.6 ROM Interface

No. Type Description KBROMCS# AE4 O Keyboard/ROM Chip Select KBROMCS# is the enable pin for the BIOS ROM and for the keyboard controller. For ROM accesses, KBROMCS# is asserted for ISA memory accesses programmed at F0 Index 52h[2:0]. For keyboard controller accesses, KBROMCS# is asserted for I/O accesses to I/O Ports 060h, 062h, 064h, and 066h.

Revision 4.1 31 www.national.com Signal Definitions(Continued) Geode™ CS5530

2.2.7 IDE Interface

No. Type Description IDE_RST# W25 O IDE Reset This signal resets all the devices that are attached to the IDE interface. IDE_ADDR[2:0] W24, U26, U25 O IDE Address Bits These address bits are used to access a register or data port in a device on the IDE bus. IDE_DATA[15:0] Refer to Table 2-3 I/O 5VT IDE Data Lines IDE_DATA[15:0] transfers data to/from the IDE devices. IDE_IOR0# R26 O IDE I/O Read for Channels 0 and 1 IDE_IOR0# is the read signal for Channel 0, and IDE_IOR1# is the read signal for Channel 1. Each signal is asserted on read accesses to the cor- responding IDE port addresses. When in Ultra DMA/33 mode, these signals are redefined: Read Cycle — DMARDY0# and DMARDY1# Write Cycle — STROBE0 and STROBE1 IDE_IOR1# R25 O IDE_IOW0# R24 O IDE I/O Write for Channels 0 and 1 IDE_IOW0# is the write signal for Channel 0, and IDE_IOW1# is the read signal for Channel 1. Each signal is asserted on write accesses to corre- sponding the IDE port addresses. When in Ultra DMA/33 mode, these signals are redefined: Read Cycle — STOP0 and STOP1 W r i t eC y c l e—S T O P 0a n dS T O P 1 IDE_IOW1# T25 O IDE_CS0# V26 O IDE Chip Selects The chip select signals are used to select the command block registers in an IDE device. IDE_CS1# Y26 O IDE_IORDY0 AD25 I 5VT I/O Ready Channels 0 and 1 When deasserted, these signals extend the transfer cycle of any host reg- ister access when the device is not ready to respond to the data transfer request. When in Ultra DMA/33 mode, these signals are redefined: Read Cycle — STROBE0 and STROBE1 W r i t eC y c l e—D M A R D Y 0 #a n dD M A R D Y 1 # IDE_IORDY1 AE26 I 5VT IDE_DREQ0 AD26 I 5VT DMA Request Channels 0 and 1 The DREQ is used to request a DMA transfer from the CS5530. The direction of the transfers are determined by the IDE_IOR/IOW signals.IDE_DREQ1 AC24 I 5VT IDE_DACK0# T26 O DMA Acknowledge Channels 0 and 1 The DACK# acknowledges the DREQ request to initiate DMA transfers.IDE_DACK1# T24 O

www.national.com 32 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530

2.2.8 USB Interface

No. Type Description POWER_EN V4 O Power Enable This pin enables the power to a self-powered USB hub. OVER_CUR# W3 I 5VT Over Current This pin indicates the USB hub has detected an overcurrent on the USB. D+_PORT1 Y2 I/O USB Port 1 Data Positive This pin is the Universal Serial Bus Data Positive for port 1. D–_PORT1 Y1 I/O USB Port 1 Data Minus This pin is the Universal Serial Bus Data Minus for port 1. D+_PORT2 AA2 I/O USB Port 2 Data Positive This pin is the Universal Serial Bus Data Positive for port 2. D–_PORT2 AA1 I/O USB Port 2 Data Minus This pin is the Universal Serial Bus Data Minus for port 2.

2.2.9 Game Port and General Purpose I/O Interface

No. Type Description GPORT_CS# AD21 O Game Port Chip Select GPORT_CS# is asserted upon any I/O reads or I/O writes to I/O Port 200h and 201h. GPCS# AF26 O General Purpose Chip Select GPCS# is asserted upon any I/O access that matches the I/O address in the General Purpose Chip Select Base Address Register (F0 Index 70h) and the conditions set in the General Purpose Chip Select Control Regis- ter (F0 Index 72h). GPIO7/SA23 AF23 I/O 5VT Limited ISA Mode: General Purpose I/Os 7 through 4 or System Address Bus Lines 23 through 20 These pins can function either as general purpose I/Os or as the upper four bits of the SA bus. Selection is done through F0 Index 43h[6,2]. Refer to GPIO[3:2] signal description for GPIO function description. GPIO6/SA22 AE23 GPIO5/SA21 AC21 GPIO4/SA20 AD22 ISA Master Mode: System Address Bus Lines 23 through 20 These pins function as the four MSB (most significant bits) of the SA bus. GPIO3 AF24 I/O 5VT General Purpose I/Os 3 and 2 GPIOs can be programmed to operate as inputs or outputs via F0 Index 90h. As an input, the GPIO can be configured to generate an external SMI. Additional configuration can select if the SMI# is generated on the rising or falling edge. GPIO external SMI generation/edge selection is done in F0 Index 92h and 97h. GPIO2 AF25 I/O 5VT

Revision 4.1 33 www.national.com Signal Definitions(Continued) Geode™ CS5530 GPIO1/ SDATA_IN2 AE24 I/O 5VT General Purpose I/O 1 or Serial Data Input 2 This pin can function either as a general purpose I/O or as a second serial data input pin if two codecs are used in the system. In order for this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0). Then setting F3BAR+Memory Offset 08h[21] = 1 selects the pin to function as SDATA_IN2. Refer to GPIO[3:2] signal description for GPIO function description. GPIO0 AC22 I/O 5VT General Purpose I/O 0 Refer to GPIO[3:2] signal description for GPIO function description.

2.2.9 Game Port and General Purpose I/O Interface (Continued)

No. Type Description

2.2.10 Audio Interface

No. Type Description BIT_CLK V2 I 5VT Audio Bit Clock The serial bit clock from the codec. SDATA_OUT V1 O Serial Data I/O This output transmits audio serial data to the codec. SDATA_IN U4 I 5VT Serial Data Input This input receives serial data from the codec. SYNC U3 O Serial Bus Synchronization This bit is asserted to synchronize the transfer of data between the CS5530 and the AC97 codec PC_BEEP V3 O PC Beep Legacy PC/AT speaker output.

www.national.com 34 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530

2.2.11 Display Interface

No. Type Description Pixel Port PCLK A13 I Pixel Clock This clock is used to sample data on the PIXEL input port. It runs at the graphics DOT clock (DCLK) rate. PIXEL[23:0] Refer to Table 2-3 I Pixel Data Port This is the input pixel data from the processor’s display controller. If F4BAR+Memory Offset 00h[29] is reset, the data is sent in RGB 8:8:8 for- mat. Otherwise, the pixel data is sent in RGB 5:6:5 format which has been dithered by the processor. The other eight bits are used in conjunction with VID_DATA[7:0] to provide 16-bit video data. This bus is sampled by the PCLK input. ENA_DISP B1 I Display Enable Input This signal qualifies active data on the pixel input port. It is used to qualify active pixel data for all display modes and configurations and is not spe- cific to flat panel display. Display CRT HSYNC C6 I Horizontal Sync Input This is the CRT horizontal sync input from the processor’s display control- ler. It is used to indicate the start of a new video line. This signal is pipe- lined for the appropriate number of clock stages to remain in sync with the pixel data. A separate output (HSYNC_OUT) is provided to re-drive the CRT and flat panel interfaces. HSYNC_OUT N1 O Horizontal Sync Output This is the horizontal sync output to the CRT. It represents a delayed ver- sion of the input horizontal sync signal with the appropriate pipeline delay relative to the pixel data. The pipeline delay and polarity of this signal are programmable. VSYNC B5 I Vertical Sync Input This is the CRT vertical sync input from the processor’s display controller. It is used to indicate the start of a new frame. This signal is pipelined for the appropriate number of clock stages to remain in sync with the pixel data. A separate output (VSYNC_OUT) is provided to re-drive the CRT and flat panel interfaces. VSYNC_OUT N2 O Vertical Sync Output This is the vertical sync output to the CRT. It represents a delayed version of the input vertical sync signal with the appropriate pipeline delay relative to the pixel data. The pipeline delay and polarity of this signal are pro- grammable. DDC_SCL M2 O DDC Serial Clock This is the serial clock for the VESA Display Data Channel interface. It is used for monitor communications. The DDC2B standard is supported by this interface.

Revision 4.1 35 www.national.com Signal Definitions(Continued) Geode™ CS5530 DDC_SDA M4 I/O 5VT DDC Serial Data This is the bidirectional serial data signal for the VESA Display Data Channel interface. It is used to monitor communications. The DDC2B standard is supported by this interface. The direction of this pin can be configured through F4BAR+Memory Off- set 04h[24]: 0 = Input; 1 = Output. IREF (Video DAC) R3 I Analog VDAC Current Reference Input Connect a 732 ohm resistor between this pin and AVSS (analog ground for Video DAC). VREF (Video DAC) T1 I Analog VDAC Voltage Reference Output Unused DAC output. Connect a 0.1 µF capacitor between this pin and AVSS (analog ground for Video DAC). EXTVREFIN (Video DAC) T2 I Analog External Voltage Reference Pin When using an external voltage reference, connect this pin to a 1.235V voltage reference. AVDD1 (DAC) U1 I Analog Analog Power for Video DAC These pins provide power to the analog portions of the Video DAC.AVDD2 (VREF) T3 AVDD3 (DAC) N4 AVSS1 (DAC) R2 I Analog Analog Ground for Video DAC These pins provide the ground plane connections to the analog portions of the Video DAC. AVSS2 (ICAP) R4 AVSS3 (VREF) T4 AVSS4 (ICAP) P1 AVSS5 (DAC) P2 IOUTR (Video DAC) P3 O Analog Red DAC Output Red analog output. IOUTG (Video DAC) P4 O Analog Green DAC Output Green analog output. IOUTB (Video DAC) R1 O Analog Blue DAC Output Blue analog output. Display TFT/TV FP_DATA17/ MASTER# F3 O Limited ISA Mode: Flat Panel Data Port Line 17 Refer to FP_DATA[15:0] signal description. I ISA Master Mode: Master Refer to Section 2.2.5 “ISA Bus Interface” on page 27 for this signal’s def- inition. FP_DATA16/ SA_OE# H3 O Limited ISA Mode: Flat Panel Data Port Line 16 Refer to FP_DATA[15:0] signal description. O ISA Master Mode: System Address Transceiver Output Enable Refer to Section 2.2.5 “ISA Bus Interface” on page 27 for this signal’s def- inition.

2.2.11 Display Interface (Continued)

No. Type Description

www.national.com 36 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530FP_DATA[15:0]/ SA[15:0] Refer to Table 2-3 O Limited ISA Mode: Flat Panel Data Port Lines 15 through 0 This is the data port to an attached active matrix TFT panel. This port may optionally be tied to a DSTN formatter chip, LVDS transmitter, or digital NTSC/P AL encoder. F4BAR+Memory Offset 04h[7] enables the flat panel data bus: 0 = FP_DATA[17:0] is forced low 1 = FP_DATA[17:0] is driven based upon power sequence control I/O ISA Master Mode: System Address Bus Lines 15 through 0 These pins function as SA[15:0] and the pins designated as SA/SD[15:0] function only as SD[15:0]. Note that SA[19:16] are dedicated address pins and GPIO[7:4] function as SA[23:20] only. FP_CLK M1 O Limited ISA Mode: Flat Panel Clock This is the clock for the flat panel interface. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 cannot support TFT flat panels or TV controllers. FP_CLK_EVEN L3 O Limited ISA Mode: Flat Panel Even Clock This is an optional output clock for a set of external latches used to de- multiplex the flat panel data bus into two channels (odd/even). Typically t h i sw o u l db eu s e dt oi n t e r f a c et oap a i ro fL V D St r a n s m i t t e r sd r i v i n ga n XGA resolution flat panel. F4BAR+Memory Offset 04h[12] enables the FP_CLK_EVEN output: 0 = Standard flat panel 1 = XGA flat panel -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. FP_HSYNC C2 I Limited ISA Mode: Flat Panel Horizontal Sync Input This is the horizontal sync input reference from the processor’s display controller. The timing of this signal is independent of the standard (CRT) horizontal sync input to allow a different timing relationship between the flat panel and an attached CRT. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. FP_HSYNC_OUT /SMEMW# E1 O Limited ISA Mode: Flat Panel Horizontal Sync Output This is the horizontal sync for an attached active matrix TFT flat panel. This represents a delayed version of the input flat panel horizontal sync signal with the appropriate pipeline delay relative to the pixel data. ISA Master Mode: System Memory Write Refer to Section 2.2.5 “ISA Bus Interface” on page 28 for this signal’s def- inition. No. Type Description

Revision 4.1 37 www.national.com Signal Definitions(Continued) Geode™ CS5530 FP_VSYNC C1 I Limited ISA Mode: Flat Panel Vertical Sync Input This is the vertical sync input reference from the processor’s display con- troller. The timing of this signal is independent of the standard (CRT) verti- cal sync input to allow a different timing relationship between the flat panel a n da na t t a c h e dC R T . -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. FP_VSYNC_OUT /SMEMR# E3 O Limited ISA Mode: Flat Panel Vertical Sync Output This is the vertical sync for an attached active matrix TFT flat panel. This represents a delayed version of the input flat panel vertical sync signal with the appropriate pipeline delay relative to the pixel data. ISA Master Mode: System Memory Read Refer to Section 2.2.5 “ISA Bus Interface” on page 28 for this signal’s def- inition. FP_DISP_ ENA_OUT F2 O Flat Panel Display Enable Output This is the display enable for an attached active matrix TFT flat panel. This signal qualifies active pixel data on the flat panel interface. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. FP_ENA_VDD L2 O Flat Panel VDD Enable This is the enable signal for the VDD supply to an attached flat panel. It is under the control of power sequence control logic. A transition on bit 6 of the Display Configuration Register (F4BAR+Memory Offset 04h) initiates a power-up/down sequence. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. FP_ENA_BKL J4 O Flat Panel Backlight Enable Output This is the enable signal for the backlight power supply to an attached flat panel. It is under control of the power sequence control logic. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. Display MPEG VID_DATA[7:0] C12, B12, A12, D11, C11, B13, C13, A11 I Video Data Port This is the input data for a video (MPEG) or graphics overlay in its native form. For video overlay, this data is in an interleaved YUV 4:2:2 format. For graphics overlay, the data is in RGB 5:6:5 format. This port operates at the VID_CLK rate. No. Type Description

www.national.com 38 Revision 4.1 Signal Definitions(Continued) Geode™ CS5530VID_CLK A6 I Video Clock This is the clock for the video port. This clock is completely asynchronous to the input pixel clock rate. VID_VAL B7 I Video Valid This signal indicates that valid video data is being presented on the VID_DATA input port. If the VID_RDY signal is also asserted, the data will advance. VID_RDY B10 O Video Ready This signal indicates that the CS5530 is ready to receive the next piece of video data on the VID_DATA port. If the VID_VAL signal is also asserted, the data will advance. No. Type Description

2.2.12 DCLK PLL

No. Type Description PLLLP N23 I Analog Loop Filter Capacitor Connection The loop filter requires an external capacitor (optionally a series resistor may be added) for adjustment of the loop filter response. The PLLLP pin connects this capacitor to the on-chip loop filter. PLLRO M26 I Analog VCO Center Frequency Set Resistor Connection The center frequency of the VCO is set with an external resistor con- nected between the PLLRO and PLLAGS pins. This resistor sets a con- stant current that controls the center frequency of the VCO. PLLAGS N24 I Analog Analog Sense Pin for Connection of External Components This pin is used as the return connection for all external components. This includes the ground connection for the loop filter capacitor and the PLLRO resistor. PLLVAA M25 I Analog Analog PLL Power (VDD) PLLVAA is the analog positive rail power connection to the PLL. PLLAGD N25 I Analog Analog PLL Ground (VSS) PLLAGD is the analog ground rail connection to the PLL. PLLDVD M23 I Analog Digital PLL Power (VDD) This pin is the digital VDD power connection for the PLL. PLLDGN N26 I Analog Digital PLL Ground This pin is the digital ground (VSS) connection for the PLL.

Revision 4.1 39 www.national.com Signal Definitions(Continued) Geode™ CS5530

2.2.13 Power, Ground, and Reserved

No. Type Description VDD Refer to Table 2-3 (Total of 19) PWR 3.3V (nominal) Power Connection VSS Refer to Table 2-3 (Total of 39) GND Ground Connection NC Refer to Table 2-3 (Total of 17) -- No Connection This line should be left disconnected. Connecting it to a pull-up/-down resistor or to an active signal could cause unexpected results and pos- sible malfunctions.

2.2.14 Internal Test and Measurement

No. Type Description TEST D3 I Test Mode TEST should be tied low for normal operation.

www.national.com 40 Revision 4.1 Geode™ CS5530

3.0 Functional Description

The Geode CS5530 I/O companion provides many sup- port functions for the GXLV processor. This chapter dis- cusses the detailed operations of the CS5530 in two categories: system-level activities and operations/pro- gramming of the major functional blocks. The system-level discussion topics revolve around events that affect the device as a whole unit and as an interface with other chips (e.g., processor): T opics include:  Processor Interface - Display Subsystem Connections - PSERIAL Pin Interface P C I B u s I n t e r f a c e - PCI Initiator -P C I T a r g e t - Special Bus Cycles - Shutdown/Halt -P C I B u s P a r i t y - PCI Interrupt Routing Support - Delayed Transactions  Resets and Clocks -R e s e t s -I S A C l o c k -D O T C l o c k  Power Management - APM Support - CPU Power Management - Peripheral Power Management All of the major functional blocks interact with the proces- sor through the PCI bus, or via its own direct interface. The major functional blocks are divided out as:  PC/AT Compatibility Logic - ISA Bus Interface - ROM Interface - Megacells - I/O Port 092h and 061h System Control - Keyboard Interface Function - External Real-Time Clock Interface  IDE Controller - IDE Interface Signal - IDE Configuration Registers  XpressAUDIO - Data Transport Hardware - VSA Technology Support Hardware  Display Subsystem Extensions - Video Interface Configuration Registers - Video Accelerator - Video Overlay -G a m m a R A M - Display Interface U S B I n t e r f a c e - USB PCI Controller - USB Host Controller - USB Power Management Note that this Functional Description section of the data book describes many of the registers used for configura- tion of the CS5530; however, not all registers are reported in detail. Some tables in the following subsections show only the bits (not the entire register) associated with a specific function being discussed. For access, register, and bit information regarding all CS5530 registers refer to Section 4.0 “Register Descriptions” on page 137.

Revision 4.1 41 www.national.com Functional Description(Continued) Geode™ CS5530

3.1 PROCESSOR INTERFACE

The CS5530 interface to the GXLV processor consists of seven miscellaneous connections, the PCI bus interface signals, plus the display controller connections. Figure 3-1 shows the interface requirements. Note that the PC/AT legacy pins NMI, WM_RST, and A20M are all virtual func- tions executed in SMM (System Management Mode) by the BIOS.  PSERIAL is a one-way serial bus from the processor to the CS5530 used to communicate power-management states and VSYNC information for VGA emulation.  IRQ13 is an input from the processor indicating that a floating point error was detected and that INTR should be asserted.  INTR is the level output from the integrated 8259 PICs and is asserted if an unmasked interrupt request (IRQn) is sampled active.  SMI# is a level-sensitive interrupt to the processor that can be configured to assert on a number of different system events. After an SMI# assertion, SMM is entered and program execution begins at the base of the SMM address space. Once asserted, SMI# remains active until the SMI source is cleared.  SUSP# and SUSPA# are handshake pins for imple- menting CPU Clock Stop and clock throttling.  CPU_RST resets the CPU and is asserted for approxi- mately 9 ms after the negation of POR#.  PCI bus interface signals.  Display subsystem interface connections. Figure 3-1. Processor Signal Connections SERIALP IRQ13 SMI# INTR SUSP# SUSPA# AD[31:0] C/BE[3:0]# PAR FRAME# IRDY# TRDY# STOP# LOCK# DEVSEL# PERR# SERR# REQ0# PSERIAL IRQ13 SMI# CPU_RST INTR SUSP# SUSPA# AD[31:0] C/BE[3:0]# PAR FRAME# IRDY# TRDY# STOP# LOCK# DEVSEL# PERR# SERR# REQ# GNT# GNT0# Geode™ GXLVGeode™ CS5530 RESET PCLK CRT_HSYNC CRT_VSYNC PIXEL[17:0] FP_HSYNC FP_VSYNC ENA_DISP VID_VAL VID_CLK VID_DATA[7:0] VID_RDY PCLK HSYNC VSYNC PIXEL[23:0] FP_HSYNC FP_VSYNC ENA_DISP VID_VAL VID_CLK VID_DATA[7:0] VID_RDY DCLKDCLK I/O Companion Processor Note: Refer to Figure 3-3 for correct interconnection of PIXEL lines with the processor. Note

www.national.com 42 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.1.1 Display Subsystem Connections

When the GXLV processor is used in a system with the CS5530, the need for an external RAMDAC is eliminated. The CS5530 contains the DACs, a video accelerator engine, and the TFT interface. The CS5530 also supports both portable and desktop configurations. Figure 3-2 shows the signal connections for both types of systems. Figure 3-3 details how PIXEL[17:0] on the processor con- nects with PIXEL[23:0] of the CS5530. Figure 3-2. Portable/Desktop Display Subsystem Configurations DCLK PCLK FP_HSYNC FP_VSYNC ENA_DISP VID_RDY VID_CLK VID_DATA[7:0] PIXEL[17:12] PIXEL[11:6] HSYNC VSYNC R[5:0] G[5:0] B[5:0] CLK VDD 12VBKL Pin 13 Pin 14 Pin 3 Pin 2 Pin 1 Pwr Cntrl ENAB VGAPin 15 Pin 12 Geode™ CS5530 I/O Companion DCLK PCLK FP_HSYNC FP_VSYNC ENA_DISP VID_RDY VID_CLK VID_DATA[7:0] PIXEL[23:18]* PIXEL[15:10]* PIXEL[5:0] VID_VAL CRT_HSYNC CRT_VSYNC PIXEL[7:2]* VID_VAL HSYNC VSYNC FP_ENA_VDD FP_ENA_BKL FP_DISP_ENA_OUT FP_HSYNC_OUT FP_VSYNC_OUT FP_CLK FP_DATA[17:12] FP_DATA[11:6] FP_DATA[5:0] Logic HSYNC_OUT VSYNC_OUT IOUTR IOUTG IOUTB DDC_SCL DDC_SDA Note: *Connect PIXEL[17:16] PIXEL[9:8], and PIXEL[1:0] on the CS5530 to ground. See Figure 3-3. Port Portable Configuration TFT Flat R[5:0] G[5:0] B[5:0] HSYNC VSYNC CLK TV NTSC/PAL Encoder Panel Geode™ Processor GXLV

Revision 4.1 43 www.national.com Functional Description(Continued) Geode™ CS5530 Figure 3-3. PIXEL Signal Connections PIXEL17 PIXEL16 PIXEL15 PIXEL14 PIXEL13 PIXEL12 PIXEL11 PIXEL10 PIXEL9 PIXEL8 PIXEL7 PIXEL6 PIXEL5 PIXEL4 PIXEL3 PIXEL2 PIXEL1 Geode™ GXLV Processor Geode™ CS5530 I/O Companion PIXEL0 PIXEL23 PIXEL22 PIXEL21 PIXEL20 PIXEL19 PIXEL18 PIXEL17 PIXEL16 PIXEL15 PIXEL14 PIXEL13 PIXEL12 PIXEL11 PIXEL10 PIXEL9 PIXEL8 PIXEL7 PIXEL6 PIXEL5 PIXEL4 PIXEL3 PIXEL2 PIXEL1 PIXEL0

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3.1.2 PSERIAL Pin Interface

The majority of the system power management logic is implemented in the CS5530, but a minimal amount of logic is contained within the GXLV processor to provide information that is not externally visible (e.g., graphics controller). The processor implements a simple serial communica- tions mechanism to transmit the CPU status to the CS5530. The processor accumulates CPU events in an 8- bit register (defined in Table 3-1) which it transmits serially every 1 to 10 µs. The packet transmitter holds the serial output pin (PSE- RIAL) low until the transmission interval counter has elapsed. Once the counter has elapsed, the PSERIAL pin is held high for two clocks to indicate the start of packet transmission. The contents of the Serial Packet Register are then shifted out starting from bit 7 down to bit 0. The PSERIAL pin is held high for one clock to indicate the end of packet transmission and then remains low until the next transmission interval. After the packet transmission is complete, the processor’s Serial Packet Register’s con- tents are cleared. The processor’s input clock is used as the clock reference for the serial packet transmitter. Once a bit in the register is set, it remains set until the completion of the next packet transmission. Successive events of the same type that occur between packet trans- missions are ignored. Multiple unique events between packet transmissions accumulate in this register. The pro- cessor transmits the contents of the serial packet only when a bit in the Serial Packet Register is set and the interval counter has elapsed. For more information on the Serial Packet Register refer- enced in Table 3-1, refer to the GXLV processor data book. The CS5530 decodes the serial packet after each trans- mission and performs the power management tasks r e l a t e dt ov i d e or e t r a c e .

3.1.2.1 Video Retrace Interrupt

Bit 7 of the “Serial Packet” can be used to generate an SMI whenever a video retrace occurs within the proces- sor. This function is normally not used for power manage- ment but for SoftVGA routines. Setting F0 Index 83h[2] = 1 (bit details on page 159) enables this function. A read only status register located at F1BAR+Memory Offset 00h[5] (bit details on page 180) can be read to see if the SMI was caused by a video retrace event. Table 3-1. GXLV Processor Serial Packet Register Bit Description

7 Video IRQ:This bit indicates the occurrence of a video

vertical sync pulse. This bit is set at the same time that the VINT (Vertical Interrupt) bit gets set in the DC_TIMING_CFG register. The VINT bit has a corre- sponding enable bit (VIEN) in the DC_TIM_CFG regis- ter.

6 CPU Activity:This bit indicates the occurrence of a

level 1 cache miss that was not a result of an instruc- tion fetch. This bit has a corresponding enable bit in the PM_CNTL_TEN register. 5:2 Reserved

1 Programmable Address Decode: This bit indicates

the occurrence of a programmable memory address decode. The bit is set based on the values of the PM_BASE register and the PM_MASK register. The PM_BASE register can be initialized to any address in the full CPU address range.

0 Video Decode:This bit indicates that the CPU has

accessed either the display controller registers or the graphics memory region. This bit has a corresponding enable bit in the PM_CNTRL_TEN.

Revision 4.1 45 www.national.com Functional Description(Continued) Geode™ CS5530

3.2 PCI BUS INTERFACE

The PCI bus interface is compliant with the PCI Bus Spec- ification Rev. 2.1. The CS5530 acts as a PCI target for PCI cycles initiated by the processor or other PCI master devices, or as an ini- tiator for DMA, ISA, IDE, and audio master transfer cycles. It supports positive decode for memory and I/O regions and is the subtractive decode agent on the PCI bus. The CS5530 also generates address and data parity and per- forms parity checking. A PCI bus arbiter is not part of the CS5530; however, one is included in the GXLV processor. The PCI Command Register, located at F0 Index 04h (T able 3-2), provides the basic control over the CS5530’s ability to respond and perform PCI bus accesses.

3.2.1 PCI Initiator

The CS5530 acts as a PCI bus master on behalf of the DMA controller or ISA, IDE, and audio interfaces. The REQ# and GNT# signals are used to arbitrate for the PCI bus. Note: In a GXLV processor-based system, the REQ#/GNT# signals of the CS5530 should con- nect to the REQ0#/GNT0# of the processor. This configuration ensures that the CS5530 is treated as a non-preemptable PCI master by the proces- sor. T h eC S 5 5 3 0a s s e r t sR E Q #i nr e s p o n s et oab u sm a s t e r - ing or DMA request for ownership of the PCI bus. GNT# is asserted by the PCI arbiter (i.e., processor) to indicate that access to the PCI bus has been granted to the CS5530. The CS5530 then issues a grant to the DMA controller. This mechanism prevents any deadlock situa- tions across the bridge. Once granted the PCI bus, the ISA master or DMA transfer commences. If an ISA master executes an I/O access, that cycle remains on the ISA bus and is not forwarded to the PCI bus. The CS5530 performs only single transfers on the PCI bus for legacy DMA cycles. Table 3-2. PCI Command Register Bit Description F0 Index 04h-05h PCI Command Register (R/W) Reset Value = 0000h 15:10 Reserved: Set to 0. 9 Fast Back-to-Back Enable (Read Only):This function is not supported when the CS5530 is a master. It is always dis- abled (always reads 0). 8 SERR#: Allow SERR# assertion on detection of special errors: 0 = Disable(Default);1=E n a b l e . 7 Wait Cycle Control (Read Only):This function is not supported in the CS5530. It is always disabled (always reads 0). 6 Parity Error:Allow the CS5530 to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when a parity error is detected: 0 = Disable(Default); 1 = Enable. 5 VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530. It is always disabled (always reads 0). 4 Memory Write and Invalidate:Allow the CS5530 to do memory write and invalidate cycles, if the PCI Cache Line Regis- ter (F0 Index 0Ch) is set to 16 bytes (04h). 0 = Disable(Default); 1 = Enable. 3 Special Cycles:Allow the CS5530 to respond to special cycles: 0 = Disable; 1 = Enable(Default). This bit must be enabled to allow the CPU Warm Reset internal signal to be triggered from a CPU Shutdown cycle. 2 Bus Master: Allow the CS5530 bus mastering capabilities: 0 = Disable; 1 = Enable(Default). This bit must be set to 1.

1 Memory Space: Allow the CS5530 to respond to memory cycles from the PCI bus:

0 = Disable; 1 = Enable(Default). 0 I/O Space:Allow the CS5530 to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable(Default).

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3.2.2 PCI Target

The CS5530 positively decodes PCI transactions intended for any internal registers, the ROM address range, and several peripheral and user-defined address ranges. For positive-decoded transactions, the CS5530 is a medium responder. Table 3-3 lists the valid C/BE# encoding for PCI target transactions. The CS5530 acts as the subtractive agent in the system since it contains the ISA bridge functionality. Subtractive decoding ensures that all accesses not positively claimed by PCI devices are forwarded to the ISA bus. The subtrac- tive-decoding sample point can be configured as slow, default, or disabled via F0 Index 41h[2:1]. T able 3-4 shows these programming bits. Figure 3-4 shows the timing for subtractive decoding. Figure 3-4. Subtractive Decoding Timing Table 3-3. PCI Command Encoding C/BE[3:0]# Command Type

0000 Interrupt Acknowledge

0001 Special Cycles: Shutdown, AD[15:0] = 0000

Special Cycles: Halt, AD[15:0] = 0001

0010 I/O Read

0011 I/O Write

0110 Memory Read

0111 Memory Write

1010 Configuration Read

1011 Configuration Write

1100 Memory Read Multiple

(memory read only)

1101 Reserved

1110 Memory Read Line (memory read only)

1111 Memory Write, Invalidate (memory write)

Table 3-4. Subtractive Decoding Related Bits Bit Description F0 Index 41h PCI Function Control Register 2 (R/W) Reset Value = 10h 2:1 Subtractive Decode:These bits determine the point at which the CS5530 accepts cycles that are not claimed by another device. The CS5530 defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively. 00 = Default sample (4th clock from FRAME# active) 01 = Slow sample (3rd clock from FRAME# active) 1x = No subtractive decode PCI_CLK FRAME# IRDY# TRDY# DEVSEL# FAST MED SLOW SUB

Revision 4.1 47 www.national.com Functional Description(Continued) Geode™ CS5530

3.2.3 Special Bus Cycles–Shutdown/Halt

The PCI interface does not pass Special Bus Cycles to the ISA interface, since special cycles by definition have no destination. However, the PCI interface monitors the PCI bus for Shutdown and Halt Special Bus Cycles. Upon detection of a Shutdown Special Bus Cycle, a WM_RST SMI is generated after a delay of three PCI clock cycles. PCI Shutdown Special Cycles are detected when C/BE[3:0]# = 0001 during the address phase and AD[31:0] = xxxx0000h during the data phase. C/BE[3:0]# are also properly asserted during the data phase. Upon detection of a Halt Special Bus Cycle, the CS5530 completes the cycle by asserting TRDY#. PCI Halt Spe- cial Bus Cycles are detected when CBE[3:0]# = 0001 dur- ing the address phase and AD[31:0] = xxxx0001h during the data phase of a Halt cycle. CBE[3:0]# are also prop- erly asserted during the data phase.

3.2.4 PCI Bus Parity

When the CS5530 is the PCI initiator, it generates address parity for read and write cycles. It checks data parity for read cycles and it generates data parity for write cycles. The PAR signal is an even-parity bit that is calcu- lated across 36 bits of AD[31:0] plus C/BE[3:0]#. By default, the CS5530 does not report parity errors. How- ever, the CS5530 detects parity errors during the data phase if F0 Index 04h[6] is set to 1. If enabled and a data parity error is detected, the CS5530 asserts PERR#. It also asserts SERR# if F0 Index 41h[5] is set to 1. This allows NMI generation. The CS5530 also detects parity errors during the address phase if F0 Index 04h[6] is set. When parity errors are detected during the address phase, SERR# is asserted internally. Parity errors are reported to the CPU by enabling the SERR# source in I/O Port 061h (Port B) con- trol register. The CS5530 sets the corresponding error bits in the PCI Status Register (F0 Index 06h[15:14]). Table 3- 5 shows these programming bits. If the CS5530 is the PCI master for a cycle and detects PERR# asserted, it generates SERR# internally. Table 3-5. PERR#/SERR# Associated Register Bits Bit Description F0 Index 04h-05h PCI Command Register (R/W) Reset Value = 0000h 6 Parity Error:Allow the CS5530 to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when a parity error is detected: 0 = Disable(Default); 1 = Enable. F0 Index 06h-07h PCI Status Register (R/W) Reset Value = 0280h 15 Detected Parity Error:This bit is set whenever a parity error is detected. Write 1 to clear. 14 Signaled System Error:This bit is set whenever the CS5530 asserts SERR# active. Write 1 to clear. F0 Index 41h PCI Function Control Register 2 (R/W) Reset Value = 10h 5 PERR# Signals SERR#: Assert SERR# any time that PERR# is asserted or detected active by the CS5530 (allows PERR# assertion to be cascaded to NMI (SMI) generation in the system): 0 = Disable; 1 = Enable.

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3.2.5 PCI Interrupt Routing Support

The CS5530 allows the PCI interrupt signals INTA#, INTB#, INTC#, and INTD# (also know in industry terms as PIRQx#) to be mapped internally to any IRQ signal via register programming (shown in T able 3-6). Further details are supplied in Section 3.5.4.4 “PCI Compatible Inter- rupts” on page 98 regarding edge/level sensitivity selec- tion.

3.2.6 Delayed Transactions

The CS5530 supports delayed transactions to prevent slow PCI cycles from occupying too much bandwidth and allows access for other PCI traffic. Note: For systems which have only the GXLV processor and CS5530 on the PCI bus, system performance is improved if delayed transactions are disabled. F0 Index 42h[5] and F0 Index 43h[1] are used to program this function. T able 3-7 shows these bit formats. Table 3-6. PCI Interrupt Steering Registers Bit Description F0 Index 5Ch PCI Interrupt Steering Register 1 (R/W) Reset Value = 00h 7:4 INTB# Target Interrupt:Selects target interrupt for INTB#: 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 3:0 INTA# Target Interrupt:Selects target interrupt for INTA#: 0000 = Disable 0100 = IRQ4 1000 = RSVD ‘ 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility F0 Index 5Dh PCI Interrupt Steering Register 2 (R/W) Reset Value = 00h 7:4 INTD# Target Interrupt:Selects target interrupt for INTD#: 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 3:0 INTC# Target Interrupt:Selects target interrupt for INTC#: 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility Table 3-7. Delay Transaction Programming Bits Bit Description F0 Index 42h PCI Function Control Register 3 (R/W) Reset Value = ACh 5 Delayed Transactions:Allow delayed transactions on the PCI bus: 0 = Disable; 1 = Enable. Also see F0 Index 43h[1]. F0 Index 43h USB Shadow Register (R/W) Reset Value = 03h 1 PCI Retry Cycles:When the CS5530 is a PCI target and the PCI buffer is not empty, allow PCI bus to retry cycles: 0 = Disable; 1 = Enable. This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid.

Revision 4.1 49 www.national.com Funcitonal Description(Continued) Geode™ CS5530

3.3 RESETS AND CLOCKS

The operations of resets and clocks in the CS5530 are described in this section of the Functional Description.

3.3.1 Resets

The CS5530 generates two reset signals, PCI_RST# to the PCI bus and CPU_RST to the GXLV processor. These resets are generated after approximately 100 µs delay from POR# active as depicted in Figure 3-5. At any state, Power-on/Resume/Reset, the 14.31818 MHz oscillator must be active for the resets to function.

3.3.2 ISA Clock

The CS5530 creates the ISACLK from dividing the PCI- CLK. For ISA compatibility, the ISACLK nominally runs at 8.33 MHz or less. The ISACLK dividers are programmed via F0 Index 50h[2:0] as shown in T able 3-8. Figure 3-5. CS5530 Reset Table 3-8. ISACLK Divider Bits Bit Description F0 Index 50h PIT Control/ISA CLK Divider (R/W) Reset Value = 7Bh 2:0 ISA Clock Divisor:Determines the divisor of the PCI clock used to make the ISA clock, which is typically programmed for approximately 8 MHz: 000 = Divide by one 100 = Divide by five 001 = Divide by two 101 = Divide by six 010 = Divide by three 110 = Divide by seven 011 = Divide by four 111 = Divide by eight If PCI clock = 25 MHz, use setting of 010 (divide by 3). If PCI clock = 30 or 33 MHz, use a setting of 011 (divide by 4). POR# CPU_RST PCI_RST# 100 µs POR# minimum pulse width for CS5530 only (i.e., not a system specification) = 100 µs and 14 MHz must be running. 9m s

www.national.com 50 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.3.3 DOT Clock

The DOT clock (DCLK) is generated from the 14.31818 MHz input (CLK_14MHZ). A combination of a phase locked loop (PLL), linear feedback shift register (LFSR) and divisors are used to generate the desired frequencies for the DOT clock. The divisors and LFSR are config- urable through the F4BAR+Memory Offset 24h. The mini- mum frequency of DCLK is 10 MHz and the maximum is 200 MHz. DCLK provides a video clock for the GXLV processor. For applications that do not use the GXLV processor’s video, this is an available clock for general purpose use. The system clock distribution for a CS5530/GXLV proces- sor based system is shown in Figure 3-6. Figure 3-6. System Clock Distribution D C L Kt oG X L VP r o c e s s o r M U X DCLK PLL TVCLK from TV Controller Clock Geode™ CS5530

48 MHz Clock to USB of CS5530

PCICLK to PCI Related Device PCICLK to PCI Bus Geode™ SDRAMCLK to SDRAM SDRAMCLK to SDRAM SDRAMCLK to SDRAM SDRAMCLK to SDRAM

14 MHz Clock to Super I/O

14.318 MHz

32 KHz for Reset and

14 MHz Clock to TV Controller

SUSP_3V OE#from CS5530

24.576 MHz Clock to AC97 Codec

14 MHz Clock

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3.3.3.1 DCLK Programming

The PLL contains an input divider (ID), feedback divider (FD) and a post divider (PD). The programming of the dividers is through F4BAR+Memory Offset 24h (see T able 3-9). The maximum output frequency is 300 MHz. The output frequency is given by equation #1: Equation #1: DCLK = [CLK_14MHZ * FD] ÷ [PD *ID] Condition:

140 MHz < [DCLK * PD] < 300 MHz

Where: CLK_14MHZ is pin P24 FD is derived from N see equation #2 and #3: PD is derived from bits [28:24] ID is derived from bits [2:0] Equation #2: If FD is an odd number then: FD = 2*N +1 Equation #3: If FD is an even number then: FD = 2*N +0 Where: N is derived from bits [22:12] +1 is achieved by setting bit 23 to 1. +0 is achieved by clearing bit 23 to 0. Example Define Target Frequency: Target frequency = 135 MHz Satisfy the “Condition”: (140 MHz < [DCLK * PD] < 300 MHz)

140 MHz < [135 MHz * 2] < 300 MHz

Therefore PD = 2 Solve Equation #1: DCLK = [CLK_14MHZ * FD] ÷ [PD *ID] 18.86 = FD ÷ ID Guess: ID = 7, Solve for FD FD = 132.02 Solve Equation #2 or #3: FD = 2*N +1 for odd FD FD = 2*N +0 for even FD FD is 132, therefore even 132 = 2*N +0 N=6 6 Summarize: PD = 2: Bits [28:24] = 00111 ID = 7: Bits [2:0] = 101 N = 66: Bits [22:12] = 073h (found in Table 3-10), clear bit 23 Result: DCLK = 135 The BIOS has been provided with a complete table of divi- sor values for supported video clock frequencies. Many combinations of divider values and VCO frequencies are possible to achieve a certain output clock frequency. T h e s eB I O Sv a l u e sm a yb ea d j u s t e df r o mt i m et ot i m et o meet system frequency accuracy and jitter requirements. For applications that do not use the GXLV processor’s video, this is an available clock for general purpose use. The transition from one DCLK frequency to another is not guaranteed to be smooth or bounded; therefore, new divider coefficients should only be programmed while the PLL is off line in a situation where the transition character- istics of the clock are “don't care”. The steps below describe (in order) how to change the DCLK frequency. 1) Program the new clock frequency 2) Program Reset (bit 31) high and Bypass PLL (bit 8) high. 3) Wait at least 500 µs for PLL to settle. 4) Program Reset (bit 31) low. 5) Program Bypass PLL (bit 8) low.

www.national.com 52 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Table 3-9. DCLK Configuration Register Bit Description F4BAR+Memory Offset 24h-27h DOT Clock Configuration Register (R/W) Reset Value = 00000000h

31 Reset:Reset the PLL: 0 = Normal operation; 1 = Reset

30 Half Clock:0 = Enable; 1 = Disable. For odd post divisors, half clock enables the falling edge of the VCO clock to be used to generate the falling edge of the post divider output to more closely approximate a 50% output duty cycle. 29 Reserved: Set to 0. 28:24 5-Bit DCLK PLL Post Divisor (PD) Value:Selects value of 1 to 31: 00000 = PD divisor of 8 01000 = PD divisor of 10 10000 = PD divisor of 9 11000 = PD divisor of 11 00001 = PD divisor of 6 01001 = PD divisor of 20 10001 = PD divisor of 7 11001 = PD divisor of 21 00010 = PD divisor of 18 01010 = PD divisor of 14 10010 = PD divisor of 19 11010 = PD divisor of 15 00011 = PD divisor of 4 01011 = PD divisor of 26 10011 = PD divisor of 5 11011 = PD divisor of 27 00100 = PD divisor of 12 01100 = PD divisor of 22 10100 = PD divisor of 13 11100 = PD divisor of 23 00101 = PD divisor of 16 01101 = PD divisor of 28 10101 = PD divisor of 17 11101 = PD divisor of 29 00110 = PD divisor of 24 01110 = PD divisor of 30 10110 = PD divisor of 25 11110 = PD divisor of 31 00111 = PD divisor of 2 01111 = PD divisor of 1* 10111 = PD divisor of 3 11111 = RSVD *See bit 11 description.

23 Plus 1 (+1):Adds 1 or 0 to FD (DCLK PLL VCO Feedback Divisor) parameter in equation (see Note):

0=A d d0t oF D ;1=A d d1t oF D 22:12 N: This bit represents “N” in the equation (see Note). It is used to solve the value of FD (DCLK PLL VCO Feedback Divi- sor). N can be a value of 1 to 400. For all values of N, refer to Table 3-10. CLK_ON: 0 = PLL disable; 1 = PLL enable. If PD = 1 (i.e., bits [28:24] = 01111) the PLL is always enabled. 10 Reserved: Set to 0. 9 Select Feedback Source:0 = DPLL; 1 = FREF . 8 Bypass PLL: Connects the input of the PLL directly to the output of the PLL: 0 = Normal Operation; 1 = Bypass PLL. If this bit is set to 1, the input of the PLL bypasses the PLL and resets the VCO control voltage, which in turn powers down the PLL. Allow 0.5 ms for the control voltage to be driven to 0V. 7:6 Reserved: Set to 0. 5 PLL Lock Indicator:0 = PLL has not locked on frequency; 1 = PLL has locked on frequency. 4:3 Reserved: Set to 0. 2:0 PLL Input Divide (ID) Value:Selects value of 2 to 9 (see Note): 000 = ID divisor of 2 100 = ID divisor of 6 001 = ID divisor of 3 101 = ID divisor of 7 010 = ID divisor of 4 110 = ID divisor of 8 011 = ID divisor of 5 111 = ID divisor of 9 Note: To calculate DCLK output frequency: Equation #1: DCLK = [CLK_14MHZ * FD] ÷ [PD *ID] Condition: 140 MHz < [DCLK * PD] < 300 MHz Where: CLK_14MHZ is pin P24 FD is derived from N see equation #2 and #3: PD is derived from bits [28:24] ID is derived from bits [2:0] Equation #2: If FD is an odd number then: FD = 2*N +1 Equation #3: If FD is an even number then: FD = 2*N +0 Where: N is derived from bits [22:12] +1 is achieved by setting bit 23 to 1. +0 s achieved by clearing bit 23 to 0.

Revision 4.1 53 www.national.com Funcitonal Description(Continued) Geode™ CS5530 Table 3-10. F4BAR+Memory Offset 24h[22:12] Decode (Value of “N”) N Reg. Value 400 33A 399 674 398 4E8 397 1D0 396 3A0 395 740 394 681 393 502 392 205 391 40B 390 16 389 2D 388 5B 387 B7 386 16F 385 2DE 384 5BD 383 37B 382 6F6 381 5EC 380 3D9 379 7B2 378 765 377 6CB 376 596 375 32D 374 65A 373 4B4 372 168 371 2D0 370 5A1 369 343 368 686 367 50C 366 219 365 433 364 66 363 CD 362 19B 361 336 360 66C 359 4D8 358 1B0 357 360 356 6C0 355 580 354 301 353 602 352 404 351 8 350 11 349 23 348 47 347 8F 346 11F 345 23E 344 47D 343 FA 342 1F5 341 3EA 340 7D4 339 7A9 338 753 337 6A7 336 54E 335 29D 334 53B 333 277 332 4EF 331 1DE 330 3BC 329 778 328 6F1 327 5E2 326 3C5 325 78A 324 715 323 62B 322 456 321 AC 320 159 319 2B2 318 565 317 2CB 316 597 315 32F 314 65E 313 4BC 312 178 311 2F0 310 5E1 309 3C3 308 786 307 70D 306 61B 305 436 304 6C 303 D9 302 1B3 301 366 N Reg. Value 300 6CC 299 598 298 331 297 662 296 4C4 295 188 294 310 293 620 292 440 291 80 290 101 289 202 288 405 287 A 286 15 285 2B 284 57 283 AF 282 15F 281 2BE 280 57D 279 2FB 278 5F7 277 3EF 276 7DE 275 7BD 274 77B 273 6F7 272 5EE 271 3DD 270 7BA 269 775 268 6EB 267 5D6 266 3AD 265 75A 264 6B5 263 56A 262 2D5 261 5AB 260 357 259 6AE 258 55C 257 2B9 256 573 255 2E7 254 5CF 253 39F 252 73E 251 67D N Reg. Value 250 4FA 249 1F4 248 3E8 247 7D0 246 7A1 245 743 244 687 243 50E 242 21D 241 43B 240 76 239 ED 238 1DB 237 3B6 236 76C 235 6D9 234 5B2 233 365 232 6CA 231 594 230 329 229 652 228 4A4 227 148 226 290 225 521 224 243 223 487 222 10E 221 21C 220 439 219 72 218 E5 217 1CB 216 396 215 72C 214 659 213 4B2 212 164 211 2C8 210 591 209 323 208 646 207 48C 206 118 205 230 204 461 203 C2 202 185 201 30A N Reg. Value 200 614 199 428 198 50 197 A1 196 143 195 286 194 50D 193 21B 192 437 191 6E 190 DD 189 1BB 188 376 187 6EC 186 5D8 185 3B1 184 762 183 6C5 182 58A 181 315 180 62A 179 454 178 A8 177 151 176 2A2 175 545 174 28B 173 517 172 22F 171 45F 170 BE 169 17D 168 2FA 167 5F5 166 3EB 165 7D6 164 7AD 163 75B 162 6B7 161 56E 160 2DD 159 5BB 158 377 157 6EE 156 5DC 155 3B9 154 772 153 6E5 152 5CA 151 395 N Reg. Value 150 72A 149 655 148 4AA 147 154 146 2A8 145 551 144 2A3 143 547 142 28F 141 51F 140 23F 139 47F 138 FE 137 1FD 136 3FA 135 7F4 134 7E9 133 7D3 132 7A7 131 74F 130 69F 129 53E 128 27D 127 4FB 126 1F6 125 3EC 124 7D8 123 7B1 122 763 121 6C7 120 58E 119 31D 118 63A 117 474 116 E8 115 1D1 114 3A2 113 744 112 689 111 512 110 225 109 44B 108 96 107 12D 106 25A 105 4B5 104 16A 103 2D4 102 5A9 101 353 N Reg. Value 100 6A6 99 54C 98 299 97 533 96 267 95 4CF 94 19E 93 33C 92 678 91 4F0 90 1E0 89 3C0 88 780 87 701 86 603 85 406 84 C 83 19 82 33 81 67 80 CF 79 19F 78 33E 77 67C 76 4F8 75 1F0 74 3E0 73 7C0 72 781 71 703 70 607 69 40E 68 1C 67 39 66 73 65 E7 64 1CF 63 39E 62 73C 61 679 60 4F2 59 1E4 58 3C8 57 790 56 721 55 643 54 486 53 10C 52 218 51 431 N Reg. Value 50 62 49 C5 48 18B 47 316 46 62C 45 458 44 B0 43 161 42 2C2 41 585 40 30B 39 616 38 42C 37 58 36 B1 35 163 34 2C6 33 58D 32 31B 31 636 30 46C 29 D8 28 1B1 27 362 26 6C4 25 588 24 311 23 622 22 444 21 88 20 111 19 222 18 445 17 8A 16 115 15 22A 14 455 13 AA 12 155 11 2AA 10 555 9 2AB 8 557 7 2AF 6 55F 5 2BF 4 57F 3 2FF 2 5FF 1 3FF N Reg. Value

www.national.com 54 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.4 POWER MANAGEMENT

The power management resources provided by a com- bined CS5530/GXLV processor based system supports a full-featured notebook implementation. The following explanations pertain to a full-featured “notebook” power management system. The extent to which these resources are employed depends on the application and on the discretion of the system designer. Power management resources can be grouped according to the function they enable or support. The major func- tions are as follows:  APM Support  CPU Power Management - Suspend Modulation -3 V o l t S u s p e n d -S a v e - t o - D i s k  Peripheral Power Management - Device Idle Timers and Traps - General Purpose Timers - ACPI Timer Register - General Purpose I/O Pins - Power Management SMI Status Reporting Registers Included in the following subsections are details regarding the registers used for configuring power management fea- tures. The majority of these registers are directly accessed through the PCI configuration register space designated as Function 0 (F0). However, included in the discussions are references to F1BAR+Memory Offset xxh. This refers to the registers accessed through a base address register in Function 1 (F1) at Index 10h (F1BAR). F1BAR sets the base address for the SMI status and ACPI timer support registers as shown in Table 3-11.

3.4.1 APM Support

Many notebook computers rely solely on an APM (Advanced Power Management) driver for enabling the operating system to power-manage the CPU. APM pro- vides several services which enhance the system power management and is theoretically the best approach; but in its current form, APM is imperfect for the following rea- sons:  APM is an OS-specific driver, and may not be available for some operating systems.  Application support is inconsistent. Some applications in foreground may prevent Idle calls.  APM does not help with Suspend determination or peripheral power management. The CS5530 provides two entry points for APM support:  Software CPU Suspend control via the CPU Suspend Command Register (F0 Index AEh)  Software SMI entry via the Software SMI Register (F0 Index D0h). This allows the APM BIOS to be part of the SMI handler. These registers are shown in T able 3-12. Table 3-11. Base Address Register (F1BAR) for SMI Status and ACPI Timer Support Bit Description F1 Index 10h-13h Base Address Register - F1BAR (R/W) Reset Value = 00000000h This register sets the base address of the memory mapped SMI status and ACPI timer related registers. Bits [7:0] are read only (00h), indicating a 256 byte memory address range. Refer to Table 4-16 for the SMI status and ACPI timer registers bit formats and reset val- ues. The upper 16 bytes are always mapped to the ACPI timer, and are always memory mapped. Note: In Silicon Revision 1.3 and above the ACPI Timer Count Register is accessible through I/O Port 121Ch. 31:8 SMI Status/Power Management Base Address 7:0 Address Range (Read Only)

Revision 4.1 55 www.national.com Functional Description(Continued) Geode™ CS5530

3.4.2 CPU Power Management

The three greatest power consumers in a system are the display, the hard drive, and the CPU. The power manage- ment of the first two is relatively straightforward and is dis- cussed in Section 3.4.3 “Peripheral Power Management” on page 60. A P M ,i fa v a i l a b l e ,i su s e dp r i m a r i l yb yC P Up o w e rm a n - agement since the operating system is most capable of reporting the Idle condition. Additional resources provided by the CS5530 supplement APM by monitoring external activity and power managing the CPU based on the sys- tem demands. The two processes for power managing the CPU are Suspend Modulation and 3 Volt Suspend.

3.4.2.1 Suspend Modulation

Suspend Modulation works by asserting and de-asserting the SUSP# pin to the CPU for configurable durations. When the SUSP# pin is asserted to the processor, the processor enters an Idle state during which time the power consumption is significantly reduced. Even though the PCI clock is still running, the processor stops clocks to its core when SUSP# is asserted. By modulating the SUSP# pin, a reduced frequency of operation is achieved. The Suspend Modulation feature works by assuming that the processor is idle unless external activity indicates oth- erwise. This approach effectively slows down the proces- sor until external activity indicates a need to run at full speed, thereby reducing power consumption. This approach is the opposite of that taken by most power management schemes in the industry, which run the sys- tem at full speed until a period of inactivity is detected, and then slows down. Suspend Modulation, the more aggressive approach, yields lower power consumption. Suspend Modulation serves as the primary CPU power management mechanism when APM is not present. It also acts as a backup for situations where APM does not correctly detect an Idle condition in the system. In order to provide high-speed performance when needed, the SUSP# pin modulation is temporarily dis- abled any time system activity is detected. When this hap- pens, the processor is “instantly” converted to full speed for a programmed duration. System activities in the CS5530 are asserted as: any unmasked IRQ, accessing Port 061h, any asserted SMI, and/or accessing the video port. Since the graphics controller is integrated in the GXLV processor, the indication of video activity is sent to the CS5530 via the serial link (see Section 3.1.2 “PSERIAL Pin Interface” on page 44 for more information on serial link) and is automatically decoded. Video activity is defined as any access to the VGA register space, the VGA frame buffer, the graphics accelerator control regis- ters and the configured graphics frame buffer. The automatic speedup events (video and IRQ) for Sus- pend Modulation should be used together with software- controlled speedup registers for major I/O events such as any access to the floppy disk controller, hard disk drive, or parallel/serial ports, since these are indications of major system activities. When major I/O events occur, Suspend Modulation should be temporarily disabled using the pro- cedures described in the Power Management Registers in the following subsections. If a bus master (Ultra DMA/33, Audio, USB) request (REQ#) occurs, the processor automatically deasserts SUSPA# and grants (GNT#) the bus to the requesting bus master. When the bus master deasserts REQ#, SUSPA# reasserts. This does not directly affect the Suspend Mod- ulation programming. Table 3-12. APM Support Registers Bit Description F0 Index AEh CPU Suspend Command Register (WO) Reset Value = 00h 7:0 Software CPU Suspend Command (Write Only):If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0] = 0), a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU in a low-power state. The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt condition. If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted after the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4] will be invoked, allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin. Note: If the clocks are stopped, the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530 pins can be used to wake-up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI events are also Resume events. F0 Index D0h Software SMI Register (WO) Reset Value = 00h 7:0 Software SMI (Write Only):A write to this location generates an SMI. The data written is irrelevant. This register allows software entry into SMM via normal bus access instructions.

www.national.com 56 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Configuring Suspend Modulation Control of the Suspend Modulation feature is accom- plished using the Suspend Modulation OFF Count Regis- ter, the Suspend Modulation ON Count Register, and the Suspend Configuration Register (F0 Index 94h, 95h, and 96h, respectively). The Power Management Enable Register 1 (F0 Index 80h) contains the global power management enable bit (bit 0), as well as the enables for the individual activity speedup timers. The global power management bit must be enabled for Suspend Modulation and all other power management resources to function. Bit 0 of the Suspend Configuration Register (F0 Index 96h) enables the Suspend Modulation feature. Bit 1 con- trols how SMI events affect the Suspend Modulation fea- ture. In general this bit should be set to a 1, which causes SMIs to disable Suspend Modulation until it is re-enabled by the SMI handler. The Suspend Modulation OFF and ON Count Registers (F0 Index 94h and 95h) control two 8-bit counters that rep- resent the number of 32 µs intervals that the SUSP# pin is asserted and then deasserted to the processor. These counters define a ratio which is the effective frequency of operation of the system while Suspend Modulation is enabled. The IRQ and Video Speedup Timer Count registers (F0 Index 8Ch and 8Dh) configure the amount of time which Suspend Modulation is disabled when the respective events occur. SMI Speedup Disable If the Suspend Modulation feature is being used for CPU power management, the occurrence of an SMI disables the Suspend Modulation function so that the system oper- ates at full speed while in SMM. There are two methods used to invoke this via bit 1 of the Suspend Configuration Register. 1) If F0 Index 96h[1] = 0: Use the IRQ Speedup Timer (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI occurs. 2) If F0 Index 96h[1] = 1: Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The SMI Speedup Disable Register prevents VSA tech- nology software from entering Suspend Modulation while operating in SMM. The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this I/O location has no effect. Table 3-13 shows the bit formats of the Suspend Modula- tion related registers. Feff=F GX86 x On Count On Count + Off Count Table 3-13. Suspend Modulation Related Registers Bit Description F1BAR+Memory Offset 08h-09h SMI Speedup Disable Register (Read to Enable) Reset Value = 0000h 15:0 SMI Speedup Disable:If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this register invokes the SMI handler to re-enable Suspend Modulation. The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this location has no effect. F0 Index 80h Power Management Enable Register 1 (R/W) Reset Value = 00h 4 Video Speedup:Any video activity, as decoded from the serial connection (PSERIAL register, bit 0) from the GXLV pro- cessor disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when system is power man- aged using CPU Suspend Modulation. 0 = Disable; 1 = Enable. The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an external VGA access (3Bx, 3, 3Dx and A000h-B7FFh) on the PCI bus is also supported. This configuration is non-stan- dard, but it does allow the power management routines to support an external VGA chip. 3 IRQ Speedup: Any unmasked IRQ (per I/O Port 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA# hand- shake) for a configurable duration when system is power managed using CPU Suspend Modulation: 0 = Disable; 1 = Enable. The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch). 0 Power Management: Global power management: 0 = Disable; 1 = Enabled. This bit must be set (1) immediately after POST for power management resources to function.

Revision 4.1 57 www.national.com Functional Description(Continued) Geode™ CS5530 F0 Index 8Ch IRQ Speedup Timer Count Register (R/W) Reset Value = 00h 7:0 IRQ Speedup Timer Count:This field represents the load value for the IRQ speedup timer. It is loaded into the counter when Suspend Modulation is enabled (F0 Index 96[0] = 1) and an INTR or an access to I/O Port 061h occurs. When the event occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the CPU. Upon expira- tion, no SMI is generated; the Suspend Modulation begins again. The IRQ speedup timer’s timebase is 1 ms. This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typi- cal value here would be 2 to 4 ms. F0 Index 8Dh Video Speedup Timer Count Register (R/W) Reset Value = 00h 7:0 Video Speedup Timer Count:This field represents the load value for the Video speedup timer. It is loaded into the counter when Suspend Modulation is enabled (F0 Index 96[0] = 1) and any access to the graphics controller occurs. When a video access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the CPU. Upon expiration, no SMI is generated; the Suspend Modulation begins again. The video speedup timer’s timebase is 1 ms. This speedup mechanism allows instantaneous response to video activity for full speed during video processing calcula- tions. A typical value here would be 50 to 100 ms. F0 Index 94h Suspend Modulation OFF Count Register (R/W) Reset Value = 00h 7:0 Suspend Signal Deasserted Count:This 8-bit counter represents the number of 32 µs intervals that the SUSP# pin is deasserted to the processor. This counter, together with the Suspend Modulation ON Count Register (F0 Index 95h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups. F0 Index 95h Suspend Modulation ON Count Register (R/W) Reset Value = 00h 7:0 Suspend Signal Asserted Count:This 8-bit counter represents the number of 32 µs intervals that the SUSP# pin is asserted. This counter, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups. F0 Index 96h Suspend Configuration Register (R/W) Reset Value = 00h 7:3 Reserved: Set to 0. 2 Suspend Mode Configuration:“Special 3 Volt Suspend” mode to support powering down the GXLV processor during Suspend: 0 = Disable; 1 = Enable.

1 SMI Speedup Configuration:Selects how Suspend Modulation function reacts when an SMI occurs:

0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI occurs. 1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA and Power Management operations occur at full speed. Two methods for accomplishing this are either to map the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0). 0 Suspend Modulation Feature Enable:Suspend Modulation feature: 0 = Disable; 1 = Enable. When enabled, the SUSP# pin is asserted and deasserted for the durations programmed in the Suspend Modulation OFF/ON Count Registers (F0 Index 94h/95h). F0 Index A8h-A9h Video Overflow Count Register (R/W) Reset Value = 0000h 15:0 Video Overflow Count:Each time the Video Speedup Counter (F0 Index 8Dh) is triggered, a 100 ms timer is started. If the 100 ms timer expires before the Video Speedup Counter lapses, the Video Overflow Count Register increments and the 100 ms timer re-triggers. Software clears the overflow register when new evaluations are to begin. The count con- tained in this register may be combined with other data to determine the type of video accesses present in the system. Table 3-13. Suspend Modulation Related Registers (Continued) Bit Description

www.national.com 58 Revision 4.1 Functional Description(Continued) Geode™ CS5530 3.4.2.2 3 Volt Suspend The CS5530 supports the stopping of the CPU and sys- tem clocks for a 3 Volt Suspend state. If appropriately con- figured, via the Clock Stop Control Register (F0 Index BCh), the CS5530 asserts the SUSP_3V pin after it has gone through the SUSP#/SUSPA# handshake. The SUSP_3V pin is a state indicator, indicating that the sys- tem is in a low-activity state and Suspend Modulation is a c t i v e .T h i si n d i c a t o rc a nb eu s e dt op u tt h es y s t e mi n t oa low-power state (the system clock can be turned off). The SUSP_3V pin is intended to be connected to the out- put enable of a clock generator or buffer chip, so that the clocks to the CPU and the CS5530 (and most other sys- tem devices) will be stopped. The CS5530 continues to decrement all of its device timers and respond to external SMI interrupts after the input clock has been stopped, as long as the 32 KHz clock continues to oscillate. Any SMI event or unmasked interrupt pin causes the CS5530 to deassert the SUSP_3V pin, restarting the system clocks. As the CPU or other device might include a PLL, the CS5530 holds SUSP# active for a pre-programmed period of delay (the PLL re-sync delay) that varies from 0 to 15 ms. After this period has expired, the CS5530 deas- serts SUSP#, stopping Suspend. SMI# is held active for the entire period, so that the CPU reenters SMM when the clocks are restarted. Note: The SUSP_3V pin can be active either high or low. The pin is an input during POR, and is sam- pled to determine its inactive state. This allows a designer to match the active state of SUSP_3V to the inactive state for a clock driver output enable with a pull-up or pull-down resistor. The bit formats for the Clock Stop Control Register are given in Table 3-14. Table 3-14. Clock Stop Control Register Bit Description F0 Index BCh Clock Stop Control Register (R/W) Reset Value = 00h 7:4 PLL Delay:The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the SUSP# pin is deasserted to the CPU. This delay is designed to allow the clock chip and CPU PLL to stabilize before start- ing execution. This delay is only invoked if the STP_CLK bit (bit 0) was set. The four-bit field allows values from 0 to 15 ms. 0000 = 0 ms 0100 = 4 ms 1000 = 8 ms 1100 = 12 ms 0001 = 1 ms 0101 = 5 ms 1001 = 9 ms 1101 = 13 ms 0010 = 2 ms 0110 = 6 ms 1010 = 10 ms 1110 = 14 ms 0011 = 3 ms 0111 = 7 ms 1011 = 11 ms 1111 = 15 ms 3:1 Reserved: Set to 0. 0 CPU Clock Stop:0 = Normal SUSP#/ SUSPA# handshake; 1 = Full system Suspend. Notes: This register configures the CS5530 to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the appropriate conditions, stopping the system clocks. A delay of 0 to 15 ms is programmable (bits 7:4) to allow for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system. A write to the CPU Suspend Command Register (F0 Index AEh) with bit 0 written as: 0 = SUSP#/SUSPA# handshake occurs. The CPU is put into a low-power state, and the system clocks are not stopped. When a break/resume event occurs, it releases the CPU halt condition. 1 = SUSP#/SUSPA# handshake occurs and the SUSP_3V pin is asserted, thus invoking a full system Suspend (both CPU and system clocks are stopped). When a break event occurs, the SUSP_3V pin will deassert, the PLL delay pro- grammed in bits [7:4] will be invoked which allows the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Revision 4.1 59 www.national.com Functional Description(Continued) Geode™ CS5530

3.4.2.3 Save-To-Disk

Save-to-Disk is supported by the CS5530. In this state, the power is typically removed from the CS5530, causing the state of the legacy peripheral devices to be lost. Shadow registers are provided for the devices which allows their state to be saved prior to removing power. This is necessary because the legacy AT peripheral devices used several write only registers. In order to restore the exact state of these devices on resume, the write only register values are “shadowed” so that the val- ues can be saved by the Power Management Software. The PC/AT compatible floppy port is not part of the CS5530. However, it is expected that one will be attached on the ISA bus in a SuperI/O or by some other means. Some of the FDC registers are shadowed because they cannot be safely read. They are shown in Table 3-15. Additional shadow registers for other functions are described in:  Table 3-39 "DMA Shadow Register" on page 93  Table 3-41 "PIT Shadow Register" on page 95  Table 3-44 "PIC Shadow Register" on page 97  Table 3-52 "Real-Time Clock Registers" on page 104 Table 3-15. Power Management Shadow Registers Bit Description F0 Index B4h Floppy Port 3F2h Shadow Register (RO) Reset Value = 00h 7:0 Floppy Port 3F2h Shadow (Read Only):Last written value of I/O Port 3F2h. Required for support of FDC power ON/OFF and Zero Volt Suspend/Resume coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation. F0 Index B5h Floppy Port 3F7h Shadow Register (RO) Reset Value = 00h 7:0 Floppy Port 3F7h Shadow (Read Only):Last written value of I/O Port 3F7h. Required for support of FDC power ON/OFF and Zero Volt Suspend/Resume coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation. F0 Index B6h Floppy Port 1F2h Shadow Register (RO) Reset Value = 00h 7:0 Floppy Port 1F2h Shadow (Read Only):Last written value of I/O Port 1F2h. Required for support of FDC power ON/OFF and Zero Volt Suspend/Resume coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation. F0 Index B7h Floppy Port 1F7h Shadow Register (RO) Reset Value = 00h 7:0 Floppy Port 1F7h Shadow (Read Only):Last written value of I/O Port 1F7h. Required for support of FDC power ON/OFF and Zero Volt Suspend/Resume coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation.

www.national.com 60 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.4.3 Peripheral Power Management

The CS5530 provides peripheral power management using a combination of device idle timers, address traps, and general purpose I/O pins. Idle timers are used in con- junction with traps to support powering down peripheral devices. Eight programmable GPIO (general purpose I/O) pins are included for external device power control as well as other functions. All I/O addresses are decoded in 16 bits. All memory addresses are decoded in 32 bits.

3.4.3.1 Device Idle Timers and Traps

Idle timers are used to power manage a peripheral by determining when the peripheral has been inactive for a specified period of time, and removing power from the peripheral at the end of that time period. Idle timers are provided for the commonly-used peripher- als (FDC, IDE, parallel/serial ports, and mouse/keyboard). In addition, there are three user-defined timers that can be configured for either I/O or memory ranges. T h ei d l et i m e r sa r e1 6 - b i tc o u n t d o w nt i m e r sw i t ha1s e c - ond time base, providing a time-out range of 1 to 65536 seconds (1092 minutes) (18 hours). When the idle timer count registers are loaded with a non- zero value and enabled, the timers decrement until one of two possibilities happens: a bus cycle occurs at that I/O or memory range, or the timer decrements to zero. If a bus cycle occurs, the timer is reloaded and begins decrementing again. If the timer decrements to zero, and power management is enabled (F0 Index 80h[0] = 1), the timer generates an SMI. When an idle timer generates an SMI, the SMI handler manages the peripheral power, disables the timer, and enables the trap. The next time an event occurs, the trap generates an SMI. This time, the SMI handler applies power to the peripheral, resets the timer, and disables the trap. T a b l e s3 - 1 6t h r o u g h3 - 2 4s h o wt h ed e v i c ea s s o c i a t e di d l e timers and traps programming bits. Table 3-16. Power Management Global Enabling Bits Bit Description F0 Index 80h Power Management Enable Register 1 (R/W) Reset Value = 00h 2 Traps:Globally enable all power management device I/O traps: 0 = Disable; 1 = Enable. This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h. 1 Idle Timers:Globally enable all power management device idle timers: 0 = Disable; 1 = Enable. Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts. This bit has no affect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h). 0 Power Management: Global power management: 0 = Disable; 1 = Enabled. This bit must be set (1) immediately after POST for power management resources to function.

Revision 4.1 61 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-17. Keyboard/Mouse Idle Timer and Trap Related Registers Bit Description F0 Index 81h Power Management Enable Register 2 (R/W) Reset Value = 00h 3 Keyboard/Mouse Idle Timer Enable:Turn on Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3]. F0 Index 82h Power Management Enable Register 3 (R/W) Reset Value = 00h 3 Keyboard/Mouse Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[3]. F0 Index 93h Miscellaneous Device Control Register (R/W) Reset Value = 00h 1 Mouse on Serial Enable:Mouse is present on a Serial Port: 0 = No; 1 = Y es. (Note) 0 Mouse Port Select:Selects which serial port the mouse is attached to: 0 = COM1; 1 = COM2. (Note) Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done because a mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the screen. These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the Paral- lel/Serial Port Idle Timer Count Register (F0 Index 9Ch). F0 Index 9Eh-9Fh Keyboard / Mouse Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Keyboard / Mouse Idle Timer Count:This idle timer determines when the keyboard and mouse are not in use so that the LCD screen can be blanked. The 16-bit value programmed here represents the period of inactivity for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to either the keyboard or mouse I/O address spaces, including the mouse serial port address space when a mouse is enabled on a serial port. The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[3] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3].

www.national.com 62 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Table 3-18. Parallel/Serial Idle Timer and Trap Related Registers Bit Description F0 Index 81h Power Management Enable Register 2 (R/W) Reset Value = 00h 2 Parallel/Serial Idle Timer Enable:Turn on Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2]. F0 Index 82h Power Management Enable Register 3 (R/W) Reset Value = 00h 2 Parallel/Serial Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[2]. F0 Index 93h Miscellaneous Device Control Register (R/W) Reset Value = 00h 1 Mouse on Serial Enable:Mouse is present on a Serial Port: 0 = No; 1 = Y es. (Note) 0 Mouse Port Select:Selects which serial port the mouse is attached to: 0 = COM1; 1 = COM2. (Note) Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done because a mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the screen. These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the Paral- lel/Serial Port Idle Timer Count Register (F0 Index 9Ch). F0 Index 9Ch-9Dh Parallel / Serial Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 P a r a l l e l/S e r i a lI d l eT i m e rC o u n t :This idle timer is used to determine when the parallel and serial ports are not in use so that the ports can be power managed. The 16-bit value programmed here represents the period of inactivity for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the parallel (LPT) or serial (COM) I/O address spaces. If the mouse is enabled on a serial port, that port is not considered here. The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[2] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2].

Revision 4.1 63 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-19. Floppy Disk Idle Timer and Trap Related Registers Bit Description F0 Index 81h Power Management Enable Register 2 (R/W) Reset Value = 00h 1 Floppy Disk Idle Timer Enable:Turn on Floppy Disk Idle Timer Count Register (F0 Index 9Ah) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h, Secondary floppy disk: I/O Port 372h-375h, 377h Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[1]. F0 Index 82h Power Management Enable Register 3 (R/W) Reset Value = 00h 1 Floppy Disk Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h, Secondary floppy disk: I/O Port 372h-375h, 377h Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[1]. F0 Index 93h Miscellaneous Device Control Register (R/W) Reset Value = 00h 7 Floppy Drive Port Select:All system resources used to power manage the floppy drive use the primary or secondary FDC addresses for decode: 0 = Secondary; 1 = Primary. F0 Index 9Ah-9Bh Floppy Disk Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Floppy Disk Idle Timer Count:This idle timer is used to determine when the floppy disk drive is not in use so that it can be powered down. The 16-bit value programmed here represents the period of floppy disk drive inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured floppy drive’s data port (I/O Port 3F5h or 375h). The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[1] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[1].

www.national.com 64 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Table 3-20. Primary Hard Disk Idle Timer and Trap Related Registers Bit Description F0 Index 81h Power Management Enable Register 2 (R/W) Reset Value = 00h 0 Primary Hard Disk Idle Timer Enable:Turn on Primary Hard Disk Idle Timer Count Register (F0 Index 98h) and gener- ate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges selected in F0 Index 93h[5], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0]. F0 Index 82h Power Management Enable Register 3 (R/W) Reset Value = 00h 0 Primary Hard Disk Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[5], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[0]. F0 Index 93h Miscellaneous Device Control Register (R/W) Reset Value = 00h 5 Partial Primary Hard Drive Decode:This bit is used to restrict the addresses which are decoded as primary hard drive accesses. 0 = Power management monitors all reads and writes I/O Port 1F0h-1F7h, 3F6h-3F7h (excludes writes to 3F7h) 1 = Power management monitors only writes to I/O Port 1F6h and 1F7h F0 Index 98h-99h Primary Hard Disk Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Primary Hard Disk Idle Timer Count:This idle timer is used to determine when the primary hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of primary hard disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured primary hard disk’s data port (configured in F0 Index 93h[5]). The counter uses a 1 second time- base. To enable this timer set F0 Index 81h[0] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0].

Revision 4.1 65 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-21. Secondary Hard Disk Idle Timer and Trap Related Registers Bit Description F0 Index 83h Power Management Enable Register 4 (R/W) Reset Value = 00h 7 Secondary Hard Disk Idle Timer Enable:Turn on Secondary Hard Disk Idle Timer Count Register (F0 Index ACh) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges selected in F0 Index 93h[4], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4]. 6 Secondary Hard Disk Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[4], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[5]. F0 Index 93h Miscellaneous Device Control Register (R/W) Reset Value = 00h 4 Partial Secondary Hard Drive Decode:This bit is used to restrict the addresses which are decoded as secondary hard drive accesses. 0 = Power management monitors all reads and writes I/O Port 170h-177h, 376h-377h (excludes writes to 377h) 1 = Power management monitors only writes to I/O Port 176h and 177h F0 Index ACh-ADh Secondary Hard Disk Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Secondary Hard Disk Idle Timer Count:This idle timer is used to determine when the secondary hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of secondary hard disk inactiv- ity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured secondary hard disk’s data port (configured in F0 Index 93h[4]). The counter uses a 1 second timebase. To enable this timer set F0 Index 83h[7] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4].

www.national.com 66 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Table 3-22. User Defined Device 1 (UDEF1) Idle Timer and Trap Related Registers Bit Description F0 Index 81h Power Management Enable Register 4 (R/W) Reset Value = 00h 4 User Defined Device 1 (UDEF1) Idle Timer Enable:Turn on UDEF1 Idle Timer Count Register (F0 Index A0h) and gen- erate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[4]. F0 Index 82h Power Management Enable Register 3 (R/W) Reset Value = 00h 4 User Defined Device 1 (UDEF1) Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF1 address pro- gramming is at F0 Index C0h (base address register), and CCh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[2]. F0 Index A0h-A1h User Defined Device 1 Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 User Defined Device 1 (UDEF1) Idle Timer Count:This idle timer determines when the device configured as UDEF1 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured in F0 Index C0h (base address register) and F0 Index CCh (control register). The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[4] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[4]. F0 Index C0h-C3h User Defined Device 1 Base Address Register (R/W) Reset Value = 00000000h 31:0 User Defined Device 1 (UDEF1) Base Address [31:0]:This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar- ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh). F0 Index CCh User Defined Device 1 Control Register (R/W) Reset Value = 00h 7 Memory or I/O Mapped:User Defined Device 1 is: 0 = I/O; 1 = Memory. 6:0 Mask: If bit 7 = 0 (I/O): Bit 6 0 = Disable write cycle tracking 1 = Enable write cycle tracking Bit 5 0 = Disable read cycle tracking 1 = Enable read cycle tracking Bits 4:0 Mask for address bits A[4:0] If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison.

Revision 4.1 67 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-23. User Defined Device 2 (UDEF2) Idle Timer and Trap Related Registers Bit Description F0 Index 81h Power Management Enable Register 4 (R/W) Reset Value = 00h 5 User Defined Device 2 (UDEF2) Idle Timer Enable:Turn on UDEF2 Idle Timer Count Register (F0 Index A2h) and gen- erate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[5]. F0 Index 82h Power Management Enable Register 3 (R/W) Reset Value = 00h 5 User Defined Device 2 (UDEF2) Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF2 address pro- gramming is at F0 Index C4h (base address register) and CDh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[3]. F0 Index A2h-A3h User Defined Device 2 Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 User Defined Device 2 (UDEF2) Idle Timer Count:This idle timer determines when the device configured as UDEF2 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured in the F0 Index C4h (base address register) and F0 Index CDh (control register). The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[5] = 1. Top level SMI status reporting is at F1BAR+Memory Offset 00h/02h[0] and secondary level SMI status reporting is at F0 Index 85h/F5h[5]. F0 Index C4h-C7h User Defined Device 2 Base Address Register (R/W) Reset Value = 00000000h 31:0 User Defined Device 2 (UDEF2) Base Address [31:0]:This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar- ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh). F0 Index CDh User Defined Device 2 Control Register (R/W) Reset Value = 00h 7 Memory or I/O Mapped:User Defined Device 2 is: 0 = I/O; 1 = Memory. 6:0 Mask: If bit 7 = 0 (I/O): Bit 6 0 = Disable write cycle tracking 1 = Enable write cycle tracking Bit 5 0 = Disable read cycle tracking 1 = Enable read cycle tracking Bits 4:0 Mask for address bits A[4:0] If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison.

www.national.com 68 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Table 3-24. User Defined Device 3 (UDEF3) Idle Timer and Trap Related Registers Bit Description F0 Index 81h Power Management Enable Register 4 (R/W) Reset Value = 00h 6 User Defined Device 3 (UDEF3) Idle Timer Enable:Turn on UDEF3 Idle Timer Count Register (F0 Index A4h) and gen- erate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[6]. F0 Index 82h Power Management Enable Register 3 (R/W) Reset Value = 00h 6 User Defined Device 3 (UDEF3) Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF3 address pro- gramming is at F0 Index C8h (base address register) and CEh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[4]. F0 Index A4h-A5h User Defined Device 3 Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 User Defined Device 3 (UDEF3) Idle Timer Count:This idle timer determines when the device configured as UDEF3 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured in the UDEF3 Base Address Register (F0 Index C8h) and UDEF3 Control Register (F0 Index CEh). The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[6] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[6]. F0 Index C8h-CBh User Defined Device 3 Base Address Register (R/W) Reset Value = 00000000h 31:0 User Defined Device 3 (UDEF3) Base Address [31:0]:This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar- ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh). F0 Index CEh User Defined Device 3 Control Register (R/W) Reset Value = 00h 7 Memory or I/O Mapped:User Defined Device 3 is: 0 = I/O; 1 = Memory. 6:0 Mask: If bit 7 = 0 (I/O): Bit 6 0 = Disable write cycle tracking 1 = Enable write cycle tracking Bit 5 0 = Disable read cycle tracking 1 = Enable read cycle tracking Bits 4:0 Mask for address bits A[4:0] If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison.

Revision 4.1 69 www.national.com Functional Description(Continued) Geode™ CS5530 Although not considered as device idle timers, two addi- tional timers are provided by the CS5530. The Video Idle Timer used for Suspend-determination and the VGA Timer used for SoftVGA. These timers and their associated programming bits are listed in Tables 3-25 and 3-26. Table 3-25. Video Idle Timer and Trap Related Registers Bit Description F0 Index 81h Power Management Enable Register 2 (R/W) Reset Value = 00h 7 Video Access Idle Timer Enable:Turn on Video Idle Timer Count Register (F0 Index A6h) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the video address range (sets bit 0 of the GXLV processor’s PSERIAL Register) the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[7]. F0 Index 82h Power Management Enable Register 3 (R/W) Reset Value = 00h 7 Video Access Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GXLV processor’s PSERIAL Reg- ister) an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[7]. F0 Index A6h-A7h Video Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Video Idle Timer Count:This idle timer determines when the graphics subsystem has been idle as part of the Suspend-determination algorithm. The 16-bit value programmed here represents the period of video inactivity after which the system is alerted via an SMI. The count in this timer is automatically reset whenever an access occurs to the graphics controller space. The counter uses a 1 second timebase. In a GXLV processor based system the graphics controller is embedded in the CPU, so video activity is communicated to the CS5530 via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530 also detects accesses to standard VGA space on PCI (3Bxh, 3h, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used. To enable this timer set F0 Index 81h[7] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[7]. Table 3-26. VGA Timer Related Registers Bit Description Index 83h Power Management Enable Register 4 (R/W) Reset Value = 00h 3 VGA Timer Enable:Turn on VGA Timer and generate an SMI when the timer reaches 0: 0 = Disable; 1 = Enable If an access occurs in the programmed address range the timer is reloaded with the programmed count. VGA Timer pro- gramming is at F0 Index 8Eh and F0 Index 8Bh[6] SMI Status reporting is at F1BAR+Memory Offset 00h/02h[6] (only). Index 8Bh General Purpose Timer 2 Control Register (R/W) Reset Value = 00h 6 VGA Timer Base: Selects timebase for VGA Timer Register (F0 Index 8Eh): 0 = 1 ms; 1 = 32 µs. Index 8Eh VGA Timer Count Register (R/W) Reset Value = 00h 7:0 VGA Timer Load Value:This field represents the load value for VGA Timer. It is loaded into the counter when the timer is enabled (F0 Index 83h[3] = 1). The counter is decremented with each clock of the configured timebase (F0 Index 8Bh[6]). Upon expiration of the counter, an SMI is generated and the status is reported in F1BAR+Memory Offset 00h/02h[6] (only). Once expired, this counter must be re-initialized by either disabling and enabling it, or writing a new count value here. This counter’s timebase is 1 ms.

www.national.com 70 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.4.3.2 General Purpose Timers

The CS5530 contains two general purpose idle timers, General Purpose Timer 1 (F0 Index 88h) and General Purpose Timer 2 (F0 Index 8Ah). These two timers are similar to the Device Idle Timers in that they count down to zero unless re-triggered, and generate an SMI when they reach zero. However, these are 8-bit timers instead of 16 bits, they have a programmable timebase, and the events which reload these timers are configurable. These timers are typically used for an indication of system inac- tivity for Suspend determination. General Purpose Timer 1 can be re-triggered by activity to any of the configured user defined devices, keyboard and mouse, parallel and serial, floppy disk, or hard disk. General Purpose Timer 2 can be re-triggered by a transi- tion on the GPIO7 pin (if GPIO7 is properly configured). Configuration of the GPIO7 is explained in Section 3.4.3.4 “General Purpose I/O Pins” on page 73. When a General Purpose Timer is enabled or when an event reloads the timer, the timer is loaded with the config- ured count value. Upon expiration of the timer an SMI is generated and a status flag is set. Once expired, this counter must be re-initialized by disabling and enabling it. The timebase for both General Purpose Timers can be configured as either 1 second (default) or 1 millisecond. The registers at F0 Index 89h and 8Bh are the control reg- isters for the General Purpose Timers. Table 3-27 show the bit formats for these registers. Table 3-27. General Purpose Timers and Control Registers Bit Description F0 Index 88h General Purpose Timer 1 Count Register (R/W) Reset Value = 00h 7:0 General Purpose Timer 1 Count:This field represents the load value for GP Timer 1. This value can represent either an 8-bit or 16-bit counter (selected in F0 Index 8Bh[4]). It is loaded into the counter when the timer is enabled (F0 Index 83h[0] =1). Once enabled, an enabled event (configured in F0 Index 89h[6:0]) reloads the timer. The counter is decremented with each clock of the configured timebase. Upon expiration of the counter, an SMI is gener- ated and the top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. The second level SMI status is reported at F1BAR+Memory Offset 04h/06h[0]). Once expired, this counter must be re-initialized by either disabling and enabling it, or writing a new count value here. This counter’s timebase can be configured as 1 msec or 1 sec at F0 Index 89h[7]. F0 Index 89h General Purpose Timer 1 Control Register (R/W) Reset Value = 00h 7 Timebase for General Purpose Timer 1:Selects timebase for GP Timer 1 (F0 Index 88h): 0 = 1 sec; 1 = 1 msec. 6 Re-trigger General Purpose Timer 1 on User Defined Device 3 (UDEF3) Activity:0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF3 reloads GP Timer 1. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register). 5 Re-trigger General Purpose Timer 1 on User Defined Device 2 (UDEF2) Activity:0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF2 reloads GP Timer 1. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register). 4 Re-trigger General Purpose Timer 1 on User Defined Device 1 (UDEF1) Activity:0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF1 reloads GP Timer 1. UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register)

3 Re-trigger General Purpose Timer 1 on Keyboard or Mouse Activity:0 = Disable; 1 = Enable

Any access to the keyboard or mouse I/O address range (listed below) reloads GP Timer 1. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) 2 Re-trigger General Purpose Timer 1 on Parallel/Serial Port Activity:0 = Disable; 1 = Enable. Any access to the parallel or serial port I/O address range (listed below) reloads the GP Timer 1. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh 1 Re-trigger General Purpose Timer 1 on Floppy Disk Activity:0 = Disable; 1 = Enable. Any access to the floppy disk drive address ranges (listed below) reloads GP Timer 1. Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h Secondary floppy disk: I/O Port 372h-375h, 377h The active floppy drive is configured via F0 Index 93h[7]. 0 Re-trigger General Purpose Timer 1 on Primary Hard Disk Activity:0 = Disable; 1 = Enable. Any access to the primary hard disk drive address range selected in F0 Index 93h[5] reloads GP Timer 1.

Revision 4.1 71 www.national.com Functional Description(Continued) Geode™ CS5530 F0 Index 8Ah General Purpose Timer 2 Count Register (R/W) Reset Value = 00h 7:0 General Purpose Timer 2 Count:This field represents the load value for GP Timer 2. This value can represent either an 8-bit or 16-bit counter (configured in F0 Index 8Bh[5]). It is loaded into the counter when the timer is enabled (F0 Index 83h[1] = 1). Once the timer is enabled and a transition occurs on GPIO7, the timer is re-loaded. The counter is decremented with each clock of the configured timebase. Upon expiration of the counter, an SMI is gener- ated and the top level of status is F1BAR+Memory Offset 00h/02h[9] and the second level of status is reported in F1BAR+Memory Offset 04h/06h[1]). Once expired, this counter must be re-initialized by either disabling and enabling it, or writing a new count value here. For GPIO7 to act as the reload for this counter, it must be enabled as such (F0 Index 8Bh[2]) and be configured as an input (F0 Index 90h[7]). This counter’s timebase can be configured as 1 msec or 1 sec in F0 Index 8Bh[3]. F0 Index 8Bh General Purpose Timer 2 Control Register (R/W) Reset Value = 00h 7 Re-trigger General Purpose Timer 1 on Secondary Hard Disk Activity:0 = Disable; 1 = Enable. Any access to the secondary hard disk drive address range selected in F0 Index 93h[4] reloads GP Timer 1. 6 VGA Timer Base: Selects timebase for VGA Timer Register (F0 Index 8Eh): 0 = 1 ms; 1 = 32 µs. 5 General Purpose Timer 2 Shift:GP Timer 2 is treated as an 8-bit or 16-bit timer: 0 = 8-bit; 1 = 16-bit. As an 8-bit timer, the count value is loaded into GP Timer 2 Count Register (F0 Index 8Ah). As a 16-bit timer, the value loaded into GP Timer 2 Count Register is shifted left by eight bits, the lower eight bits become zero, and this 16-bit value is used as the count for GP Timer 2. 4 General Purpose Timer 1 Shift:GP Timer 1 is treated as an 8-bit or 16-bit timer: 0 = 8-bit; 1 = 16-bit. As an 8-bit timer, the count value is that loaded into GP Timer 1 Count Register (F0 Index 88h). As a 16-bit timer, the value loaded into GP Timer 1 Count Register is shifted left by eight bit, the lower eight bits become zero, and this 16-bit value is used as the count for GP Timer 1. 3 Time Basis for General Purpose Timer 2:Selects timebase for GP Timer 2 (F0 Index 8Ah): 0 = 1 sec; 1 = 1 msec. 2 Re-trigger General Purpose Timer 2 on GPIO7 Pin Transition:A configured transition on the GPIO7 pin reloads GP Timer 2 (F0 Index 8Ah): 0 = Disable; 1 = Enable. F0 Index 92h[7] selects whether a rising- or a falling-edge transition acts as a reload. For GPIO7 to work here, it must first be configured as an input (F0 Index 90h[7] = 0). 1:0 Reserved: Set to 0. Table 3-27. General Purpose Timers and Control Registers (Continued) Bit Description

www.national.com 72 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.4.3.3 ACPI Timer Register

The ACPI Timer Register (F1BAR+Memory Offset 1Ch or at I/O Port 121Ch in Silicon Revision 1.3 and above pro- vides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled (F0 Index 83h[5] = 1), an SMI is generated when bit 23 tog- gles. Table 3-28 shows the ACPI Timer Count register and the ACPI Timer SMI enable bit. V-ACPI I/O Register Space The register space designated as V-ACPI (Virtualized ACPI) I/O does not physically exist in the CS5530. ACPI is supported in the CS5530 by virtualizing this register space. In order for ACPI to be supported, the V-ACPI module must be included in the BIOS. The register descriptions that follow, are supplied here for reference only. Fixed Feature space registers are required to be imple- mented by all ACPI-compatible hardware. The Fixed Fea- ture registers in the V-ACPI solution are mapped to normal I/O space starting at offset AC00h. However, the designer can relocate this register space at compile time, hereafter referred to as ACPI_BASE. Registers within the V-ACPI I/O space must only be accessed on their defined boundaries. For example, BYTE aligned registers must not be accessed via WORD I/O instructions, WORD aligned registers must not be accessed as DWORD I/O instructions, etc. Table 3-29 summarizes the registers available in the V- ACPI I/O Register Space. The “Reference” column gives a table and page number where the bit formats for the regis- ters are located. Table 3-28. ACPI Timer Related Registers/Bits Bit Description F1BAR+Memory Offset 1Ch-1Fh (Note) ACPI Timer Count Register (RO) Reset Value = 00FFFFFCh ACPI_COUNT (Read Only): This read-only register provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled via F0 Index 83h[5], an SMI is generated when the MSB toggles. The MSB toggles every 2.343 seconds. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0]. 31:24 Reserved: Always returns 0. 23:0 Counter Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch in Silicon Revision 1.3 and above. F0 Index 83h Power Management Enable Register 4 (R/W) Reset Value = 00h 5 ACPI Timer SMI:Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch in Silicon Revision 1.3 and above): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0]. Table 3-29. V-ACPI I/O Register Space Summary ACPI_ BASE Type Align Length Name Reset Value Reference (Table 4- 32) 00h-03h R/W 4 4 P_CNT: Processor Control Register 00h Page 217 04h RO 1 1 P_LVL2: Enter C2 Power State Register 00h Page 217 05h -- 1 1 Reserved 00h Page 217 06h R/W 1 1 SMI_CMD: OS/BIOS Requests Register (ACPI enable/disable port) 00h Page 217 07h -- 1 1 Reserved 00h Page 218 08h-09h R/W 2 2 PM1A_STS: PM1A Status Register 00h Page 218 0Ah-0Bh R/W 2 2 PM1A_EN: PM1A Enable Register 00h Page 218 0Ch-0Dh R/W 4 2 PM1A_CNT: PM1A Control Register 00h Page 218 0Eh-0Fh R/W 2 2 SETUP_IDX: Setup Index Register (V-ACPI internal index register) 00h Page 219 10h-11h R/W 2 2 GPE0_STS: General Purpose Event 0 Status Register 00h Page 219 12h-13h R/W 2 2 GPE0_EN: General Purpose Event 0 Enable Register 00h Page 220 14h-17h R/W 4 4 SETUP_DATA: Setup Data Register (V-ACPI internal data register) 00h Page 220 18h-1Fh -- 8 Reserved -- For Future V-ACPI Implementations 00h Page 220

Revision 4.1 73 www.national.com Functional Description(Continued) Geode™ CS5530

3.4.3.4 General Purpose I/O Pins

The CS5530 provides up to eight GPIO (general purpose I/O) pins. Five of the pins (GPIO[7:4] and GPIO1) have alternate functions. Table 3-30 shows the bits used for GPIO pin function selection. Each GPIO pin can be configured as an input or output. GPIO[7:0] can be independently configured to act as edge-sensitive SMI events. Each pin can be enabled and configured to be either positive-edge sensitive or nega- tive-edge sensitive. These pins then cause an SMI to be generated when an appropriate edge condition is detected. The power management status registers indi- cate that a GPIO external SMI event has occurred. The GPIO Pin Direction Register 1 (F0 Index 90h) selects whether the GPIO pin is an input or output. The GPIO Pin Data Register 1 (F0 Index 91h) contains the direct values of the GPIO pins. Write operations are valid only for bits defined as output. Reads from this register will read the last written value if the pin is an output. GPIO Control Register 1 (F0 Index 92h) configures the operation of the GPIO pins for their various alternate func- tions. Bits [5:3] set the edge sensitivity for generating an SMI on the GPIO[2:0] (input) pins respectively. Bits [2:0] enable the generation of an SMI. Bit 6 enables GPIO6 to act as the lid switch input. Bit 7 determines which edge transition will cause the General Purpose Timer 2 (F0 Index 8Ah) to reload. Table 3-31 shows the bit formats for the GPIO pin configu- ration and control registers. Table 3-30. GPIO Pin Function Selection Bit Description F0 Index 43h USB Shadow Register (R/W) Reset Value = 03h 6 Enable SA20:Pin AD22 configuration: 0 = GPIO4; 1 = SA20. If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20. 2 Enable SA[23:20]:Pins AF23, AE23, AC21, and AD22 configuration: 0 = GPIO[7:4]; 1 = SA[23:20]. If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20. F3BAR+Memory Offset 08h-0Bh Codec Status Register (R/W) Reset Value = 00000000h 21 Enable SDATA_IN2: Pin AE24 functions as: 0 = GPIO1; 1 = SDATA_IN2. For this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0). Table 3-31. GPIO Pin Configuration/Control Registers Bit Description F0 Index 90h GPIO Pin Direction Register 1 (R/W) Reset Value = 00h 7 GPIO7 Direction:Selects if GPIO7 is an input or output: 0 = Input; 1 = Output. 6 GPIO6 Direction:Selects if GPIO6 is an input or output: 0 = Input; 1 = Output. 5 GPIO5 Direction:Selects if GPIO5 is an input or output: 0 = Input; 1 = Output. 4 GPIO4 Direction:Selects if GPIO4 is an input or output: 0 = Input; 1 = Output. 3 GPIO3 Direction:Selects if GPIO3 is an input or output: 0 = Input; 1 = Output. 2 GPIO2 Direction:Selects if GPIO2 is an input or output: 0 = Input; 1 = Output. 1 GPIO1 Direction:Selects if GPIO1 is an input or output: 0 = Input; 1 = Output. 0 GPIO0 Direction:Selects if GPIO0 is an input or output: 0 = Input; 1 = Output. Note: Several of these pins have specific alternate functions. The direction configured here must be consistent with the pins’ use as the alternate function. F0 Index 91h GPIO Pin Data Register 1 (R/W) Reset Value = 00h 7 GPIO7 Data:Reflects the level of GPIO7: 0 = Low; 1 = High. 6 GPIO6 Data:Reflects the level of GPIO6: 0 = Low; 1 = High. 5 GPIO5 Data:Reflects the level of GPIO5: 0 = Low; 1 = High. 4 GPIO4 Data:Reflects the level of GPIO4: 0 = Low; 1 = High. 3 GPIO3 Data:Reflects the level of GPIO3: 0 = Low; 1 = High. 2 GPIO2 Data:Reflects the level of GPIO2: 0 = Low; 1 = High. 1 GPIO1 Data:Reflects the level of GPIO1: 0 = Low; 1 = High. 0 GPIO0 Data:Reflects the level of GPIO0: 0 = Low; 1 = High. Note: This register contains the direct values of GPIO[7:0] pins. Write operations are valid only for bits defined as output. Reads from this register will read the last written value if the pin is an output. The pins are configured as inputs or outputs in F0 Index 90h.

www.national.com 74 Revision 4.1 Functional Description(Continued) Geode™ CS5530 F0 Index 92h GPIO Control Register 1 (R/W) Reset Value = 00h

7 GPIO7 Edge Sense for Reload of General Purpose Timer 2:Selects which edge transition of GPIO7 causes

GP Timer 2 to reload: 0 = Rising; 1 = Falling, (Note 2) 6 GPIO6 Enabled as Lid Switch:Allows GPIO6 to act as the lid switch input: 0 = GPIO6; 1 = Lid switch. When enabled, every transition of the GPIO6 pin causes the lid switch status to toggle and generate an SMI. The top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[3]. If GPIO6 is enabled as the lid switch, F0 Index 87h/F7h[4] reports the current status of the lid’s position.

5 GPIO2 Edge Sense for SMI:Selects which edge transition of the GPIO2 pin generates an SMI:

0 = Rising; 1 = Falling. Bit 2 must be set to enable this bit.

4 GPIO1 Edge Sense for SMI:Selects which edge transition of the GPIO1 pin generates an SMI:

0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit.

3 GPIO0 Edge Sense for SMI:Selects which edge transition of the GPIO0 pin generates an SMI:

0 = Rising; 1 = Falling. Bit 0 must be set to enable this bit. 2 Enable GPIO2 as an External SMI Source:Allow GPIO2 to be an external SMI source and generate an SMI on either a rising or falling edge transition (depends upon setting of bit 5): 0 = Disable; 1 = Enable (Note 3). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[7]. 1 Enable GPIO1 as an External SMI Source:Allow GPIO1 to be an external SMI source and generate an SMI on either a rising- or falling-edge transition (depends upon setting of bit 4): 0 = Disable; 1 = Enable (Note 3). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[6]. 0 Enable GPIO0 as an External SMI Source:Allow GPIO0 to be an external SMI source and generate an SMI on either a rising or falling edge transition (depends upon setting of bit 3): 0 = Disable; 1 = Enable (Note 3) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[5]. Notes:1) For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h). 2) GPIO7 can generate an SMI (F0 Index 97h[3]) or re-trigger General Purpose Timer 2 (F0 Index 8Bh[2]) or both. 3) If GPIO[2:0] are enabled as external SMI sources, they are the only GPIOs that can be used as SMI sources to wake-up the system from Suspend when the clocks are stopped. Table 3-31. GPIO Pin Configuration/Control Registers (Continued) Bit Description

Revision 4.1 75 www.national.com Functional Description(Continued) Geode™ CS5530

3.4.3.5 Power Management SMI Status Reporting

The CS5530 updates status registers to reflect the SMI sources. Power management SMI sources are the device idle timers, address traps, and general purpose I/O pins. Power management events are reported to the processor through the SMI# pin. It is active low. When an SMI is initi- ated, the SMI# pin is asserted low and is held low until all SMI sources are cleared. At that time, SMI# is deas- serted. All SMI sources report to the Top Level SMI Status Regis- ter (F1BAR+Memory Offset 02h) and the Top Level SMI Status Mirror Register (F1BAR+Memory Offset 00h). The Top SMI Status and Status Mirror Registers are the top level of hierarchy for the SMI Handler in determining the source of an SMI. These two registers are identical except that reading the register at F1BAR+Memory Offset 02h clears the status. Since all SMI sources report to the Top Level SMI Status Register, many of its bits combine a large number of events requiring a second level of SMI status reporting. The second level of SMI status reporting is set up very much like the top level. There are two status reporting reg- isters, one “read only” (mirror) and one “read to clear”. The data returned by reading either offset is the same, the difference between the two being that the SMI can not be cleared by reading the mirror register. Figure 3-7 shows an example SMI tree for checking and clearing the source of General Purpose Timers and the User Defined Trap generated SMI. Table 3-32 shows the bit formats of the read to clear Top Level SMI Status Register (F1BAR+Memory Offset 02h). T a b l e3 - 3 3s h o w st h eb i tf o r m a t so ft h er e a dt oc l e a rs e c - ond level SMI status registers. For information regarding the location of the corresponding mirror register, refer to the note in the footer of the register description. Keep in mind, all SMI sources in the CS5530 are reported into the T op Level SMI Status Registers (F1BAR+Memory Offset 00h/02h); however, this discussion is regarding power management SMIs. For details regarding audio SMI events/reporting, refer to Section 3.7.2.2 “Audio SMI Related Registers” on page 120. Index 97h GPIO Control Register 2 (R/W) Reset Value = 00h

7 GPIO7 Edge Sense for SMI:Selects which edge transition of the GPIO7 pin generates an SMI:

0 = Rising; 1 = Falling. Bit 3 must be set to enable this bit.

6 GPIO5 Edge Sense for SMI:Selects which edge transition of the GPIO5 pin generates an SMI:

0 = Rising; 1 = Falling. Bit 2 must be set to enable this bit.

5 GPIO4 Edge Sense for SMI:Selects which edge transition of the GPIO4 pin generates an SMI:

0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit.

4 GPIO3 Edge Sense for SMI:Selects which edge transition of the GPIO3 pin will cause an external SMI:

0 = Rising; 1 = Falling. Bit 0 must be set to enable this bit. 3 Enable GPIO7 as an External SMI Source:Allow GPIO7 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 7): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[3]. 2 Enable GPIO5 as an External SMI Source:Allow GPIO5 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 6): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[2]. 1 Enable GPIO4 as an External SMI Source:Allow GPIO4 to be an external SMI source and to generate an SMI on either a rising- or falling-edge transition (depends upon setting of bit 5): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[1]. 0 Enable GPIO3 as an External SMI Source:Allow GPIO3 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 4) 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[0]. Note: For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h). Table 3-31. GPIO Pin Configuration/Control Registers (Continued) Bit Description

www.national.com 76 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Figure 3-7. General Purpose Timer and UDEF Trap SMI Tree Example SMI# Asserted SMM software reads SMI Header If Bit X = 0 (Internal SMI) If Bit X = 1 (External SMI) Call internal SMI handler to take appropriate action Geode™ CS5530 F1BAR+Memory Read to Clear to determine top-level source of SMI F1BAR+Memory Offset 06h Read to Clear Bits [15:10] Bits [8:0] Bit 9 GTMR_TRP_SMI Offset 02h Geode™ to determine second-level source of SMI Bit 5 PCI_TRP_SMI Bit 4 UDEF3_TRP_SMI Bit 3 UDEF2_TRP_SMI Bit 2 UDEF1_TRP_SMI Bit 1 GPT2_SMI Bit 0 GPT1_SMI Take Appropriate ActionOther_SMI Other_SMI If bit 9 = 1, Source of SMI is GP Timer or UDEF Trap Bits 15:6 RSVD Top Level Second Level SMI Deasserted after all SMI Sources are Cleared (i.e., Top and Second Levels - note some sources may have a Third Level) GXLV Processor

Revision 4.1 77 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-32. Top Level SMI Status Register (Read to Clear) Bit Description F1BAR+Memory Offset 02h-03h Top Level SMI Status Register (RC) Reset Value = 0000h 15 Suspend Modulation Enable Mirror (Read to Clear):This bit mirrors the Suspend Modulation Feature Enable bit (F0 Index 96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR+Memory Offset 08h) must be cleared on exit. 14 SMI Source is USB (Read to Clear):SMI was caused by USB activity? 0 = No; 1 = Y es. SMI generation is configured in F0 Index 42h[7:6]. 13 SMI Source is Warm Reset Command (Read to Clear):SMI was caused by Warm Reset command? 0=N o ;1=Y e s . 12 SMI Source is NMI (Read to Clear):SMI was caused by NMI activity? 0 = No; 1 = Y es. 11:10 Reserved (Read to Clear):Always reads 0. 9 SMI Source is General Purpose Timers/User Defined Device Traps/Register Space Trap (Read to Clear):SMI was caused by expiration of GP Timer 1/2; trapped access to UDEF3/2/1; trapped access to F1-F4 or ISA Legacy Register Space? 0 = No; 1 = Y es. The next level of status is found at F1BAR+Memory Offset 04h/06h. 8 SMI Source is Software Generated (Read to Clear):SMI was caused by software? 0 = No; 1 = Yes. 7 SMI on an A20M# Toggle (Read to Clear):SMI was caused by an access to either Port 092h or the keyboard command which initiates an A20M# SMI? 0 = No; 1 = Y es. This method of controlling the internal A20M# in the GXLV processor is used instead of a pin. SMI generation enabling is at F0 Index 53h[0].

6 SMI Source is a VGA Timer Event (Read to Clear):SMI was caused by the expiration of the VGA Timer

(F0 Index 8Eh)? 0 = No; 1 = Y es. SMI generation enabling is at F0 Index 83h[3]. 5 SMI Source is Video Retrace (IRQ2) (Read to Clear):SMI was caused by a video retrace event as decoded from the serial connection (PSERIAL register, bit 7) from the GXLV processor? 0 = No; 1 = Yes. SMI generation enabling is at F0 Index 83h[2]. 4:2 Reserved (Read to Clear):Always reads 0. 1 SMI Source is Audio Interface (Read to Clear):SMI was caused by the audio interface? 0 = No; 1 = Y es. The next level SMI status registers is found in F3BAR+Memory Offset 10h/12h.

0 SMI Source is Power Management Event (Read to Clear):SMI was caused by one of the power management

resources? 0 = No; 1 = Yes. The next level of status is found at F0 Index 84h-87h/F4h-F7h. Note: The status for the General Purpose Timers and the User Device Defined Traps are checked separately in bit 9. Note: Reading this register clears all the SMI status bits. Note that bits 9, 1, and 0 have another level (second) of status reporting. A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 00h. If the value of the register must be read with- out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.

www.national.com 78 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) Bit Description F1BAR+Memory Offset 06h-07h Second Level General Traps/Timers Reset Value = 0000h SMI Status Register (RC) 15:6 Reserved (Read to Clear) 5 PCI Function Trap (Read to Clear):SMI was caused by a trapped configuration cycle (listed below)? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. Trapped Access to F1 Register Space; SMI generation enabling is at F0 Index 41h[3]. Trapped Access to F2 Register Space; SMI generation enabling is at F0 Index 41h[6]. Trapped Access to F3 Register Space; SMI generation enabling is at F0 Index 42h[0]. Trapped Access to F4 Register Space; SMI generation enabling is at F0 Index 42h[1]. Trapped Access to ISA Legacy I/O Register Space; SMI generation enabling is at F0 Index 41h[0]. 4 SMI Source is Trapped Access to User Defined Device 3 (Read to Clear):SMI was caused by a trapped I/O or mem- ory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[6]. 3 SMI Source is Trapped Access to User Defined Device 2 (Read to Clear):SMI was caused by a trapped I/O or mem- ory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[5]. 2 SMI Source is Trapped Access to User Defined Device 1 (Read to Clear):SMI was caused by a trapped I/O or mem- ory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[4]. 1 SMI Source is Expired General Purpose Timer 2 (Read to Clear):SMI was caused by the expiration of General Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[1]. 0 SMI Source is Expired General Purpose Timer 1 (Read to Clear):SMI was caused by the expiration of General Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[0]. Note: Reading this register clears all the SMI status bits. A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 04h. If the value of the register must be read with- out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.

Revision 4.1 79 www.national.com Functional Description(Continued) Geode™ CS5530 F0 Index F4h Second Level Power Management Status Register 1 (RC) Reset Value = 00h 7:5 Reserved 4 Game Port SMI Status (Read to Clear):SMI was caused by a R/W access to game port (I/O Port 200h and 201h)? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. Game Port Read SMI generation enabling is at F0 Index 83h[4]. Game Port Write SMI generation enabling is at F0 Index 53h[3]. 3 GPIO7 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO7 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[3]. 2 GPIO5 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO5 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[2]. 1 GPIO4 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO4 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[1]. 0 GPIO3 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO3 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[0]. Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI. This register provides status on various power-management SMI events. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 84h. Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued) Bit Description

www.national.com 80 Revision 4.1 Functional Description(Continued) Geode™ CS5530 F0 Index F5h Second Level Power Management Status Register 2 (RC) Reset Value = 00h 7 Video Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Video Idle Timer Count Register (F0 Index A6h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[7]. 6 User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the UDEF3 Idle Timer Count Register (F0 Index A4h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[6]. 5 User Defined Device 2 (UDEF2) Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the UDEF2 Idle Timer Count Register (F0 Index A2h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[5]. 4 User Defined Device 1 (UDEF1) Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the UDEF1 Idle Timer Count Register (F0 Index A0h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[4]. 3 Keyboard/Mouse Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[3]. 2 Parallel/Serial Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[2]. 1 Floppy Disk Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Floppy Disk Idle Timer Count Register (F0 Index 9Ah)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[1]. 0 Primary Hard Disk Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Primary Hard Disk Idle Timer Count Register (F0 Index 98h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[0]. Note: This register provides status on the Device Idle Timers to the SMI handler. A bit set here indicates that the device was idle for the duration configured in the Idle Timer Count register for that device, causing an SMI. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 85h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), F0 Index 85h may be read instead. Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued) Bit Description

Revision 4.1 81 www.national.com Functional Description(Continued) Geode™ CS5530 F0 Index F6h Second Level Power Management Status Register 3 (RC) Reset Value = 00h 7 Video Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the Video I/O Trap? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[7].

6 Reserved (Read Only)

5 Secondary Hard Disk Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the secondary hard disk? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[6]. 4 Secondary Hard Disk Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Hard Disk Idle Timer Count Register (F0 Index ACh)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[7]. 3 Keyboard/Mouse Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the keyboard or mouse? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[3]. 2 Parallel/Serial Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to either the serial or parallel ports? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[2].

1 Floppy Disk Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the

floppy disk? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[1]. 0 Primary Hard Disk Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the primary hard disk? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[0]. Note: This register provides status on the Device Traps to the SMI handler. A bit set here indicates that an access occurred to the device while the trap was enabled, causing an SMI. Reading this register clears the SMI status bits. A read-only (mirror) ver- sion of this register exists at F0 Index 86h. If the value of the register must be read without clearing the SMI source (and con- sequently deasserting SMI), F0 Index 86h may be read instead. Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued) Bit Description

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3.4.3.6 Device Power Management Register Programming Summary

Table 3-34 provides a programming register summary of the device idle timers, address traps, and general purpose I/O pins. For complete bit information regarding the regis- ters listed in Table 3-34, refer to Section 4.3.1 “Bridge Configuration Registers - Function 0” on page 149 and Section 4.3.2 “SMI Status and ACPI Timer Registers - Function 1” on page 179. F0 Index F7h Second Level Power Management Status Register 4 (RO/RC) Reset Value = 00h 7 GPIO2 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO2 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[2]. 6 GPIO1 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO1 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[1]. 5 GPIO0 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO0 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[0]. 4 Lid Position (Read Only):This bit maintains the current status of the lid position. If the GPIO6 pin is configured as the lid switch indicator, this bit reflects the state of the pin. 3 Lid Switch SMI Status (Read to Clear):SMI was caused by a transition on the GPIO6 (lid switch) pin? 0=N o ;1=Y e s . For this to happen, the GPIO6 pin must be configured both as an input (F0 Index 90h[6] = 0) and as the lid switch (F0 Index 92h[6] =1). 2 Codec SDATA_IN SMI Status (Read to Clear):SMI was caused by an AC97 codec producing a positive edge on SDA TA_IN? 0 = No; 1 = Y es. This is the second level of status is reporting. The top level status is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 80h[5]. 1 RTC Alarm (IRQ8) SMI Status (Read to Clear):SMI was caused by an RTC interrupt? 0 = No; 1 = Y es. This SMI event can only occur while in 3V Suspend and RTC interrupt occurs. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. 0 ACPI Timer SMI Status (Read to Clear):SMI was caused by an ACPI Timer MSB toggle? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation configuration is at F0 Index 83h[5]. Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI. This register provides status on several miscellaneous power management events that generate SMIs, as well as the status of the Lid Switch. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 87h. Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued) Bit Description

Revision 4.1 83 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-34. Device Power Management Programming Summary Device Power Management Resource Located at F0 Index xxh Unless Otherwise Noted Enable Configuration Second Level SMI Status/No Clear Second Level SMI Status/With Clear Global Timer Enable 80h[1] N/A N/A N/A Keyboard / Mouse Idle Timer 81h[3] 93h[1:0] 85h[3] F5h[3] Parallel / Serial Idle Timer 81h[2] 93h[1:0] 85h[2] F5h[2] Floppy Disk Idle Timer 81h[1] 9Ah[15:0], 93h[7] 85h[1] F5h[1] Video Idle Timer (Note 1) 81h[7] A6h[15:0] 85h[7] F5h[7] VGA Timer (Note 2) 83h[3] 8Eh[7:0] F1BAR+Memory Offset 00h[6] F1BAR+Memory Offset 02h[6] Primary Hard Disk Idle Timer 81h[0] 98h[15:0], 93h[5] 85h[0] F5h[0] Secondary Hard Disk Idle Timer 83h[7] ACh[15:0], 93h[4] 86h[4] F6h[4] User Defined Device 1 Idle Timer 81h[4] A0h[15:0], C0h[31:0], CCh[7:0] 85h[4] F5h[4] User Defined Device 2 Idle Timer 81h[5] A2h[15:0], C4h[31:0], CDh[7:0] 85h[5] F5h[5] User Defined Device 3 Idle Timer 81h[6] A4h[15:0], C8h[31:0], CEh[7:0] 85h[6] F5h[6] Global Trap Enable 80h[2] N/A N/A N/A Keyboard / Mouse Trap 82h[3] 9Eh[15:0] 93h[1:0] 86h[3] F6h[3] Parallel / Serial Trap 82h[2] 9Ch[15:0], 93h[1:0] 86h[2] F6h[2] Floppy Disk Trap 82h[1] 93h[7] 86h[1] F6h[1] Video Access Trap 82h[7] N/A 86h[7] F6h[7] Primary Hard Disk Trap 82h[0] 93h[5] 86h[0] F6h[0] Secondary Hard Disk Trap 83h[6] 93h[4] 86h[5] F6h[5] User Defined Device 1 Trap 82h[4] C0h[31:0], CCh[7:0] F1BAR+Memory Offset 04h[2] F1BAR+Memory Offset 06h[2] User Defined Device 2 Trap 82h[5] C4h[31:0], CDh[7:0] F1BAR+Memory Offset 04h[3] F1BAR+Memory Offset 06h[3] User Defined Device 3 Trap 82h[6] C8h[31:0], CEh[7:0] F1BAR+Memory Offset 04h[4] F1BAR+Memory Offset 06h[4] General Purpose Timer 1 83h[0] 88h[7:0], 89h[7:0], 8Bh[4] F1BAR+Memory Offset 04h[0] F1BAR+Memory Offset 06h[0] General Purpose Timer 2 83h[1] 8Ah[7:0], 8Bh[5,3,2] F1BAR+Memory Offset 04h[1] F1BAR+Memory Offset 06h[1] GPIO7 Pin N/A 90h[7], 91h[7], 92h[7], 97h[7,3] 91h[7] N/A GPIO6 Pin N/A 90h[6], 91h[6], 92h[6] 87h[4,3], 91h[6] F7h[4,3] GPIO5 Pin N/A 90h[5], 91h[5], 97h[6,2] 91h[5] N/A GPIO4 Pin N/A 90h[4], 91h[4], 97h[5,1] 91h[4] N/A GPIO3 Pin N/A 90h[3], 91h[3], 97h[4,0] 91h[3] N/A GPIO2 Pin N/A 90h[2], 91h[2], 92h[5,2] 87h[7], 91h[2] F7h[7] GPIO1 Pin N/A 90h[1], 91h[1] 92h[4,1] 87h[6], 91h[1] F7h[6] GPIO0 Pin N/A 90h[0], 91h[0], 92h[3,0] 87h[5], 91h[0] F7h[5] Suspend Modulation OFF/ON Video Speedup IRQ Speedup 96h[0] 80h[4] 80h[3] 94h[7:0]/95h[7:0] 8Dh[7:0] 8Ch[7:0] N/A A8h[15:0] N/A N/A N/A N/A Note: 1. This function is used for Suspend determination. 2. This function is used for SoftVGA.

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3.5 PC/AT COMPATIBILITY LOGIC

The CS5530’s PC/AT compatibility logic provides support for the standard PC architecture. This subsystem also provides legacy support for existing hardware and soft- ware. Support functions for the GXLV processor provided by these subsystems include:  ISA Subtractive Decode  ISA Bus Interface - Delayed PCI Transactions - Limited ISA and ISA Master Modes  ROM Interface  Megacells - Direct Memory Access (DMA) - Programmable Interval Timer - Programmable Interrupt Controller - PCI Compatible Interrupts - System Control I/O Port 092h and 061h - Keyboard Interface Function - External Real-Time Clock Interface The following subsections give a detailed description for each of these functions.

3.5.1 ISA Subtractive Decode

The CS5530 provides an ISA bus controller. The CS5530 is the default subtractive-decoding agent, and forwards all unclaimed memory and I/O cycles to the ISA interface. However, the CS5530 can be configured using F0 Index 04h[1:0] to ignore either I/O, memory, or all unclaimed cycles (subtractive decode disabled, F0 Index 41h[2:1] = 1x (Table 3-35). Table 3-35. Cycle Configuration Bits Bit Description F0 Index 04h-05h PCI Command Register (R/W) Reset Value = 0000h 0 = Disable; 1 = Enable(Default). 0 I/O Space:Allow the CS5530 to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable(Default). F0 Index 41h PCI Function Control Register 2 (R/W) Reset Value = 10h 2:1 Subtractive Decode:These bits determine the point at which the CS5530 accepts cycles that are not claimed by another device. The CS5530 defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively. 00 = Default sample (4th clock from FRAME# active) 01 = Slow sample (3rd clock from FRAME# active) 1x = No subtractive decode

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3.5.2 ISA Bus Interface

The ISA bus controller issues multiple ISA cycles to sat- isfy PCI transactions that are larger than 16 bits. A full 32- bit read or write results in two 16-bit ISA transactions or four 8-bit ISA transactions. The ISA controller gathers the data from multiple ISA read cycles and returns TRDY# only after all of the data can be presented to the PCI bus at the same time. SA[23:0] are a concatenation of ISA LA[23:17] and SA[19:0] and perform equivalent functionality at a reduced pin count. Figure 3-8 shows the relationship between a PCI cycle and the corresponding ISA cycle generated. Figure 3-8. Non-Posted PCI-to-ISA Access PCI_CLK ISACLK FRAME# IRDY# TRDY# AD[31:0] (Read) IOR#/IOW# AD[31:0] (Write) BALE STOP# MEMR#/MEMW#

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3.5.2.1 Delayed PCI Transactions

If PCI delayed transactions are enabled (F0 Index 42h[5] = 1) multiple PCI cycles occur for every slower ISA cycle. Figure 3-9 shows the relationship of PCI cycles to an ISA cycle with PCI delayed transactions enabled. See Section 3.2.6 “Delayed Transactions” on page 48 for additional information. Figure 3-9. PCI to ISA Cycles with Delayed Transaction Enabled REQ# GNT# FRAME# IRDY# TRDY# STOP# IOR# BALE PCI 1 1 1-D e l a y 2 - IDE bus master - starts and completes 3 - End of ISA cycle ISA

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3.5.2.2 Limited ISA and ISA Master Modes

The CS5530 supports two modes on the ISA interface. The default mode of the ISA bus is a fully functional ISA mode, but it does not support ISA masters, as shown in Figure 3-10 “Limited ISA Mode”. When in this mode, the address and data buses are multiplexed together, requir- i n ga ne x t e r n a ll a t c ht ol a t c ht h el o w e r1 6b i t so fa d d r e s s of the ISA cycle. The signal SA_LATCH is generated when the data on the SA/SD bus is a valid address. Addi- tionally, the upper four address bits, SA[23:20], are multi- plexed on GPIO[7:4]. The second mode of the ISA interface supports ISA bus masters, as shown in Figure 3-11. When the CS5530 is placed in the ISA Master mode, a large number of pins are redefined as shown in Table 3-36. In this mode of operation, the CS5530 cannot support TFT flat panels or TV controllers, since most of the signals used to support these functions have been redefined. This mode is required if ISA slots or ISA masters are used. ISA master cycles are only passed to the PCI bus if they access memory. I/O accesses are left to complete on the ISA bus. SA[15:0] and MASTER# are not 5.0V tolerant; therefore, the SA lines require a buffer and MASTER# should be pulled up to 3.3V (not 5.0V). The mode of operation is selected by the strapping of pin P26 (INTR):  I S AL i m i t e dM o d e—S t r a pp i nP 2 6( I N T R )l o wt h r o u g h a 10-kohm resistor.  ISA Master Mode — Strap pin P26 (INTR) high through a 10-kohm resistor. Bit 7 of F0 Index 44h[7] (bit details on page 152) reports t h es t r a pv a l u eo ft h eI N T Rp i n( p i nP 2 6 )d u r i n gP O R :0= ISA Limited; 1 = ISA Master. This bit can be written after POR# deassertion to change the ISA mode selected. Writing to this bit is not recom- mended due to the actual strapping done on the board. ISA memory and ISA refresh cycles are not supported by the CS5530. Although, the refresh toggle bit in I/O Port 061h still exists for software compatibility reasons. Note: If Limited ISA Mode of operation has been selected, SMEMW# and SMEMR# can be output on these pins by programming F0 Index 53[2] = 0 (bit details on page 154). Table 3-36. Signal Assignments Pin No. Limited ISA Mode ISA Master Mode AD15 SA_LATCH SA_DIR AE25, AD24, AE22, AE21, AF21, AC20, AD19, AF19, AF4, AF5, AD5, AF6, AC6, AD9, AE6, AE9 H2, K1, K2, L1, D1, E2, F1, G1, G3, G4, G2, H1, J 1 ,J 3 ,J 2 ,K 3 FP_DATA[15:0] SA[15:0] H3 FP_DATA[16] SA_OE# F3 FP_DATA[17] MASTER# E1 FP_HSYNC_OUT SMEMW# E3 FP_VSYNC_OUT SMEMR# AF3 (Note) SMEMW# RTCCS# AD4 (Note)S M E M R # R T C A L E AF23, AE23, AC21, AD22 GPIO[7:4] SA[23:20] SA[23:20]

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3.5.2.3 ISA Bus Data Steering

T h eC S 5 5 3 0p e r f o r m sa l lo ft h er e q u i r e dd a t as t e e r i n g from SD[7:0] to SD[15:0] during normal 8-bit ISA cycles, as well as during DMA and ISA master cycles. It handles data transfers between the 32-bit PCI data bus and the ISA bus. 8/16-bit devices can reside on the ISA bus. Vari- ous PC-compatible I/O registers, DMA controller registers, interrupt controller registers, and counter/timer registers lie on the on-chip I/O data bus. Either the PCI bus master o rt h eD M Ac o n t r o l l e r sc a nb e c o m et h eb u so w n e r . When the PCI bus master is the bus owner, the CS5530 data steering logic provides data conversion necessary for 8/16/32-bit transfers to and from 8/16-bit devices on either the ISA bus or the 8-bit registers on the on-chip I/O data bus. When PCI data bus drivers of the CS5530 are tristated, data transfers between the PCI bus master and PCI bus devices are handled directly via the PCI data bus. When the DMA requestor is the bus owner, the CS5530 allows 8/16-bit data transfer between the ISA bus and the PCI data bus.

3.5.2.4 I/O Recovery Delays

In normal operation, the CS5530 inserts a delay between back-to-back ISA I/O cycles that originate on the PCI bus. The default delay is four ISACLK cycles. Thus, the second of consecutive I/O cycles is held in the ISA bus controller until this delay count has expired. The delay is measured between the rising edge of IOR#/IOW# and the falling edge of BALE. This delay can be adjusted to a greater delay through the ISA I/O Recovery Control Register (F0 Index 51h, see Table 3-37). Note: This delay is not inserted for a 16-bit ISA I/O access that is split into two 8-bit I/O accesses. Table 3-37. I/O Recovery Programming Register Bit Description F0 Index 51h ISA I/O Recovery Control Register (R/W) Reset Value = 44h 7:4 8-Bit I/O Recovery:These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This count is in addition to a preset one-clock delay built into the controller. 0000 = 1 PCI clock 0100 = 5 PCI clocks 1000 = 9 PCI clocks 1100 = 13 PCI clocks 0001 = 2 PCI clocks 0101 = 6 PCI clocks 1001 = 10 PCI clocks 1101 = 14 PCI clocks 0010 = 3 PCI clocks 0110 = 7 PCI clocks 1010 = 11 PCI clocks 1110 = 15 PCI clocks 0011 = 4 PCI clocks 0111 = 8 PCI clocks 1011 = 12 PCI clocks 1111 = 16 PCI clocks 3:0 16-Bit I/O Recovery:These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This count is in addition to a preset one-clock delay built into the controller. 0000 = 1 PCI clock 0100 = 5 PCI clocks 1000 = 9 PCI clocks 1100 = 13 PCI clocks 0001 = 2 PCI clocks 0101 = 6 PCI clocks 1001 = 10 PCI clocks 1101 = 14 PCI clocks 0010 = 3 PCI clocks 0110 = 7 PCI clocks 1010 = 11 PCI clocks 1110 = 15 PCI clocks 0011 = 4 PCI clocks 0111 = 8 PCI clocks 1011 = 12 PCI clocks 1111 = 16 PCI clocks

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3.5.2.5 ISA DMA

DMA transfers occur between ISA I/O peripherals and system memory. The data width can be either 8 or 16 bits. Out of the seven DMA channels available, four are used for 8-bit transfers while the remaining three are used for 16-bit transfers. One BYTE or WORD is transferred in each DMA cycle. Note: The CS5530 does not support DMA transfers to ISA memory. The ISA DMA device initiates a DMA request by asserting o n eo ft h eD R Q [ 7 : 5 ,3 : 0 ]s i g n a l s .W h e nt h eC S 5 5 3 0 receives this request, it sends a bus grant request to the PCI arbiter. After the PCI bus has been granted, the r e s p e c t i v eD A C K #i sd r i v e na c t i v e . The CS5530 generates PCI memory read or write cycles in response to a DMA cycle. Figures 3-12 and 3-13 are examples of DMA memory read and memory write cycles. Upon detection of the DMA controller’s MEMR# or M E M W #a c t i v e ,t h eC S 5 5 3 0s t a r t st h eP C Ic y c l e ,a s s e r t s FRAME#, and negates an internal IOCHRDY . This assures the DMA cycle does not complete before the PCI cycle has provided or accepted the data. IOCHRDY is internally asserted when IRDY# and TRDY# are sampled active. Figure 3-12. ISA DMA Read from PCI Memory Figure 3-13. ISA DMA Write To PCI Memory PCICLK ISACLK MEMR# IOW# FRAME# AD[31:0] IRDY# TRDY# SD[15:0] IOCHRDY PCICLK ISACLK MEMW# IOR# FRAME# AD[31:0] IRDY# TRDY# SD[15:0] IOCHRDY

Revision 4.1 91 www.national.com Functional Description(Continued) Geode™ CS5530

3.5.3 ROM Interface

The CS5530 positively decodes memory addresses 000F0000h-000FFFFFh (64 KB) and FFFC0000h- FFFFFFFFh (256 KB) at reset. These memory cycles cause the CS5530 to claim the cycle, and generate an ISA bus memory cycle with KBROMCS# asserted. The CS5530 can also be configured to respond to memory addresses FF000000h-FFFFFFFFh (16 MB) and 000E0000h-000FFFFFh (128 KB). Flash ROM is supported in the CS5530 by enabling the KBROMCS# signal on write accesses to the ROM region. Normally only read cycles are passed to the ISA bus, and the KBROMCS# signal is suppressed. When the ROM Write Enable bit (F0 Index 52h[1]) is set, a write access to the ROM address region causes an 8-bit write cycle to occur with MEMW# and KBROMCS# asserted. Table 3-38 shows the ROM interface related programming bits.

3.5.4 Megacells

The CS5530 core logic integrates:  Two 8237-equivalent DMA controllers (DMAC) with full 32-bit addressing for DMA transfers.  Two 8259-equivalent interrupt controllers providing 13 individually programmable external interrupts.  An 8254-equivalent timer for refresh, timer, and speaker logic.  NMI control and generation for PCI system errors and all parity errors.  Support for standard AT keyboard controllers, reset control, and VSA technology audio. Table 3-38. ROM Interface Related Bits Bit Description F0 Index 52h ROM/AT Logic Control Register (R/W) Reset Value = F8h

2 Upper ROM Address Range: KBROMCS# is asserted for ISA memory read accesses:

0 = FFFC0000h-FFFFFFFFh (256 KB,Default); 1 = FF000000h-FFFFFFFFh (16 MB) Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]).

1 ROM Write Enable:Assert KBROMCS# during writes to configured ROM space (configured in bits 2 and 0),

allowing Flash programming: 0 = Disable; 1 = Enable.

0 Lower ROM Address Range: KBROMCS# is asserted for ISA memory read accesses:

0 = 000F0000h-000FFFFFh (64 KB,Default); 1 = 000E0000h-000FFFFFh (128 KB). Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]). F0 Index 5Bh Decode Control Register 2 (R/W) Reset Value = 20h 5 BIOS ROM Positive Decode:Selects PCI positive or subtractive decoding for accesses to the configured ROM space: 0 = Subtractive; 1 = Positive. ROM configuration is at F0 Index 52h[2:0].

www.national.com 92 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.5.4.1 Direct Memory Access (DMA)

The 8237-compatible DMA controllers on the CS5530 control transfers between ISA I/O devices and PCI or ISA memory. They generate a bus request to the PCI bus when an I/O device requests a DMA operation. Once they are granted the bus, the DMA transfer cycle occurs. DMA transfers can occur over the entire 32-bit address range of the PCI bus. The CS5530 contains registers for driving the high address bits (high page) and registers for generating the middle address bits (low page) output by the 8237 control- ler. DMA Controllers The CS5530 supports seven DMA channels using two standard 8237-equivalent controllers. DMA Controller 1 contains Channels 0 through 3 and supports 8-bit I/O adapters. These channels are used to transfer data between 8-bit peripherals and PCI memory or 8/16-bit ISA memory. Using the high and low page address registers, a full 32-bit PCI address is output for each channel so they can all transfer data throughout the entire 4 GB system address space. Each channel can transfer data in 64 KB pages. DMA Controller 2 contains Channels 4 through 7. Chan- nel 4 is used to cascade DMA Controller 1, so it is not available externally. Channels 5 through 7 support 16-bit I/O adapters to transfer data between 16-bit I/O adapters and 16-bit system memory. Using the high and low page address registers, a full 32-bit PCI address is output for each channel so they can all transfer data throughout the entire 4 GB system address space. Each channel can transfer data in 128 KB pages. Channels 5, 6, and 7 trans- fer 16-bit words on even byte boundaries only. DMA Transfer Modes Each DMA channel can be programmed for single, block, demand or cascade transfer modes. In the most com- monly used mode, single transfer mode, one DMA cycle occurs per DRQ and the PCI bus is released after every cycle. This allows the CS5530 to timeshare the PCI bus with the CPU. This is imperative, especially in cases involving large data transfers, because the CPU gets locked out for too long. In block transfer mode, the DMA controller executes all of its transfers consecutively without releasing the PCI bus. In demand transfer mode, DMA transfer cycles continue to occur as long as DRQ is high or terminal count is not reached. In this mode, the DMA controller continues to execute transfer cycles until the I/O device drops DRQ to indicate its inability to continue providing data. For this case, the PCI bus is held by the CS5530 until a break in the transfers occurs. In cascade mode, the channel is connected to another DMA controller or to an ISA bus master, rather than to an I/O device. In the CS5530, one of the 8237 controllers is designated as the master and the other as the slave. The HOLD output of the slave is tied to the DRQ0 input of the master (Channel 4), and the master’s DACK0# output is tied to the slave’s HLDA input. In each of these modes, the DMA controller can be pro- grammed for read, write, or verify transfers. Both DMA controllers are reset at Power On Reset (POR) to fixed priority. Since master Channel 0 is actually con- nected to the slave DMA controller, the slave’s four DMA channels have the highest priority, with Channel 0 as highest and Channel 3 as the lowest. Immediately follow- ing slave Channel 3, master Channel 1 (Channel 5) is the next highest, followed by Channels 6 and 7. DMA Controller Registers The DMA controller can be programmed with standard I/O cycles to the standard register space for DMA. The I/O addresses of all registers for the DMA controller are listed in Table 4-25 "DMA Channel Control Registers" on page 208. Addresses under Master are for the 16-bit DMA channels, and Slave corresponds to the 8-bit channels. When writ- ing to a channel's address or word-count register, the data is written into both the base register and the current regis- ter simultaneously. When reading a channel address or word count register, only the current address or word count can be read. The base address and base word count are not accessible for reading. DMA Transfer Types Each of the seven DMA channels may be programmed to perform one of three types of transfers: read, write, or ver- i f y .T h et r a n s f e rt y p es e l e c t e dd e f i n e st h em e t h o du s e dt o transfer a BYTE or WORD during one DMA bus cycle. For read transfer types, the CS5530 reads data from m e m o r ya n dw r i t e si tt ot h eI / Od e v i c ea s s o c i a t e dw i t ht h e DMA channel. For write transfer types, the CS5530 reads data from the I/O device associated with the DMA channel and writes to the memory. The verify transfer type causes the CS5530 to execute DMA transfer bus cycles, including generation of memory addresses, but neither the Read nor Write command lines are activated. This transfer type was used by DMA Chan- nel 0 to implement DRAM refresh in the original IBM PC/XT™. DMA Priority The DMA controller may be programmed for two types of priority schemes: fixed and rotate (I/O Ports 008h[4] and 0D0h[4], as shown in T able 4-25 "DMA Channel Control Registers" on page 208. In fixed priority, the channels are fixed in priority order based on the descending values of their numbers. Thus, Channel 0 has the highest priority. In rotate priority, the last channel to get service becomes the lowest-priority

Revision 4.1 93 www.national.com Functional Description(Continued) Geode™ CS5530 channel with the priority of the others rotating accordingly. This prevents a channel from dominating the system. The address and word count registers for each channel are 16-bit registers. The value on the data bus is written into the upper byte or lower byte, depending on the state of the internal addressing byte pointer. This pointer can be cleared by the Clear Byte Pointer command. After this command, the first read/write to an address or word count register will read/write to the low byte of the 16-bit register and the byte pointer will point to the high byte. The next read/write to an address or word-count register will read or write to the high byte of the 16-bit register and the byte pointer will point back to the low byte. When programming the 16-bit channels (Channels 5, 6, and 7), the address which is written to the base address register must be the real address divided by two. Also, the base word count for the 16-bit channels is the number of 16-bit words to be transferred, not the number of bytes as is the case for the 8-bit channels. T h eD M Ac o n t r o l l e ra l l o w st h eu s e rt op r o g r a mt h ea c t i v e level (low or high) of the DRQ and DACK# signals. Since the two controllers are cascaded together internally on the chip, these signals should always be programmed with the DRQ signal active high and the DACK# signal active low. DMA Shadow Registers The CS5530 contains a shadow register located at F0 Index B8h (T able 3-39) for reading the configuration of the DMA controllers. This read-only register can sequence to read through all of the DMA registers. DMA Addressing Capability DMA transfers occur over the entire 32-bit address range of the PCI bus. This is accomplished by using the DMA controller’s 16-bit memory address registers in conjunc- tion with an 8-bit DMA Low Page register and an 8-bit DMA High Page register. These registers, associated with each channel, provide the 32-bit memory address capa- bility. A write to the Low Page register clears the High Page register, for backward compatibility with the PC/AT standard. The starting address for the DMA transfer must be programmed into the DMA controller registers and the channel’s respective Low and High Page registers prior to beginning the DMA transfer. DMA Page Registers and Extended Addressing The DMA Page registers provide the upper address bits during DMA cycles. DMA addresses do not increment or decrement across page boundaries. Page boundaries for the 8-bit channels (Channels 0 through 3) are every 64 KB and page boundaries for the 16-bit channels (Chan- nels 5, 6, and 7) are every 128 KB. Before any DMA operations are performed, the Page Registers must be written at the I/O Port addresses shown in Table 4-26 "DMA Page Registers" on page 211 to select the correct page for each DMA channel. The other address locations between 080h and 08Fh and 480h and 48Fh are not used by the DMA channels, but c a nb er e a do rw r i t t e nb yaP C Ib u sm a s t e r .T h e s er e g i s - ters are reset to zero at POR. A write to the Low Page register clears the High Page register, for backward com- patibility with the PC/AT standard. For most DMA transfers, the High Page register is set to zeros and is driven onto PCI address bits AD[31:24] dur- ing DMA cycles. This mode is backward compatible with the PC/AT standard. For DMA extended transfers, the High Page register is programmed and the values are driven onto the PCI addresses AD[31:24] during DMA cycles to allow access to the full 4 GB PCI address space. DMA Address Generation The DMA addresses are formed such that there is an upper address, a middle address, and a lower address portion. The upper address portion, which selects a specific page, is generated by the Page registers. The Page registers for each channel must be set up by the system before a DMA operation. The DMA Page register values are driven on PCI address bits AD[31:16] for 8-bit channels and AD[31:17] for 16-bit channels. Table 3-39. DMA Shadow Register Bit Description F0 Index B8h DMA Shadow Register (RO) Reset Value = xxh 7:0 DMA Shadow (Read Only): This 8-bit port sequences through the following list of shadowed DMA Controller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. DMA Channel 0 Mode Register 2. DMA Channel 1 Mode Register 3. DMA Channel 2 Mode Register 4. DMA Channel 3 Mode Register 5. DMA Channel 4 Mode Register 6. DMA Channel 5 Mode Register 7. DMA Channel 6 Mode Register 8. DMA Channel 7 Mode Register 9. DMA Channel Mask Register (bit 0 is channel 0 mask, etc.) 10. DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1 msec, all other bits are 0)

www.national.com 94 Revision 4.1 Functional Description(Continued) Geode™ CS5530 The middle address portion, which selects a block within the page, is generated by the DMA controller at the begin- ning of a DMA operation and any time the DMA address increments or decrements through a block boundary. Block sizes are 256 bytes for 8-bit channels (Channels 0 through 3) and 512 bytes for 16-bit channels (Channels 5, 6 ,a n d7 ) .T h em i d d l ea d d r e s sb i t sa r ed r i v e no nP C I address bits AD[15:8] for 8-bit channels and AD[16:9] for 16-bit channels. The lower address portion is generated directly by the DMA controller during DMA operations. The lower address bits are output on PCI address bits AD[7:0] for 8- bit channels and AD[8:1] for 16-bit channels. SBHE# is configured as an output during all DMA opera- tions. It is driven as the inversion of AD0 during 8-bit DMA cycles and forced low for all 16-bit DMA cycles.

3.5.4.2 Programmable Interval Timer

The CS5530 contains an 8254-equivalent Programmable Interval Timer (PIT) configured as shown in Figure 3-14. T h eP I Th a st h r e et i m e r s / c o u n t e r s ,e a c hw i t ha ni n p u tf r e - quency of 1.19318 MHz (OSC divided by 12), and individ- ually programmable to different modes. The gates of Counter 0 and 1 are usually enabled, how- ever, they can be controlled via F0 Index 50h (see T able 3- 40). The gate of Counter 2 is connected to I/O Port 061h[0]. The output of Counter 0 is connected internally to IRQ0. This timer is typically configured in Mode 3 (square wave output), and used to generate IRQ0 at a periodic rate to be used as a system timer function. The output of Counter 1 is connected to I/O Port 061h[4]. The reset state of I/O Port 061h[4] is 0 and every falling edge of Counter 1 output causes I/O Port 061h[4] to flip states. The output of Counter 2 is brought out to the PC_BEEP output. This output is gated with I/O Port 061h[1]. Figure 3-14. PIT Timer Table 3-40. PIT Control and I/O Port 061h Associated Register Bits Bit Description F0 Index 50h PIT Control/ISA CLK Divider (R/W) Reset Value = 7Bh 7 PIT Software Reset:0 = Disable; 1 = Enable.

6 PIT Counter 1:0 = Forces Counter 1 output (OUT1) to zero;

1 = Allows Counter 1 output (OUT1) to pass to I/O Port 061h[4]. 5 PIT Counter 1 Enable:0 = Sets GATE1 input low; 1 = Sets GATE1 input high. 4 PIT Counter 0:0 = Forces Counter 0 output (OUT0) to zero; 1 = Allows Counter 0 output (OUT0) to pass to IRQ0. 3 PIT Counter 0 Enable:0 = Sets GATE0 input low; 1 = Sets GATE0 input high. I/O Port 061h Port B Control Register (R/W) Reset Value = 00x01100b 5 PIT OUT2 State (Read Only):This bit reflects the current status of the PIT Counter 2 (OUT2). 4 Toggle (Read Only):This bit toggles on every falling edge of Counter 1 (OUT1). 1 PIT Counter 2 (SPKR):0 = Forces Counter 2 output (OUT2) to zero. 1 = Allows Counter 2 output (OUT2) to pass to the speaker 0 PIT Counter 2 Enable:0 = Sets GATE2 input low. 1 = Sets GATE2 input high. CLK0 CLK1 CLK2 GATE0 GATE1 GATE2 XD[7:0] A[1:0] IOW# IOR# I/O Port 061h[1] I/O Port 061h[0] IRQ0 I/O Port 061h[4] PC_BEEP

1.19318 MHz

WR# RD# OUT0 OUT1 OUT2 F0 Index 50h[4] F0 Index 50h[6] F0 Index 50h[3] F0 Index 50h[5]

Revision 4.1 95 www.national.com Functional Description(Continued) Geode™ CS5530 PIT Registers The PIT registers are summarized and bit formats are in Table 4-27 "Programmable Interval Timer Registers" on page 212. PIT Shadow Register The PIT registers are shadowed to allow for Zero Volt Suspend to save/restore the PIT state by reading the PITs counter and write-only registers. The read sequence for the shadow register is listed in F0 Index BAh, Table 3-41.

3.5.4.3 Programmable Interrupt Controller

The CS5530 includes an AT -compatible Programmable Interrupt Controller (PIC) configuration with two 8259- equivalent interrupt controllers in a master/slave configu- ration (Figure 3-15). Figure 3-15. PIC Interrupt Controllers IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 INTR Processor

8254 Timer 0

RTC_IRQ# INTR IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Table 3-41. PIT Shadow Register Bit Description F0 Index BAh PIT Shadow Register (RO) Reset Value = xxh 7:0 PIT Shadow (Read Only):This 8-bit port sequences through the following list of shadowed Programmable Interval Timer registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. Counter 0 LSB (least significant byte) 2. Counter 0 MSB 3. Counter 1 LSB 4. Counter 1 MSB 5. Counter 2 LSB 6. Counter 2 MSB 7. Counter 0 Command Word 8. Counter 1 Command Word 9. Counter 2 Command Word Note: The LSB/MSB of the count is the Counter base value, not the current value. Bits [7:6] of the command words are not used.

www.national.com 96 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Since the two controllers are cascaded and three of the interrupt request inputs are connected to the internal 8254 PIT , the coprocessor interface, and the real-time clock interface, a total of 13 external interrupt requests are available. See Table 3-42. The CS5530 allows the PCI interrupt signals INTA#- I N T D #( a l s ok n o w ni ni n d u s t r yt e r m sa sP I R Q x # )t ob e routed internally to any IRQ signal. The routing can be modified through CS5530’s configuration registers. If this is done, the IRQ input must be configured to be level- rather than edge-sensitive. IRQ inputs may be individually programmed to be active low, level-sensitive with the Interrupt Sensitivity configuration registers at I/O address space 4D0h and 4D1h. PCI interrupt configuration is dis- cussed in further detail in Section 3.5.4.4 “PCI Compatible Interrupts” on page 98. PIC Interrupt Sequence A typical AT -compatible interrupt sequence is as follows. Any unmasked interrupt generates the INTR signal to the CPU. The interrupt controller then responds to the inter- rupt acknowledge (INTA) cycles from the CPU. On the first INTA cycle the cascading priority is resolved to determine which of the two 8259 controllers output the interrupt vec- tor onto the data bus. On the second INT A cycle the appropriate 8259 controller drives the data bus with the correct interrupt vector for the highest priority interrupt. By default, the CS5530 responds to PCI INTA cycles because the system interrupt controller is located within the CS5530. This may be disabled with F0 Index 40h[7] (see Table 3-43). When the CS5530 responds to a PCI INTA cycle, it holds the PCI bus and internally generate the two INTA cycles to obtain the correct interrupt vector. It then asserts TRDY# and returns the interrupt vector. PIC I/O Registers Each PIC contains registers located in the standard I/O address locations, as shown in Table 4-28 "Programmable Interrupt Controller Registers" on page 213. An initialization sequence must be followed to program the interrupt controllers. The sequence is started by writ- ing Initialization Command Word 1 (ICW1). After ICW1 has been written, the controller expects the next writes to follow in the sequence ICW2, ICW3, and ICW4 if it is needed. The Operation Control Words (OCW) can be written after initialization. The PIC must be programmed before operation begins. Since the controllers are operating in cascade mode, ICW3 of the master controller should be programmed with a value indicating that IRQ2 input of the master interrupt controller is connected to the slave interrupt controller rather than an I/O device as part of the system initializa- tion code. In addition, ICW3 of the slave interrupt control- ler should be programmed with the value 02h (slave ID) and corresponds to the input on the master controller. Table 3-42. PIC Interrupt Mapping Master IRQ# Mapping IRQ0 Connected to the OUT0 (system timer) of the internal 8254 PIT. IRQ2 Connected to the slave’s INTR for a cas- caded configuration. IRQ8# Connected to external real-time clock. IRQ13 Connected to the coprocessor interface. IRQ[15:14, 12:9, 7:3, 1] External interrupts. Table 3-43. PCI INTA Cycle Disable/Enable Bit Bit Description F0 Index 40h PCI Function Control Register 1 (R/W) Reset Value = 89h

7 PCI Interrupt Acknowledge Cycle Response:The CS5530 responds to PCI interrupt acknowledge cycles:

0 = Disable; 1 = Enable.

Revision 4.1 97 www.national.com Functional Description(Continued) Geode™ CS5530 PIC Shadow Register The PIC registers are shadowed to allow for Zero Volt Suspend to save/restore the PIC state by reading the PICs write-only registers. A write to this register resets the read sequence to the first register. The read sequence for the shadow register is listed in F0 Index B9h (Table 3-44). Table 3-44. PIC Shadow Register Bit Description F0 Index B9h PIC Shadow Register (RO) Reset Value = xxh 7:0 PIC Shadow (Read Only):This 8-bit port sequences through the following list of shadowed Interrupt Controller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. PIC1 ICW1 2. PIC1 ICW2 3. PIC1 ICW3 4. PIC1 ICW4 - Bits [7:5] of ICW4 are always 0 5. PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (Note) 6. PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1 7. PIC2 ICW1 8. PIC2 ICW2 9. PIC2 ICW3 10. PIC2 ICW4 - Bits [7:5] of ICW4 are always 0 11. PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note) 12. PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1 Note: To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register v a l u e ,t h e nw i t ht h es h a d o wr e g i s t e rv a l u eO R e dw i t hC 0 h .

www.national.com 98 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.5.4.4 PCI Compatible Interrupts

The CS5530 allows the PCI interrupt signals INTA#, INTB#, INTC#, and INTD# (also known in industry terms as PIRQx#) to be mapped internally to any IRQ signal with the PCI Interrupt Steering Registers 1 and 2, F0 Index 5Ch and 5Dh (T able 3-45). PCI interrupts are low-level sensitive, whereas PC/AT interrupts are positive-edge sensitive; therefore, the PCI interrupts are inverted before being connected to the 8259. Although the controllers default to the PC/A T -compatible mode (positive-edge sensitive), each IRQ may be individ- ually programmed to be edge or level sensitive using the Interrupt Edge/Level Sensitivity registers in I/O Port 4D0h and 4D1h, as shown in Table 3-46. However, if the control- lers are programmed to be level-sensitive via ICW1, all interrupts must be level-sensitive. Figure 3-16 shows the PCI interrupt mapping for the master/slave 8259 interrupt controller. Figure 3-16. PCI and IRQ Interrupt Mapping PCI INTA#-INTD#IRQ[15:14,12:9,7:3,1] Steering Registers F0 Index 5Ch,5Dh ICW1 4D0h/4D1h 12 4 MASTER/SLAVE

8259 PIC

IRQ[13,8,0] 3 Level/Edge IRQ3 IRQ4 IRQ15 Sensitivity Table 3-45. PCI Interrupt Steering Registers Bit Description F0 Index 5Ch PCI Interrupt Steering Register 1 (R/W) Reset Value = 00h 7:4 INTB# Target Interrupt: 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 3:0 INTA# Target Interrupt: 0000 = Disable 0100 = IRQ4 1000 = RSVD ‘ 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility F0 Index 5Dh PCI Interrupt Steering Register 2 (R/W) Reset Value = 00h 7:4 INTD# Target Interrupt: 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 3:0 INTC# Target Interrupt: 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility

Revision 4.1 99 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-46. Interrupt Edge/Level Select Registers Bit Description I/O Port 4D0h Interrupt Edge/Level Select Register 1 (R/W) Reset Value = 00h 7 IRQ7 Edge or Level Select:Selects PIC IRQ7 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 6 IRQ6 Edge or Level Select:Selects PIC IRQ6 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 5 IRQ5 Edge or Level Select:Selects PIC IRQ5 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 4 IRQ4 Edge or Level Select:Selects PIC IRQ4 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 3 IRQ3 Edge or Level Select:Selects PIC IRQ3 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 2 Reserved: Set to 0. 1 IRQ1 Edge or Level Select:Selects PIC IRQ1 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 0 Reserved: Set to 0. Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). I/O Port 4D1h Interrupt Edge/Level Select Register 2 (R/W) Reset Value = 00h 7 IRQ15 Edge or Level Select:Selects PIC IRQ15 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 6 IRQ14 Edge or Level Select:Selects PIC IRQ14 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 5 Reserved: Set to 0. 4 IRQ12 Edge or Level Select:Selects PIC IRQ12 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 3 IRQ11 Edge or Level Select: Selects PIC IRQ11 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 2 IRQ10 Edge or Level Select:Selects PIC IRQ10 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 1 IRQ9 Edge or Level Select:Selects PIC IRQ9 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 0 Reserved: Set to 0. Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared).

www.national.com 100 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.5.5 I/O Ports 092h and 061h System Control

The CS5530 supports control functions of I/O Ports 092h (Port A) and 061h (Port B) for PS/2 compatibility. I/O Port 092h allows a fast assertion of the A20M# or CPU_RST. I/O Port 061h controls NMI generation and reports system status. Table 3-47 shows these register bit formats. The CS5530 does not use a pin to control A20 Mask when used together with a GXLV processor. Instead, it generates an SMI for every internal change of the A20M# state and the SMI handler sets the A20M# state inside the CPU. This method is used for both the Port 092h (PS/2) and Port 061h (keyboard) methods of controlling A20M#. Table 3-47. I/O Ports 061h and 092h Bit Description I/O Port 061h Port B Control Register (R/W) Reset Value = 00x01100b 7 PERR#/SERR# Status (Read Only):Was a PCI bus error (PERR#/ SERR#) asserted by a PCI device or by CS5530? 0=N o ;1=Y e s . This bit can only be set if ERR_EN is set 0. This bit is set 0 after a write to ERR_EN with a 1 or after reset. 6 IOCHK# Status (Read Only):Is an I/O device reporting an error to the CS5530? 0 = No; 1 = Yes. This bit can only be set if IOCHK_EN is set 0. This bit is set 0 after a write to IOCHK_EN with a 1 or after reset. 5 PIT OUT2 State (Read Only):This bit reflects the current status of the PIT Timer2-OUT2. 4 Toggle (Read Only):This bit toggles on every falling edge of Counter 1 (OUT1).

3 IOCHK Enable:

0 = Generates an NMI if IOCHK# is driven low by an I/O device to report an error. Note that NMI is under SMI control. 1 = Ignores the IOCHK# input signal and does not generate NMI.

2 PERR#/ SERR# Enable: Generate an NMI if PERR#/ SERR# is driven active to report an error:

0 = Enable; 1 = Disable 1 PIT Counter2 (SPKR):0 = Forces Counter 2 output (OUT2) to zero. 1 = Allows Counter 2 output (OUT2) to pass to the speaker 0 PIT Counter2 Enable:0 = Sets GATE2 input low. 1 = Sets GATE2 input high. I/O Port 092h Port A Control Register (R/W) Reset Value = 02h 7:2 Reserved: Set to 0. 1 A20M# SMI Assertion:Assert A20# SMI: 0 = Enable; 1 = Disable. 0 Fast CPU Reset:WM_RST SMI is asserted to the BIOS: 0 = Disable; 1 = Enable. This bit must be cleared before the generation of another reset.

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3.5.5.1 I/O Port 092h System Control

I/O Port 092h allows for a fast keyboard assertion of an A20# SMI and a fast keyboard CPU reset. Decoding for this register may be disabled via F0 Index 52h[3] (Table 3- 48). The assertion of a fast keyboard A20# SMI is controlled by either I/O Port 092h or by monitoring for the keyboard command sequence (see Section 3.5.6.1 “Fast Keyboard Gate Address 20 and CPU Reset” on page 103). If bit 1 of I/O Port 092h is cleared, the CS5530 internally asserts an A20M# SMI, which in turn causes an SMI to the proces- sor. If bit 1 is set, A20M# SMI is internally deasserted again causing an SMI. The assertion of a fast keyboard reset (WM_RST SMI) is controlled by bit 0 in I/O Port 092h or by monitoring for the keyboard command sequence. If bit 0 is changed from a 0 to a 1, the CS5530 generates a reset to the processor by generating a WM_RST SMI. When the WM_RST SMI occurs, the BIOS jumps to the Warm Reset vector. This bit remains set until the CS5530 is externally reset, or this bit is cleared by program control. Note that Warm Reset is not a pin, it is under SMI control.

3.5.5.2 I/O Port 061h System Control

Through I/O Port 061h, the speaker output can be enabled, NMI from IOCHK# or SERR# can be enabled, t h es t a t u so fI O C H K #a n dS E R R #c a nb er e a d ,a n dt h e state of the speaker data (Timer2 output) and refresh tog- gle (Timer1 output) can be read back. Note that NMI is under SMI control.

3.5.5.3 SMI Generation for NMI

Figure 3-17 shows how the CS5530 can generate an SMI for an NMI. Note that NMI is not a pin.Figure 3-17. SMI Generation for NMI Table 3-48. I/O Port 092h Decode Enable Bit Bit Description F0 Index 52h ROM/AT Logic Control Register (R/W) Reset Value = F8h 3 Enable Port 092h Decode (Port A):I/O Port 092h decode and the logical functions: 0 = Disable; 1 = Enable. PERR# IOCHK# F0 Index 04h[6] SERR# F0 Index 04h[8] F0 Index 41h[5] I/O Port 061h[2] I/O Port 061h[3] I/O Port 070h[7] Parity Errors AND System Errors NMI NMI SMI F0 Index 04h: PCI Command Register Bit 6 = PE (Parity Error Enable) Bit 8 = SERR# (SERR# Enable) F0 Index 41h: PCI Function Control Register 2 Bit 5 = PES (PERR# Signals SERR#) I/O Port 061h: Port B Bit 2 = ERR_EN (PERR#/SERR# enable) Bit 3 = IOCHK_EN (IOCHK Enable) I/O Port 070h: RTC Index Register (WO) Bit 7 = NMI (NMI Enable) AND AND AND AND OR AND OR

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3.5.6 Keyboard Interface Function

The CS5530 actively decodes the keyboard controller I/O Ports 060h and 064h, and generate an ISA I/O cycle with KBROMCS# asserted. Access to I/O Ports 062h and 066h must be enabled for KBROMCS# to be asserted. The CS5530 also actively decodes the keyboard control- ler I/O Ports 062h and 066h if F0 Index 5Bh[7] is set. Key- board positive decoding can be disabled if F0 Index 5Ah[1] is cleared. Table 3-49 shows these two decoding bits. Table 3-50 lists the standard keyboard control I/O regis- ters and their bit formats. Table 3-49. Decode Control Registers Bit Description F0 Index 5Ah Decode Control Register 1 (R/W) Reset Value = 03h 1 Keyboard Controller Positive Decode:Selects positive or subtractive decoding for accesses to I/O Port 060h and 064h (and 062h/066h if enabled): 0 = Subtractive; 1 = Positive. Note: Positive decoding by the CS5530 speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530. It is assumed that if positive decode is enabled, the port exists on the ISA bus. F0 Index 5Bh Decode Control Register 2 (R/W) Reset Value = 20h 7 Keyboard I/O Port 062h/066h Decode:This alternate port to the keyboard controller is provided in support of the 8051SL notebook keyboard controller mailbox:0 = Disable; 1 = Enable. Note: Positive decoding by the CS5530 speeds up the I/O cycle time. The Keyboard, LPT3, LPT2, and LPT1 I/O Ports do not exist in the CS5530. It is assumed that if positive decode is enabled, the port exists on the ISA bus. Table 3-50. External Keyboard Controller Registers Bit Description I/O Port 060h (R/W) External Keyboard Controller Data Register Keyboard Controller Data Register:All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset fea- tures are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port assert the A20M# pin or cause a warm CPU reset. I/O Port 062h (R/W) External Keyboard Controller Mailbox Register Keyboard Controller Mailbox Register:Accesses to this port asserts KBROMCS# if the I/O Port 062h/066h decode is enabled through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]). I/O Port 064h (R/W) External Keyboard Controller Command Register Keyboard Controller Command Register:All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port assert the A20M# pin or cause a warm CPU reset. I/O Port 066h (R/W) External Keyboard Controller Mailbox Register Keyboard Controller Mailbox Register:Accesses to this port assert KBROMCS# if the I/O Port 062h/066h decode is enabled through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]).

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3.5.6.1 Fast Keyboard Gate Address 20 and CPU

The CS5530 monitors the keyboard I/O Ports 064h and 060h for the fast keyboard A20M# and CPU reset control sequences. If a write to I/O Port 060h[1] = 1 after a write takes place to I/O Port 064h with data of D1h, then the CS5530 asserts the A20M# signal. A20M# remains asserted until cleared by: (1) a write to bit 1 of I/O Port 092h, (2) a CPU reset of some kind, or (3) write to I/O Port 060h[1] = 0 after a write takes place to I/O Port 064h with data of D1h, The CS5530 also monitors the keyboard ports for the CPU reset control sequence. If a write to I/O Port 060h with data bit 0 set occurs after a write to I/O Port 064h with data of D1h, the CS5530 asserts a WM_RST SMI. The fast keyboard A20M# and CPU reset can be disabled through F0 Index 52h[7]. By default, bit 7 is cleared, and the fast keyboard A20M# and CPU reset monitor logic is active. If bit 7 is clear, the CS5530 forwards the com- mands to the keyboard controller. By default, the CS5530 forces the deassertion of A20M# during a warm reset. This action may be disabled if F0 Index 52h[4] is cleared. Table 3-51. A20 Associated Programming Bits Bit Description F0 Index 52h ROM/AT Logic Control Register (R/W) Reset Value = F8h 7 Snoop Fast Keyboard Gate A20 and Fast Reset:Enables the snoop logic associated with keyboard commands for A20 Mask and Reset: 0 = Disable; 1 = Enable (snooping). If disabled, the keyboard controller handles the commands. 4 Enable A20M# Deassertion on Warm Reset:Force A20M# high during a Warm Reset (guarantees that A20M# is deas- serted regardless of the state of A20): 0 = Disable; 1 = Enable.

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3.5.7 External Real-Time Clock Interface

I/O Ports 070h and 071h decodes are provided to inter- face to an external real-time clock controller. I/O Port 070h, a write only port, is used to set up the address of the desired data in the controller. This causes the address to be placed on the ISA data bus, and the RTCALE signal to be triggered. A read of I/O Port 071h causes an ISA I/O read cycle to be performed while asserting the RTCCS# s i g n a l .Aw r i t et oI / OP o r t0 7 1 hc a u s e sa nI S AI / Ow r i t e cycle to be performed with the desired data being placed o nt h eI S Ab u sa n dt h eR T C C S #s i g n a lt ob ea s s e r t e d . RTCCS#/SMEMW# and RTCALE/SMEMR# are multi- plexed pins. The function selection is made through F0 Index 53h[2]. The connection between the CS5530 and an external real-time clock is shown in Figure 3-18. The CS5530 also provides the RTC Index Shadow Regis- ter (F0 Index BBh) to store the last write to I/O Port 070h. Table 3-52 shows the bit formats for the associated regis- ters for interfacing with an external real-time clock. Figure 3-18. External RTC interface SD[7:0] RTCALE/SMEMR# IOR# IOW# RTC RTCCS#/SMEMW# IRQ8# Table 3-52. Real-Time Clock Registers Bit Description I/O Port 070h RTC Address Register (WO) 7 NMI Mask: 0 = Enable; 1 = Mask. 6:0 RTC Register Index:A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered. Note: This register is shadowed within the CS5530 and is read through the RTC Shadow Register (F0 Index BBh). I/O Port 071h RTC Data Register (R/W) A read of this register returns the value of the register indexed by the RTC Address Register plus initiates a RTCCS#. A write of this register sets the value into the register indexed by the RTC Address Register plus initiates a RTCCS#. F0 Index BBh RTC Index Shadow Register (RO) Reset Value = xxh 7:0 RTC Index Shadow (Read Only):The RTC Shadow register contains the last written value of the RTC Index register (I/O Port 070h). F0 Index 53h Alternate CPU Support Register (R/W) Reset Value = 00h

2 RTC Enable and RTC Pin Configuration:0 = SMEMW# (Pin AF3) and SMEMR# (Pin AD4), RTC decode disabled

1 = RTCCS# (Pin AF3) and RTCALE (Pin AD4), RTC decode enabled. Note: Shadow register is independent of the enable register.

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3.6 IDE CONTROLLER

The CS5530 integrates a fully-buffered, 32-bit, ANSI AT A- 4-compliant (Ultra DMA/33) IDE interface. The IDE inter- face supports two channels, primary and secondary, each supporting two devices that can operate in PIO Modes 1, 2, 3, 4, Multiword DMA, or Ultra DMA/33. The IDE interface provides a variety of features to opti- mize system performance, including 32-bit disk access, post write buffers, bus master, Multiword DMA, look- ahead read buffer, and prefetch mechanism for each channel respectively. The IDE interface timing is completely programmable. Timing control covers the command active and recover pulse widths, and command block register accesses. The IDE data-transfer speed for each device on each channel can be independently programmed allowing high-speed IDE peripherals to coexist on the same channel as older, compatible devices. The CS5530 also provides a software-accessible buffered reset signal to the IDE drive, F0 Index 44h[3:2] (Table 3- 53). The IDE_RST# signal is driven low during reset to the CS5530 and can be driven low or high as needed for device-power-off conditions.

3.6.1 IDE Interface Signals

The CS5530 has two completely separate IDE control sig- nals, however, the IDE_RST#, IDE_ADDR[2:0] and IDE_DATA[15:0] are shared. The connections between the CS5530 and IDE devices are shown as Figure 3-19. Figure 3-19. CS5530 and IDE Channel Connections Table 3-53. IDE Reset Bits Bit Description F0 Index 44h Reset Control Register (R/W) Reset Value = xx000000b 3 IDE Controller Reset:Reset the IDE Controller: 0 = Disable; 1 = Enable. Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled. 2 IDE Reset:Reset IDE bus: 0 = Disable; 1 = Enable. Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled. IDE_ADDR[2:0] IRQ14 IRQ15 IDE_DATA[15:0] Primary Channel Secondary Channel IDE_RST# IDE_CS0#, IDE_DREQ0, IDE_DACK0#, IDE_IORDY0, IDE_IOR0#, IDE_IOW0# IDE_CS1#, IDE_DREQ1, IDE_DACK1#, IDE_IORDY1, IDE_IOR1#, IDE_IOW1#

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3.6.2 IDE Configuration Registers

Registers for configuring the IDE interface are accessed through F2 Index 20h, the Base Address Register (F2BAR) in Function 2. F2BAR sets the base address for the IDE Controllers Configuration Registers as shown in Table 3-54. For complete bit information, refer to Section 4.3.3 “IDE Controller Registers - Function 2” on page 184. The following subsections discuss CS5530 opera- tional/programming details concerning PIO, Bus Master, and Ultra DMA/33 modes.

3.6.2.1 PIO Mode

The IDE data port transaction latency consists of address latency, asserted latency and recovery latency. Address latency occurs when a PCI master cycle targeting the IDE data port is decoded, and the IDE_ADDR[2:0] and IDE_CS# lines are not set up. Address latency provides the setup time for the IDE_ADDR[2:0] and IDE_CS# lines prior to IDE_IOR# and IDE_IOW#. Asserted latency consists of the I/O command strobe assertion length and recovery time. Recovery time is pro- vided so that transactions may occur back-to-back on the IDE interface without violating minimum cycle periods for the IDE interface. If IDE_IORDY is asserted when the initial sample point is reached, no wait states are added to the command strobe assertion length. If IDE_IORDY is negated when the initial sample point is reached, additional wait states are added. Recovery latency occurs after the IDE data port transac- tions have completed. It provides hold time on the IDE_ADDR[2:0] and IDE_CS# lines with respect to the read and write strobes (IDE_IOR# and IDE_IOW#). The PIO portion of the IDE registers is enabled through:  Channel 0 Drive 0 Programmed I/O Register (F2BAR+I/O Offset 20h)  Channel 0 Drive 1 Programmed I/O Register (F2BAR+I/O Offset 28h)  Channel 1 Drive 0 Programmed I/O Register (F2BAR+I/O Offset 30h)  Channel 1 Drive 1 Programmed I/O Register (F2BAR+I/O Offset 38h) The IDE channels and devices can be individually pro- grammed to select the proper address setup time, asserted time, and recovery time. T h eb i tf o r m a t sf o rt h e s er e g i s t e r sa r es h o w ni nT a b l e3 - 55. Note that there are different bit formats for each of the PIO programming registers depending on the operating format selected: Format 0 or Format 1. F2BAR+I/O Offset 24h[31] (Channel 0 Drive 0 — DMA Control Register) sets the format of the PIO register. If bit 31 = 0, Format 0 is used and it selects the slowest PIO- MODE (bits [19:16]) per channel for commands. If bit 31 = 1, Format 1 is used and it allows independent control of command and data. Also listed in the bit formats are recommended values for the different PIO modes. Note: These are only recommended settings and are not 100% tested. Table 3-54. Base Address Register (F2BAR) for IDE Support Registers Bit Description F2 Index 20h-23h Base Address Register — F2BAR (R/W) Reset Value = 00000001h This register sets the base address of the I/O mapped bus mastering IDE and controller registers. Bits [6:0] are read only (0000 001), indicating a 128 byte I/O address range. Refer to Table 4-18 for the IDE configuration registers bit formats and reset values. 31:7 Bus Mastering IDE Base Address 6:0 Address Range (Read Only)

Revision 4.1 107 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-55. PIO Programming Registers Bit Description F2BAR+I/O Offset 20h-23h Channel 0 Drive 0 PIO Register (R/W) Reset Value = 0000E132h (Note) If Offset 24h[31] = 0, Format 0:Selects slowest PIOMODE per channel for commands. Format 0 settings for: PIO Mode 0 = 00009172h PIO Mode 1 = 00012171h PIO Mode 2 = 00020080h PIO Mode 3 = 00032010h PIO Mode 4 = 00040010h 31:20 Reserved: Set to 0. 19:16 PIOMODE: PIO mode 15:12 t2I:Recovery time (value + 1 cycle) 11:8 t3:IDE_IOW# data setup time (value + 1 cycle) 7:4 t2W: IDE_IOW# width minus t3 (value + 1 cycle) 3:0 t1:Address Setup Time (value + 1 cycle) If Offset 24h[31] = 1, Format 1:Allows independent control of command and data. Format 1 settings for: PIO Mode 0 = 9172D132h PIO Mode 1 = 21717121h PIO Mode 2 = 00803020h PIO Mode 3 = 20102010h PIO Mode 4 = 00100010h 31:28 t2IC:Command cycle recovery time (value + 1 cycle) 27:24 t3C:Command cycle IDE_IOW# data setup (value + 1 cycle) 23:20 t2WC: Command cycle IDE_IOW# pulse width minus t3 (value + 1 cycle) 19:16 t1C:Command cycle address setup time (value + 1 cycle) 15:12 t2ID:Data cycle recovery time (value + 1 cycle) 11:8 t3D:Data cycle IDE_IOW# data setup (value + 1 cycle) 7:4 t2WD: Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle) 3:0 t1D:Data cycle address Setup Time (value + 1 cycle) Note: The reset value of this register is not a valid PIO Mode. F2BAR+I/O Offset 28h-2Bh Channel 0 Drive 1 PIO Register (R/W) Reset Value = 0000E132h Channel 0 Drive 1 Programmed I/O Control Register:Refer to F2BAR+I/O Offset 20h for bit descriptions. F2BAR+I/O Offset 30h-33h Channel 1 Drive 0 PIO Register (R/W) Reset Value = 0000E132h Channel 1 Drive 0 Programmed I/O Control Register:Refer to F2BAR+I/O Offset 20h for bit descriptions. F2BAR+I/O Offset 38h-3Bh Channel 1 Drive 1 PIO Register (R/W) Reset Value = 0000E132h Channel 1 Drive 1 Programmed I/O Control Register:Refer to F2BAR+I/O Offset 20h for bit descriptions.

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3.6.2.2 Bus Master Mode

Two IDE bus masters are provided to perform the data transfers for the primary and secondary channels. The CS5530 off-loads the CPU and improves system perfor- mance in multitasking environments. The bus master mode programming interface is an exten- sion of the standard IDE programming model. This means that devices can always be dealt with using the standard IDE programming model, with the master mode function- ality used when the appropriate driver and devices are present. Master operation is designed to work with any IDE device that supports DMA transfers on the IDE bus. Devices that work in PIO mode can only use the standard IDE programming model. T h eI D Eb u sm a s t e r su s eas i m p l es c a t t e r / g a t h e rm e c h a - nism allowing large transfer blocks to be scattered to or gathered from memory. This cuts down on the number of interrupts to and interactions with the CPU. Physical Region Descriptor Table Address Before the controller starts a master transfer it is given a pointer (shown in T able 3-56) to a Physical Region Descriptor Table. This pointer sets the starting memory location of the Physical Region Descriptors (PRDs). The P R D sd e s c r i b et h ea r e a so fm e m o r yt h a ta r eu s e di nt h e data transfer. The PRDs must be aligned on a 4-byte boundary and the table cannot cross a 64 KB boundary in memory. Primary and Secondary IDE Bus Master Registers The IDE Bus Master Registers for each channel (primary and secondary) have an IDE Bus Master Command Reg- ister and Bus Master Status Register. These registers must be accessed only individually; a 32-bit DWORD access attempting to include both the Command and Sta- tus registers may not operate correctly. Bit formats of these registers are given in Table 3-57. Table 3-56. IDE Bus Master PRD Table Address Registers Bit Description F2BAR+I/O Offset 04h-07h IDE Bus Master 0 PRD Table Address — Primary (R/W) Reset Value = 00000000h 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for IDE Bus Master 0. When written, this register points to the first entry in a PRD table. Once IDE Bus Master 0 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. F2BAR+I/O Offset 0Ch-0Fh IDE Bus Master 1 PRD Table Address — Secondary (R/W) Reset Value = 00000000h 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for IDE Bus Master 1. When written, this register points to the first entry in a PRD table. Once IDE Bus Master 1 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0.

Revision 4.1 109 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-57. IDE Bus Master Command and Status Registers Bit Description F2BAR+I/O Offset 00h IDE Bus Master 0 Command Register — Primary (R/W) Reset Value = 00h 7:4 Reserved: Set to 0. Must return 0 on reads.

3 Read or Write Control:Sets the direction of bus master transfers: 0 = PCI reads performed;

1 = PCI writes performed. This bit should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the bus master: 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 to 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is dis- carded. This bit should be reset after completion of data transfer. F2BAR+I/O Offset 02h IDE Bus Master 0 Status Register — Primary (R/W) Reset Value = 00h 7 Simplex Mode (Read Only):Can both the primary and secondary channel operate independently? 0 = Y es; 1 = No (simplex mode) 6 Drive 1 DMA Capable:Allow Drive 1 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 5 Drive 0 DMA Capable:Allow Drive 0 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 4:3 Reserved: Set to 0. Must return 0 on reads. 2 Bus Master Interrupt:Has the bus master detected an interrupt? 0 = No; 1 = Y es. Write 1 to clear. 1 Bus Master Error:Has the bus master detected an error during data transfer? 0 = No; 1 = Y es. Write 1 to clear. 0 Bus Master Active (Read Only):Is the bus master active? 0 = No; 1 = Y es. F2BAR+I/O Offset 08h IDE Bus Master 1 Command Register — Secondary (R/W) Reset Value = 00h 7:4 Reserved: Set to 0. Must return 0 on reads. 1 = PCI writes performed. This bit should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the bus master: 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 = 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is dis- carded. This bit should be reset after completion of data transfer. F2BAR+I/O Offset 0Ah Bus Master 1 Status Register — Secondary (R/W) Reset Value = 00h 7 Simplex Mode (Read Only):Can both the primary and secondary channel operate independently? 0 = Y es; 1 = No (simplex mode) 6 Drive 1 DMA Capable:Allow Drive 1 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 5 Drive 0 DMA Capable:Allow Drive 0 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 4:3 Reserved: Set to 0. Must return 0 on reads. 2 Bus Master Interrupt:Has the bus master detected an interrupt? 0 = No; 1 = Y es. Write 1 to clear. 1 Bus Master Error:Has the bus master detected an error during data transfer? 0 = No; 1 = Y es. Write 1 to clear. 0 Bus Master Active (Read Only):Is the bus master active? 0 = No; 1 = Y es.

www.national.com 110 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descriptor (PRD) as illus- trated in Table 3-58. When the bus master is enabled (Command Register bit 0 = 1), data transfer proceeds until each PRD in the PRD table has been transferred. The bus master does not cache PRDs. The PRD table consists of two DWORDs. The first DWORD contains a 32-bit pointer to a buffer to be trans- ferred. This pointer must be 16-byte aligned. The second DWORD contains the size (16 bits) of the buffer and the EOT flag. The size must be in multiples of 16 bytes. The EOT bit (bit 31) must be set to indicate the last PRD in the PRD table. Programming Model The following steps explain how to initiate and maintain a bus master transfer between memory and an IDE device. 1) Software creates a PRD table in system memory. Each PRD entry is 8 bytes long, consisting of a base address pointer and buffer size. The maximum data that can be transferred from a PRD entry is 64 KB. A PRD table must be aligned on a 4-byte boundary. T h el a s tP R Di naP R Dt a b l em u s th a v et h eE O Tb i t set. 2) Software loads the starting address of the PRD table by programming the PRD T able Address Register. 3) Software must fill the buffers pointed to by the PRDs with IDE data. 4) Write 1 to the Bus Master Interrupt bit and Bus Master Error (Status Register bits 2 and 1) to clear the bits. 5) Set the correct direction to the Read or Write Control bit (Command Register bit 3). Engage the bus master by writing a “1” to the Bus Master Control bit (Command Register bit 0). The bus master reads the PRD entry pointed to by the PRD Table Address Register and increments the address by 08h to point to the next PRD. The transfer begins. 6) The bus master transfers data to/from memory responding to bus master requests from the IDE device. At the completion of each PRD, the bus master’s next response depends on the settings of the EOT flag in the PRD. If the EOT bit is set, then the IDE bus master clears the Bus Master Active bit (Status Register bit 0) and stops. If any errors occurred during the transfer, the bus master sets the Bus Master Error bit Status Register bit 1). Table 3-58. Physical Region Descriptor Format DWORD Byte 3 Byte 2 Byte 1 Byte 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 Memory Region Physical Base Address [31:4] (IDE Data Buffer) 0 0 0 0

O T Reserved Size [15:4] 0 0 0 0

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3.6.2.3 Ultra DMA/33 Mode

The CS5530 supports Ultra DMA/33. It utilizes the stan- dard IDE Bus Master functionality to interface, initiate and control the transfer. Ultra DMA/33 definition also incorpo- rates a Cyclic Redundancy Checking (CRC) error check- ing protocol to detect errors. The Ultra DMA/33 protocol requires no extra signal pins on the IDE connector. The CS5530 redefines three stan- dard IDE control signals when in Ultra DMA/33 mode. These definitions are shown in Table 3-59. All other signals on the IDE connector retain their func- tional definitions during the Ultra DMA/33 operation. IDE_IOW# is defined as STOP for both read and write transfers to request to stop a transaction. IDE_IOR# is redefined as DMARDY# for transferring data from the IDE device to the CS5530. It is used by the CS5530 to signal when it is ready to transfer data and to add wait states to the current transaction. IDE_IOR# sig- nal is defined as STROBE for transferring data from the CS5530 to the IDE device. It is the data strobe signal driven by the CS5530 on which data is transferred during each rising and falling edge transition. IDE_IORDY is redefined as STROBE for transferring data from the IDE device to the CS5530 during a read cycle. It is the data strobe signal driven by the IDE device on which data is transferred during each rising and falling edge transition. IDE_IORDY is defined as DMARDY# during a write cycle for transferring data from the CS5530 to the IDE device. It is used by the IDE device to signal when it is ready to transfer data and to add wait states to the current transaction. Ultra DMA/33 data transfer consists of three phases, a startup phase, a data transfer phase and a burst termina- tion phase. The IDE device begins the startup phase by asserting IDE_DREQ. When ready to begin the transfer, the CS5530 asserts IDE_DACK#. When IDE_DACK# is asserted, the CS5530 drives IDE_CS0# and IDE_CS1# asserted, and IDE_ADDR[2:0] low. For write cycles, the CS5530 negates STOP , waits for the IDE device to assert DMARDY#, and then drives the first data word and STROBE signal. For read cycles, the CS5530 negates STOP , and asserts DMARDY#. The IDE device then sends the first data word and asserts STROBE. The data transfer phase continues the burst transfers with the CS5530 and the IDE via providing data, toggling STROBE and DMARDY#. The IDE_DATA[15:0] is latched by receiver on each rising and falling edge of STROBE. The transmitter can pause the burst cycle by holding STROBE high or low, and resume the burst cycle by again toggling STROBE. The receiver can pause the burst cycle by negating DMARDY# and resumes the burst cycle by asserting DMARDY#. The current burst cycle can be terminated by either the transmitter or the receiver. A burst cycle must first be paused as described above before it can be terminated. T h eC S 5 5 3 0c a nt h e ns t o pt h eb u r s tc y c l eb ya s s e r t i n g STOP , with the IDE device acknowledging by negating IDE_DREQ. The IDE device then stops the burst cycle by negating IDE_DREQ and the CS5530 acknowledges by a s s e r t i n gS T O P .T h et r a n s m i t t e rt h e nd r i v e st h eS T R O B E signal to a high level. The CS5530 then puts the result of the CRC calculation onto the IDE_DATA[15:0] while deas- serting IDE_DACK#. The IDE device latches the CRC value on the rising edge of IDE_DACK#. T h eC R Cv a l u ei su s e df o re r r o rc h e c k i n go nU l t r a DMA/33 transfers. The CRC value is calculated for all data by both the CS5530 and the IDE device during the Ultra DMA/33 burst transfer cycles. This result of the CRC calculation is defined as all data transferred with a valid STROBE edge while IDE_DACK# is asserted. At the end of the burst transfer, the CS5530 drives the result of the CRC calculation onto IDE_DATA[15:0] which is then strobed by the deassertion of IDE_DACK#. The IDE device compares the CRC result of the CS5530 to its own and reports an error if there is a mismatch. The timings for Ultra DMA/33 are programmed into the DMA control registers:  Channel 0 Drive 0 DMA Control Register (F2BAR+I/O Offset 24h)  Channel 0 Drive 1 DMA Control Register (F2BAR+I/O Offset 2Ch)  Channel 1 Drive 0 DMA Control Register (F2BAR+I/O Offset 34h)  Channel 1 Drive 1 DMA Control Register (F2BAR+I/O Offset 3Ch) The bit formats for these registers are given in T able 3-60. Note that F2BAR+I/O Offset 24h[20] is used to select either Multiword or Ultra DMA mode. Bit 20 = 0 selects Multiword DMA mode. If bit 20 = 1, then Ultra DMA/33 mode is selected. Once mode selection is made using this bit, the remaining DMA Control Registers also operate in the selected mode. Also listed in the bit formats are recommended values for both Multiword DMA Modes 0-2 and Ultra DMA/33 Modes 0-2. Note: These are only recommended settings and are not 100% tested. Table 3-59. Ultra DMA/33 Signal Definitions CS5530 IDE Channel Signal Ultra DMA/33 Read Cycle Ultra DMA/33 Write Cycle IDE_IOW# STOP STOP IDE_IOR# DMARDY# STROBE IDE_IORDY STROBE DMARDY#

www.national.com 112 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Table 3-60. MDMA/UDMA Control Registers Bit Description F2BAR+I/O Offset 24h-27h Channel 0 Drive 0 DMA Control Register (R/W) Reset Value = 00077771h If bit 20 = 0, Multiword DMA Settings for: Multiword DMA Mode 0 = 00077771h Multiword DMA Mode 1 = 00012121h Multiword DMA Mode 2 = 00002020h

31 PIO Mode Format:0 = Format 0; 1 = Format 1

30:21 Reserved: Set to 0. 20 DMA Select:DMA operation: 0 = Multiword DMA; 1 = Ultra DMA/33. 19:16 tKR: IDE_IOR# recovery time (4-bit) (value + 1 cycle) 15:12 tDR: IDE_IOR# pulse width (value + 1 cycle) 11:8 tKW: IDE_IOW# recovery time (4-bit) (value + 1 cycle) 7:4 tDW: IDE_IOW# pulse width (value + 1 cycle) 3:0 tM:IDE_CS0#/CS1# to IDE_IOR#/IOW# setup; IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1# I fb i t2 0=1 ,U l t r aD M A / 3 3 Settings for: Ultra DMA/33 Mode 0 = 00921250h Ultra DMA/33 Mode 1 = 00911140h Ultra DMA/33 Mode 2 = 00911030h 30:21 Reserved: Set to 0. 20 DMA Select:DMA operation: 0 = Multiword DMA, 1 = Ultra DMA/33. 19:16 tCRC: CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS) 15:12 tSS:UDMA out (value + 1 cycle) 11:8 tCYC: Data setup and cycle time UDMA out (value + 2 cycles) 7:4 tRP: Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock. 3:0 tACK: IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1# (value + 1 cycle) F2BAR+I/O Offset 2Ch-2Fh Channel 0 Drive 1 DMA Control Register (R/W) Reset Value = 00017771h Channel 0 Drive 1 MDMA/UDMA Control Register:Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. F2BAR+I/O Offset 34h-37h Channel 1 Drive 0 DMA Control Register (R/W) Reset Value = 00017771h Channel 1 Drive 0 MDMA/UDMA Control Register:Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. F2BAR+I/O Offset 3Ch-3Fh Channel 1 Drive 1 DMA Control Register (R/W) Reset Value = 00017771h Channel 1 Drive 1 MDMA/UDMA Control Register:Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only.

Revision 4.1 113 www.national.com Functional Description(Continued) Geode™ CS5530

3.7 XPRESSAUDIO

Through XpressAUDIO, the CS5530 offers a combined hardware/software support solution to meet industry stan- dard audio requirements. XpressAUDIO uses Virtual Sys- tem Architecture (VSA) technology along with additional hardware features to provide the necessary support for industry standard 16-bit stereo synthesis and OPL3 emu- lation. The hardware portion of XpressAUDIO is for transporting streaming audio data to/from the system memory and an AC97 codec. This hardware includes:  Six (three inbound/three outbound) buffered PCI bus mastering engines that drive specific AC97 interface slots.  Interfaces to AC97 codecs (e.g., LM4548) for audio input/output. Additional hardware provides the necessary functionality for VSA technology. This hardware includes the ability to:  Generate an SMI to alert software to update required data. An SMI is generated when either audio buffer is half empty or full. If the buffers become completely empty or full, the Empty bit is asserted.  Generate an SMI on I/O traps.  Trap accesses for sound card compatibility at either I/O Port 220h-22Fh, 240h-24Fh, 260h-26Fh, or 280h- 28Fh.  Trap accesses for FM compatibility at I/O Port 388h- 38Bh.  Trap accesses for MIDI UART interface at I/O Port 300h-301h or 330h-331h.  Trap accesses for serial input and output at COM2 (I/O Port 2F8h-2FFh) or COM4 (I/O Port 2E8h-2EFh).  Support trapping for low (I/O Port 00h-0Fh) and/or high (I/O Port C0h-DFh) DMA accesses.  Support hardware status register reads in CS5530, minimizing SMI overhead.  Support is provided for software-generated IRQs on IRQ 2, 3, 5, 7, 10, 11, 12, 13, 14, and 15. Included in the following subsections are details regarding the registers used for configuring the audio interface. The registers are accessed through F3 Index 10h, the Base Address Register (F3BAR) in Function 3. F3BAR sets the base address for XpressAUDIO support registers as shown in Table 3-61.

3.7.1 Subsystem Data Transport Hardware

The data transport hardware can be broadly divided into two sections: bus mastering and the codec interface.

3.7.1.1 Audio Bus Masters

The CS5530 audio hardware includes six PCI bus mas- ters (three for input and three for output) for transferring digitized audio between memory and the external codec. With these bus master engines, the CS5530 off-loads the CPU and improves system performance. The programming interface defines a simple scat- ter/gather mechanism allowing large transfer blocks to be scattered to or gathered from memory. This cuts down on the number of interrupts to and interactions with the CPU. Table 3-61. Base Address Register (F3BAR) for XpressAUDIO Registers Bit Description F3 Index 10h-13h Base Address Register — F3BAR (R/W) Reset Value = 00000000h This register sets the base address of the memory mapped audio interface control register block. This is a 4 KB block of registers used to control the audio FIFO and codec interface, as well as to support SMIs produced by VSA technology. Bits [11:0] are read only (0000 0000 0000), indicating a 4 KB memory address range. Refer to Table 4-20 for the bit formats and reset values of XpressAUDIO registers. 31:12 Audio Interface Base Address 11:0 Address Range (Read Only)

www.national.com 114 Revision 4.1 Functional Description(Continued) Geode™ CS5530 The six bus masters that directly drive specific slots on the AC97 interface:  Audio Bus Master 0 - Output to codec - PCI read -3 2 - B i t - Left and right channels -S l o t s 3 a n d 4  Audio Bus Master 1 - Input from codec -P C I w r i t e -3 2 - B i t - Left and right channels -S l o t s 3 a n d 4  Audio Bus Master 2 - Output to codec - PCI read -1 6 - B i t -S l o t 5  Audio Bus Master 3 - Input from codec -P C I w r i t e -1 6 - B i t -S l o t 5 A u d i o B u s M a s t e r 4 - Output to codec -P C I r e a d - 16-Bit - Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot) A u d i o B u s M a s t e r 5 - Input from codec - PCI write - 16-Bit - Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot) Bus Master Audio Configuration Registers The format for the bus master audio configuration regis- ters is similar in that each bus master has a Command Register, an SMI Status Register and a PRD Table Address Register. Programming of the bus masters is generic in many ways, although specific programming is required of bit 3 in the Command Register. This bit selects read or write control and is dependent upon which Audio Bus Master is being programmed. Table 3-62. Generic Bit Formats for Audio Bus Master Configuration Registers Bit Description Command Register (R/W) 7:4 Reserved: Set to 0. Must return 0 on reads.

3 Read or Write Control:Set the transfer direction of Audio Bus Master X: 0 = PCI reads performed;

1 = PCI writes performed. This bit should not be changed when the bus master is active. The setting of this bit is dependent upon the assigned bus master. Note: Must be R/W as a byte. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the Audio Bus Master X: 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must either be paused or have reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. SMI Status Register (RC) 7:2 Reserved (Read to Clear) 1 Bus Master Error (Read to Clear):Hardware encountered a second EOP (end of page) before software has cleared the f i r s t ?0=N o ;1=Y e s . If hardware encounters a second EOP before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. Note: Must be R/W as a byte. 0 End of Page (Read to Clear):Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0=N o ;1=Y e s . Note: Must be read and written as a BYTE. PRD Table Address (R/W) 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for Audio Bus Master X. When written, this register points to the first entry in a PRD table. Once Audio Bus Master X is enabled (Command Reg- ister bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0.

Revision 4.1 115 www.national.com Functional Description(Continued) Geode™ CS5530 For example, Audio Bus Master 0 is defined as an output only, so bit 3 of Audio Bus Master 0 Command Register (F3BAR+Memory Offset 20h[3]) must always be set to 1. Table 3-62 explains the generic format for the six audio bus masters. T able 3-63 gives the register locations, reset values and specific programming information of bit 3, Read or Write Control, in the Command Register for the Audio Bus Masters. Table 3-63. Audio Bus Master Configuration Register Summary Bit Description Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. F3BAR+Memory Offset 20h Command Register (R/W) Reset Value = 00h F3BAR+Memory Offset 21h SMI Status Register (RC) Reset Value = 00h F3BAR+Memory Offset 22h-23h Not Used F3BAR+Memory Offset 24h-27h PRD Table Address (R/W) Reset Value = 00000000h Refer to Table 3-62 for bit descriptions. Note: Bit 3 of the Command Register must be set to 0 (read) and should not be changed when the bus master is active. Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. F3BAR+Memory Offset 28h Command Register (R/W) Reset Value = 00h F3BAR+Memory Offset 29h SMI Status Register (RC) Reset Value = 00h F3BAR+Memory Offset 2Ah-2Bh Not Used F3BAR+Memory Offset 2Ch-2Fh PRD Table Address (R/W) Reset Value = 00000000h Refer to Table 3-62 for bit descriptions. Note: Bit 3 of the Command Register must be set to 1 (write) and should not be changed when the bus master is active. Audio Bus Master 2: Output to Codec; 16-Bit; Slot 5 F3BAR+Memory Offset 30h Command Register (R/W) Reset Value = 00h F3BAR+Memory Offset 31h SMI Status Register (RC) Reset Value = 00h F3BAR+Memory Offset 32h-33h Not Used F3BAR+Memory Offset 34h-37h PRD Table Address (R/W) Reset Value = 00000000h Refer to Table 3-62 for bit descriptions. Note: Bit 3 of the Command Register must be set to 0 (read) and should not be changed when the bus master is active. Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5. F3BAR+Memory Offset 38h Command Register (R/W) Reset Value = 00h F3BAR+Memory Offset 39h SMI Status Register (RC) Reset Value = 00h F3BAR+Memory Offset 3Ah-3Bh Not Used F3BAR+Memory Offset 3Ch-3Fh PRD Table Address (R/W) Reset Value = 00000000h Refer to Table 3-62 for bit descriptions. Note: Bit 3 of the Command Register must be set to 1 (write) and should not be changed when the bus master is active. Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot). F3BAR+Memory Offset 40h Command Register (R/W) Reset Value = 00h F3BAR+Memory Offset 41h SMI Status Register (RC) Reset Value = 00h F3BAR+Memory Offset 42h-43h Not Used F3BAR+Memory Offset 44h-47h PRD Table Address (R/W) Reset Value = 00000000h Refer to Table 3-62 for bit descriptions. Note: Bit 3 of the Command Register must be set to 0 (read) and should not be changed when the bus master is active. Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot). F3BAR+Memory Offset 48h Command Register (R/W) Reset Value = 00h F3BAR+Memory Offset 49h SMI Status Register (RC) Reset Value = 00h F3BAR+Memory Offset 4Ah-4Bh Not Used F3BAR+Memory Offset 4Ch-4Fh PRD Table Address (R/W) Reset Value = 00000000h Refer to Table 3-62 for bit descriptions. Note: Bit 3 of the Command Register must be set to 1 (write) and should not be changed when the bus master is active.

www.national.com 116 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.7.1.2 Physical Region Descriptor Table Address

Before the bus master starts a master transfer it must be programmed with a pointer (PRD Table Address Register) to a Physical Region Descriptor Table. This pointer sets the starting memory location of the Physical Region Descriptors (PRDs). The PRDs describe the areas of memory that are used in the data transfer. The descriptor table entries must be aligned on a 4-byte boundary and the table cannot cross a 64 KB boundary in memory.

3.7.1.3 Physical Region Descriptor Format

Each physical memory region to be transferred is described by a Physical Region Descriptor (PRD) as illus- trated in Table 3-64. When the bus master is enabled (Command Register bit 0 = 1), data transfer proceeds until each PRD in the PRD table has been transferred. The bus master does not cache PRDs. The PRD table consists of two DWORDs. The first DWORD contains a 32-bit pointer to a buffer to be trans- ferred. The second DWORD contains the size (16 bits) of the buffer and flags (EOT, EOP , JMP). The description of the flags are as follows:  EOT bit - If set in a PRD, this bit indicates the last entry in the PRD table (bit 31). The last entry in a PRD table must have either the EOT bit or the JMP bit set. A PRD can not have both the JMP and EOT bits set.  EOP bit - If set in a PRD and the bus master has completed the PRD’s transfer, the End of Page bit is set (Status Register bit 0 = 1) and an SMI is generated. If a second EOP is reached due to the completion of another PRD before the End of Page bit is cleared, the Bus Master Error bit is set (Status Register bit 1 = 1) and the bus master pauses. In this paused condition, reading the Status Register clears both the Bus Master Error and the End of Page bits and the bus master continues.  JMP bit - This PRD is special. If set, the Memory Region Physical Base Address is now the target address of the JMP . There is no data transfer with this PRD. This PRD allows the creation of a looping mecha- nism. If a PRD table is created with the JMP bit set in the last PRD, the PRD table does not need a PRD with the EOT bit set. A PRD can not have both the JMP and EOT bits set. Table 3-64. Physical Region Descriptor Format DWORD Byte 3 Byte 2 Byte 1 Byte 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 Memory Region Base Address [31:1] (Audio Data Buffer) 0

O T E O P J M P Reserved Size [15:1] 0

Revision 4.1 117 www.national.com Functional Description(Continued) Geode™ CS5530

3.7.1.4 Programming Model

The following discussion explains, in steps, how to initiate and maintain a bus master transfer between memory and an audio slave device. In the steps listed below, the reference to “Example” refers to Figure 3-20, PRD T able Example. 1) Software creates a PRD table in system memory. Each PRD entry is 8 bytes long; consisting of a base address pointer and buffer size. The maximum data that can be transferred from a PRD entry is 64 KB. A PRD table must be aligned on a 4-byte boundary. T h el a s tP R Di naP R Dt a b l em u s th a v et h eE O To r JMP bit set. Example - Assume the data is outbound. There are three PRDs in the example PRD table. The first two PRDs (PRD_1, PRD_2) have only the EOP bit set. The last PRD (PRD_3) has only the JMP bit set. This example creates a PRD loop. 2) Software loads the starting address of the PRD table by programming the PRD T able Address Register. Example - Program the PRD Table Address Register with Address_3. 3) Software must fill the buffers pointed to by the PRDs with audio data. It is not absolutely necessary to fill the buffers; however, the buffer filling process must stay ahead of the buffer emptying. The simplest way to do this is by using the EOP flags to generate an SMI when a PRD is empty. Example - Fill Audio Buffer_1 and Audio Buffer_2. The SMI generated by the EOP from the first PRD allows the software to refill Audio Buffer_1. The second SMI will refill Audio Buffer_2. The third SMI will refill Audio Buffer_1 and so on. 4) Read the SMI Status Register to clear the Bus Master Error and End of Page bits (bits 1 and 0). Set the correct direction to the Read or Write Control bit (Command Register bit 3). Note that the direction of the data transfer of a particular bus master is fixed and therefore the direction bit must be programmed accordingly. It is assumed that the codec has been properly programmed to receive the audio data. Engage the bus master by writing a “1” to the Bus Master Control bit (Command Register bit 0). The bus master reads the PRD entry pointed to by the PRD Table Address Register and increments the address by 08h to point to the next PRD. The transfer begins. Example - The bus master is now properly programmed to transfer Audio Buffer_1 to a specific slot(s) in the AC97 interface. Figure 3-20. PRD Table Example Address_1 Size_1 EOT = 0 Audio Buffer_1 Audio Buffer_2 Size_1 Size_2 Address_1 EOP = 1 JMP = 0 Address_2 Size_2 EOT = 0 EOP = 1 JMP = 0 Address_3 Don’t Care EOT = 0 EOP = 0 JMP = 1 PRD_1 PRD_2 PRD_3 Address_2 Address_3

www.national.com 118 Revision 4.1 Functional Description(Continued) Geode™ CS5530 5) The bus master transfers data to/from memory responding to bus master requests from the AC97 interface. At the completion of each PRD, the bus master’s next response depends on the settings of the flags in the PRD. Example - At the completion of PRD_1 an SMI is generated because the EOP bit is set while the bus master continues on to PRD_2. The address in the PRD Table Address Register is incremented by 08h and is now pointing to PRD_3. The SMI Status Register is read to clear the End of Page status flag. Since Audio Buffer_1 is now empty, the software can refill it. A tt h ec o m p l e t i o no fP R D _ 2a nS M Ii sg e n e r a t e d because the EOP bit is set. The bus master then c o n t i n u e so nt oP R D _ 3 .T h ea d d r e s si nt h eP R D Table Address Register is incremented by 08h. The DMA SMI Status Register is read to clear the End of Page status flag. Since Audio Buffer_2 is now empty, the software can refill it. Audio Buffer_1 has been refilled from the previous SMI. PRD_3 has the JMP bit set. This means the bus master uses the address stored in PRD_3 (Address_3) to locate the next PRD. It does not use the address in the PRD Table Address Register to get the next PRD. Since Address_3 is the location of PRD_1, the bus master has looped the PRD table. Stopping the bus master can be accomplished by not reading the SMI Status Register End of Page status flag. This will lead to a second EOP which causes a Bus Master Error and pauses the bus master. In effect, once a bus master has been enabled it never has to be disabled, just paused. The bus master cannot be disabled unless the bus master has been paused or has reached an EOT.

3.7.1.5 AC97 Codec Interface

The CS5530 provides an AC97 Specification Revision 1.3, 2.0, and 2.1 compatible interface. Any AC97 codec which supports sample rate conversion (SRC) can be used with the CS5530. This type of codec allows for a design which meets the requirements for PC97 and PC98-compliant audio as defined by Microsoft Corpora- tion. The AC97 codec (e.g., LM4548) is the master of the serial interface and generates the clocks to CS5530, Figure 3- 21 shows the codec and CS5530 signal connections. For specifications on the serial interface, refer to the appropri- ate codec manufacturer’s data sheet. For PC speaker synthesis, the CS5530 outputs the PC speaker signal on the PC_BEEP pin which is connected to the PC_BEEP input of the AC97 codec. Figure 3-21. AC97 Signal Connections Codec Configuration/Control Registers The codec related registers consist of four 32-bit regis- ters:  Codec GPIO Status Register  Codec GPIO Control Register  Codec Status Register  Codec Command Register Codec GPIO Status and Control Registers (F3BAR+ Memory Offset 00h and 04h) The Codec GPIO Status and Control Registers are used for codec GPIO related tasks such as enabling a codec GPIO interrupt to cause an SMI. Codec Status Register (F3BAR+Memory Offset 08h) The Codec Status Register stores the codec status word. It updates every valid Status Word slot. Codec Control Register (F3BAR+Memory Offset 0Ch) The Codec Control Register writes the control word to the codec. By writing the appropriate control words to this port, the features of the codec can be controlled. The con- tents of this register are written to the codec during the Control Word slot. BITCLK PC_BEEP SDAT_I SDAT_O PC_BEEP SDATA_IN SDATA_OUT AC97 BIT_CLK 24.576MHz SYNC SYNC External Source Codec Geode™ CS5530 I/O Companion

Revision 4.1 119 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-65. Codec Configuration/Control Registers Bit Description F3BAR+Memory Offset 00h-03h Codec GPIO Status Register (R/W) Reset Value = 00000000h 31 Codec GPIO Interface:0 = Disable; 1 = Enable. 30 Codec GPIO SMI: Allow codec GPIO interrupt to generate an SMI: 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset10h/12h[1]. 29:21 Reserved: Set to 0. 20 Codec GPIO Status Valid (Read Only):Is the status read valid? 0 = Y es; 1 = No. 19:0 Codec GPIO Pin Status (Read Only):This is the GPIO pin status that is received from the codec in slot 12 on SDATA_IN signal. F3BAR+Memory Offset 04h-07h Codec GPIO Control Register (R/W) Reset Value = 00000000h 31:20 Reserved: Set to 0. 19:0 Codec GPIO Pin Data:This is the GPIO pin data that is sent to the codec in slot 12 on the SDATA_OUT signal. F3BAR+Memory Offset 08h-0Bh Codec Status Register (R/W) Reset Value = 00000000h 31:24 Codec Status Address (Read Only):Address of the register for which status is being returned. This address comes from slot 1 bits [19:12]. 23 Codec Serial INT SMI:Allow codec serial interrupt to generate an SMI: 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset10h/12h[1]. 22 SYNC Pin: Selects SYNC pin level: 0 = Low; 1 = High. 21 Enable SDATA_IN2: Pin AE24 functions as: 0 = GPIO1; 1 = SDATA_IN2. For this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0).

20 Audio Bus Master 5 AC97 Slot Select:Selects slot for Audio Bus Master 5 to receive data:

0 = Slot 6; 1 = Slot 11.

19 Audio Bus Master 4 AC97 Slot Select:Selects slot for Audio Bus Master 4 to transmit data:

0 = Slot 6; 1 = Slot 11. 18 Reserved: Set to 0. 17 Status Tag (Read Only):Determines if the status in bits [15:0] is new or not: 0 = Not new; 1 = New. 16 Codec Status Valid (Read Only):I st h es t a t u si nb i t s[ 1 5 : 0 ]v a l i d ?0=N o ;1=Y e s . 15:0 Codec Status (Read Only):This is the codec status data that is received from the codec in slot 2 on SDATA_IN. Only bits [19:4] are used from slot 2. F3BAR+Memory Offset 0Ch-0Fh Codec Command Register (R/W) Reset Value = 00000000h 31:24 Codec Command Address: Address of the codec control register for which the command is being sent. This address goes in slot 1 bits [19:12] on SDATA_OUT. 23:22 CS5530 Codec Communication: Selects which codec to communicate with: 00 = Primary codec 10 = Third codec 01 = Secondary codec 11 = Fourth codec Note: 00 and 01 are the only valid settings for these bits. 21:17 Reserved: Set to 0. 16 Codec Command Valid: Is the command in bits [15:0] valid? 0 = No; 1 = Y es. This bit is set by hardware when a command is loaded. It remains set until the command has been sent to the codec. 15:0 Codec Command: This is the command being sent to the codec in bits [19:12] of slot 2 on SDATA_OUT.

www.national.com 120 Revision 4.1 Functional Description(Continued) Geode™ CS5530

3.7.2 VSA Technology Support Hardware

The CS5530 I/O companion incorporates the required hardware in order to support the Virtual System Architec- ture (VSA) technology for capture and playback of audio using an external codec. This eliminates much of the hardware traditionally associated with industry standard audio functions. XpressAUDIO software provides 16-bit compatible sound. This software is available to OEMs for incorporation into the system BIOS ROM.

3.7.2.1 VSA Technology

VSA technology provides a framework to enable software implementation of traditionally hardware-only compo- nents. VSA technology software executes in System Man- agement Mode (SMM), enabling it to execute transparently to the operating system, drivers and appli- cations. The VSA technology design is based upon a simple model for replacing hardware components with software. Hardware to be virtualized is merely replaced with simple access detection circuitry which asserts the SMI# (System Management Interrupt) pin when hardware accesses are detected. The current execution stream is immediately preempted, and the processor enters SMM. The SMM system software then saves the processor state, initial- izes the VSA technology execution environment, decodes the SMI source and dispatches handler routines which have registered requests to service the decoded SMI source. Once all handler routines have completed, the processor state is restored and normal execution resumes. In this manner, hardware accesses are trans- parently replaced with the execution of SMM handler soft- ware. Historically, SMM software was used primarily for the sin- gle purpose of facilitating active power management for notebook designs. That software’s only function was to manage the power up and down of devices to save power. With high performance processors now available, it is feasible to implement, primarily in SMM software, PC capabilities traditionally provided by hardware. In contrast to power management code, this virtualization software generally has strict performance requirements to prevent application performance from being significantly impacted.

3.7.2.2 Audio SMI Related Registers

The SMI related registers consist of:  Second Level Audio SMI Status Registers  I/O T rap SMI and Fast Write Status Register  I/O T rap SMI Enable Register The Top SMI Status Mirror and Status Registers are the top level of hierarchy for the SMI Handler in determining t h es o u r c eo fa nS M I .T h e s et w or e g i s t e r sa r ea t F1BAR+Memory Offset 00h (Status Mirror) and F1BAR+Memory Offset 02h (Status). The registers are identical except that reading the register at F1BAR+Mem- ory Offset 02h clears the status. Second Level Audio SMI Status Registers-T h es e c - ond level of audio SMI status reporting is set up very much like the top level. There are two status reporting registers, one “read only” (mirror) and one “read to clear”. The data returned by reading either offset is the same (i.e., SMI was caused by an audio related event). The dif- ference between F3BAR+Memory Offset 12h (mirror) and 10h is in the ability to clear the SMI source at 10h. Figure 3-22 shows an SMI tree for checking and clearing the source of an audio SMI. Only the audio SMI bit is detailed here. For details regarding the remaining bits in the Top SMI Status Mirror and Status Registers refer to Table 4-16 "F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers" on page 180. I/O Trap SMI and Fast Write Status Register -This 32- bit read-only register (F3BAR+Memory Offset 14h) not only indicates if the enabled I/O trap generated an SMI, but also contains Fast Path Write related bits. I/O Trap SMI Enable Register -The I/O T rap SMI Enable Register (F3BAR+Memory Offset 18h) allows traps for specified I/O addresses and configures generation for I/O events. It also contains the enabling bit for Fast Path Write/Read features. Status Fast Path Read- If enabled, the CS5530 inter- cepts and responds to reads to several status registers. This speeds up operations, and prevents SMI generation for reads to these registers. This process is called Status Fast Path Read. Status Fast Path Read is enabled via F3BAR+Memory Offset 18h[4]. In Status Fast Path Read the CS5530 responds to reads of the following addresses: 388h-38Bh 2x0h, 2x1, 2x2h, 2x3, 2x8 and 2x9h Note that if neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible. Fast Path Write- If enabled, the CS5530 captures cer- tain writes to several I/O locations. This feature prevents two SMIs from being asserted for write operations that are known to take two accesses (the first access is an index and the second is data). This process is called Fast Path Write. Fast Path Write is enabled in via F3BAR+Memory Offset 18h[11].

Revision 4.1 121 www.national.com Functional Description(Continued) Geode™ CS5530 Fast Path Write captures the data and address bit 1 (A1) of the first access, but does not generate an SMI. A1 is stored in F3BAR+Memory Offset 14h[15]. The second access causes an SMI, and the data and address are captured as in a normal trapped I/O. In Fast Path Write, the CS5530 responds to writes to the following addresses: 388h, 38Ah and 38B 2x0h, 2x2h, and 2x8h Table 3-66 and Table 3-67 show the bit formats of the sec- ond and third level SMI status reporting registers, respec- tively. Table 3-68 shows the sound card I/O trap and Fast Path Read/Write programming bits. Figure 3-22. Audio SMI Tree Example SMI# Asserted SMM software reads SMI Header If Bit X = 0 (Internal SMI) If Bit X = 1 (External SMI) Call internal SMI handler to take appropriate actionGeode™ GXLV Geode™ CS5530 F1BAR+Memory Read to Clear to determine top-level source of SMI F3BAR+Memory Offset 10h Read to Clear SMI Deasserted after all SMI Sources are Cleared Bit 7 ABM5_SMIBits [15:2] Bit 0 Bit 1 AUDIO_SMI Offset 02h Processor to determine second-level source of SMI Bits [15:8] Bit 6 ABM4_SMI Bit 5 ABM3_SMI Bit 4 ABM2_SMI Bit 3 ABM1_SMI Bit 2 ABM0_SMI Bit 1 SER_INTR_SMI Bit 0 I/O_TRAP_SMI F3BAR+Memory Offset 14h Read to Clear to determine third-level source of SMI Bit 13 SMI_SC/FM_TRAP Bits [31:14] Bit 12 SMI_DMA_TRAP Bit 11 SMI_MPU_TRAP Bit 10 SMI_SC/FM_TRAP Bit [9:0] (i.e., Top, Second, and Third Levels) Take Appropriate Action Take Appropriate Action Other_SMI Other_SMI RSVD Other_RO Other_RO Top Level Second Level Third Level If bit 1 = 1, Source of SMI is If bit 0 = 1, Source of SMI is I/O Trap Audio Event I/O Companion

www.national.com 122 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Table 3-66. Second Level SMI Status Reporting Registers Bit Description F3BAR+Memory Offset 10h-11h Second Level Audio SMI Status Mirror Register (RC) Reset Value = 0000h 15:8 Reserved: Set to 0. 7 Audio Bus Master 5 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 5? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1). 6 Audio Bus Master 4 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 4? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR+Memory Offset 40h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 41h[0] = 1). 5 Audio Bus Master 3 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 3? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1). 4 Audio Bus Master 2 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 2? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1). 3 Audio Bus Master 1 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 1? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1). 2 Audio Bus Master 0 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 0? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1). 1 Codec Serial or GPIO Interrupt SMI Status (Read to Clear):SMI was caused by a serial or GPIO interrupt from codec? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1. SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1. 0 I/O Trap SMI Status (Read to Clear):SMI was caused by an I/O trap? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. Note: Reading this register clears the status bits. Note that bit 0 has another level (third) of SMI status reporting. A read-only “Mirror” version of this register exists at F3BAR+Memory Offset 00h. If the value of the register must be read with- out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.

Revision 4.1 123 www.national.com Functional Description(Continued) Geode™ CS5530 F3BAR+Memory Offset 12h-13h Second Level Audio SMI Status Register (RO) Reset Value = 0000h 15:8 Reserved: Set to 0. 7 Audio Bus Master 5 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 5? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1). 6 Audio Bus Master 4 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 4? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR+Memory Offset 40h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 41h[0] = 1). 5A udio Bus Master 3 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 3? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1). 4 Audio Bus Master 2 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 2? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1). 3 Audio Bus Master 1 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 1? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1). 2 Audio Bus Master 0 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 0? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1). 1 Codec Serial or GPIO Interrupt SMI Status (Read Only):SMI was caused by a serial or GPIO interrupt from codec? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1. SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1. 0 I/O Trap SMI Status (Read Only):SMI was caused by an I/O trap? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. Note: Reading this register does not clear the status bits. See F3BAR+Memory Offset 10h. Table 3-66. Second Level SMI Status Reporting Registers (Continued) Bit Description

www.national.com 124 Revision 4.1 Functional Description(Continued) Geode™ CS5530 Table 3-67. Third Level SMI Status Reporting Registers Bit Description F3BAR+Memory Offset 14h-17h I/O Trap SMI and Fast Write Status Register (RO/RC) Reset Value = 00000000h 31:24 Fast Path Write Even Access Data (Read Only):These bits contain the data from the last Fast Path Write Even access. These bits change only on a fast write to an even address. 23:16 Fast Path Write Odd Access Data (Read Only):These bits contain the data from the last Fast Path Write Odd access. These bits change on a fast write to an odd address, and also on any non-fast write. 15 Fast Write A1 (Read Only):This bit contains the A1 value for the last Fast Write access. 14 Read or Write I/O Access (Read Only):Last trapped I/O access was a read or a write? 0 = Read; 1 = Write. 13 Sound Card or FM Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the Sound Card or FM I/O Trap? 0 = No; 1 = Yes. (Note) Fast Path Write must be enabled, F3BAR+Memory Offset 18h[11] = 1, for the SMI to be reported here. If Fast Path Write is disabled, the SMI is reported in bit 10 of this register. This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[2]. 12 DMA Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the DMA I/O Trap? 0=N o ;1=Y e s .( N o t e ) This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[8:7]. 11 MPU Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the MPU I/O Trap? 0=N o ;1=Y e s .( N o t e ) This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[6:5]. 10 Sound Card or FM Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the Sound Card or FM I/O Trap? 0 = No; 1 = Yes. (Note) Fast Path Write must be disabled, F3BAR+Memory Offset 18h[11] = 0, for the SMI to be reported here. If Fast Path Write is enabled, the SMI is reported in bit 13 of this register. This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[2]. 9:0 X-Bus Address (Read Only):Bits [9:0] contain the captured ten bits of X-Bus address. Note: For the four SMI status bits (bits [13:10]), if the activity was a fast write to an even address, no SMI is generated regardless of the DMA, MPU, or sound status. If the activity was a fast write to an odd address, an SMI is generated but bit 13 is set to 1.

Revision 4.1 125 www.national.com Functional Description(Continued) Geode™ CS5530 Table 3-68. Sound Card I/O Trap and Fast Path Enable Registers Bit Description F3BAR+Memory Offset 18h-19h I/O Trap SMI Enable Register (R/W) Reset Value = 0000h 15:12 Reserved: Set to 0. 11 Fast Path Write Enable:Fast Path Write (an SMI is not generated on certain writes to specified addresses): 0 = Disable; 1 = Enable. In Fast Path Write, the CS5530 responds to writes to the following addresses: 388h, 38Ah and 38B; 2x0h, 2x2h, and 2x8h. 10:9 Fast Read:These two bits hold part of the response that the CS5530 returns for reads to several I/O locations. 8 High DMA I/O Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port C0h-DFh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12]. 7 Low DMA I/O Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 00h-0Fh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12]. 6 High MPU I/O Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 330h and 331h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11]. 5 Low MPU I/O Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 300h and 301h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11]. 4 Fast Path Read Enable/SMI Disable:Read Fast Path (an SMI is not generated on reads from specified addresses): 0 = Disable; 1 = Enable. In Fast Path Read the CS5530 responds to reads of the following addresses: 388h-38Bh; 2x0h, 2x1, 2x2h, 2x3, 2x8 and 2x9h. Note that if neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible. 3 FM I/O Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 388h to 38Bh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0].

2 Sound Card I/O Trap:0 = Disable; 1 = Enable

If this bit is enabled and an access occurs in the address ranges selected in by bits [1:0], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[10]. 1:0 Sound Card Address Range Select:These bits select the address range for the sound card I/O trap. 00 = I/O Port 220h-22Fh 10 = I/O Port 260h-26Fh 01 = I/O Port 240h-24Fh 11 = I/O Port 280h-28Fh

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3.7.2.3 IRQ Configuration Registers

The CS5530 provides the ability to set and clear IRQs internally through software control. If the IRQs are config- ured for software control, they will not respond to external hardware. There are three registers provided for this fea- ture:  Internal IRQ Enable Register  Internal IRQ Mask Register  Internal IRQ Control Register Internal IRQ Enable Register- This register configures the IRQs as internal (software) interrupts or external (hardware) interrupts. Any IRQ used as an internal soft- ware driven source must be configured as internal. Internal IRQ Mask Register-E a c hb i ti nt h eM a s kr e g i s - ter individually disables the corresponding bit in the Con- trol Register. Internal IRQ Control Register- This register allows indi- vidual software assertion/deassertion of the IRQs that are enabled as internal and unmasked. The bit formats for these registers are given in Table 3-69. Table 3-69. IRQ Configuration Registers Bit Description F3BAR+Memory Offset 1Ah-1Bh Internal IRQ Enable Register (R/W) Reset Value = 0000h Note: Must be R/W as a WORD. 15 IRQ15 Internal:Configure IRQ15 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 14 IRQ14 Internal:Configure IRQ14 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 13 Reserved: Set to 0. 12 IRQ12 Internal:Configure IRQ12 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 11 IRQ11 Internal:Configure IRQ11 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 10 IRQ10 Internal:Configure IRQ10 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 9 IRQ9 Internal:Configure IRQ9 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 8 Reserved: Set to 0. 7 IRQ7 Internal:Configure IRQ7 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 6 Reserved: Set to 0. 5 IRQ5 Internal:Configure IRQ5 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 4 IRQ4 Internal:Configure IRQ4 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 3 IRQ3 Internal:Configure IRQ3 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 2:0 Reserved: Set to 0. Note: This register must be read and written as a WORD. F3BAR+Memory Offset 1Ch-1Dh Internal IRQ Control Register (R/W) Reset Value = 00000000h 15 Assert Masked Internal IRQ15:0 = Disable; 1 = Enable. 14 Assert Masked Internal IRQ14:0 = Disable; 1 = Enable. 13 Reserved: Set to 0. 12 Assert Masked Internal IRQ12:0 = Disable; 1 = Enable. 11 Assert masked internal IRQ11:0 = Disable; 1 = Enable. 10 Assert Masked Internal IRQ10:0 = Disable; 1 = Enable. 9 Assert Masked Internal IRQ9:0 = Disable; 1 = Enable. 8 Reserved: Set to 0. 7 Assert Masked Internal IRQ7:0 = Disable; 1 = Enable. 6 Reserved: Set to 0. 5 Assert Masked Internal IRQ5:0 = Disable; 1 = Enable. 4 Assert Masked Internal IRQ4:0 = Disable; 1 = Enable. 3 Assert Masked Internal IRQ3:0 = Disable; 1 = Enable. 2:0 Reserved: Set to 0.

Revision 4.1 127 www.national.com Functional Description(Continued) Geode™ CS5530 F3BAR+Memory Offset 1Eh-1Fh Internal IRQ Mask Register (Write Only) Reset Value = 00000000h 15 Mask Internal IRQ15:0 = Disable; 1 = Enable. 14 Mask Internal IRQ14:0 = Disable; 1 = Enable. 13 Reserved: Set to 0. 12 Mask Internal IRQ12:0 = Disable; 1 = Enable. 11 Mask Internal IRQ11:0 = Disable; 1 = Enable. 10 Mask Internal IRQ10:0 = Disable; 1 = Enable. 9 Mask Internal IRQ9:0 = Disable; 1 = Enable. 8 Reserved: Set to 0. 7 Mask Internal IRQ7:0 = Disable; 1 = Enable. 6 Reserved: Set to 0. 5 Mask Internal IRQ5:0 = Disable; 1 = Enable. 4 Mask Internal IRQ4:0 = Disable; 1 = Enable. 3 Mask Internal IRQ3:0 = Disable; 1 = Enable. 2:0 Reserved: Set to 0. Table 3-69. IRQ Configuration Registers (Continued) Bit Description

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3.8 DISPLAY SUBSYSTEM EXTENSIONS

The CS5530 incorporates extensions to the GXLV proces- sor’s display subsystem. These include:  Video Accelerator - Buffers and formats input YUV video data from GXLV processor - Supports 8-bit interface to GXLV processor - X & Y scaler with bilinear filter - Color space converter (YUV to RGB)  Video Overlay Logic -C o l o r k e y - Data switch for graphics and video data  Gamma RAM - Brightness and contrast control  Display Interface - Integrated RGB video DACs - VESA DDC2B/DPMS support - Flat Panel interface Figure 3-23 shows the data path of the display subsystem extensions.

3.8.1 Video Interface Configuration Registers

Registers for configuring the video interface are accessed through F4 Index 10h, the Base Address Register (F4BAR) in Function 4. F4BAR sets the base address for the Video Interface Configuration Registers as shown in Table 3-70. Note: All Video Interface Configuration Registers have a 32-bit access granularity (only). The following subsections describe the video interface and the registers used for programming purposes. How- ever, for complete bit information refer to Section 4.3.5 “Video Controller Registers - Function 4” on page 199. Figure 3-23. 8-Bit Display Subsystem Extensions Table 3-70. Base Address Register (F4BAR) for Video Controller Support Registers Bit Description F4 Index 10h-13h Base Address Register — F4BAR (R/W) Reset Value = 00000000h This register sets the base address of the memory mapped video controller registers. Bits [11:0] are read only (0000 0000 0000), indi- cating a 4 KB memory address range. Refer to Table 4-22 for the video controller register bit formats and reset values. 31:12 Video Controller and Clock Control Base I/O Address 11:0 Address Range (Read Only) VID_DATA[7:0] 8 Input Buffer 0 (3x360x32 bit) Buffer 1 Buffer 2 Formatter Scaler Vertical Filter Horizontal Filter Color Space Converter Formatter Color Key Color Compare PIXEL[23:0] Bypass Gamma RAM FP_DATA 1824 Enable Gamma Correction Register Register

Revision 4.1 129 www.national.com Functional Description(Continued) Geode™ CS5530

3.8.2 Video Accelerator

The CS5530 off-loads the processor from several comput- ing-intensive tasks related to the playback of full motion video. By incorporating this level of hardware-assist, a CS5530/GXLV processor based system can sustain 30 frames-per-second of MPEG quality video.

3.8.2.1 Line Buffers

The CS5530 accepts an 8-bit video stream from the pro- cessor and provides three full MPEG resolution line buff- ers (3x360x32-bit). MPEG source horizontal resolutions up to 720 pixels are supported. By having three line buff- ers, the display pipeline can read from two lines while the next line of data is being loaded from the processor. This minimizes memory bandwidth utilization by requiring that a source line be transferred only once per frame. Peak bandwidth is also reduced by requiring that the video source line be transferred within the horizontal line time rather than forcing the transfer to occur during the active video window. This efficient utilization of memory band- width allows the processor and graphics accelerator an increased opportunity to access the memory subsystem and improves overall system performance during video playback.

3.8.2.2 Video Port Protocol

The video port operates at one-half the processor’s core clock rate and utilizes a two-wire handshake protocol. The VID_VAL input signal indicates that valid data has been placed on the VID_DATA[7:0] bus. When the CS5530 is ready to accept data, it asserts VID_RDY to indicate that a l i n eb u f f e ri sf r e et oa c c e p tt h en e x tl i n e .W h e nb o t h VID_VAL and VID_RDY are asserted, VID_DATA advances. The VID_RDY signal is driven by the CS5530 one clock early to the processor while the VID_VAL signal is driven by the processor coincident with valid data on VID_DATA. A sample timing diagram is shown in Figure 3-24. Figure 3-24. Video Port Protocol VID_CLK VID_VAL 8C L K s 8 + 2CLKs VID_RDY 2C L K s 3C L K sVID_DATA[7:0] 8C L K s Note: VID_CLK = CORE_CLK/2

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3.8.2.3 Video Format

The video input data can be in interleaved YUV 4:2:2 or RGB 5:6:5 format. The sequence of the individual YUV components is selectable to one of four formats via bits [3:2] in the Video Configuration Register (F4BAR+Mem- ory Offset 00h[3:2]). The decode for these bits is shown in Table 3-71. Table 3-71. Video Input Format Bits Bit Description F4BAR+Memory Offset 00h-03h Video Configuration Register (R/W) Reset Value = 00000000h

31 Reserved: Set to 0

30 High Speed Timing for Video Interface:High speed timings for the video interface: 0 = Disable; 1= Enable. If bit 30 is enabled, bit 25 should be set to 0. 29 16-bit Video Interface:Allow video interface to be 16 bits: 0 = Disable; 1= Enable. If bit 29 is enabled, 8 bits of pixel data is used for video. The 24-bit pixel data is then dithered to 16 bits. Note: F4BAR+Memory Offset 04h[25] should be set to the same value as this bit (bit 29). 28 YUV 4:2:2 or 4:2:0 Mode:0 = 4:2:2 Mode; 1= 4:2:0 Mode. If 4:2:0 mode is selected, bits [3:2] should be set to 01 if in 8-bit video mode and 10 if in 16-bit video mode. Note: The GXLV processor does not support 4:2:0 mode. 27 Video Line Size (DWORDs):This is the MSB of the Video Line Size (DWORDs). See bits [15:8] for description.

26 Reserved: Set to 0

25 Early Video Ready:Generate VID_RDY output signal one-half VID_CLK period early to improve the speed of the video port operation: 0 = Disable; 1 = Enable. Bit 25 should be set to 0 if bit 30 is enabled. 24 Initial Buffer Read Address:This is the MSB of the Initial Buffer Read Address. See bits [23:16] for description. 23:16 Initial Buffer Read Address:This field is used to preload the starting read address for the line buffers at the beginning of each display line. It is used for hardware clipping of the video window at the left edge of the active display. It represents the DWORD address of the source pixel which is to be displayed first. For an unclipped window, this value should be 0. 15:8 Video Line Size (DWORDs):This field represents the horizontal size of the source video data in DWORDs. 7 YF i l t e rE n a b l e :Vertical filter: 0 = Disable; 1= Enable. 6 XF i l t e rE n a b l e :Horizontal filter: 0 = Disable; 1 = Enable. 5 CSC Bypass: Allow color-space-converter to be bypassed. Primarily used for displaying an RGB graphics overlay rather than a YUV video overlay. 0 = Overlay data passes through CSC; 1 = Overlay data bypasses CSC.

4 GV Select:Selects whether graphics or video data will be passed through the scaler hardware:

0 = Video data; 1 = Graphics data. 3:2 Video Input Format:This field defines the byte ordering of the video data on the VID_DATA bus. 8-Bit Mode (Value Byte Order [0:3]) 16-Bit Mode (Value Byte Order [0:3]) 00 = U Y0 V Y1 (also used for RGB 5:6:5 input) 00 = U Y0 V Y1 (also used for RGB 5:6:5 input) 01 = Y1 V Y0 U or 4:2:0 01 = Y0 U Y1 V 10 = Y0 U Y1 V 10 = Y1 V Y0 U or 4:2:0 11 = Y0 V Y1 U 11 = Reserved If bit 28 is enabled, bits [3:2] should be set to 01 if in 8-bit video mode and 10 if in 16-bit video mode. Note: U=C b ,V=C r 1 Video Register Update:Allow video position and scale registers to be updated simultaneously on next occurrence of vertical sync: 0 = Disable; 1 = Enable. 0 Video Enable:Video acceleration hardware: 0 = Disable; 1 = Enable.

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3.8.2.4 X and Y Scaler / Filter

The CS5530 supports horizontal and vertical scaling of the video stream up to eight times the source resolution. The scaler uses a Digital-Differential-Analyzer (DDA) b a s e du p o nt h ev a l u e sp r o g r a m m e di nt h eV i d e oS c a l e Register (F4BAR+Memory Offset 10h, see Table 3-72) The scaled video stream is then passed through horizon- tal and vertical filters which perform a 2-tap, 8-phase bilin- ear filter on the resulting stream. The filtering function removes the "blockiness" of the scaled video thereby sig- nificantly improving the quality of the displayed image. By performing the scaling and filtering function in hard- ware, video performance is substantially improved over pure software implementations by requiring that the decompression software only output the video stream at the native source resolution. This saves both processor overhead and memory bandwidth.

3.8.2.5 Color-Space-Converter

After scaling and filtering have been applied, the YUV video data is passed through the color-space converter to obtain 24-bit RGB video data. The color-space conversion equations are based on the CCIR Recommendation 601- 1a sf o l l o w s : The color-space converter clamps inputs to acceptable limits if the data is not well behaved. The color-space con- verter is bypassed for overlaying 16 bpp RGB graphics data. Table 3-72. Video Scale Register Bit Description F4BAR+Memory Offset 10h-13h Video Scale Register (R/W) Reset Value = xxxxxxxxh 31:30 Reserved: Set to 0. 29:16 Video Y Scale Factor:This field represents the video window vertical scale factor according to the following formula: VID_Y_SCL = 8192 * (Ys - 1) / (Yd - 1) Where: Ys = Video Source vertical size in lines Yd = Video Destination vertical size in lines 15:14 Reserved: Set to 0. 13:0 Video X Scale Factor:This field represents the video window horizontal scale factor according to the following formula: VID_X_SCL = 8192 * (Xs - 1) / (Xd - 1) Where: Xs = Video Source horizontal size in pixels Xd = Video Destination horizontal size in pixels

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3.8.3 Video Overlay

The video data from the color-space converter is then mixed with the graphics data based upon the video win- dow position. The video window position is programmable via the Video X and Y Position Registers (F4BAR+Mem- ory Offset 08h and 0Ch). A color-keying mechanism is employed to compare either the source (video) or destina- tion (graphics) color to the color key programmed via the Video Color Key Register (FBAR+Offset 14h) and to select the appropriate pixel for display within the video window. The range of the color key is programmable by setting the appropriate bits in the Video Color Mask Reg- ister (F4BAR+Memory Offset 18h). This mechanism greatly reduces the software overhead for computing visi- ble pixels, and ensures that the video display window may be partially occluded by overlapping graphics data. Tables 3-73 and 3-74 show the bit formats for these regis- ters The CS5530 accepts graphics data over the PIXEL[23:0] interface from the GXLV processor at the screen DOT clock rate. The CS5530 is capable of displaying graphics resolutions up to 1600x1200 at color depths up to 24 bits per pixel (bpp) while simultaneously overlaying a video window. Table 3-73. Video X and Y Position Registers Bit Description F4BAR+Memory Offset 08h-0Bh Video X Register (R/W) Reset Value = xxxxxxxxh 31:27 Reserved: Set to 0. 26:16 V i d e oXE n dP o s i t i o n :This field represents the horizontal end position of the video window according to the following formula: Position programmed = screen position + (H_TOTAL – H_SYNC_END) – 13. 15:11 Reserved: Set to 0. 10:0 Video X Start Position:This field represents the horizontal start position of the video window according to the following formula: Position programmed = screen position + (H_TOTAL – H_SYNC_END) – 13. F4BAR+Memory Offset 0Ch-0Fh Video Y Register (R/W) Reset Value = xxxxxxxxh 31:27 Reserved: Set to 0. 26:16 V i d e oYE n dP o s i t i o n :This field represents the vertical end position of the video window according to the following for- mula: Position programmed = screen position + (V_TOTAL – V_SYNC_END) + 1. 15:11 Reserved: Set to 0. 10:0 Video Y Start Position:This field represents the vertical start position of the video window according to the following for- mula: Position programmed = screen position + (V_TOTAL – V_SYNC_END) + 1. Table 3-74. Video Color Registers Bit Description F4BAR+Memory Offset 14h-17h Video Color Key Register (R/W) Reset Value = xxxxxxxxh 31:24 Reserved: Set to 0. 23:0 Video Color Key:This field represents the video color key. It is a 24-bit RGB value. The graphics or video data being compared may be masked prior to the compare by programming the Video Color Mask register appropriately. F4BAR+Memory Offset 18h-1Bh Video Color Mask Register (R/W) Reset Value = xxxxxxxxh 31:24 Reserved: Set to 0. 23:0 Video Color Mask:This field represents the video color mask. It is a 24-bit RGB value. Zeroes in the mask cause the corresponding bits in the graphics or video stream being compared to be ignored.

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3.8.4 Gamma RAM

Either the graphics or video stream may be routed through an on-chip gamma RAM (3x256x8-bit) which can be used for gamma-correction of either data stream, or contrast/brightness adjustments in the case of video data. A bypass path is provided for either the graphics or video stream (depending on which is sent through the gamma RAM). The two streams are merged based on the results of the color key compare. Configuration for this feature and the display interface are through the Video Configuration Register (F4BAR+Mem- ory Offset 04h). Table 3-75 shows the bit formats for this register. Table 3-75. Display Configuration Register Bit Description F4BAR+Memory Offset 04h-07h Display Configuration Register (R/W) Reset Value = 00h 31 DDC Input Data (Read Only):This is the DDC input data bit for reads. 30 Red Comparator (Read Only):This is the value of the red video DAC comparator. 29 Green Comparator (Read Only):This is the value of the green video DAC comparator. 28 Blue Comparator (Read Only):This is the value of the blue video DAC comparator. 27 Flat Panel On (Read Only):This bit indicates whether the attached flat panel display is powered on or off. The bit transi- tions at the end of the power-up or power-down sequence. 0 = Off; 1 = On. 26 DAC External Voltage Reference Enable:This bit enables the use of an external voltage reference for the video DAC. When enabled, an external voltage reference should be connected to the EXTVREFIN pin. When disabled, the DAC inter- nal voltage reference will be used. 0 = Disable; 1 = Enable. 25 16-Bit Graphics Enable:This bit works in conjunction with the 16-bit Video Interface bit at F4BAR+Memory Offset 00h[29]. This bit should be set to the same value as the 16-bit Video Interface bit. 24 DDC Output Enable:This bit enables the DDC_SDA line to be driven for write data. 0 = DDC_SDA pin is input; 1 = DDC_SDA pin is output. 23 DDC Output Data:This is the DDC data bit. 22 DDC Clock: This is the DDC clock bit. It is used to clock the DDC_SDA bit.

21 Palette Bypass:Selects whether graphics or video data should bypass the Gamma RAM:

0 = Video data; 1 = Graphics data. 20 Video/Graphics Color Key Select:Selects whether the video or graphics data stream will be used for color/chroma key- ing. 0 = Graphics data is compared to color key; 1 = Video data is compared to color key. 19:17 Power Sequence Delay:This field selects the number of frame periods that will transpire between successive transitions of the power sequence control lines. Valid values are 001h to 111h. 16:14 CRT Sync Skew: This 3-bit field represents the number of pixel clocks to skew the horizontal and vertical syncs that are sent to the CRT. This field should be programmed to 100 as the baseline. The syncs may be moved forward or backward relative to the pixel data via this register. It is used to compensate for the pipeline delay through the graphics pipeline. 13 Flat Panel Dither Enable:This bit will enable the flat panel dithering. It enables 24 bpp display data to be approximated with an 18-bit flat panel display. 0 = Disable; 1 = Enable. 12 XGA Flat Panel:This bit enables the FP_CLK_ EVEN output signal which can be used to demultiplex the FP_DATA bus into even and odd pixels. 0 = Standard flat panel; 1 = XGA flat panel.

11 Flat Panel Vertical Synchronization Polarity:Selects the flat panel vertical sync polarity:

0 = FP vertical sync is normally low, transitioning high during sync interval. 1 = FP vertical sync is normally high, transitioning low during sync interval.

10 Flat Panel Horizontal Synchronization Polarity:Selects the flat panel horizontal sync polarity:

0 = FP horizontal sync is normally low, transitioning high during sync interval. 1 = FP horizontal sync is normally high, transitioning low during sync interval.

9 CRT Vertical Synchronization Polarity:Selects the CRT vertical sync polarity:

0 = CRT vertical sync is normally low, transitioning high during sync interval. 1 = CRT vertical sync is normally high, transitioning low during sync interval.

8 CRT Horizontal Synchronization Polarity:Selects the CRT horizontal sync polarity:

0 = CRT horizontal sync is normally low, transitioning high during sync interval. 1 = CRT horizontal sync is normally high, transitioning low during sync interval.

7 Flat Panel Data Enable:Enables the flat panel data bus:

0 = FP_DATA [17:0] is forced low; 1 = FP_DATA [17:0] is driven based upon power sequence control.

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3.8.5 Display Interface

The CS5530 interfaces directly to a variety of display devices including conventional analog CRT displays, TFT flat panels, the National Semiconductor CS9210 DSTN Controller, or optionally to digital NTSC/PAL encoder devices.

3.8.5.1 Video DACs

The CS5530 incorporates triple 8-bit video Digital-to-Ana- log Converters (DACs) for interfacing directly to CRT dis- plays. The video DACs are capable of operation up to 170 MHz for supporting up to 1600x1200 display at a 75 Hz refresh rate.

3.8.5.2 VESA DDC2B / DPMS

The CS5530 supports the VESA DDC2B and DPMS stan- dards for enhanced monitor communications and power management support.

3.8.5.3 Flat Panel Support

The CS5530 also interfaces directly to industry standard 18-bit Active Matrix Thin-Film-Transistor (TFT) flat panels. The CS5530 includes 24-bit to 18-bit dithering logic to increase the apparent number of colors displayed on 18- bit flat panels. In addition, the CS5530 incorporates power sequencing logic to simplify the design of a portable system. The flat panel port of the CS5530 may optionally drive the CS9210 DSTN Controller device for color dual-scan dis- play (DSTN) support. If flat panel support is not required, the flat panel output port may be used to supply digital video data to one of several types of NTSC/PAL encoder devices on the market. 6 Flat Panel Power Enable:The transition of this bit initiates a flat panel power-up or power-down sequence: 0 -> 1 = Power-up flat panel; 1 -> 0 = Power-down flat panel. 5 DAC Power-down (active low):This bit must be set to power-up the video DACs. It can be cleared to power-down the video DACs when not in use. 0 = DACs are powered down; 1 = DACs are powered up. 4 Reserved: Set to 0. 3 DAC Blank Enable:This bit enables the blank to the video DACs. 0 = DACs are constantly blanked; 1 = DACs are blanked normally. 2 CRT Vertical Sync Enable:Enables the CRT vertical sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable. 1 CRT Horizontal Sync Enable:Enables the CRT horizontal sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable. 0 Display Enable:Enables the graphics display pipeline. It is used as a reset for the display control logic. 0 = Reset display control logic; 1 = Enable display control logic Table 3-75. Display Configuration Register (Continued) Bit Description

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3.9 UNIVERSAL SERIAL BUS SUPPORT

The CS5530 integrates a Universal Serial Bus (USB) con- troller which supports two ports. The USB controller is OpenHCI compliant, a standard developed by Compaq, Microsoft, and National Semiconductor. The USB core consists of three main interface blocks: the USB PCI interface controller, the USB host controller, and the USB interface controller. Legacy keyboard and mouse controllers are also supported for DOS compatibility with those USB devices. This document must be used along with the following pub- lic domain reference documents for a complete functional description of the USB controller:  USB Specification Revision 1.0  OpenHCI Specification, Revision 1.0  PCI Specification, Version 2.1

3.9.1 USB PCI Controller

The PCI controller interfaces the host controller to the PCI bus. As a master, the PCI controller is responsible for run- ning cycles on the PCI bus on behalf of the host controller. As a target, the PCI controller monitors the cycles on the PCI bus and determines when to respond to these cycles. The USB core is a PCI target when it decodes cycles to its internal PCI configuration registers or to its internal PCI memory mapped I/O registers. The USB core is implemented as a unique PCI device in the CS5530. It has its own PCI Header and Configuration space and is mapped through PCI Configuration Mecha- nism #1 as: Bus #0, Device #0 (AD28 = 1 or AD26 = 1), Function #0 (referred to as PCIUSB). The USB core can be enabled/disabled through F0 Index 43h[0]. All registers can be accessed via 8-, 16-, or 32-bit cycles (i.e., each byte is individually selected by the byte enables.) Registers marked as reserved, and reserved bits within a register are not implemented and should return 0s when read. Writes have no effect for reserved registers. These registers are summarized in Table 3-76. For complete bit information, see Section 4.4 “USB Con- troller Registers - PCIUSB” on page 206. Table 3-76. USB PCI Header Registers PCIUSB Name Access 00h-01h Vendor ID RO 02h-03h Device ID RO 04h-05h Command R/W 06h-07h Status R/W 08h Revision ID RO 09h-0Bh Class Code RO 0Ch Cache Line Size Register R/W 0Dh Latency Timer Register R/W 0Eh Header Type RO 0Fh BIST Register RO 10h-13h Base Address Register 0 R/W 14h-3Bh Reserved -- 3Ch Interrupt Line R/W 3Dh Interrupt Pin R/W 3Eh Minimum Grant R/W 3Fh Maximum Latency R/W 40h-43h T est Mode Enable R/W 44h Operational Mode Enable R/W 45h-FFh Reserved --

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3.9.2 USB Host Controller

In the USB core is the operational control block. It is responsible for the host controllers operational states (Suspend, Disable, Enable), special USB signals (Reset, Resume), status, interrupt control, and host controller configuration. The host controller interface registers are PCI memory mapped I/O. They are summarized in Table 3-77.

3.9.3 USB Power Management

At this time, USB supports minimal system level power management features. The only power management fea- ture implemented is the disabling of the USB clock gener- ator in USB Suspend state. Additional power management features will require slight modifications. The design supports PCICLK frequencies from 0 to 33 MHz. Synchronization between the PCI and USB clock domains is frequency independent. Remote wakeup of USB is asynchronously implemented from the USB Ports to PCI INTA#. The design needs USBCLK to be operational at all times. If it is necessary to stop the 48 MHz clock, the system design requires that the signal used to enable/disable the USB clock generators is also used to wake the 48 MHz clock source. Currently, the RemoteWakeupConnected and RemoteWakeupEnable bits in the HcControl register are not implemented. Table 3-77. USB Host Controller Registers Offset Name 00h-03h HcRevision 04h-07h HcControl 08h-0Bh HcCommandStatus 0Ch-0Fh HcInterruptStatus 10h-13h HcInterruptEnable 14h-17h HcInterruptDisable 18h-1Bh HcHCCA 1Ch-1Fh HcPeriodCurrentED 20h-23h HcControlHeadED 24h-27h HcControlCurrentED 28h-2Bh HcBulkHeadED 2Ch-2Fh HcBulkCurrentED 30h-33h HcDoneHead 34h-37h HcFmInterval 38h-3Bh HcFrameRemaining 3Ch-3Fh HcFmNumber 40h-43h HcPeriodicStart 44h-47h HcLSThreshold 48h-4Bh HcRhDescriptorA 4Ch-4Fh HcRhDescriptorB 50h-53h HcRhStatus 54h-57h HcRhPortStatus[1] 58h-5Ch HcRhPortStatus[2] 100h-103h HceControl 104h-107h HceInput 108h-10Bh HceOutput 10C-10Fh HceStatus

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4.0 Register Descriptions

The Geode CS5530 is a multi-function device. Its register space can be broadly divided into four categories in which specific types of registers are located: 1) Chipset Register Space (F0-F4) 2) USB Controller Register Space (PCIUSB) 3) ISA Legacy I/O Register Space (I/O Port) 4) V-ACPI I/O Register Space (I/O Port) The Chipset and the USB Controller Register Spaces are accessed through the PCI interface using the PCI Type One Configuration Mechanism. The Chipset Register Spaceof the CS5530 is comprised of five separate functions (F0-F4). Each with its own regis- ter space consisting of PCI header registers and memory or I/O mapped registers. F0: Bridge Configuration Registers F1: SMI Status and ACPI Timer Registers F2: IDE Controller Registers F3: XpressAUDIO Subsystem Registers F4: Video Controller Registers The PCI header is a 256-byte region used for configuring a PCI device or function. The first 64 bytes are the same for all PCI devices and are predefined by the PCI specifi- cation. These registers are used to configure the PCI for the device. The rest of the 256-byte region is used to con- figure the device or function itself. The USB Controller Register Spaceconsists of the standard PCI header registers. The USB controller sup- ports two ports and is OpenHCI- compliant. The ISA Legacy I/O Register Spacecontains all the leg- acy compatibility I/O ports that are internal, trapped, shad- owed, or snooped. The V-ACPI I/O Register Spacecontains two types of registers: Fixed Feature and General Purpose. These reg- isters are emulated by the SMI handling code rather than existing in physical hardware. To the ACPI-compliant operating system, the SMI-base virtualization is transpar- ent. An ACPI compliant system is one whose underlying BIOS, device drivers, chipset and peripherals conform to revision 1.0 or newer of the Advanced Control and Power Interface specification. The CS5530 V-ACPI (Virtual ACPI) solution provides the following support:  CPU States — C1, C2  Sleep States — S1, S2, S4, S4BIOS, S5  Embedded Controller (Optional) — SCI and SWI event inputs  General Purpose Events — Fully programmable GPE0 Event Block registers The remaining subsections of this chapter is as follows:  A brief discussion on how to access the registers located in the PCI Configuration Space  Register summary  Detailed bit formats of all registers

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4.1 PCI CONFIGURATION SPACE AND ACCESS METHODS

Configuration cycles are generated in the processor. All configuration registers in the CS5530 are accessed through the PCI interface using the PCI Type One Config- uration Mechanism. This mechanism uses two DWORD I/O locations at 0CF8h and 0CFCh. The first location (0CF8h) references the Configuration Address Register. The second location (0CFCh) references the Configura- tion Data Register. To access PCI configuration space, write the Configura- tion Address (0CF8h) Register with data that specifies the CS5530 as the device on PCI being accessed, along with the configuration register offset. On the following cycle, a read or write to the Configuration Data Register (CDR) causes a PCI configuration cycle to the CS5530. BYTE, WORD, or DWORD accesses are allowed to the CDR at 0CFCh, 0CFDh, 0CFEh, or 0CFFh. The CS5530 has six configuration register sets, one for each function (F0-F4) and USB (PCIUSB). Base Address Registers (BARs) in the PCI header registers are pointers for additional I/O or memory mapped configuration regis- ters. Table 4-1 shows the PCI Configuration Address Register (0CF8h) and how to access the PCI header registers. Table 4-1. PCI Configuration Address Register (0CF8h) 31 30 24 23 16 15 11 10 8 7 2 1 0 Configuration Space Mapping RSVD Bus Number Device Number Function Index DWORD 1 (Enable) 000 0000 0000 0000 xxxx x (Note) xxx xxxx xx 00 (Always) Function 0 (F0): Bridge Configuration Register Space 80h 0000 0000 1001 0 or 1000 0 000 Index Function 1 (F1): SMI Status and ACPI Timer Register Space 80h 0000 0000 1001 0 or 1000 0 001 Index Function 2 (F2): IDE Controller Register Space 80h 0000 0000 1001 0 or 1000 0 010 Index Function 3 (F3): XpressAUDIO Subsystem Register Space 80h 0000 0000 1001 0 or 1000 0 011 Index Function 4 (F4): Video Controller Register Space 80h 0000 0000 1001 0 or 1000 0 100 Index PCIUSB: USB Controller Register Space 80h 0000 0000 1001 1 or 1000 1 000 Index Note: The device number depends upon the strapping of pin H26 (HOLD_REQ#) during POR. Strap pin H26 low: IDSEL = AD28 (Chipset Register Space) and AD29 (USB Register Space) Strap pin H26 high: IDSEL = AD26 (Chipset Register Space) and AD27 (USB Register Space) The strapping of pin H26 can be read back in F0 Index 44h[6].

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4.2 REGISTER SUMMARY

The tables in this subsection summarize all the registers of the CS5530. Included in the tables are the register’s reset values and page references where the bit formats are found. Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary F0 Index Width (Bits) Type Name Reset Value Reference (Table 4-14) 00h-01h 16 RO Vendor Identification Register 1078h Page 149 02h-03h 16 RO Device Identification Register 0100h Page 149 04h-05h 16 R/W PCI Command Register 0000h Page 149 06h-07h 16 R/W PCI Status Register 0280h Page 149 08h 8 RO Device Revision ID Register xxh Page 150 09h-0Bh 24 RO PCI Class Code Register 060100h Page 150 0Ch 8 R/W PCI Cache Line Size Register 00h Page 150 0Dh 8 R/W PCI Latency Timer Register 00h Page 150 0Eh 8 RO PCI Header Type Register 00h Page 150 0Fh 8 RO PCI BIST Register 00h Page 150 10h-3Fh -- -- Reserved -- Page 150 40h 8 R/W PCI Function Control Register 1 89h Page 150 41h 8 R/W PCI Function Control Register 2 10h Page 151 42h 8 R/W PCI Function Control Register 3 0Fh Page 151 43h 8 R/W USB Shadow Register 03h Page 152 44h 8 R/W Reset Control Register xx000000b Page 152 45h-4Fh -- -- Reserved -- Page 153 50h 8 R/W PIT Control/ISA CLK Divider 7Bh Page 153 51h 8 R/W ISA I/O Recovery Control Register 40h Page 153 52h 8 R/W ROM/AT Logic Control Register F8h Page 153 53h 8 R/W Alternate CPU Support Register 00h Page 154 54h-59h -- -- Reserved -- Page 154 5Ah 8 R/W Decode Control Register 1 03h Page 154 5Bh 8 R/W Decode Control Register 2 20h Page 155 5Ch 8 R/W PCI Interrupt Steering Register 1 00h Page 155 5Dh 8 R/W PCI Interrupt Steering Register 2 00h Page 155 5Eh-6Fh -- -- Reserved -- Page 156 70h-71h 16 R/W General Purpose Chip Select Base Address Register 0000h Page 156 72h 8 R/W General Purpose Chip Select Control Register 00h Page 156 73h-7Fh -- -- Reserved -- Page 156 80h 8 R/W Power Management Enable Register 1 00h Page 156 81h 8 R/W Power Management Enable Register 2 00h Page 157 82h 8 R/W Power Management Enable Register 3 00h Page 158 83h 8 R/W Power Management Enable Register 4 00h Page 159 84h 8 RO Second Level Power Management Status Mirror Register 1 40h Page 160 85h 8 RO Second Level Power Management Status Mirror Register 2 00h Page 161 86h 8 RO Second Level Power Management Status Mirror Register 3 00h Page 162 87h 8 RO Second Level Power Management Status Mirror Register 4 00h Page 163 88h 8 R/W General Purpose Timer 1 Count Register 00h Page 164 89h 8 R/W General Purpose Timer 1 Control Register 00h Page 164 8Ah 8 R/W General Purpose Timer 2 Count Register 00h Page 165 8Bh 8 R/W General Purpose Timer 2 Control Register 00h Page 165 8Ch 8 R/W IRQ Speedup Timer Count Register 00h Page 165 8Dh 8 R/W Video Speedup Timer Count Register 00h Page 165

www.national.com 140 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 8Eh 8 R/W VGA Timer Count Register 00h Page 165 8Fh -- -- Reserved -- Page 166 90h 8 R/W GPIO Pin Direction Register 1 00h Page 166 91h 8 R/W GPIO Pin Data Register 1 00h Page 166 92h 8 R/W GPIO Control Register 1 00h Page 167 93h 8 R/W Miscellaneous Device Control Register 00h Page 167 94h 8 R/W Suspend Modulation OFF Count Register 00h Page 168 95h 8 R/W Suspend Modulation ON Count Register 00h Page 168 96h 8 R/W Suspend Configuration Register 00h Page 168 97h 8 R/W GPIO Control Register 2 00h Page 169 98h-99h 16 R/W Primary Hard Disk Idle Timer Count Register 0000h Page 169 9Ah-9Bh 16 R/W Floppy Disk Idle Timer Count Register 0000h Page 169 9Ch-9Dh 16 R/W Parallel / Serial Idle Timer Count Register 0000h Page 170 9Eh-9Fh 16 R/W Keyboard / Mouse Idle Timer Count Register 0000h Page 170 A0h-A1h 16 R/W User Defined Device 1 Idle Timer Count Register 0000h Page 170 A2h-A3h 16 R/W User Defined Device 2 Idle Timer Count Register 0000h Page 170 A4h-A5h 16 R/W User Defined Device 3 Idle Timer Count Register 0000h Page 170 A6h-A7h 16 R/W Video Idle Timer Count Register 0000h Page 171 A8h-A9h 16 R/W Video Overflow Count Register 0000h Page 171 AAh-ABh -- -- Reserved -- Page 171 ACh-ADh 16 R/W Secondary Hard Disk Idle Timer Count Register 0000h Page 171 AEh 8 WO CPU Suspend Command Register 00h Page 171 AFh 8 WO Suspend Notebook Command Register 00h Page 171 B0h-B3h -- -- Reserved -- Page 171 B4h 8 RO Floppy Port 3F2h Shadow Register xxh Page 172 B5h 8 RO Floppy Port 3F7h Shadow Register xxh Page 172 B6h 8 RO Floppy Port 1F2h Shadow Register xxh Page 172 B7h 8 RO Floppy Port 1F7h Shadow Register xxh Page 172 B8h 8 RO DMA Shadow Register xxh Page 172 B9h 8 RO PIC Shadow Register xxh Page 172 BAh 8 RO PIT Shadow Register xxh Page 173 BBh 8 RO RTC Index Shadow Register xxh Page 173 BCh 8 R/W Clock Stop Control Register 00h Page 173 BDh-BFh -- -- Reserved -- Page 173 C0h-C3h 32 R/W User Defined Device 1 Base Address Register 00000000h Page 173 C4h-C7h 32 R/W User Defined Device 2 Base Address Register 00000000h Page 173 C8h-CBh 32 R/W User Defined Device 3 Base Address Register 00000000h Page 173 CCh 8 R/W User Defined Device 1 Control Register 00h Page 174 CDh 8 R/W User Defined Device 2 Control Register 00h Page 174 CEh 8 R/W User Defined Device 3 Control Register 00h Page 174 CFh -- -- Reserved -- Page 174 D0h 8 WO Software SMI Register 00h Page 174 D1h-EBh -- -- Reserved -- Page 174 ECh 8 R/W Timer Test Register 00h Page 174 EDh-F3h -- -- Reserved -- Page 174 F4h 8 RC Second Level Power Management Status Register 1 84h Page 175 F5h 8 RC Second Level Power Management Status Register 2 00h Page 176 F6h 8 RC Second Level Power Management Status Register 3 00h Page 177 Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary (Continued) F0 Index Width (Bits) Type Name Reset Value Reference (Table 4-14)

Revision 4.1 141 www.national.com Register Descriptions(Continued) Geode™ CS5530 F7h 8 RO/RC Second Level Power Management Status Register 4 00h Page 178 F8h-FFh -- -- Reserved -- Page 178 Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary (Continued) F0 Index Width (Bits) Type Name Reset Value Reference (Table 4-14) Table 4-3. Function 1: PCI Header Registers for SMI Status and ACPI Timer Summary F1 Index Width (Bits) Type Name Reset Value Reference (Table 4-15) 00h-01h 16 RO Vendor Identification Register 1078h Page 179 02h-03h 16 RO Device Identification Register 0101h Page 179 04h-05h 16 R/W PCI Command Register 0000h Page 179 06h-07h 16 RO PCI Status Register 0280h Page 179 08h 8 RO Device Revision ID Register 00h Page 179 09h-0Bh 24 RO PCI Class Code Register 068000h Page 179 0Ch 8 RO PCI Cache Line Size Register 00h Page 179 0Dh 8 RO PCI Latency Timer Register 00h Page 179 0Eh 8 RO PCI Header Type Register 00h Page 179 0Fh 8 RO PCI BIST Register 00h Page 179 10h-13h 32 R/W Base Address Register (F1BAR): Sets base address for memory mapped SMI status and ACPI timer support regis- ters (summarized in Table 4-4). 00000000h Page 179 14h-FFh -- -- Reserved -- Page 179 Table 4-4. F1BAR: SMI Status and ACPI Timer Registers Summary F1BAR+ Memory Offset Width (Bits) Type Name Reset Value Reference (Table 4-16) 00h-01h 16 RO Top SMI Status Mirror Register 0000h Page 180 02h-03h 16 RC Top SMI Status Register 0000h Page 181 04h-05h 16 RO Second Level General Traps & Timers Status Mirror 0000h Page 182 06h-07h 16 RC Second Level General Traps & Timers Status Register 0000h Page 183 08h-09h 16 Read to Enable SMI Speedup Disable Register 0000h Page 183 0Ah-1Bh -- -- Reserved -- Page 183 1Ch-1Fh 32 RO ACPI Timer Count Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch in Silicon Revision 1.3 and above. 00FFFFFCh Page 183 20h-4Fh -- -- Not Used -- Page 183 50h-FFh Note: The registers located at F1BAR+Memory Offset 50h-FFh can also be accessed at F0 Index 50h-FFh. The pre- ferred method is to program these registers through the F0 Register Space. Refer to Table 4-2 "Function 0: PCI Header and Bridge Configuration Registers Summary" on page 139 for summary information.

www.national.com 142 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Table 4-5. Function 2: PCI Header Registers for IDE Controller Summary F2 Index Width (Bits) Type Name Reset Value Reference (Table 4-17) 00h-01h 16 RO Vendor Identification Register 1078h Page 184 02h-03h 16 RO Device Identification Register 0102h Page 184 04h-05h 16 R/W PCI Command Register 0000h Page 184 06h-07h 16 RO PCI Status Register 0280h Page 184 08h 8 RO Device Revision ID Register 00h Page 184 09h-0Bh 24 RO PCI Class Code Register 010180h Page 184 0Ch 8 RO PCI Cache Line Size Register 00h Page 184 0Dh 8 RO PCI Latency Timer Register 00h Page 184 0Eh 8 RO PCI Header Type Register 00h Page 184 0Fh 8 RO PCI BIST Register 00h Page 184 10h-1Fh -- -- Reserved -- Page 184 20h-23h 32 R/W Base Address Register (F2BAR): Sets base address for I/O mapped IDE controller configuration registers (summarized in Table 4-6). 00000001h Page 184 24h-FFh -- -- Reserved -- Page 184 Table 4-6. F2BAR: IDE Controller Configuration Registers Summary F2BAR+ I/O Offset Width (Bits) Type Name Reset Value Reference (Table 4-18) 00h 8 R/W IDE Bus Master 0 Command Register: Primary 00h Page 185 01h -- -- Not Used -- Page 185 02h 8 R/W IDE Bus Master 0 Status Register: Primary 00h Page 185 03h -- -- Not Used -- Page 185 04h-07h 32 R/W IDE Bus Master 0 PRD Table Address: Primary 00000000h Page 185 08h 8 R/W IDE Bus Master 1 Command Register: Secondary 00h Page 185 09h -- -- Not Used -- Page 185 0Ah 8 R/W IDE Bus Master 1 Status Register: Secondary 00h Page 186 0Bh -- -- Not Used -- Page 186 0Ch-0Fh 32 R/W IDE Bus Master 1 PRD Table Address: Secondary 00000000h Page 186 10h-1Fh -- -- Not Used -- Page 186 20h-23h 32 R/W Channel 0 Drive 0: PIO Register 0000E132h Page 186 24h-27h 32 R/W Channel 0 Drive 0: DMA Control Register 00017771h Page 187 28h-2Bh 32 R/W Channel 0 Drive 1: PIO Register 0000E132h Page 187 2Ch-2Fh 32 R/W Channel 0 Drive 1: DMA Control Register 00017771h Page 187 30h-33h 32 R/W Channel 1 Drive 0: PIO Register 0000E132h Page 187 34h-37h 32 R/W Channel 1 Drive 0: DMA Control Register 00017771h Page 187 38h-3Bh 32 R/W Channel 1 Drive 1: PIO Register 0000E132h Page 187 3Ch-3Fh 32 R/W Channel 1 Drive 1: DMA Control Register 00017771h Page 187

Revision 4.1 143 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-7. Function 3: PCI Header Registers for XpressAUDIO Subsystem Summary F3 Index Width (Bits) Type Name Reset Value Reference (Table 4-19) 00h-01h 16 RO Vendor Identification Register 1078h Page 188 02h-03h 16 RO Device Identification Register 0103h Page 188 04h-05h 16 R/W PCI Command Register 0000h Page 188 06h-07h 16 RO PCI Status Register 0280h Page 188 08h 8 RO Device Revision ID Register 00h Page 188 09h-0Bh 24 RO PCI Class Code Register 040100h Page 188 0Ch 8 RO PCI Cache Line Size Register 00h Page 188 0Dh 8 RO PCI Latency Timer Register 00h Page 188 0Eh 8 RO PCI Header Type Register 00h Page 188 0Fh 8 RO PCI BIST Register 00h Page 188 10h-13h 32 R/W Base Address Register (F3BAR): Sets base address for memory mapped XpressAUDIO subsystem configuration registers (summarized in Table 4-8). 00000000h Page 188 14h-FFh -- -- Reserved -- Page 188 Table 4-8. F3BAR: XpressAUDIO Subsystem Configuration Registers Summary F3BAR+ Memory Offset Width (Bits) Type Name Reset Value Reference (Table 4-20) 00h-03h 32 R/W Codec GPIO Status Register 00000000h Page 189 04h-07h 32 R/W Codec GPIO Control Register 00000000h Page 189 08h-0Bh 32 R/W Codec Status Register 00000000h Page 189 0Ch-0Fh 32 R/W Codec Command Register 00000000h Page 189 10h-11h 16 RO Second Level Audio SMI Source Mirror Register 0000h Page 190 12h-13h 16 RC Second Level Audio SMI Source Register 0000h Page 191 14h-17h 32 RO/RC I/O Trap SMI and Fast Write Status Register 00000000h Page 192 18h-19h 16 R/W I/O Trap SMI Enable Register 0000h Page 193 1Ah-1Bh 16 R/W Internal IRQ Enable Register 0000h Page 194 1Ch-1Dh 16 R/W Internal IRQ Control Register 0000h Page 194 1Eh-1Fh 16 WO Internal IRQ Mask Register 0000h Page 194 20h 8 R/W Audio Bus Master 0 Command Register 00h Page 195 21h 8 RC Audio Bus Master 0 SMI Status Register 00h Page 195 22h-23h -- -- Not Used -- Page 195 24h-27h 32 R/W Audio Bus Master 0 PRD Table Address 00000000h Page 195 28h 8 R/W Audio Bus Master 1 Command Register 00h Page 195 29h 8 RC Audio Bus Master 1 SMI Status Register 00h Page 196 2Ah-2Bh -- -- Not Used -- Page 196 2Ch-2Fh 32 R/W Audio Bus Master 1 PRD Table Address 00000000h Page 196 30h 8 R/W Audio Bus Master 2 Command Register 00h Page 196 31h 8 RC Audio Bus Master 2 SMI Status Register 00h Page 196 32h-33h -- -- Not Used -- Page 196 34h-37h 32 R/W Audio Bus Master 2 PRD Table Address 00000000h Page 196 38h 8 R/W Audio Bus Master 3 Command Register 00h Page 197 39h 8 RC Audio Bus Master 3 SMI Status Register 00h Page 197 3Ah-3Bh -- -- Not Used -- Page 197 3Ch-3Fh 32 R/W Audio Bus Master 3 PRD Table Address 00000000h Page 197

www.national.com 144 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 x 40h 8 R/W Audio Bus Master 4 Command Register 00h Page 197 41h 8 RC Audio Bus Master 4 SMI Status Register 00h Page 198 42h-43h -- -- Not Used -- Page 198 44h-47h 32 R/W Audio Bus Master 4 PRD Table Address 00000000h Page 198 48h 8 R/W Audio Bus Master 5 Command Register 00h Page 198 49h 8 RC Audio Bus Master 5 SMI Status Register 00h Page 198 4Ah-4Bh -- -- Not Used -- Page 198 4Ch-4Fh 32 R/W Audio Bus Master 5 PRD Table Address 00000000h Page 198 Table 4-8. F3BAR: XpressAUDIO Subsystem Configuration Registers Summary (Continued) F3BAR+ Memory Offset Width (Bits) Type Name Reset Value Reference (Table 4-20) Table 4-9. Function 4: PCI Header Registers for Video Controller Summary F4 Index Width (Bits) Type Name Reset Value Reference (Table 4-21) 00h-01h 16 RO Vendor Identification 1078h Page 199 02h-03h 16 RO Device Identification 0104h Page 199 04h-05h 16 R/W PCI Command 0000h Page 199 06h-07h 16 RO PCI Status 0280h Page 199 08h 8 RO Device Revision ID 00h Page 199 09h-0Bh 24 RO PCI Class Code 030000h Page 199 0Ch 8 RO PCI Cache Line Size 00h Page 199 0Dh 8 RO PCI Latency Timer 00h Page 199 0Eh 8 RO PCI Header Type 00h Page 199 0Fh 8 RO PCI BIST Register 00h Page 199 10h-13h 32 R/W Base Address Register (F4BAR): Sets base address for memory mapped video controller configuration registers (summarized in Table 4-10). 00000000h Page 199 14h-FFh -- -- Reserved Page 199 Table 4-10. F4BAR: Video Controller Configuration Registers Summary F4BAR+ Memory Offset Width (Bits) Type Register Name Reset Value Reference (Table 4-22) 00h-03h 32 R/W Video Configuration Register 00000000h Page 200 04h-07h 32 R/W Display Configuration Register 00000000h Page 200 08h-0Bh 32 R/W Video X Register xxxxxxxxh Page 201 0Ch-0Fh 32 R/W Video Y Register xxxxxxxxh Page 202 10h-13h 32 R/W Video Scale Register xxxxxxxxh Page 202 14h-17h 32 R/W Video Color Key Register xxxxxxxxh Page 202 18h-1Bh 32 R/W Video Color Mask Register xxxxxxxxh Page 202 1Ch-1Fh 32 R/W Palette Address Register xxxxxxxxh Page 202 20h-23h 32 R/W Palette Data Register xxxxxxxxh Page 202 24h-27h 32 R/W Dot Clock Configuration Register 00000000h Page 202 28h-2Bh 32 R/W CRC Signature and TFT/TV Configuration Register 00000100h Page 204

Revision 4.1 145 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-11. PCIUSB 00h-FFh Register Summary PCIUSB Index Width (Bits) Type Name Reset Value Reference (Table 4-24) 00h-01h 16 RO Vendor Identification 0E11h Page 206 02h-03h 16 RO Device Identification A0F8h Page 206 04h-05h 16 R/W Command Register 0000h Page 206 06h-07h 16 R/W Status Register 0280h Page 206 08h 8 RO Device Revision ID 00h Page 206 09h-0Bh 24 RO Class Code 0C0310h Page 207 0Ch 8 R/W Cache Line Size 00h Page 207 0Dh 8 R/W Latency Timer 00h Page 207 0Eh 8 RO Header Type 00h Page 207 0Fh 8 RO BIST Register 00h Page 207 10h-13h 32 R/W Base Address Register 00000000h Page 207 14h-3Bh -- -- Reserved -- Page 207 3Ch 8 R/W Interrupt Line Register 00h Page 207 3Dh 8 RO Interrupt Pin Register 01h Page 207 3Eh 8 RO Min. Grant Register 00h Page 207 3Fh 8 RO Max. Latency Register 00h Page 207 40h-43h 32 R/W ASIC Test Mode Enable Register 00000000h Page 207 44h 8 R/W ASIC Operational Mode Enable 00h Page 207 45h-FFh -- -- Reserved -- Page 207

www.national.com 146 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Table 4-12. ISA Legacy I/O Register Summary I/O Port Type Name Reference DMA Channel Control Registers (Table 4-25) 000h R/W DMA Channel 0 Address Register Page 208 001h R/W DMA Channel 0 Transfer Count Register Page 208 002h R/W DMA Channel 1 Address Register Page 208 003h R/W DMA Channel 1 Transfer Count Register Page 208 004h R/W DMA Channel 2 Address Register Page 208 005h R/W DMA Channel 2 Transfer Count Register Page 208 006h R/W DMA Channel 3 Address Register Page 208 007h R/W DMA Channel 3 Transfer Count Register Page 208 008h Read DMA Status Register, Channels 3:0 Page 208 Write DMA Command Register, Channels 3:0 Page 208 009h WO Software DMA Request Register, Channels 3:0 Page 209 00Ah R/W DMA Channel Mask Register, Channels 3:0 Page 209 00Bh WO DMA Channel Mode Register, Channels 3:0 Page 209 00Ch WO DMA Clear Byte Pointer Command, Channels 3:0 Page 209 00Dh WO DMA Master Clear Command, Channels 3:0 Page 209 00Eh WO DMA Clear Mask Register Command, Channels 3:0 Page 209 00Fh WO DMA Write Mask Register Command, Channels 3:0 Page 209 0C0h R/W DMA Channel 4 Address Register (Not used) Page 209 0C2h R/W DMA Channel 4 Transfer Count Register (Not Used) Page 209 0C4h R/W DMA Channel 5 Address Register Page 209 0C6h R/W DMA Channel 5 Transfer Count Register Page 209 0C8h R/W DMA Channel 6 Address Register Page 209 0CAh R/W DMA Channel 6 Transfer Count Register Page 209 0CCh R/W DMA Channel 7 Address Register Page 209 0CEh R/W DMA Channel 7 Transfer Count Register Page 209 0D0h Read DMA Status Register, Channels 7:4 Page 210 Write DMA Command Register, Channels 7:4 Page 210 0D2h WO Software DMA Request Register, Channels 7:4 Page 210 0D4h R/W DMA Channel Mask Register, Channels 7:0 Page 210 0D6h WO DMA Channel Mode Register, Channels 7:4 Page 210 0D8h WO DMA Clear Byte Pointer Command, Channels 7:4 Page 210 0DAh WO DMA Master Clear Command, Channels 7:4 Page 210 0DCh WO DMA Clear Mask Register Command, Channels 7:4 Page 210 0DEh WO DMA Write Mask Register Command, Channels 7:4 Page 210 DMA Page Registers (Table 4-26) 081h R/W DMA Channel 2 Low Page Register Page 211 082h R/W DMA Channel 3 Low Page Register Page 211 083h R/W DMA Channel 1 Low Page Register Page 211 087h R/W DMA Channel 0 Low Page Register Page 211 089h R/W DMA Channel 6 Low Page Register Page 211 08Ah R/W DMA Channel 7 Low Page Register Page 211 08Bh R/W DMA Channel 5 Low Page Register Page 211 08Fh R/W ISA Refresh Low Page Register Page 211 481h R/W DMA Channel 2 High Page Register Page 211 482h R/W DMA Channel 3 High Page Register Page 211 483h R/W DMA Channel 1 High Page Register Page 211 487h R/W DMA Channel 0 High Page Register Page 211

Revision 4.1 147 www.national.com Register Descriptions(Continued) Geode™ CS5530 489h R/W DMA Channel 6 High Page Register Page 211 48Ah R/W DMA Channel 7 High Page Register Page 211 48Bh R/W DMA Channel 5 High Page Register Page 211 Programmable Interval Timer Registers (Table 4-27) 040h Write PIT Timer 0 Counter Page 212 Read PIT Timer 0 Status Page 212 041h Write PIT Timer 1 Counter (Refresh) Page 212 Read PIT Timer 1 Status (Refresh) Page 212 042h Write PIT Timer 2 Counter (Speaker) Page 212 Read PIT Timer 2 Status (Speaker) Page 212 043h Write PIT Mode Control Word Register Page 212 043h R/W PIT Read-Back Command Read Status Command Counter Latch Command Programmable Interrupt Controller Registers (Table 4-28) 020h / 0A0h WO Master / Slave PCI IWC1 Page 213 021h / 0A1h WO Master / Slave PIC ICW2 Page 213 021h / 0A1h WO Master / Slave PIC ICW3 Page 213 021h / 0A1h WO Master / Slave PIC ICW4 Page 213 021h / 0A1h R/W Master / Slave PIC OCW1 Page 213 020h / 0A0h WO Master / Slave PIC OCW2 Page 213 020h / 0A0h WO Master / Slave PIC OCW3 Page 214 020h / 0A0h RO Master / Slave PIC Interrupt Request and Service Registers for OCW3 Commands Page 214 Keyboard Controller Registers (Table 4-29) 060h R/W External Keyboard Controller Data Register Page 215 061h R/W Port B Control Register Page 215 062h R/W External Keyboard Controller Mailbox Register Page 215 064h R/W External Keyboard Controller Command Register Page 215 066h R/W External Keyboard Controller Mailbox Register Page 215 092h R/W Port A Control Register Page 215 Real Time Clock Registers (Table 4-30) 070h WO RTC Address Register Page 215 071h R/W RTC Data Register Page 215 Miscellaneous Registers (Table 4-31) 170h-177h/ 376h-377h R/W Secondary IDE Registers Page 216 1F0h-1F7h/ 3F6h-3F7h R/W Primary IDE Registers Page 216 4D0h R/W Interrupt Edge/Level Select Register 1 Page 216 4D1h R/W Interrupt Edge/Level Select Register 2 Page 216 121Ch-121Fh RO ACPI Timer Count Register Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch in Silicon Revision 1.3 and above. Otherwise use F1BAR+Offset 1Ch. Page 216 Table 4-12. ISA Legacy I/O Register Summary (Continued) I/O Port Type Name Reference

www.national.com 148 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Table 4-13. V-ACPI I/O Register Space Summary ACPI_ BASE Type Align Length Name Reset Value Reference (Table 4-32) 00h-03h R/W 4 4 P_CNT: Processor Control Register 00000000h Page 217 04h RO 1 1 P_LVL2: Enter C2 Power State Register 00h Page 217 05h -- 1 1 Reserved 00h Page 217 06h R/W 1 1 SMI_CMD: OS/BIOS Requests Register (ACPI Enable/Disable Port) 00h Page 217 07h -- 1 1 Reserved 00h Page 218 08h-09h R/W 2 2 PM1A_STS: PM1A Status Register 0000h Page 218 0Ah-0Bh R/W 2 2 PM1A_EN: PM1A Enable Register 0000h Page 218 0Ch-0Dh R/W 4 2 PM1A_CNT: PM1A Control Register 0000h Page 218 0Eh-0Fh R/W 2 2 SETUP_IDX: Setup Index Register (V-ACPI internal index register) 0000h Page 219 10h-11h R/W 2 2 GPE0_STS: General Purpose Event 0 Status Register 0000h Page 219 12h-13h R/W 2 2 GPE0_EN: General Purpose Event 0 Enable Register 0000h Page 220 14h-17h R/W 4 4 SETUP_DATA: Setup Data Register (V-ACPI internal data register) 00000000h Page 220 18h-1Fh -- 8 Reserved: For Future V-ACPI Implementations -- Page 220

Revision 4.1 149 www.national.com Register Descriptions(Continued) Geode™ CS5530

4.3 CHIPSET REGISTER SPACE

The Chipset Register Space of the CS5530 is comprised of five separate functions (Function 0 through 4, F0-F4), each with its own register space and PCI header regis- ters. F1-F4 have memory or I/O mapped registers from a Base Address Register (BAR). The PCI header registers in all functions are very similar. F0: Bridge Configuration Register Space F1: SMI Status and ACPI Timer Register Space F2: IDE Controller Register Space F3: XpressAUDIO Subsystem Register Space F4: Video Controller Register Space

4.3.1 Bridge Configuration Registers - Function 0

The register space designated as Function 0 (F0) con- tains registers used to configure features (e.g., power management) and functionality unique to the CS5530. All registers in Function 0 are directly accessed (i.e., there are no memory or I/O mapped registers in F0). T able 4-14 gives the bit formats for these registers. Note: The registers at F0 Index 50h-FFh can also be accessed at F1BAR+Memory Offset 50h-FFh. H o w e v e r ,t h ep r e f e r r e dm e t h o di st op r o g r a m these registers through the F0 register space. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers Bit Description Index 00h-01h Vendor Identification Register (RO) Reset Value = 1078h 15:0 Vendor Identification Register (Read Only) Index 02h-03h Device Identification Register (RO) Reset Value = 0100h 15:0 Device Identification Register (Read Only) Index 04h-05h PCI Command Register (R/W) Reset Value = 0000h 15:10 Reserved: Set to 0. 9 Fast Back-to-Back Enable (Read Only):This function is not supported when the CS5530 is a master. It is always dis- abled (always reads 0). 8 SERR#: Allow SERR# assertion on detection of special errors: 0 = Disable(Default);1=E n a b l e . 7 Wait Cycle Control (Read Only):This function is not supported in the CS5530. It is always disabled (always reads 0). 6 Parity Error:Allow the CS5530 to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when a parity error is detected: 0 = Disable(Default); 1 = Enable. 5 VGA Palette Snoop Enable (Read Only):This function is not supported in the CS5530. It is always disabled (always reads 0). 4 Memory Write and Invalidate:Allow the CS5530 to do memory write and invalidate cycles, if the PCI Cache Line Regis- ter (F0 Index 0Ch) is set to 16 bytes (04h). 0 = Disable(Default); 1 = Enable. 3 Special Cycles:Allow the CS5530 to respond to special cycles: 0 = Disable; 1 = Enable(Default). This bit must be enabled to allow the CPU Warm Reset internal signal to be triggered from a CPU Shutdown cycle. 2 Bus Master:Allow the CS5530 bus mastering capabilities: 0 = Disable; 1 = Enable(Default). This bit must be set to 1. 0 = Disable; 1 = Enable(Default). 0 I/O Space:Allow the CS5530 to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable(Default). Index 06h-07h PCI Status Register (R/W) Reset Value = 0280h 15 Detected Parity Error:This bit is set whenever a parity error is detected. Write 1 to clear. 14 Signaled System Error:This bit is set whenever the CS5530 asserts SERR# active. Write 1 to clear. 13 Received Master Abort:This bit is set whenever a master abort cycle occurs while the CS5530 is the master. A master abort will occur when a PCI cycle is not claimed, except for special cycles. Write 1 to clear. 12 Received Target Abort:This bit is set whenever a target abort is received while the CS5530 is the master for the PCI cycle. Write 1 to clear. 11 Signaled Target Abort:This bit is set whenever the CS5530 signals a target abort. This occurs when an address parity error occurs for an address that hits in the active address decode space of the CS5530. Write 1 to clear.

www.national.com 150 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 10:9 DEVSEL# Timing: These bits are always 01, as the CS5530 always responds to cycles for which it is an active target with medium DEVSEL# timing: 00 = Fast; 01 = Medium; 10 = Slow; 11 = Reserved

8 Data Parity Detected:This bit is set when:

1) The CS5530 asserted PERR# or observed PERR# asserted. 2) The CS5530 is the master for the cycle in which a parity error occurred and the Parity Error bit is set (F0 Index 04h[6] =1 ) . Write 1 to clear. 7 Fast Back-to-Back Capable:As a target, the CS5530 is capable of accepting fast back-to-back transactions: 0 = Disable; 1 = Enable. This bit is always set to 1. 6:0 Reserved: Set to 0. Index 08h Device Revision ID Register (RO) Reset Value = xxh 7:0 Device Revision ID (Read Only):00h = Silicon Rev 1.2 or below; 13h = Silicon Rev 1.3. Index 09h-0Bh PCI Class Code Register (RO) Reset Value = 060100h Index 0Ch PCI Cache Line Size Register (R/W) Reset Value = 00h 7:0 PCI Cache Line Size Register:This register sets the size of the PCI cache line, in increments of four bytes. For memory write and invalidate cycles, the PCI cache line size must be set to 16 bytes (04h), and the Memory Write and Invalidate bit must be set (F0 Index 04h[4] = 1). Index 0Dh PCI Latency Timer Register (R/W) Reset Value = 00h 7:4 Reserved: Set to 0. 3:0 PCI Latency Timer Value:The PCI Latency Timer Register prevents system lockup when a slave does not respond to a cycle that the CS5530 masters. If the value is set to 00h (default), the timer is disabled. If the timer is written with any other value, bits [3:0] become the four most significant bytes in a timer that counts PCI clocks for slave response. The timer is reset on each valid data transfer. If the counter expires before the next assertion of TRDY# is received, the CS5530 stops the transaction with a master abort and asserts SERR#, if enabled to do so (F0 Index 04h[8] = 1). Index 0Eh PCI Header Type (RO) Reset Value = 00h 7:0 PCI Header Type Register (Read Only):This register defines the format of this header. This header is of type format 0. Additionally, bit 7 defines whether this PCI device is a multifunction device (bit 7 = 1) or not (bit 7 = 0). Index 0Fh PCI BIST Register (RO) Reset Value = 00h 7 BIST Capable (Read Only):Is device capable of running a built-in self-test (BIST)? 0 = No; 1 = Y es, 6 Start BIST:Setting this bit to a one starts up a BIST on the device. The device resets this bit when the BIST has been completed. (Not supported.) 5:4 Reserved (Read Only) 3:0 BIST Completion Code (Read Only):Upon completion of the BIST, the completion code is stored in these bits. A com- pletion code of zero indicates the BIST has successfully been completed. All other values indicate some type of BIST fail- ure. Index 10h-3Fh Reserved Index 40h PCI Function Control Register 1 (R/W) Reset Value = 89h 0 = Disable; 1 = Enable. 6 Single Write Mode:The CS5530 accepts only single cycle write transfers as a slave on the PCI bus and performs a tar- get disconnect with the first data transferred: 0 = Disable (accepts burst write cycles); 1 = Enable. 5 Single Read Mode:The CS5530 accepts only single cycle read transfers as a slave on the PCI bus and performs a tar- get disconnect with the first data transferred. 0 = Disable (accepts burst read cycles); 1 = Enable.

4 Retry PCI Cycles:Retry inbound PCI cycles if data is buffered and waiting to go outbound on PCI:

0 = No Retry; 1 = Retry. 3 Write Buffer:PCI slave write buffer: 0 = Disable; 1 = Enable. 2:1 Reserved: Set to 0. 0 BS8/16:This bit can not be written. Always = 1. Note: Bits 6 and 5 emulate the behavior of first generation SIO devices developed for PCI. They should normally remain cleared. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 151 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 41h PCI Function Control Register 2 (R/W) Reset Value = 10h 7 Burst to Beat:Bursts are converted to single beats for X-Bus to PCI bus reads: 0 = Disable; 1 = Enable. 6 IDE Configuration Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the F2 Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. 5 PERR# Signals SERR#: Assert SERR# any time that PERR# is asserted or detected active by the CS5530 (allows PERR# assertion to be cascaded to NMI (SMI) generation in the system): 0 = Disable; 1 = Enable. 4 Write Buffer Enable:Allow 16-byte buffering for X-Bus to PCI bus writes: 0 = Disable; 1 = Enable. 3 Power Management Configuration Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the F1 Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. 2:1 Subtractive Decode:These bits determine the point at which the CS5530 accepts cycles that are not claimed by another device. The CS5530 defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively. 00 = Default sample (4th clock from FRAME# active) 01 = Slow sample (3rd clock from FRAME# active) 1x = No subtractive decode 0 Legacy Configuration SMI:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the ISA Legacy I/O Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. Index 42h PCI Function Control Register 3 (R/W) Reset Value = 0Fh

7 USB SMI I/O Configuration:Route USB-generated SMI to SMI# pin: 0 = Disable;

1 = Enable, USB-generated SMI pulls SMI# pin active (low). 6 USB SMI Power Mgmnt Configuration:Route USB-generated SMI to Top Level SMI Status Register, F1BAR+Memory Offset 00h/02h[14]: 0 = Disable; 1 = Enable. 5 Delayed Transactions:Allow delayed transactions on the PCI bus: 0 = Disable; 1 = Enable. Also see F0 Index 43h[1]. 4 DMA Priority:Allow USB DMA to have priority over other DMA requests: 0 = Disable; 1 = Enable. 3 No X-Bus ARB, Buffer Enable:When the CS5530 is a PCI target, allow buffer PCI transactions without X-Bus arbitration: 0 = Disable; 1 = Enable. 2 HOLD_REQ# (Pin H26): HOLD_REQ# signal (pin H26): 0 = Disable; 1 = Enable. Note: Although the HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., enabled, set to 1) for non-preemptive arbitration to operate correctly. 1 Video Configuration Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the F4 Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. 0 Audio Configuration SMI:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the F3 Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 152 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 43h USB Shadow Register (R/W) Reset Value = 03h 7 Reserved: Set to 0. 6 Enable SA20:Pin AD22 configuration: 0 = GPIO4; 1 = SA20. If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20.

5 Legacy Cycles Assert HOLD_REQ#: Allow legacy cycles to cause HOLD_REQ# to be asserted:

0 = Disable; 1 = Enable. Note: The HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., disabled, set to 0).

4 Read Cycles Assert HOLD_REQ#: Allow read cycles to cause HOLD_REQ# to be asserted:

0 = Disable; 1 = Enable. Note: The HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., disabled, set to 0). 3 Any Cycle Asserts HOLD_REQ#: Allow any cycle to cause HOLD_REQ# to be asserted: 0 = Disable; 1 = Enable. Note: The HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., disabled, set to 0). 2 Enable SA[23:20]:Pins AF23, AE23, AC21, and AD22 configuration: 0 = GPIO[7:4]; 1 = SA[23:20]. If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20. 1 PCI Retry Cycles:When the CS5530 is a PCI target and the PCI buffer is not empty, allow PCI bus to retry cycles: 0 = Disable; 1 = Enable. This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid. 0 USB: USB core: 0 = Disable; 1 = Enable. Index 44h Reset Control Register (R/W) Reset Value = xx000000b

7 ISA Mode: This bit is set to read back the strap value of the INTR pin (pin P26) during POR:

0 = ISA Limited; 1 = ISA Master. This bit can be written after POR# deasserts to change the ISA mode selected. However, writing to this bit is not recom- mended due to the actual strapping done on the board.

6 IDSEL Mode: This bit is set to read back the strap value of the HOLD_REQ# pin (pin H26) during POR:

0 = AD28 is IDSEL for Chipset Register Space and AD29 is IDSEL for USB Register Space; 1 = AD26 is IDSEL for Chipset Register Space and AD27 is IDSEL for USB Register Space. This bit can be written after POR# deasserts to change the IDSEL settings. However, writing to this bit is not recom- mended due to the actual strapping done on the board. 5:4 Clock 32K Control:Controls the source of the CLK_32K pin (AE3): 00 = CLK_32K is internally derived from CLK_14MHZ (pin P24) and is not output on pin AE3 (Default) 01 = CLK_32K is internally derived from CLK_14MHZ (pin P24) and is output on pin AE3 10 = CLK_32K is an input 11 = Invalid 3 IDE Controller Reset:Reset the IDE Controller: 0 = Disable; 1 = Enable. Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled. 2 IDE Reset:Reset IDE bus: 0 = Disable; 1 = Enable. Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled. 1 PCI Reset:Reset PCI bus: 0 = Disable; 1 = Enable. When set, the CS5530 PCI_RST# output signal (pin C14) is asserted and all devices on the PCI bus including PCIUSB are reset. No other function within the CS5530 is affected by this bit. Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

0 X-Bus Warm Start:Reading and writing this bit has two different meanings/functions:

Reading this bit: Has a warm start occurred since power-up? 0 = Y es; 1 = No Writing this bit: 0 = NOP; 1 = Execute system wide reset (used only for clock configuration at power-up) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 153 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 45h-4Fh Reserved Index 50h PIT Control/ISA CLK Divider (R/W) Reset Value = 7Bh 7 PIT Software Reset:0 = Disable; 1 = Enable. 6 PIT Counter 1:0 = Forces Counter 1 output (OUT1) to zero; 1 = Allows Counter 1 output (OUT1) to pass to I/O Port 061h[4]. 5 PIT Counter 1 Enable:0 = Sets GATE1 input low; 1 = Sets GATE1 input high. 4 PIT Counter 0:0 = Forces Counter 0 output (OUT0) to zero; 1 = Allows Counter 0 output (OUT0) to pass to IRQ0. 3 PIT Counter 0 Enable:0 = Sets GATE0 input low; 1 = Sets GATE0 input high. 2:0 ISA Clock Divisor:Determines the divisor of the PCI clock used to make the ISA clock, which is typically programmed for approximately 8 MHz: 000 = Divide by one 100 = Divide by five 001 = Divide by two 101 = Divide by six 010 = Divide by three 110 = Divide by seven 011 = Divide by four 111 = Divide by eight If PCI clock = 25 MHz, use setting of 010 (divide by 3). If PCI clock = 30 or 33 MHz, use a setting of 011 (divide by 4). Index 51h ISA I/O Recovery Control Register (R/W) Reset Value = 40h 7:4 8-Bit I/O Recovery:These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This count is in addition to a preset one-clock delay built into the controller. 0000 = 1 PCI clock 0100 = 5 PCI clocks 1000 = 9 PCI clocks 1100 = 13 PCI clocks 0001 = 2 PCI clocks 0101 = 6 PCI clocks 1001 = 10 PCI clocks 1101 = 14 PCI clocks 0010 = 3 PCI clocks 0110 = 7 PCI clocks 1010 = 11 PCI clocks 1110 = 15 PCI clocks 0011 = 4 PCI clocks 0111 = 8 PCI clocks 1011 = 12 PCI clocks 1111 = 16 PCI clocks 3:0 16-Bit I/O Recovery:These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This count is in addition to a preset one-clock delay built into the controller. 0000 = 1 PCI clock 0100 = 5 PCI clocks 1000 = 9 PCI clocks 1100 = 13 PCI clocks 0001 = 2 PCI clocks 0101 = 6 PCI clocks 1001 = 10 PCI clocks 1101 = 14 PCI clocks 0010 = 3 PCI clocks 0110 = 7 PCI clocks 1010 = 11 PCI clocks 1110 = 15 PCI clocks 0011 = 4 PCI clocks 0111 = 8 PCI clocks 1011 = 12 PCI clocks 1111 = 16 PCI clocks Index 52h ROM/AT Logic Control Register (R/W) Reset Value = F8h 7 Snoop Fast Keyboard Gate A20 and Fast Reset:Enables the snoop logic associated with keyboard commands for A20 Mask and Reset: 0 = Disable; 1 = Enable (snooping). If disabled, the keyboard controller handles the commands. 6 Game Port GPORT_CS# on Writes: Allow GPORT_CS# to be asserted for writes to the game port (I/O Port 200h and 201h): 0 = Disable; 1 = Enable. 5 Game Port GPORT_CS# on Reads: Allow GPORT_CS# to be asserted for reads to the game port (I/O Port 200h and 201h): 0 = Disable; 1 = Enable. 4 Enable A20M# Deassertion on Warm Reset:Force A20M# high during a Warm Reset (guarantees that A20M# is deas- serted regardless of the state of A20): 0 = Disable; 1 = Enable. 3 Enable I/O Port 092h Decode (Port A):I/O Port 092h decode and the logical functions: 0 = Disable; 1 = Enable. 0 = FFFC0000h-FFFFFFFFh (256 KB,Default); 1 = FF000000h-FFFFFFFFh (16 MB) Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]). allowing Flash programming: 0 = Disable; 1 = Enable. 0 = 000F0000h-000FFFFFh (64 KB,Default); 1 = 000E0000h-000FFFFFh (128 KB). Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]). Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 154 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 53h Alternate CPU Support Register (R/W) Reset Value = 00h 7 Reserved: Set to 0.

6 Game Port Write Blocks ISA:Block ISA cycle on game port (I/O Port 200h and 201h) write:

0 = Disable; 1 = Enable. 5 Bidirectional SMI Enable:0 = Disable; 1 = Enable. This bit must be set to 0. 4 Game Port Read Block ISA:Block ISA cycle on game port (I/O Port 200h and 201h) read: 0 = Disable; 1 = Enable.

3 Game Port Write SMI:Allow SMI generation on writes to game port (I/O Port 200h and 201h):

0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 84h/F4h[4]. For “Game Port Read SMI”, see F0 Index 83h[4].

2 RTC Enable/RTC Pin Configuration:0 = SMEMW# (Pin AF3) and SMEMR# (Pin AD4), RTC decode disabled;

1 = RTCCS# (Pin AF3) and RTCALE (Pin AD4), RTC decode enabled. Note: The RTC Index Shadow Register (F0 Index BBh) is independent of the setting of this bit. 1 Reserved: Set to 1. 0 Generate SMI on A20M# toggle:0 = Disable; 1 = Enable. This bit must be set to 1. SMI status is reported in F1BAR+Memory Offset 00h/02h[7] (only). Index 54h-59h Reserved Index 5Ah Decode Control Register 1 (R/W) Reset Value = 03h 7 Secondary Floppy Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 372h-375h and 377h: 0 = Subtractive; 1 = Positive. 6 Primary Floppy Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 3F2h-3F5h and 3F7h: 0 = Subtractive; 1 = Positive.

5 COM4 Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 2E8h-2EFh:

0 = Subtractive; 1 = Positive.

4 COM3 Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 3E8h-3EFh:

0 = Subtractive; 1 = Positive.

3 COM2 Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 2F8h-2FFh:

0 = Subtractive; 1 = Positive.

2 COM1 Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 3F8h-3FFh:

0 = Subtractive; 1 = Positive. 1 Keyboard Controller Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 060h and 064h (and 062h/066h if enabled): 0 = Subtractive; 1 = Positive.

0 Real Time Clock Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port

070h and 071h: 0 = Subtractive; 1 = Positive. Note: Positive decoding by the CS5530 speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530. It is assumed that if positive decode is enabled, the port exists on the ISA bus. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 155 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 5Bh Decode Control Register 2 (R/W) Reset Value = 20h 7 Keyboard I/O Port 062h/066h Decode:This alternate port to the keyboard controller is provided in support of the 8051SL notebook keyboard controller mailbox:0 = Disable; 1 = Enable. 6 Reserved: Set to 0. 5 BIOS ROM Positive Decode:Selects PCI positive or subtractive decoding for accesses to the configured ROM space: 0 = Subtractive; 1 = Positive. ROM configuration is at F0 Index 52h[2:0]. 4 Secondary IDE Controller Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 170h- 177h and 376h-377h (excluding writes to 377h): 0 = Subtractive; 1 = Positive. Note: Subtractive Decode mode disables this IDE controller entirely and routes any register references to the ISA Bus. 3 Primary IDE Controller Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 1F0h- 1F7h and 3F6h-3F7h (excluding writes to 3F7h): 0 = Subtractive; 1 = Positive. Note: Subtractive Decode mode disables this IDE controller entirely and routes any register references to the ISA Bus. 2 LPT3 Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 3BCh-3BEh and 7BCh- 7BEh: 0 = Subtractive; 1 = Positive. 1 LPT2 Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 278h-27Fh and 678h-67Ah: 0 = Subtractive; 1 = Positive. 0 LPT1 Positive Decode:Selects PCI positive or subtractive decoding for accesses to I/O Port 378h-37Fh and 778h-77Ah: 0 = Subtractive; 1 = Positive. Note: Positive decoding by the CS5530 speeds up the I/O cycle time. The keyboard, LPT3, LPT2, and LPT1 I/O Ports do not exist in the CS5530. It is assumed that if positive decode is enabled, the port exists on the ISA bus. Index 5Ch PCI Interrupt Steering Register 1 (R/W) Reset Value = 00h 7:4 INTB# Target Interrupt:Selects target interrupt for INTB#: 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 3:0 INTA# Target Interrupt:Selects target interrupt for INTA#: 0000 = Disable 0100 = IRQ4 1000 = RSVD ‘ 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. Index 5Dh PCI Interrupt Steering Register 2 (R/W) Reset Value = 00h 7:4 INTD# Target Interrupt:Selects target interrupt for INTD#: 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 3:0 INTC# Target Interrupt:Selects target interrupt for INTC#: 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 156 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 5Eh-6Fh Reserved Index 70h-71h General Purpose Chip Select Base Address Register (R/W) Reset Value = 0000h 15:0 General Purpose Chip Select I/O Base Address:This 16-bit value represents the I/O base address used to enable the assertion of the GPCS# signal. This register, together with General Purpose Chip Select Control Register (F0 Index 72h) is used to configure the operation of the GPCS# pin. Index 72h General Purpose Chip Select Control Register (R/W) Reset Value = 00h 7 General Purpose Chip Select:GPCS# (pin AF26): 0 = Disable; 1 = Enable. 6 Writes Result in Chip Select:Writes to configured I/O address (base address configured in F0 Index 70h and range configured in bits [4:0]) causes GPCS# signal to be asserted: 0 = Disable; 1 = Enable. 5 Reads Result in Chip Select:Reads from configured I/O address (base address configured in F0 Index 70h and range configured in bits [4:0]) causes GPCS# signal to be asserted: 0 = Disable; 1 = Enable. 4:0 General Purpose Chip Select I/O Address Range:This 5-bit field selects the range of GPCS# signal: 00000 = 1byte 01111 = 16 bytes 00001 = 2 bytes 11111 = 32 bytes 00011 = 4 bytes All other combinations are reserved. 00111 = 8 bytes Note: This register, together with General Purpose Chip Select Base Address Register (F0 Index 70h) is used to configure the oper- ation of the GPCS# pin. Index 73h-7Fh Reserved Index 80h Power Management Enable Register 1 (R/W) Reset Value = 00h 7:6 Reserved: Set to 0. 5 Codec SDATA_IN SMI: Allow AC97 codec to generate an SMI due to codec producing a positive edge on SDATA_IN: 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[2]. 4 Video Speedup:Any video activity, as decoded from the serial connection (PSERIAL register, bit 0) from the GXLV processor disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when the system is power managed using CPU Suspend modulation. 0 = Disable; 1 = Enable. The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an external VGA access (3Bx, 3, 3Dx and A000h-B7FFh) on the PCI bus is also supported. This configuration is non-stan- dard, but it does allow the power management routines to support an external VGA chip. 3 IRQ Speedup: Any unmasked IRQ (per I/O Port 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA# hand- shake) for a configurable duration when the system is power managed using CPU Suspend modulation: 0 = Disable; 1 = Enable. The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch). 2 Traps:Globally enable all power management device I/O traps: 0 = Disable; 1 = Enable. This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h. 1 Idle Timers:Globally enable all power management device idle timers: 0 = Disable; 1 = Enable. Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts. This bit has no effect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h). 0 Power Management: Global power management: 0 = Disable; 1 = Enabled. This bit must be set (1) immediately after POST for power management resources to function. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 157 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 81h Power Management Enable Register 2 (R/W) Reset Value = 00h 7 Video Access Idle Timer Enable:Turn on Video Idle Timer Count Register (F0 Index A6h) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the video address range (sets bit 0 of the GXLV processor’s PSERIAL Register) the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[7]. 6 User Defined Device 3 (UDEF3) Idle Timer Enable:Turn on UDEF3 Idle Timer Count Register (F0 Index A4h) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[6]. 5 User Defined Device 2 (UDEF2) Idle Timer Enable:Turn on UDEF2 Idle Timer Count Register (F0 Index A2h) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[5]. 4 User Defined Device 1 (UDEF1) Idle Timer Enable:Turn on UDEF1 Idle Timer Count Register (F0 Index A0h) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[4]. 3 Keyboard/Mouse Idle Timer Enable:Turn on Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3]. 2 Parallel/Serial Idle Timer Enable:Turn on Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2]. 1 Floppy Disk Idle Timer Enable:Turn on Floppy Disk Idle Timer Count Register (F0 Index 9Ah) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h, Secondary floppy disk: I/O Port 372h-375h, 377h Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[1]. 0 Primary Hard Disk Idle Timer Enable:Turn on Primary Hard Disk Idle Timer Count Register (F0 Index 98h) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges selected in F0 Index 93h[5], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0]. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 158 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 82h Power Management Enable Register 3 (R/W) Reset Value = 00h 7 Video Access Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GXLV processor’s PSERIAL Register) an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[7]. 6 User Defined Device 3 (UDEF3) Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[4]. 5 User Defined Device 2 (UDEF2) Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[3]. 4 User Defined Device 1 (UDEF1) Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF1 address programming is at F0 Index C0h (base address register), and CCh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[2]. 3 Keyboard/Mouse Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[3]. 2 Parallel/Serial Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[2]. 1 Floppy Disk Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h, Secondary floppy disk: I/O Port 372h-375h, 377h Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[1]. 0 Primary Hard Disk Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[5], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[0]. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 159 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 83h Power Management Enable Register 4 (R/W) Reset Value = 00h 7 Secondary Hard Disk Idle Timer Enable:Turn on Secondary Hard Disk Idle Timer Count Register (F0 Index ACh) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges selected in F0 Index 93h[4], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4]. 6 Secondary Hard Disk Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[4], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[5]. 5 ACPI Timer SMI:Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch in Silicon Revision 1.3 and above): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0].

4 Game Port Read SMI:Allow SMI generation on reads to game port (I/O Port 200h and 201h):

0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 84h/8Fh[4]. For “Game Port Write SMI” see F0 Index 53h[3]. 3 VGA Timer Enable:Turn on VGA Timer and generate an SMI when the timer reaches 0: 0 = Disable; 1 = Enable If an access occurs in the programmed address range the timer is reloaded with the programmed count. VGA Timer programming is at F0 Index 8Eh and F0 Index 8Bh[6] SMI Status reporting is at F1BAR+Memory Offset 00h/02h[6] (only). 2 Video Retrace Interrupt SMI:Allow SMI generation whenever video retrace occurs: 0 = Disable; 1 = Enable. This information is decoded from the serial connection (PSERIAL register, bit 7) from the GXLV processor. This function is normally not used for power management but for softVGA routines. SMI status reporting is at F1BAR+Memory Offset 00h/02h[5] (only). 1 General Purpose Timer 2 (GP Timer 2) Enable:Turn on GP Timer 2 and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. This idle timer is reloaded from the assertion of GPIO7 (if programmed to do so). GP Timer 2 programming is at F0 Index 8Ah and 8Bh[5,3,2]. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[1]. 0 General Purpose Timer 1 (GP Timer 1) Enable:Turn on GP Timer 1 and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. This idle timer’s load is multi-sourced and is reloaded any time an enabled event (F0 Index 89h[6:0]) occurs. GP Timer 1 programming is at F0 Index 88h and 8Bh[4]. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[0] Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 160 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 84h Second Level Power Management Status Mirror Register 1 (RO) Reset Value = 40h 7:5 Reserved 4 Game Port SMI Status (Read Only):SMI was caused by R/W access to game port (I/O Port 200h and 201h)? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. Game Port Read SMI generation enabling is at F0 Index 83h[4]. Game Port Write SMI generation enabling is at F0 Index 53h[3]. 3 GPIO7 SMI Status (Read Only):SMI was caused by transition on (properly-configured) GPIO7 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[3]. 2 GPIO5 SMI Status (Read Only):SMI was caused by transition on (properly-configured) GPIO5 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[2]. 1 GPIO4 SMI Status (Read Only):SMI was caused by transition on (properly-configured) GPIO4 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[1]. 0 GPIO3 SMI Status (Read Only):SMI was caused by transition on (properly-configured) GPIO3 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[0]. Notes: Properly-configured means that the GPIO pin must be enabled: as a GPIO (if multiplexed pin), as an input, and to cause an SMI. This register provides status on various power management SMI events to the SMI handler. It is called a Mirror register since an identical register exists at F0 Index F4h. Reading this register does not clear the status, while reading its coun- terpart at F0 Index F4h does clear the status. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 161 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 85h Second Level Power Management Status Mirror Register 2 (RO) Reset Value = 00h 7 Video Idle Timer SMI Status (Read Only):SMI was caused by expiration of the Video Idle Timer Count Register (F0 Index A6h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[7]. 6 User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read Only):SMI was caused by expiration of the UDEF3 Idle Timer Count Register (F0 Index A4h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[6]. 5 User Defined Device 2 (UDEF2) Idle Timer SMI Status (Read Only):SMI was caused by expiration of the UDEF2 Idle Timer Count Register (F0 Index A2h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[5]. 4 User Defined Device 1 (UDEF1) Idle Timer SMI Status (Read Only):SMI was caused by expiration of the UDEF1 Idle Timer Count Register (F0 Index A0h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[4]. 3 Keyboard/Mouse Idle Timer SMI Status (Read Only):SMI was caused by expiration of the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[3]. 2 Parallel/Serial Idle Timer SMI Status (Read Only):SMI was caused by expiration of the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[2]. 1 Floppy Disk Idle Timer SMI Status (Read Only):SMI was caused by expiration of the Floppy Disk Idle Timer Count Register (F0 Index 9Ah)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[1]. 0 Primary Hard Disk Idle Timer SMI Status (Read Only):SMI was caused by expiration of the Primary Hard Disk Idle Timer Count Register (F0 Index 98h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[0]. Note: This register provides status on the Device Idle Timers to the SMI handler. A bit set here indicates that the device was idle for the duration configured in the Idle Timer Count register for that device, causing an SMI. It is called a Mirror register since an identical register exists at F0 Index F5h. Reading this register does not clear the status, while reading its counterpart at F0 Index F5h does clear the status. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 162 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 86h Second Level Power Management Status Mirror Register 3 (RO) Reset Value = 00h 7 Video Access Trap SMI Status (Read Only):SMI was caused by a trapped I/O access to the Video I/O Trap? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[7].

5 Secondary Hard Disk Access Trap SMI Status (Read Only):SMI was caused by a trapped I/O access to the

secondary hard disk? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[6]. 4 Secondary Hard Disk Idle Timer SMI Status (Read Only):SMI was caused by expiration of Hard Disk Idle Timer Count Register (F0 Index ACh)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[7]. 3 Keyboard/Mouse Access Trap SMI Status (Read Only):SMI was caused by a trapped I/O access to the keyboard or mouse? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[3]. 2 Parallel/Serial Access Trap SMI Status (Read Only):SMI was caused by a trapped I/O access to either the serial or parallel ports? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[2]. 1 Floppy Disk Access Trap SMI Status (Read Only):SMI was caused by a trapped I/O access to the floppy disk? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[1]. 0 Primary Hard Disk Access Trap SMI Status (Read Only):SMI was caused by a trapped I/O access to the primary hard disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[0]. Note: This register provides status on the Device Traps to the SMI handler. A bit set here indicates that an access occurred to the device while the trap was enabled, causing an SMI. It is called a Mirror register since an identical register exists at F0 Index F6h of this register. Reading this register does not clear the status, while reading its counterpart at F0 Index F6h does clear the status. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 163 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 87h Second Level Power Management Status Mirror Register 4 (RO) Reset Value = 00h 7 GPIO2 SMI Status (Read Only):SMI was caused by transition on (properly-configured) GPIO2 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[2]. 6 GPIO1 SMI Status (Read Only):SMI was caused by transition on (properly-configured) GPIO1 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[1]. 5 GPIO0 SMI Status (Read Only):SMI was caused by transition on (properly-configured) GPIO0 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[0]. 4 Lid Position (Read Only):This bit maintains the current status of the lid position. If the GPIO6 pin is configured as the lid switch indicator, this bit reflects the state of the pin. 3 Lid Switch SMI Status (Read Only):SMI was caused by a transition on the GPIO6 (lid switch) pin? 0=N o ;1=Y e s . For this to happen, the GPIO6 pin must be configured both as an input (F0 Index 90h[6] = 0) and as the lid switch (F0 Index 92h[6] =1). 2 Codec SDATA_IN SMI Status (Read Only):SMI was caused by AC97 codec producing a positive edge on SDATA_IN? 0=N o ;1=Y e s . This is the second level of status is reporting. The top level status is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 80h[5]. 1 RTC Alarm (IRQ8) SMI Status (Read Only):SMI was caused by an RTC interrupt? 0 = No; 1 = Y es. This SMI event can only occur while in 3V Suspend and RTC interrupt occurs. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. 0 ACPI Timer SMI Status (Read Only):SMI was caused by an ACPI Timer MSB toggle? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation configuration is at F0 Index 83h[5]. Notes: Properly-configured means that the GPIO pin must be enabled as a GPIO (if multiplexed pin), an input, and to cause an SMI. This register provides status on several miscellaneous power management events that generate SMIs, as well as the sta- tus of the Lid Switch. It is called a Mirror register since an identical register exists at F0 Index F7h. Reading this register does not clear the status, while reading its counterpart at F0 Index F7h does clear the status. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 164 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 88h General Purpose Timer 1 Count Register (R/W) Reset Value = 00h 7:0 General Purpose Timer 1 Count:This field represents the load value for GP Timer 1. This value can represent either an 8-bit or 16-bit counter (selected in F0 Index 8Bh[4]). It is loaded into the counter when the timer is enabled (F0 Index 83h[0] =1). Once enabled, an enabled event (configured in F0 Index 89h[6:0]) reloads the timer. The counter is decremented with each clock of the configured timebase. Upon expiration of the counter, an SMI is gener- ated and the top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. The second level SMI status is reported at F1BAR+Memory Offset 04h/06h[0]). Once expired, this counter must be re-initialized by either disabling and enabling it, or writing a new count value here. This counter’s timebase can be configured as 1 msec or 1 sec at F0 Index 89h[7]. Index 89h General Purpose Timer 1 Control Register (R/W) Reset Value = 00h 7 Timebase for General Purpose Timer 1:Selects timebase for GP Timer 1 (F0 Index 88h): 0 = 1 sec; 1 = 1 msec. 6 Re-trigger General Purpose Timer 1 on User Defined Device 3 (UDEF3) Activity:0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF3 reloads GP Timer 1. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register). 5 Re-trigger General Purpose Timer 1 on User Defined Device 2 (UDEF2) Activity:0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF2 reloads GP Timer 1. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register). 4 Re-trigger General Purpose Timer 1 on User Defined Device 1 (UDEF1) Activity:0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF1 reloads GP Timer 1. UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register) Any access to the keyboard or mouse I/O address range (listed below) reloads GP Timer 1. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) 2 Re-trigger General Purpose Timer 1 on Parallel/Serial Port Activity:0 = Disable; 1 = Enable. Any access to the parallel or serial port I/O address range (listed below) reloads the GP Timer 1. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh 1 Re-trigger General Purpose Timer 1 on Floppy Disk Activity:0 = Disable; 1 = Enable. Any access to the floppy disk drive address ranges (listed below) reloads GP Timer 1. Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h Secondary floppy disk: I/O Port 372h-375h, 377h The active floppy drive is configured via F0 Index 93h[7]. 0 Re-trigger General Purpose Timer 1 on Primary Hard Disk Activity:0 = Disable; 1 = Enable. Any access to the primary hard disk drive address range selected in F0 Index 93h[5] reloads GP Timer 1. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 165 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 8Ah General Purpose Timer 2 Count Register (R/W) Reset Value = 00h 7:0 General Purpose Timer 2 Count:This field represents the load value for GP Timer 2. This value can represent either an 8-bit or 16-bit counter (configured in F0 Index 8Bh[5]). It is loaded into the counter when the timer is enabled (F0 Index 83h[1] = 1). Once the timer is enabled and a transition occurs on GPIO7, the timer is re-loaded. The counter is decremented with each clock of the configured timebase. Upon expiration of the counter, an SMI is gener- ated and the top level of status is F1BAR+Memory Offset 00h/02h[9] and the second level of status is reported in F1BAR+Memory Offset 04h/06h[1]). Once expired, this counter must be re-initialized by either disabling and enabling it, or writing a new count value here. For GPIO7 to act as the reload for this counter, it must be enabled as such (F0 Index 8Bh[2]) and be configured as an input (F0 Index 90h[7]). This counter’s timebase can be configured as 1 msec or 1 sec in F0 Index 8Bh[3]. Index 8Bh General Purpose Timer 2 Control Register (R/W) Reset Value = 00h 7 Re-trigger General Purpose Timer 1 on Secondary Hard Disk Activity:0 = Disable; 1 = Enable. Any access to the secondary hard disk drive address range selected in F0 Index 93h[4] reloads GP Timer 1. 6 VGA Timer Base: Selects timebase for VGA Timer Register (F0 Index 8Eh): 0 = 1 ms; 1 = 32 µs. 5 General Purpose Timer 2 Shift:GP Timer 2 is treated as an 8-bit or 16-bit timer: 0 = 8-bit; 1 = 16-bit. As an 8-bit timer, the count value is loaded into GP Timer 2 Count Register (F0 Index 8Ah). As a 16-bit timer, the value loaded into GP Timer 2 Count Register is shifted left by eight bits, the lower eight bits become zero, and this 16-bit value is used as the count for GP Timer 2. 4 General Purpose Timer 1 Shift:GP Timer 1 is treated as an 8-bit or 16-bit timer: 0 = 8-bit; 1 = 16-bit. As an 8-bit timer, the count value is that loaded into GP Timer 1 Count Register (F0 Index 88h). As a 16-bit timer, the value loaded into GP Timer 1 Count Register is shifted left by eight bit, the lower eight bits become zero, and this 16-bit value is used as the count for GP Timer 1. 3 Time Basis for General Purpose Timer 2:Selects timebase for GP Timer 2 (F0 Index 8Ah): 0 = 1 sec; 1 = 1 msec. 2 Re-trigger General Purpose Timer 2 on GPIO7 Pin Transition:A configured transition on the GPIO7 pin reloads GP Timer 2 (F0 Index 8Ah): 0 = Disable; 1 = Enable. F0 Index 92h[7] selects whether a rising- or a falling-edge transition acts as a reload. For GPIO7 to work here, it must first be configured as an input (F0 Index 90h[7] = 0). 1:0 Reserved: Set to 0. Index 8Ch IRQ Speedup Timer Count Register (R/W) Reset Value = 00h 7:0 IRQ Speedup Timer Count:This field represents the load value for the IRQ speedup timer. It is loaded into the counter when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and an INTR or an access to I/O Port 061h occurs. When the event occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the CPU. Upon expira- tion, no SMI is generated; the Suspend Modulation begins again. The IRQ speedup timer’s timebase is 1 ms. This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typi- cal value here would be 2 to 4 ms. Index 8Dh Video Speedup Timer Count Register (R/W) Reset Value = 00h 7:0 Video Speedup Timer Count:This field represents the load value for the Video speedup timer. It is loaded into the counter when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and any access to the graphics controller occurs. When a video access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the CPU. Upon expiration, no SMI is generated; the Suspend Modulation begins again. The video speedup timer’s timebase is 1 ms. This speedup mechanism allows instantaneous response to video activity for full speed during video processing calcula- tions. A typical value here would be 50 to 100 ms. Index 8Eh VGA Timer Count Register (R/W) Reset Value = 00h 7:0 VGA Timer Load Value:This field represents the load value for VGA Timer. It is loaded into the counter when the timer is enabled (F0 Index 83h[3] = 1). The counter is decremented with each clock of the configured timebase (F0 Index 8Bh[6]). Upon expiration of the counter, an SMI is generated and the status is reported in F1BAR+Memory Offset 00h/02h[6] (only). Once expired, this counter must be re-initialized by either disabling and enabling it, or writing a new count value here. This counter’s timebase is 1 ms. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 166 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 8Fh Reserved Index 90h GPIO Pin Direction Register 1 (R/W) Reset Value = 00h 7 GPIO7 Direction:Selects if GPIO7 is an input or output: 0 = Input; 1 = Output. 6 GPIO6 Direction:Selects if GPIO6 is an input or output: 0 = Input; 1 = Output. 5 GPIO5 Direction:Selects if GPIO5 is an input or output: 0 = Input; 1 = Output. 4 GPIO4 Direction:Selects if GPIO4 is an input or output: 0 = Input; 1 = Output. 3 GPIO3 Direction:Selects if GPIO3 is an input or output: 0 = Input; 1 = Output. 2 GPIO2 Direction:Selects if GPIO2 is an input or output: 0 = Input; 1 = Output. 1 GPIO1 Direction:Selects if GPIO1 is an input or output: 0 = Input; 1 = Output. 0 GPIO0 Direction:Selects if GPIO0 is an input or output: 0 = Input; 1 = Output. Note: Several of these pins have specific alternate functions. The direction configured here must be consistent with the pins’ use as the alternate function. Index 91h GPIO Pin Data Register 1 (R/W) Reset Value = 00h 7 GPIO7 Data:Reflects the level of GPIO7: 0 = Low; 1 = High. 6 GPIO6 Data:Reflects the level of GPIO6: 0 = Low; 1 = High. 5 GPIO5 Data:Reflects the level of GPIO5: 0 = Low; 1 = High. 4 GPIO4 Data:Reflects the level of GPIO4: 0 = Low; 1 = High. 3 GPIO3 Data:Reflects the level of GPIO3: 0 = Low; 1 = High. 2 GPIO2 Data:Reflects the level of GPIO2: 0 = Low; 1 = High. 1 GPIO1 Data:Reflects the level of GPIO1: 0 = Low; 1 = High. 0 GPIO0 Data:Reflects the level of GPIO0: 0 = Low; 1 = High. Note: This register contains the direct values of GPIO[7:0] pins. Write operations are valid only for bits defined as output. Reads from this register read the last written value if the pin is an output. The pins are configured as inputs or outputs in F0 Index 90h. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 167 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 92h GPIO Control Register 1 (R/W) Reset Value = 00h GP Timer 2 to reload: 0 = Rising; 1 = Falling, (Note 2) 6 GPIO6 Enabled as Lid Switch:Allow GPIO6 to act as the lid switch input: 0 = GPIO6; 1 = Lid switch. When enabled, every transition of the GPIO6 pin causes the lid switch status to toggle and generate an SMI. The top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[3]. If GPIO6 is enabled as the lid switch, F0 Index 87h/F7h[4] reports the current status of the lid’s position. 0 = Rising; 1 = Falling. Bit 2 must be set to enable this bit. 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. 2 Enable GPIO2 as an External SMI Source:Allow GPIO2 to be an external SMI source and generate an SMI on either a rising or falling edge transition (depends upon setting of bit 5): 0 = Disable; 1 = Enable (Note 3). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[7]. 1 Enable GPIO1 as an External SMI Source:Allow GPIO1 to be an external SMI source and generate an SMI on either a rising- or falling-edge transition (depends upon setting of bit 4): 0 = Disable; 1 = Enable (Note 3). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[6]. 0 Enable GPIO0 as an External SMI Source:Allow GPIO0 to be an external SMI source and generate an SMI on either a rising or falling edge transition (depends upon setting of bit 3): 0 = Disable; 1 = Enable (Note 3) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[5]. Notes:1) For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h). 2) GPIO7 can generate an SMI (F0 Index 97h[3]) or re-trigger General Purpose Timer 2 (F0 Index 8Bh[2]) or both. 3) If GPIO[2:0] are enabled as external SMI sources, they are the only GPIOs that can be used as SMI sources to wake-up the system from Suspend when the clocks are stopped. Index 93h Miscellaneous Device Control Register (R/W) Reset Value = 00h 7 Floppy Drive Port Select:All system resources used to power manage the floppy drive use the primary or secondary FDC addresses for decode: 0 = Secondary; 1 = Primary. 6 Reserved: This bit must always be set to 1. 5 Partial Primary Hard Disk Decode:This bit is used to restrict the addresses which are decoded as primary hard disk accesses. 0 = Power management monitors all reads and writes I/O Port 1F0h-1F7h, 3F6h-3F7h (excludes writes to 3F7h) 1 = Power management monitors only writes to I/O Port 1F6h and 1F7h 4 Partial Secondary Hard Disk Decode:This bit is used to restrict the addresses which are decoded as secondary hard Disk accesses. 0 = Power management monitors all reads and writes I/O Port 170h-177h, 376h-377h (excludes writes to 377h) 1 = Power management monitors only writes to I/O Port 176h and 177h 3:2 Reserved: Set to 0. 1 Mouse on Serial Enable:Mouse is present on a Serial Port: 0 = No; 1 = Y es. (Note) 0 Mouse Port Select:Selects which serial port the mouse is attached to: 0 = COM1; 1 = COM2. (Note) Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done because a mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the screen. These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the Paral- lel/Serial Port Idle Timer Count Register (F0 Index 9Ch). Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 168 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 94h Suspend Modulation OFF Count Register (R/W) Reset Value = 00h 7:0 Suspend Signal Deasserted Count:This 8-bit counter represents the number of 32 µs intervals that the SUSP# pin will be deasserted to the GXLV processor. This counter, together with the Suspend Modulation ON Count Register (F0 Index 95h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups. Index 95h Suspend Modulation ON Count Register (R/W) Reset Value = 00h 7:0 Suspend Signal Asserted Count:This 8-bit counter represents the number of 32 µs intervals that the SUSP# pin will be asserted. This counter, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups. Index 96h Suspend Configuration Register (R/W) Reset Value = 00h 7:3 Reserved: Set to 0. 2 Suspend Mode Configuration:“Special 3 Volt Suspend” mode to support powering down a GXLV processor during Suspend: 0 = Disable; 1 = Enable. 0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI occurs. 1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA technology and Power Management operations occur at full speed. Two methods for accomplishing this are either to map the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0). 0 Suspend Modulation Feature Enable:Suspend Modulation feature: 0 = Disable; 1 = Enable. When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation OFF/ON Count Registers (F0 Index 94h/95h). Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 169 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 97h GPIO Control Register 2 (R/W) Reset Value = 00h 0 = Rising; 1 = Falling. Bit 3 must be set to enable this bit. 0 = Rising; 1 = Falling. Bit 2 must be set to enable this bit. 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. 0 = Rising; 1 = Falling. Bit 0 must be set to enable this bit. 3 Enable GPIO7 as an External SMI Source:Allow GPIO7 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 7): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[3]. 2 Enable GPIO5 as an External SMI Source:Allow GPIO5 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 6): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[2]. 1 Enable GPIO4 as an External SMI Source:Allow GPIO4 to be an external SMI source and to generate an SMI on either a rising- or falling-edge transition (depends upon setting of bit 5): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[1]. 0 Enable GPIO3 as an External SMI Source:Allow GPIO3 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 4) 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[0]. Note: For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h). Index 98h-99h Primary Hard Disk Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Primary Hard Disk Idle Timer Count:This idle timer is used to determine when the primary hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of primary hard disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured primary hard disk’s data port (configured in F0 Index 93h[5]). The counter uses a 1 second time- base. To enable this timer set F0 Index 81h[0] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0]. Index 9Ah-9Bh Floppy Disk Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Floppy Disk Idle Timer Count:This idle timer is used to determine when the floppy disk drive is not in use so that it can be powered down. The 16-bit value programmed here represents the period of floppy disk drive inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured floppy drive’s data port (I/O Port 3F5h or 375h). The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[1] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[1]. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 170 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index 9Ch-9Dh Parallel / Serial Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 P a r a l l e l/S e r i a lI d l eT i m e rC o u n t :This idle timer is used to determine when the parallel and serial ports are not in use so that the ports can be power managed. The 16-bit value programmed here represents the period of inactivity for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the parallel (LPT) or serial (COM) I/O address spaces. If the mouse is enabled on a serial port, that port is not considered here. The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[2] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2]. Index 9Eh-9Fh Keyboard / Mouse Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Keyboard / Mouse Idle Timer Count:This idle timer determines when the keyboard and mouse are not in use so that the LCD screen can be blanked. The 16-bit value programmed here represents the period of inactivity for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to either the keyboard or mouse I/O address spaces, including the mouse serial port address space when a mouse is enabled on a serial port. The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[3] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3]. Index A0h-A1h User Defined Device 1 Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 User Defined Device 1 (UDEF1) Idle Timer Count:This idle timer determines when the device configured as UDEF1 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured in F0 Index C0h (base address register) and F0 Index CCh (control register). The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[4] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[4]. Index A2h-A3h User Defined Device 2 Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 User Defined Device 2 (UDEF2) Idle Timer Count:This idle timer determines when the device configured as UDEF2 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured in the F0 Index C4h (base address register) and F0 Index CDh (control register). The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[5] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[5]. Index A4h-A5h User Defined Device 3 Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 User Defined Device 3 (UDEF3) Idle Timer Count:This idle timer determines when the device configured as UDEF3 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured in the UDEF3 Base Address Register (F0 Index C8h) and UDEF3 Control Register (F0 Index CEh). The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[6] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[6]. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 171 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index A6h-A7h Video Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Video Idle Timer Count:This idle timer determines when the graphics subsystem has been idle as part of the Suspend-determination algorithm. The 16-bit value programmed here represents the period of video inactivity after which the system is alerted via an SMI. The count in this timer is automatically reset whenever an access occurs to the graphics controller space. The counter uses a 1 second timebase. In a GXLV processor based system the graphics controller is embedded in the CPU, so video activity is communicated to the CS5530 via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530 also detects accesses to standard VGA space on PCI (3Bxh, 3h, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used. To enable this timer set F0 Index 81h[7] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[7]. Index A8h-A9h Video Overflow Count Register (R/W) Reset Value = 0000h 15:0 Video Overflow Count:Each time the Video Speedup Counter (F0 Index 8Dh) is triggered, a 100 ms timer is started. If the 100 ms timer expires before the Video Speedup Counter lapses, the Video Overflow Count Register increments and the 100 ms timer re-triggers. Software clears the overflow register when new evaluations are to begin. The count con- tained in this register may be combined with other data to determine the type of video accesses present in the system. Index AAh-ABh Reserved Index ACh-ADh Secondary Hard Disk Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Secondary Hard Disk Idle Timer Count:This idle timer is used to determine when the secondary hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of secondary hard disk inactiv- ity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured secondary hard disk’s data port (configured in F0 Index 93h[4]). The counter uses a 1 second timebase. To enable this timer set F0 Index 83h[7] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4]. Index AEh CPU Suspend Command Register (WO) Reset Value = 00h 7:0 Software CPU Suspend Command (Write Only):If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0] = 0), a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU in a low-power state. The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt condition. If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted after the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4] is invoked, allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin. Note: If the clocks are stopped the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530 pins can be used to wake-up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI events are also Resume events. Index AFh Suspend Notebook Command Register (WO) Reset Value = 00h 7:0 Software CPU Stop Clock Suspend (Write Only):A write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU in a low-power state. Following this handshake, the SUSP_3V pin is asserted. The SUSP_3V pin is intended to be used to stop all system clocks. Upon a Resume event (see note), the SUSP_3V pin is deasserted. After a slight delay, the CS5530 deasserts the SUSP# signal. Once the clocks are stable, the processor deasserts SUSPA# and system operation resumes. Note: If the clocks are stopped the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530 pins can be used to wake-up the system from Suspend when the clocks are stopped. Index B0h-B3h Reserved Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 172 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index B4h Floppy Port 3F2h Shadow Register (RO) Reset Value = xxh 7:0 Floppy Port 3F2h Shadow (Read Only):Last written value of I/O Port 3F2h. Required for support of FDC power ON/OFF and Zero Volt Suspend/Resume coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation. Index B5h Floppy Port 3F7h Shadow Register (RO) Reset Value = xxh 7:0 Floppy Port 3F7h Shadow (Read Only):Last written value of I/O Port 3F7h. Required for support of FDC power ON/OFF and Zero Volt Suspend/Resume coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation. Index B6h Floppy Port 1F2h Shadow Register (RO) Reset Value = xxh 7:0 Floppy Port 1F2h Shadow (Read Only):Last written value of I/O Port 1F2h. Required for support of FDC power ON/OFF and Zero Volt Suspend/Resume coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation. Index B7h Floppy Port 1F7h Shadow Register (RO) Reset Value = xxh 7:0 Floppy Port 1F7h Shadow (Read Only):Last written value of I/O Port 1F7h. Required for support of FDC power ON/OFF and Zero Volt Suspend/Resume coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation. Index B8h DMA Shadow Register (RO) Reset Value = xxh 7:0 DMA Shadow (Read Only):This 8-bit port sequences through the following list of shadowed DMA Controller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. DMA Channel 0 Mode Register 2. DMA Channel 1 Mode Register 3. DMA Channel 2 Mode Register 4. DMA Channel 3 Mode Register 5. DMA Channel 4 Mode Register 6. DMA Channel 5 Mode Register 7. DMA Channel 6 Mode Register 8. DMA Channel 7 Mode Register 9. DMA Channel Mask Register (bit 0 is channel 0 mask, etc.) 10. DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1ms, all other bits are 0) Index B9h PIC Shadow Register (RO) Reset Value = xxh 7:0 PIC Shadow (Read Only):This 8-bit port sequences through the following list of shadowed Programmable Interrupt Con- troller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. PIC1 ICW1 2. PIC1 ICW2 3. PIC1 ICW3 4. PIC1 ICW4 - Bits [7:5] of ICW4 are always 0 5. PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (Note) 6. PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1 7. PIC2 ICW1 8. PIC2 ICW2 9. PIC2 ICW3 10. PIC2 ICW4 - Bits [7:5] of ICW4 are always 0 11. PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note) 12. PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1 Note: To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register v a l u e ,t h e nw i t ht h es h a d o wr e g i s t e rv a l u eO R e dw i t hC 0 h . Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 173 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index BAh PIT Shadow Register (RO) Reset Value = xxh 7:0 PIT Shadow (Read Only):This 8-bit port sequences through the following list of shadowed Programmable Interval Timer registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. Counter 0 LSB (least significant byte) 2. Counter 0 MSB 3. Counter 1 LSB 4. Counter 1 MSB 5. Counter 2 LSB 6. Counter 2 MSB 7. Counter 0 Command Word 8. Counter 1 Command Word 9. Counter 2 Command Word Note: The LSB/MSB of the count is the Counter base value, not the current value. Bits [7:6] of the command words are not used. Index BBh RTC Index Shadow Register (RO) Reset Value = xxh 7:0 RTC Index Shadow (Read Only):The RTC Shadow register contains the last written value of the RTC Index register (I/O Port 070h). Index BCh Clock Stop Control Register (R/W) Reset Value = 00h 7:4 PLL Delay:The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the SUSP# pin is deasserted to the CPU. This delay is designed to allow the clock chip and CPU PLL to stabilize before start- ing execution. This delay is only invoked if the STP_CLK bit (bit 0) was set. The four-bit field allows values from 0 to 15 ms. 0000 = 0 ms 0100 = 4 ms 1000 = 8 ms 1100 = 12 ms 0001 = 1 ms 0101 = 5 ms 1001 = 9 ms 1101 = 13 ms 0010 = 2 ms 0110 = 6 ms 1010 = 10 ms 1110 = 14 ms 0011 = 3 ms 0111 = 7 ms 1011 = 11 ms 1111 = 15 ms 3:1 Reserved: Set to 0. 0 CPU Clock Stop:0 = Normal SUSP#/ SUSPA# handshake; 1 = Full system Suspend. Note: This register configures the CS5530 to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the appropriate conditions, stopping the system clocks. A delay of 0 to 15 ms is programmable (bits 7:4) to allow for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system. A write to the CPU Suspend Command Register (F0 Index AEh) with bit 0 written as: 0 = SUSP#/SUSPA# handshake occurs. The CPU is put into a low-power state, and the system clocks are not stopped. When a break/resume event occurs, it releases the CPU halt condition. 1 = SUSP#/SUSPA# handshake occurs and the SUSP_3V pin is asserted, thus invoking a full system Suspend (both CPU and system clocks are stopped). When a break event occurs, the SUSP_3V pin will deassert, the PLL delay programmed in bits [7:4] will be invoked which allows the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin. Index BDh-BFh Reserved Index C0h-C3h User Defined Device 1 Base Address Register (R/W) Reset Value = 00000000h 31:0 User Defined Device 1 (UDEF1) Base Address [31:0]:This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar- ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh). Index C4h-C7h User Defined Device 2 Base Address Register (R/W) Reset Value = 00000000h 31:0 User Defined Device 2 (UDEF2) Base Address [31:0]:This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar- ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh). Index C8h-CBh User Defined Device 3 Base Address Register (R/W) Reset Value = 00000000h 31:0 User Defined Device 3 (UDEF3) Base Address [31:0]:This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar- ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh). Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 174 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index CCh User Defined Device 1 Control Register (R/W) Reset Value = 00h 7 Memory or I/O Mapped:User Defined Device 1 is: 0 = I/O; 1 = Memory. 6:0 Mask: If bit 7 = 0 (I/O): Bit 6 0 = Disable write cycle tracking 1 = Enable write cycle tracking Bit 5 0 = Disable read cycle tracking 1 = Enable read cycle tracking Bits 4:0 Mask for address bits A[4:0] If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. Index CDh User Defined Device 2 Control Register (R/W) Reset Value = 00h 7 Memory or I/O Mapped:User Defined Device 2 is: 0 = I/O; 1 = Memory. 6:0 Mask: If bit 7 = 0 (I/O): Bit 6 0 = Disable write cycle tracking 1 = Enable write cycle tracking Bit 5 0 = Disable read cycle tracking 1 = Enable read cycle tracking Bits 4:0 Mask for address bits A[4:0] If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. Index CEh User Defined Device 3 Control Register (R/W) Reset Value = 00h 7 Memory or I/O Mapped:User Defined Device 3 is: 0 = I/O; 1 = Memory. 6:0 Mask: If bit 7 = 0 (I/O): Bit 6 0 = Disable write cycle tracking 1 = Enable write cycle tracking Bit 5 0 = Disable read cycle tracking 1 = Enable read cycle tracking Bits 4:0 Mask for address bits A[4:0] If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. Index CFh Reserved Index D0h Software SMI Register (WO) Reset Value = 00h 7:0 Software SMI (Write Only):A write to this location generates an SMI. The data written is irrelevant. This register allows software entry into SMM via normal bus access instructions. Index D1h-EBh Reserved Index ECh Timer Test Register (R/W) Reset Value = 00h 7:0 Timer Test Value:The Timer Test Register is intended only for test and debug purposes. It is not intended for setting operational timebases. Index EDh-F3h Reserved Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 175 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index F4h Second Level Power Management Status Register 1 (RC) Reset Value = 84h 7:5 Reserved 4 Game Port SMI Status (Read to Clear):SMI was caused by a R/W access to game port (I/O Port 200h and 201h)? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. Game Port Read SMI generation enabling is at F0 Index 83h[4]. Game Port Write SMI generation enabling is at F0 Index 53h[3]. 3 GPIO7 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO7 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[3]. 2 GPIO5 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO5 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[2]. 1 GPIO4 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO4 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[1]. 0 GPIO3 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO3 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[0]. Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI. This register provides status on various power-management SMI events. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 84h. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 176 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index F5h Second Level Power Management Status Register 2 (RC) Reset Value = 00h 7 Video Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Video Idle Timer Count Register (F0 Index A6h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[7]. 6 User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the UDEF3 Idle Timer Count Register (F0 Index A4h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[6]. 5 User Defined Device 2 (UDEF2) Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the UDEF2 Idle Timer Count Register (F0 Index A2h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[5]. 4 User Defined Device 1 (UDEF1) Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the UDEF1 Idle Timer Count Register (F0 Index A0h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[4]. 3 Keyboard/Mouse Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[3]. 2 Parallel/Serial Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[2]. 1 Floppy Disk Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Floppy Disk Idle Timer Count Register (F0 Index 9Ah)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[1]. 0 Primary Hard Disk Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Primary Hard Disk Idle Timer Count Register (F0 Index 98h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[0]. Note: This register provides status on the Device Idle Timers to the SMI handler. A bit set here indicates that the device was idle for the duration configured in the Idle Timer Count register for that device, causing an SMI. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 85h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), F0 Index 85h may be read instead. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 177 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index F6h Second Level Power Management Status Register 3 (RC) Reset Value = 00h 7 Video Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the Video I/O Trap? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[7]. 5 Secondary Hard Disk Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the secondary hard disk? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[6]. 4 Secondary Hard Disk Idle Timer SMI Status (Read to Clear):SMI was caused by expiration of the Hard Disk Idle Timer Count Register (F0 Index ACh)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[7]. 3 Keyboard/Mouse Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the keyboard or mouse? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[3]. 2 Parallel/Serial Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to either the serial or parallel ports? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[2]. floppy disk? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[1]. 0 Primary Hard Disk Access Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the primary hard disk? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[0]. Note: This register provides status on the Device Traps to the SMI handler. A bit set here indicates that an access occurred to the device while the trap was enabled, causing an SMI. Reading this register clears the SMI status bits. A read-only (mirror) ver- sion of this register exists at F0 Index 86h. If the value of the register must be read without clearing the SMI source (and con- sequently deasserting SMI), F0 Index 86h may be read instead. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

www.national.com 178 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Index F7h Second Level Power Management Status Register 4 (RO/RC) Reset Value = 00h 7 GPIO2 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO2 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[2]. 6 GPIO1 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO1 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[1]. 5 GPIO0 SMI Status (Read to Clear):SMI was caused by transition on (properly-configured) GPIO0 pin? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[0]. 4 Lid Position (Read Only):This bit maintains the current status of the lid position. If the GPIO6 pin is configured as the lid switch indicator, this bit reflects the state of the pin. 3 Lid Switch SMI Status (Read to Clear):SMI was caused by a transition on the GPIO6 (lid switch) pin? 0=N o ;1=Y e s . For this to happen, the GPIO6 pin must be configured both as an input (F0 Index 90h[6] = 0) and as the lid switch (F0 Index 92h[6] =1). 2 Codec SDATA_IN SMI Status (Read to Clear):SMI was caused by an AC97 codec producing a positive edge on SDA TA_IN? 0 = No; 1 = Y es. This is the second level of status is reporting. The top level status is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 80h[5]. 1 RTC Alarm (IRQ8) SMI Status (Read to Clear):SMI was caused by an RTC interrupt? 0 = No; 1 = Y es. This SMI event can only occur while in 3V Suspend and RTC interrupt occurs. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. 0 ACPI Timer SMI Status (Read to Clear):SMI was caused by an ACPI Timer MSB toggle? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation configuration is at F0 Index 83h[5]. Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI. This register provides status on several miscellaneous power management events that generate SMIs, as well as the status of the Lid Switch. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 87h. Index F8h-FFh Reserved Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description

Revision 4.1 179 www.national.com Register Descriptions(Continued) Geode™ CS5530

4.3.2 SMI Status and ACPI Timer Registers - Function 1

The register space for the SMI status and ACPI Timer reg- isters is divided into two sections. The first section is used to configure the PCI portion of this support hardware. A Base Address Register at F1 Index 10h (F1BAR) points to the base address of where the second portion of the reg- ister space is located. This second section contains the SMI status and ACPI timer support registers. Note: In Silicon Revision 1.3 and above the ACPI Timer Count Register is accessible through I/O Port 121Ch. Table 4-15 shows the PCI header registers of F1. The memory mapped registers accessed through F1BAR are shown in Table 4-16. Table 4-15. F1 Index xxh: PCI Header Registers for SMI Status and ACPI Timer Bit Description Index 00h-01h Vendor Identification Register (RO) Reset Value = 1078h Index 02h-03h Device Identification Register (RO) Reset Value = 0101h Index 04h-05h PCI Command Register (R/W) Reset Value = 0000h 15:2 Reserved (Read Only) 1 Memory Space: Allow CS5530 to respond to memory cycles from the PCI bus: 0 = Disable; 1 = Enable. This bit must be enabled to access memory offsets through F1BAR (F1 Index 10h).

0 Reserved (Read Only)

Index 06h-07h PCI Status Register (RO) Reset Value = 0280h Index 08h Device Revision ID Register (RO) Reset Value = 00h Index 09h-0Bh PCI Class Code Register (RO) Reset Value = 068000h Index 0Ch PCI Cache Line Size Register (RO) Reset Value = 00h Index 0Dh PCI Latency Timer Register (RO) Reset Value = 00h Index 0Eh PCI Header Type (RO) Reset Value = 00h Index 0Fh PCI BIST Register (RO) Reset Value = 00h Index 10h-13h Base Address Register — F1BAR (R/W) Reset Value = 00000000h This register sets the base address of the memory mapped SMI status and ACPI timer related registers. Bits [7:0] are read only (00h), indicating a 256 byte memory address range. Refer to Table 4-16 for the SMI status and ACPI timer registers bit formats and reset val- ues. The upper 16 bytes are always mapped to the ACPI timer, and are always memory mapped. Note: In Silicon Revision 1.3 and above the ACPI Timer Count Register is accessible through I/O Port 121Ch. 31:8 SMI Status/Power Management Base Address 7:0 Address Range (Read Only) Index 14h-FFh Reserved

www.national.com 180 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers Bit Description Offset 00h-01h Top Level SMI Status Mirror Register (RO) Reset Value = 0000h 15 Suspend Modulation Enable Mirror (Read Only):This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR+Memory Offset 08h) must be cleared on exit. 14 S M IS o u r c ei sU S B( R e a dO n l y ) :SMI was caused by USB activity? 0 = No; 1 = Y es. SMI generation is configured in F0 Index 42h[7:6]. 13 SMI Source is Warm Reset Command (Read Only):SMI was caused by Warm Reset command? 0 = No; 1 = Y es. 12 S M IS o u r c ei sN M I( R e a dO n l y ) :SMI was caused by NMI activity? 0 = No; 1 = Y es. 11:10 Reserved (Read Only):Always reads 0. 9 SMI Source is General Purpose Timers/User Defined Device Traps/Register Space Trap (Read Only):SMI was caused by expiration of GP Timer 1/2; trapped access to UDEF3/2/1; trapped access to F1-F4 or ISA Legacy Register Space? 0 = No; 1 = Y es. The next level of status is found at F1BAR+Memory Offset 04h/06h. 8 SMI Source is Software Generated (Read Only):SMI was caused by software? 0 = No; 1 = Yes. 7 S M Io na nA 2 0 M #T o g g l e( R e a dO n l y ) :SMI was caused by an access to either Port 092h or the keyboard command which initiates an A20M# SMI? 0 = No; 1 = Y es. This method of controlling the internal A20M# in the GXLV processor is used instead of a pin. SMI generation enabling is at F0 Index 53h[0].

6 SMI Source is a VGA Timer Event (Read Only):SMI was caused by the expiration of the VGA Timer

(F0 Index 8Eh)? 0 = No; 1 = Y es. SMI generation enabling is at F0 Index 83h[3]. 5 SMI Source is Video Retrace (IRQ2) (Read Only):SMI was caused by a video retrace event as decoded from the serial connection (PSERIAL register, bit 7) from the GXLV processor? 0 = No; 1 = Y es. SMI generation enabling is at F0 Index 83h[2]. 4:2 Reserved (Read Only):Always reads 0. 1 SMI Source is Audio Interface (Read Only):SMI was caused by the audio interface? 0 = No; 1 = Y es. The next level SMI status registers is found in F3BAR+Memory Offset 10h/12h. 0 SMI Source is Power Management Event (Read Only):SMI was caused by one of the power management resources? 0=N o ;1=Y e s . The next level of status is found at F0 Index 84h-87h/F4h-F7h. Note: The status for the General Purpose Timers and the User Device Defined Traps are checked separately in bit 9. Note: Reading this register does not clear the status bits. See F1BAR+Memory Offset 02h.

Revision 4.1 181 www.national.com Register Descriptions(Continued) Geode™ CS5530 Offset 02h-03h Top Level SMI Status Register (RC) Reset Value = 0000h 15 Suspend Modulation Enable Mirror (Read to Clear):This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR+Memory Offset 08h) must be cleared on exit. 14 SMI Source is USB (Read to Clear):SMI was caused by USB activity? 0 = No; 1 = Y es. SMI generation is configured in F0 Index 42h[7:6]. 13 SMI Source is Warm Reset Command (Read to Clear):SMI was caused by Warm Reset command? 0=N o ;1=Y e s . 12 SMI Source is NMI (Read to Clear):SMI was caused by NMI activity? 0 = No; 1 = Y es. 11:10 Reserved (Read to Clear):Always reads 0. 9 SMI Source is General Purpose Timers/User Defined Device Traps/Register Space Trap (Read to Clear):SMI was caused by expiration of GP Timer 1/2; trapped access to UDEF3/2/1; trapped access to F1-F4 or ISA Legacy Register Space? 0 = No; 1 = Y es. The next level of status is found at F1BAR+Memory Offset 04h/06h. 8 SMI Source is Software Generated (Read to Clear):SMI was caused by software? 0 = No; 1 = Yes. 7 SMI on an A20M# Toggle (Read to Clear):SMI was caused by an access to either Port 092h or the keyboard command which initiates an A20M# SMI? 0 = No; 1 = Y es. This method of controlling the internal A20M# in the GXLV processor is used instead of a pin. SMI generation enabling is at F0 Index 53h[0]. (F0 Index 8Eh)? 0 = No; 1 = Y es. SMI generation enabling is at F0 Index 83h[3]. 5 SMI Source is Video Retrace (IRQ2) (Read to Clear):SMI was caused by a video retrace event as decoded from the from the serial connection (PSERIAL register, bit 7) from the GXLV processor? 0 = No; 1 = Yes. SMI generation enabling is at F0 Index 83h[2]. 4:2 Reserved (Read to Clear):Always reads 0. 1 SMI Source is Audio Interface (Read to Clear):SMI was caused by the audio interface? 0 = No; 1 = Y es. The next level SMI status registers is found in F3BAR+Memory Offset 10h/12h. resources? 0 = No; 1 = Yes. The next level of status is found at F0 Index 84h-87h/F4h-F7h. Note: The status for the General Purpose Timers and the User Device Defined Traps are checked separately in bit 9. Note: Reading this register clears all the SMI status bits. Note that bits 9, 1, and 0 have another level (second) of status reporting. A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 00h. If the value of the register must be read with- out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead. Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued) Bit Description

www.national.com 182 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Offset 04h-05h Second Level General Traps & Timers SMI Status Mirror Register (RO) Reset Value = 0000h 15:6 Reserved (Read Only) 5 PCI Function Trap (Read Only):SMI was caused by a trapped configuration cycle (listed below)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. Trapped Access to F1 Register Space; SMI generation enabling is at F0 Index 41h[3]. Trapped Access to F2 Register Space; SMI generation enabling is at F0 Index 41h[6]. Trapped Access to F3 Register Space; SMI generation enabling is at F0 Index 42h[0]. Trapped Access to F4 Register Space; SMI generation enabling is at F0 Index 42h[1]. Trapped Access to ISA Legacy I/O Register Space; SMI generation enabling is at F0 Index 41h[0]. 4 SMI Source is Trapped Access to User Defined Device 3 (Read Only):SMI was caused by a trapped I/O or memory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[6]. 3 SMI Source is Trapped Access to User Defined Device 2 (Read Only):SMI was caused by a trapped I/O or memory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[5]. 2 SMI Source is Trapped Access to User Defined Device 1 (Read Only):SMI was caused by a trapped I/O or memory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[4].

1 SMI Source is Expired General Purpose Timer 2 (Read Only):SMI was caused by the expiration of General

Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[1].

0 SMI Source is Expired General Purpose Timer 1 (Read Only):SMI was caused by the expiration of General

Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[0]. Note: Reading this register does not clear the status bits. See F1BAR+Memory Offset 06h. Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued) Bit Description

Revision 4.1 183 www.national.com Register Descriptions(Continued) Geode™ CS5530 Offset 06h-07h Second Level General Traps & Timers SMI Status Register (RC) Reset Value = 0000h 15:6 Reserved (Read to Clear) 5 PCI Function Trap (Read to Clear):SMI was caused by a trapped configuration cycle (listed below)? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. Trapped Access to F1 Register Space; SMI generation enabling is at F0 Index 41h[3]. Trapped Access to F2 Register Space; SMI generation enabling is at F0 Index 41h[6]. Trapped Access to F3 Register Space; SMI generation enabling is at F0 Index 42h[0]. Trapped Access to F4 Register Space; SMI generation enabling is at F0 Index 42h[1]. Trapped Access to ISA Legacy I/O Register Space; SMI generation enabling is at F0 Index 41h[0]. 4 SMI Source is Trapped Access to User Defined Device 3 (Read to Clear):SMI was caused by a trapped I/O or mem- ory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[6]. 3 SMI Source is Trapped Access to User Defined Device 2 (Read to Clear):SMI was caused by a trapped I/O or mem- ory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[5]. 2 SMI Source is Trapped Access to User Defined Device 1 (Read to Clear):SMI was caused by a trapped I/O or mem- ory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[4]. 1 SMI Source is Expired General Purpose Timer 2 (Read to Clear):SMI was caused by the expiration of General Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[1]. 0 SMI Source is Expired General Purpose Timer 1 (Read to Clear):SMI was caused by the expiration of General Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[0]. Note: Reading this register clears all the SMI status bits. A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 04h. If the value of the register must be read with- out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead. Offset 08h-09h SMI Speedup Disable Register (Read to Enable) Reset Value = 0000h 15:0 SMI Speedup Disable:If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this register invokes the SMI handler to re-enable Suspend Modulation. The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this I/O location has no effect. Offset 0Ah-1Bh Reserved Offset 1Ch-1Fh (Note) ACPI Timer Count Register (RO) Reset Value = 00FFFFFCh ACPI_COUNT (Read Only): This read-only register provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled via F0 Index 83h[5], an SMI is generated when the MSB toggles. The MSB toggles every 2.343 seconds. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0]. 31:24 Reserved: Always returns 0. 23:0 Counter Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch in Silicon Revision 1.3 and above. Offset 20h-4Fh Not Used Offset 50h-FFh The memory mapped registers located here (F1BAR+Memory Offset 50h-FFh) can also be accessed at F0 Index 50h- FFh. The preferred method is to program these register through the F0 register space. Refer to Table 4-14 "F0 Index xxh: PCI Header and Bridge Configuration Registers" on page 149 for bit information regarding these registers. Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued) Bit Description

www.national.com 184 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530

4.3.3 IDE Controller Registers - Function 2

The register space for the IDE controllers is divided into two sections. The first section is used to configure the PCI portion of the controller. A Base Address Register at F2 Index 20h points to the base address of where the second portion of the register space is located. This second sec- tion contains the registers used by the IDE controllers to carry out operations. Table 4-17 shows the PCI header registers of F2. The I/O mapped registers, accessed through F2BAR are shown in Table 4-18. Table 4-17. F2 Index xxh: PCI Header Registers for IDE Configuration Bit Description Index 00h-01h Vendor Identification Register (RO) Reset Value = 1078h Index 02h-03h Device Identification Register (RO) Reset Value = 0102h Index 04h-05h PCI Command Register (R/W) Reset Value = 0000h 15:3 Reserved (Read Only)

2 Enable Mastering:0 = Disable, 1 = Enable

1 Reserved (Read Only)

0 I/O Space:Allow CS5530 to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable. This bit must be enabled to access I/O offsets through F2BAR (F2 Index 20h). Index 06h-07h PCI Status Register (RO) Reset Value = 0280h Index 08h Device Revision ID Register (RO) Reset Value = 00h Index 09h-0Bh PCI Class Code Register (RO) Reset Value = 010180h Index 0Ch PCI Cache Line Size Register (RO) Reset Value = 00h Index 0Dh PCI Latency Timer Register (RO) Reset Value = 00h Index 0Eh PCI Header Type (RO) Reset Value = 00h Index 0Fh PCI BIST Register (RO) Reset Value = 00h Index 10h-1Fh Reserved Index 20h-23h Base Address Register - F2BAR (R/W) Reset Value = 00000001h This register sets the base address of the I/O mapped bus mastering IDE and controller registers. Bits [6:0] are read only (0000 001), indicating a 128 byte I/O address range. Refer to Table 4-18 for the IDE configuration registers bit formats and reset values. 31:7 Bus Mastering IDE Base Address 6:0 Address Range (Read Only) Index 24h-FFh Reserved

Revision 4.1 185 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-18. F2BAR+I/O Offset xxh: IDE Configuration Registers Bit Description Offset 00h IDE Bus Master 0 Command Register — Primary (R/W) Reset Value = 00h 7:4 Reserved: Set to 0. Must return 0 on reads. 1 = PCI writes performed. This bit should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the bus master: 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 to 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is dis- carded. This bit should be reset after completion of data transfer. Offset 01h Not Used Offset 02h IDE Bus Master 0 Status Register — Primary (R/W) Reset Value = 00h 7 Simplex Mode (Read Only):Can both the primary and secondary channel operate independently? 0 = Y es; 1 = No (simplex mode) 6 Drive 1 DMA Capable:Allow Drive 1 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 5 Drive 0 DMA Capable:Allow Drive 0 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 4:3 Reserved: Set to 0. Must return 0 on reads. 2 Bus Master Interrupt:Has the bus master detected an interrupt? 0 = No; 1 = Y es. Write 1 to clear. 1 Bus Master Error:Has the bus master detected an error during data transfer? 0 = No; 1 = Y es. Write 1 to clear. 0 Bus Master Active (Read Only):Is the bus master active? 0 = No; 1 = Y es. Offset 03h Not Used Offset 04h-07h IDE Bus Master 0 PRD Table Address — Primary (R/W) Reset Value = 00000000h 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for IDE Bus Master 0. When written, this register points to the first entry in a PRD table. Once IDE Bus Master 0 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Offset 08h IDE Bus Master 1 Command Register — Secondary (R/W) Reset Value = 00h 7:4 Reserved: Set to 0. Must return 0 on reads. 1 = PCI writes performed. This bit should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the bus master: 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 = 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is dis- carded. This bit should be reset after completion of data transfer. Offset 09h Not Used

www.national.com 186 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Offset 0Ah IDE Bus Master 1 Status Register — Secondary (R/W) Reset Value = 00h 7 Simplex Mode (Read Only):Can both the primary and secondary channel operate independently? 0 = Y es; 1 = No (simplex mode) 6 Drive 1 DMA Capable:Allow Drive 1 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 5 Drive 0 DMA Capable:Allow Drive 0 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 4:3 Reserved: Set to 0. Must return 0 on reads. 2 Bus Master Interrupt:Has the bus master detected an interrupt? 0 = No; 1 = Y es. Write 1 to clear. 1 Bus Master Error:Has the bus master detected an error during data transfer? 0 = No; 1 = Y es. Write 1 to clear. 0 Bus Master Active (Read Only):Is the bus master active? 0 = No; 1 = Y es. Offset 0Bh Not Used Offset 0Ch-0Fh IDE Bus Master 1 PRD Table Address — Secondary (R/W) Reset Value = 00000000h 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for IDE Bus Master 1. When written, this register points to the first entry in a PRD table. Once IDE Bus Master 1 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Offset 10h-1Fh Not Used Offset 20h-23h Channel 0 Drive 0 PIO Register (R/W) Reset Value = 0000E132h (Note) If Offset 24h[31] = 0, Format 0:Selects slowest PIOMODE per channel for commands. Format 0 settings for: PIO Mode 0 = 00009172h PIO Mode 1 = 00012171h PIO Mode 2 = 00020080h PIO Mode 3 = 00032010h PIO Mode 4 = 00040010h 31:20 Reserved: Set to 0. 19:16 PIOMODE: PIO mode 15:12 t2I:Recovery time (value + 1 cycle) 11:8 t3:IDE_IOW# data setup time (value + 1 cycle) 7:4 t2W: IDE_IOW# width minus t3 (value + 1 cycle) 3:0 t1:Address Setup Time (value + 1 cycle) If Offset 24h[31] = 1, Format 1:Allows independent control of command and data. Format 1 settings for: PIO Mode 0 = 9172D132h PIO Mode 1 = 21717121h PIO Mode 2 = 00803020h PIO Mode 3 = 20102010h PIO Mode 4 = 00100010h 31:28 t2IC:Command cycle recovery time (value + 1 cycle) 27:24 t3C:Command cycle IDE_IOW# data setup (value + 1 cycle) 23:20 t2WC: Command cycle IDE_IOW# pulse width minus t3 (value + 1 cycle) 19:16 t1C:Command cycle address setup time (value + 1 cycle) 15:12 t2ID:Data cycle recovery time (value + 1 cycle) 11:8 t3D:Data cycle IDE_IOW# data setup (value + 1 cycle) 7:4 t2WD: Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle) 3:0 t1D:Data cycle address Setup Time (value + 1 cycle) Note: The reset value of this register is not a valid PIO Mode. Table 4-18. F2BAR+I/O Offset xxh: IDE Configuration Registers (Continued) Bit Description

Revision 4.1 187 www.national.com Register Descriptions(Continued) Geode™ CS5530 Offset 24h-27h Channel 0 Drive 0 DMA Control Register (R/W) Reset Value = 00017771h If bit 20 = 0, Multiword DMA Settings for: Multiword DMA Mode 0 = 00077771h Multiword DMA Mode 1 = 00012121h Multiword DMA Mode 2 = 00002020h 30:21 Reserved: Set to 0. 20 DMA Select:DMA operation: 0 = Multiword DMA; 1 = Ultra DMA. 19:16 tKR: IDE_IOR# recovery time (4-bit) (value + 1 cycle) 15:12 tDR: IDE_IOR# pulse width (value + 1 cycle) 11:8 tKW: IDE_IOW# recovery time (4-bit) (value + 1 cycle) 7:4 tDW: IDE_IOW# pulse width (value + 1 cycle) 3:0 tM:IDE_CS0#/CS1# to IDE_IOR#/IOW# setup; IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1# I fb i t2 0=1 ,U l t r aD M A Settings for: Ultra DMA Mode 0 = 00921250h Ultra DMA Mode 1 = 00911140h Ultra DMA Mode 2 = 00911030h 30:21 Reserved: Set to 0. 20 DMA Select:DMA operation: 0 = Multiword DMA, 1 = Ultra DMA. 19:16 tCRC: CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS) 15:12 tSS:UDMA out (value + 1 cycle) 11:8 tCYC: Data setup and cycle time UDMA out (value + 2 cycles) 7:4 tRP: Ready to pause time (value + 1 cycle).Note:tRFS + 1 tRP on next clock. 3:0 tACK: IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1# (value + 1 cycle) Offset 28h-2Bh Channel 0 Drive 1 PIO Register (R/W) Reset Value = 0000E132h Channel 0 Drive 1 Programmed I/O Control Register:Refer to F2BAR+I/O Offset 20h for bit descriptions. Offset 2Ch-2Fh Channel 0 Drive 1 DMA Control Register (R/W) Reset Value = 00017771h Channel 0 Drive 1 MDMA/UDMA Control Register:Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. Offset 30h-33h Channel 1 Drive 0 PIO Register (R/W) Reset Value = 0000E132h Channel 1 Drive 0 Programmed I/O Control Register:Refer to F2BAR+I/O Offset 20h for bit descriptions. Offset 34h-37h Channel 1 Drive 0 DMA Control Register (R/W) Reset Value = 00017771h Channel 1 Drive 0 MDMA/UDMA Control Register:Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. Offset 38h-3Bh Channel 1 Drive 1 PIO Register (R/W) Reset Value = 0000E132h Channel 1 Drive 1 Programmed I/O Control Register:Refer to F2BAR+I/O Offset 20h for bit descriptions. Offset 3Ch-3Fh Channel 1 Drive 1 DMA Control Register (R/W) Reset Value = 00017771h Channel 1 Drive 1 MDMA/UDMA Control Register:Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. Table 4-18. F2BAR+I/O Offset xxh: IDE Configuration Registers (Continued) Bit Description

www.national.com 188 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530

4.3.4 XpressAUDIO Registers - Function 3

The register space for XpressAUDIO is divided into two sections. The first section is used to configure the PCI portion of the audio interface hardware. A Base Address Register at F3 Index 10h (F3BAR) points to the base address of where the second portion of the register space is located. This second section contains the control and data registers of the audio interface. Table 4-19 shows the PCI header registers of F3. The memory mapped registers accessed through F3BAR are shown in Table 4-20. Table 4-19. F3 Index xxh: PCI Header Registers for XpressAUDIO Bit Description Index 00h-01h Vendor Identification Register (RO) Reset Value = 1078h Index 02h-03h Device Identification Register (RO) Reset Value = 0103h Index 04h-05h PCI Command Register (R/W) Reset Value = 0000h 15:3 Reserved (Read Only) 1 Memory Space: Allow CS5530 to respond to memory cycles from the PCI bus: 0 = Disable; 1 = Enable. This bit must be enabled to access memory offsets through F3BAR (F3 Index 10h). Index 06h-07h PCI Status Register (RO) Reset Value = 0280h Index 08h Device Revision ID Register (RO) Reset Value = 00h Index 09h-0Bh PCI Class Code Register (RO) Reset Value = 040100h Index 0Ch PCI Cache Line Size Register (RO) Reset Value = 00h Index 0Dh PCI Latency Timer Register (RO) Reset Value = 00h Index 0Eh PCI Header Type (RO) Reset Value =00h Index 0Fh PCI BIST Register (RO) Reset Value = 00h Index 10h-13h Base Address Register - F3BAR (R/W) Reset Value = 00000000h This register sets the base address of the memory mapped audio interface control register block. This is a 128 byte block of registers used to control the audio FIFO and codec interface, as well as to support SMIs produced by VSA technology. Bits [6:0] are read only (0000 0000), indicating a 128 byte memory address range. Refer to Table 4-20 for the bit formats and reset values of the XpressAU- DIO registers. 31:7 Audio Interface Base Address 6:0 Address Range (Read Only) Index 14h-FFh Reserved

Revision 4.1 189 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers Bit Description Offset 00h-03h Codec GPIO Status Register (R/W) Reset Value = 00000000h 31 Codec GPIO Interface:0 = Disable; 1 = Enable. 30 Codec GPIO SMI: Allow codec GPIO interrupt to generate an SMI: 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[1]. 29:21 Reserved: Set to 0. 20 Codec GPIO Status Valid (Read Only):Is the status read valid? 0 = Y es; 1 = No. 19:0 Codec GPIO Pin Status (Read Only):This is the GPIO pin status that is received from the codec in slot 12 on SDATA_IN signal. Offset 04h-07h Codec GPIO Control Register (R/W) Reset Value = 00000000h 31:20 Reserved: Set to 0. 19:0 Codec GPIO Pin Data:This is the GPIO pin data that is sent to the codec in slot 12 on the SDATA_OUT signal. Offset 08h-0Bh Codec Status Register (R/W) Reset Value = 00000000h 31:24 Codec Status Address (Read Only):Address of the register for which status is being returned. This address comes from slot 1 bits [19:12]. 23 Codec Serial INT SMI:Allow codec serial interrupt to generate an SMI: 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[1]. 22 SYNC Pin: Selects SYNC pin level: 0 = Low; 1 = High. 21 Enable SDATA_IN2: Pin AE24 functions as: 0 = GPIO1; 1 = SDATA_IN2. For this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0). 0 = Slot 6; 1 = Slot 11. 0 = Slot 6; 1 = Slot 11. 18 Reserved: Set to 0. 17 Status Tag (Read Only):Determines if the status in bits [15:0] is new or not: 0 = Not new; 1 = New. 16 Codec Status Valid (Read Only):I st h es t a t u si nb i t s[ 1 5 : 0 ]v a l i d ?0=N o ;1=Y e s . 15:0 Codec Status (Read Only):This is the codec status data that is received from the codec in slot 2 on SDATA_IN. Only bits [19:4] are used from slot 2. Offset 0Ch-0Fh Codec Command Register (R/W) Reset Value = 00000000h 31:24 Codec Command Address: Address of the codec control register for which the command is being sent. This address goes in slot 1 bits [19:12] on SDATA_OUT. 23:22 CS5530 Codec Communication: Selects which codec to communicate with: 00 = Primary codec 10 = Third codec 01 = Secondary codec 11 = Fourth codec Note: 00 and 01 are the only valid settings for these bits. 21:17 Reserved: Set to 0. 16 Codec Command Valid: Is the command in bits [15:0] valid? 0 = No; 1 = Y es. This bit is set by hardware when a command is loaded. It remains set until the command has been sent to the codec. 15:0 Codec Command: This is the command being sent to the codec in bits [19:12] of slot 2 on SDATA_OUT.

www.national.com 190 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Offset 10h-11h Second Level Audio SMI Status Mirror Register (RC) Reset Value = 00000000h 15:8 Reserved: Set to 0. 7 Audio Bus Master 5 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 5? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1). 6 Audio Bus Master 4 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 4? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR+Memory Offset 40h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 41h[0] = 1). 5 Audio Bus Master 3 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 3? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1). 4 Audio Bus Master 2 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 2? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1). 3 Audio Bus Master 1 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 1? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1). 2 Audio Bus Master 0 SMI Status (Read to Clear):SMI was caused by an event occurring on Audio Bus Master 0? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1). 1 Codec Serial or GPIO Interrupt SMI Status (Read to Clear):SMI was caused by a serial or GPIO interrupt from codec? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1. SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1. 0 I/O Trap SMI Status (Read to Clear):SMI was caused by an I/O trap? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. Note: Reading this register clears the status bits. Note that bit 0 has another level (third) of SMI status reporting. A read-only “Mirror” version of this register exists at F3BAR+Memory Offset 00h. If the value of the register must be read with- out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead. Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description

Revision 4.1 191 www.national.com Register Descriptions(Continued) Geode™ CS5530 Offset 12h-13h Second Level Audio SMI Status Register (RO) Reset Value = 0000h 15:8 Reserved: Set to 0. 7 Audio Bus Master 5 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 5? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then gen- erated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1). 6 Audio Bus Master 4 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 4? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR+Memory Offset 40h[0] = 1). An SMI is then gen- erated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 41h[0] = 1). 5 Audio Bus Master 3 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 3? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then gen- erated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1). 4 Audio Bus Master 2 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 2? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then gen- erated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1). 3 Audio Bus Master 1 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 1? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then gen- erated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1). 2 Audio Bus Master 0 SMI Status (Read Only):SMI was caused by an event occurring on Audio Bus Master 0? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then gen- erated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1). 1 Codec Serial or GPIO Interrupt SMI Status (Read Only):SMI was caused by a serial or GPIO interrupt from codec? 0=N o ;1=Y e s . This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1. SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1. 0 I/O Trap SMI Status (Read Only):SMI was caused by an I/O trap? 0 = No; 1 = Y es. This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. Note: Reading this register does not clear the status bits. See F3BAR+Memory Offset 10h. Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description

www.national.com 192 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Offset 14h-17h I/O Trap SMI and Fast Write Status Register (RO/RC) Reset Value = 00000000h 31:24 Fast Path Write Even Access Data (Read Only):These bits contain the data from the last Fast Path Write Even access. These bits change only on a fast write to an even address. 23:16 Fast Path Write Odd Access Data (Read Only):These bits contain the data from the last Fast Path Write Odd access. These bits change on a fast write to an odd address, and also on any non-fast write. 15 Fast Write A1 (Read Only):This bit contains the A1 value for the last Fast Write access. 14 Read or Write I/O Access (Read Only):Last trapped I/O access was a read or a write? 0 = Read; 1 = Write. 13 Sound Card or FM Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the Sound Card or FM I/O Trap? 0 = No; 1 = Y es. (Note) Fast Path Write must be enabled, F3BAR+Memory Offset 18h[11] = 1, for the SMI to be reported here. If Fast Path Write is disabled, the SMI is reported in bit 10 of this register. This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[2]. 12 DMA Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the DMA I/O Trap? 0=N o ;1=Y e s .( N o t e ) This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[8:7]. 11 MPU Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the MPU I/O Trap? 0=N o ;1=Y e s .( N o t e ) This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[6:5]. 10 Sound Card or FM Trap SMI Status (Read to Clear):SMI was caused by a trapped I/O access to the Sound Card or FM I/O Trap? 0 = No; 1 = Y es. (Note) Fast Path Write must be disabled, F3BAR+Memory Offset 18h[11] = 0, for the SMI to be reported here. If Fast Path Write is enabled, the SMI is reported in bit 13 of this register. This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[2]. 9:0 X-Bus Address (Read Only):Bits [9:0] contain the captured ten bits of X-Bus address. Note: For the four SMI status bits (bits [13:10]), if the activity was a fast write to an even address, no SMI is generated regardless of the DMA, MPU, or Sound Card status. If the activity was a fast write to an odd address, an SMI is generated but bit 13 is set to a1 . Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description

Revision 4.1 193 www.national.com Register Descriptions(Continued) Geode™ CS5530 Offset 18h-19h I/O Trap SMI Enable Register (R/W) Reset Value = 0000h 15:12 Reserved: Set to 0. 11 Fast Path Write Enable:Fast Path Write (an SMI is not generated on certain writes to specified addresses): 0 = Disable; 1 = Enable. In Fast Path Write, the CS5530 responds to writes to the following addresses: 388h, 38Ah and 38B; 2x0h, 2x2h, and 2x8h. 10:9 Fast Read:These two bits hold part of the response that the CS5530 returns for reads to several I/O locations. 8 High DMA I/O Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port C0h-DFh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12]. 7 Low DMA I/O Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 00h-0Fh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12]. 6 High MPU I/O Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 330h and 331h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11]. 5 Low MPU I/O Trap:I0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 300h and 301h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11]. 4 Fast Path Read Enable/SMI Disable:Read Fast Path (an SMI is not generated on reads from specified addresses): 0 = Disable; 1 = Enable. In Fast Path Read the CS5530 responds to reads of the following addresses: 388h-38Bh; 2x0h, 2x1, 2x2h, 2x3, 2x8 and 2x9h. Note that if neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible. 3 FM I/O Trap:0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 388h to 38Bh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. If this bit is enabled and an access occurs in the address ranges selected by bits [1:0], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[10]. 1:0 Sound Card Address Range Select:These bits select the address range for the sound card I/O trap. 00 = I/O Port 220h-22Fh 10 = I/O Port 260h-26Fh 01 = I/O Port 240h-24Fh 11 = I/O Port 280h-28Fh Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description

www.national.com 194 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Offset 1Ah-1Bh Internal IRQ Enable Register (R/W) Reset Value = 0000h Note: Must be R/W as a WORD. 15 IRQ15 Internal:Configure IRQ15 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 14 IRQ14 Internal:Configure IRQ14 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 13 Reserved: Set to 0. 12 IRQ12 Internal:Configure IRQ12 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 11 IRQ11 Internal:Configure IRQ11 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 10 IRQ10 Internal:Configure IRQ10 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 9 IRQ9 Internal:Configure IRQ9 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 8 Reserved: Set to 0. 7 IRQ7 Internal:Configure IRQ7 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 6 Reserved: Set to 0. 5 IRQ5 Internal:Configure IRQ5 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 4 IRQ4 Internal:Configure IRQ4 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 3 IRQ3 Internal:Configure IRQ3 for internal (software) or external (hardware) use: 0 = External; 1 = Internal. 2:0 Reserved: Set to 0. Note: This register must be read and written as a WORD. Offset 1Ch-1Dh Internal IRQ Control Register (R/W) Reset Value = 00000000h 15 Assert Masked Internal IRQ15:0 = Disable; 1 = Enable. 14 Assert Masked Internal IRQ14:0 = Disable; 1 = Enable. 13 Reserved: Set to 0. 12 Assert Masked Internal IRQ12:0 = Disable; 1 = Enable. 11 Assert masked internal IRQ11:0 = Disable; 1 = Enable. 10 Assert Masked Internal IRQ10:0 = Disable; 1 = Enable. 9 Assert Masked Internal IRQ9:0 = Disable; 1 = Enable. 8 Reserved: Set to 0. 7 Assert Masked Internal IRQ7:0 = Disable; 1 = Enable. 6 Reserved: Set to 0. 5 Assert Masked Internal IRQ5:0 = Disable; 1 = Enable. 4 Assert Masked Internal IRQ4:0 = Disable; 1 = Enable. 3 Assert Masked Internal IRQ3:0 = Disable; 1 = Enable. 2:0 Reserved: Set to 0. Offset 1Eh-1Fh Internal IRQ Mask Register (Write Only) Reset Value = 00000000h 15 Mask Internal IRQ15:0 = Disable; 1 = Enable. 14 Mask Internal IRQ14:0 = Disable; 1 = Enable. 13 Reserved: Set to 0. 12 Mask Internal IRQ12:0 = Disable; 1 = Enable. 11 Mask Internal IRQ11:0 = Disable; 1 = Enable. 10 Mask Internal IRQ10:0 = Disable; 1 = Enable. 9 Mask Internal IRQ9:0 = Disable; 1 = Enable. 8 Reserved: Set to 0. 7 Mask Internal IRQ7:0 = Disable; 1 = Enable. 6 Reserved: Set to 0. 5 Mask Internal IRQ5:0 = Disable; 1 = Enable. 4 Mask Internal IRQ4:0 = Disable; 1 = Enable. 3 Mask Internal IRQ3:0 = Disable; 1 = Enable. 2:0 Reserved: Set to 0. Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description

Revision 4.1 195 www.national.com Register Descriptions(Continued) Geode™ CS5530 Offset 20h Audio Bus Master 0 Command Register (R/W) Reset Value = 00h Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 Reserved: Set to 0. Must return 0 on reads.

3 Read or Write Control:Set the transfer direction of Audio Bus Master 0: 0 = PCI reads performed;

1 = PCI writes performed. This bit must be set to 0 (read) and should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the Audio Bus Master 0: 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must either be paused or reach EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior; including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Offset 21h Audio Bus Master 0 SMI Status Register (RC) Reset Value = 00h Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 Reserved (Read to Clear) 1 Bus Master Error (Read to Clear):Hardware encountered a second EOP before software has cleared the first? 0=N o ;1=Y e s . If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear):Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0=N o ;1=Y e s . Note: Must be read and written as a BYTE. Offset 22h-23h Not Used Offset 24h-27h Audio Bus Master 0 PRD Table Address (R/W) Reset Value = 00000000h Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for Audio Bus Master 0. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 0 is enabled (Command Regis- ter bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Offset 28h Audio Bus Master 1 Command Register (R/W) Reset Value = 00h Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 Reserved: Set to 0. Must return 0 on reads.

3 Read or Write Control:Set the transfer direction of Audio Bus Master 1: 0 = PCI reads performed;

1 = PCI writes performed. This bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the Audio Bus Master 1: 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description

www.national.com 196 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Offset 29h Audio Bus Master 1 SMI Status Register (RC) Reset Value = 00h Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:2 Reserved (Read to Clear) 1 Bus Master Error (Read to Clear):Hardware encountered a second EOP before software has cleared the first? 0=N o ;1=Y e s . If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear):Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0=N o ;1=Y e s . Note: Must be read and written as a BYTE. Offset 2Ah-2Bh Not Used Offset 2Ch-2Fh Audio Bus Master 1 PRD Table Address (R/W) Reset Value = 00000000h Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for Audio Bus Master 1. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 1 is enabled (Command Regis- ter bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Offset 30h Audio Bus Master 2 Command Register (R/W) Reset Value = 00h Audio Bus Master 2: Output to Codec; 16-Bit; Slot 5. 7:4 Reserved: Set to 0. Must return 0 on reads.

3 Read or Write Control:Set the transfer direction of Audio Bus Master 2: 0 = PCI reads performed;

1 = PCI writes performed. This bit must be set to 0 (read) and should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the Audio Bus Master 2: 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Offset 31h Audio Bus Master 2 SMI Status Register (RC) Reset Value = 00h Audio Bus Master 2: Output to Codec; 16-Bit; Slot 5. 7:4 Reserved (Read to Clear) 1 Bus Master Error (Read to Clear):Hardware encountered a second EOP before software has cleared the first? 0=N o ;1=Y e s . If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear):Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0=N o ;1=Y e s . Note: Must be read and written as a BYTE. Offset 32h-33h Not Used Offset 34h-37h Audio Bus Master 2 PRD Table Address (R/W) Reset Value = 00000000h Audio Bus Master 2: Output to Codec; 16-Bit; Slot 5. 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for Audio Bus Master 2. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 2 is enabled (Command Regis- ter bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description

Revision 4.1 197 www.national.com Register Descriptions(Continued) Geode™ CS5530 Offset 38h Audio Bus Master 3 Command Register (R/W) Reset Value = 00h Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5. 7:4 Reserved: Set to 0. Must return 0 on reads.

3 Read or Write Control:Set the transfer direction of Audio Bus Master 3: 0 = PCI reads performed;

1 = PCI writes performed. This bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the Audio Bus Master 3: 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Offset 39h Audio Bus Master 3 SMI Status Register (RC) Reset Value = 00h Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5. 7:4 Reserved (Read to Clear) 1 Bus Master Error (Read to Clear):Hardware encountered a second EOP before software has cleared the first? 0=N o ;1=Y e s . If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear):Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0=N o ;1=Y e s . Note: Must be read and written as a BYTE. Offset 3Ah-3Bh Not Used Offset 3Ch-3Fh Audio Bus Master 3 PRD Table Address (R/W) Reset Value = 00000000h Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5. 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for Audio Bus Master 3. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 3 is enabled (Command Regis- ter bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Offset 40h Audio Bus Master 4 Command Register (R/W) Reset Value = 00h Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot). 7:4 Reserved: Set to 0. Must return 0 on reads.

3 Read or Write Control:Set the transfer direction of Audio Bus Master 4: 0 = PCI reads performed;

1 = PCI writes performed. This bit must be set to 0 (read) and should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the Audio Bus Master 4: 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description

www.national.com 198 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Offset 41h Audio Bus Master 4 SMI Status Register (RC) Reset Value = 00h Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot). 7:4 Reserved (Read to Clear) 1 Bus Master Error (Read to Clear):Hardware encountered a second EOP before software has cleared the first? 0=N o ;1=Y e s . If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear):Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0=N o ;1=Y e s . Note: Must be read and written as a BYTE. Offset 42h-43h Not Used Offset 44h-47h Audio Bus Master 4 PRD Table Address (R/W) Reset Value = 00000000h Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot). 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for Audio Bus Master 4. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 4 is enabled (Command Regis- ter bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Offset 48h Audio Bus Master 5 Command Register (R/W) Reset Value = 00h Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot). 7:4 Reserved: Set to 0. Must return 0 on reads.

3 Read or Write Control:Set the transfer direction of Audio Bus Master 5: 0 = PCI reads performed;

1 = PCI writes performed. This bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control:Controls the state of the Audio Bus Master 5: 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Offset 49h Audio Bus Master 5 SMI Status Register (RC) Reset Value = 00h Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot). 7:4 Reserved (Read to Clear) 1 Bus Master Error (Read to Clear):Hardware encountered a second EOP before software has cleared the first? 0=N o ;1=Y e s . If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear):Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0=N o ;1=Y e s . Note: Must be read and written as a BYTE. Offset 4Ah-4Bh Not Used Offset 4Ch-4Fh Audio Bus Master 5 PRD Table Address (R/W) Reset Value = 00000000h Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot). 31:2 Pointer to the Physical Region Descriptor Table:This register is a PRD table pointer for Audio Bus Master 5. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 5 is enabled (Command Regis- ter bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description

Revision 4.1 199 www.national.com Register Descriptions(Continued) Geode™ CS5530

4.3.5 Video Controller Registers - Function 4

The register space for the video controller is divided into two sections. The first section is used to configure the PCI portion of the controller. A Base Address Register at F4 Index 10h (F4BAR) points to the base address of where the second portion of the register space is located. The second section contains the registers used by the video controller to carry out video operations. Table 4-21 shows the PCI header registers of F4. The memory mapped registers accessed through F4BAR, and shown in Table 4-22, must be accessed using DWORD operations. When writing to one of these 32-bit registers, all four bytes must be written. Table 4-21. F4 Index xxh: PCI Header Registers for Video Controller Configuration Bit Description Index 00h-01h Vendor Identification Register (RO) Reset Value = 1078h Index 02h-03h Device Identification Register (RO) Reset Value = 0104h Index 04h-05h PCI Command Register (R/W) Reset Value = 0000h 15:2 Reserved (Read Only) 1 Memory Space: Allow CS5530 to respond to memory cycles from the PCI bus: 0 = Disable; 1 = Enable. This bit must be enabled to access memory offsets through F4BAR (F4 Index 10h). Index 06h-07h PCI Status Register (RO) Reset Value = 0280h Index 08h Device Revision ID Register (RO) Reset Value = 00h Index 09h-0Bh PCI Class Code Register (RO) Reset Value = 030000h Index 0Ch PCI Cache Line Size Register (RO) Reset Value = 00h Index 0Dh PCI Latency Timer Register (RO) Reset Value = 00h Index 0Eh PCI Header Type (RO) Reset Value = 00h Index 0Fh PCI BIST Register (RO) Reset Value = 00h Index 10h-13h Base Address Register - F4BAR (R/W) Reset Value = 00000000h This register sets the base address of the memory mapped video controller registers. Bits [11:0] are read only (0000 0000 0000), indi- cating a 4 KB memory address range. Refer to Table 4-22 for the video controller register bit formats and reset values. 31:12 Video Controller and Clock Control Base I/O Address 11:0 Address Range (Read Only) Index 14h-FFh Reserved

www.national.com 200 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Table 4-22. F4BAR+Memory Offset xxh: Video Controller Configuration Registers Bit Description Offset 00h-03h Video Configuration Register (R/W) Reset Value = 00000000h 30 High Speed Timing for Video Interface:High speed timings for the video interface: 0 = Disable; 1= Enable. If bit 30 is enabled, bit 25 should be set to 0. 29 16-bit Video Interface:Allow video interface to be 16 bits: 0 = Disable; 1= Enable. If bit 29 is enabled, 8 bits of pixel data is used for video. The 24-bit pixel data is then dithered to 16 bits. Note: F4BAR+Memory Offset 04h[25] should be set to the same value as this bit (bit 29). 28 YUV 4:2:2 or 4:2:0 Mode:0 = 4:2:2 Mode; 1= 4:2:0 Mode. If 4:2:0 mode is selected, bits [3:2] should be set to 01 if in 8-bit video mode and 10 if in 16-bit video mode. Note: The GXLV processor does not support 4:2:0 mode. 27 Video Line Size (DWORDs):This is the MSB of the Video Line Size (DWORDs). See bits [15:8] for description. 25 Early Video Ready:Generate VID_RDY output signal one-half VID_CLK period early to improve the speed of the video port operation: 0 = Disable; 1 = Enable. If bit 30 is enabled, this bit (bit 25) should be set to 0. 24 Initial Buffer Read Address:This is the MSB of the Initial Buffer Read Address. See bits [23:16] for description. 23:16 Initial Buffer Read Address:This field is used to preload the starting read address for the line buffers at the beginning of each display line. It is used for hardware clipping of the video window at the left edge of the active display. It represents the DWORD address of the source pixel which is to be displayed first. For an unclipped window, this value should be 0. 15:8 Video Line Size (DWORDs):This field represents the horizontal size of the source video data in DWORDs. 7 YF i l t e rE n a b l e :Vertical filter: 0 = Disable; 1= Enable. 6 XF i l t e rE n a b l e :Horizontal filter: 0 = Disable; 1 = Enable. 5 CSC Bypass: Allows color-space-converter to be bypassed. Primarily used for displaying an RGB graphics overlay rather than a YUV video overlay. 0 = Overlay data passes through CSC; 1 = Overlay data bypasses CSC. 0 = Video data; 1 = Graphics data. 3:2 Video Input Format:This field defines the byte ordering of the video data on the VID_DATA bus. 8-Bit Mode (Value Byte Order [0:3]) 16-Bit Mode (Value Byte Order [0:3]) 00 = U Y0 V Y1 (also used for RGB 5:6:5 input) 00 = U Y0 V Y1 (also used for RGB 5:6:5 input) 01 = Y1 V Y0 U or 4:2:0 01 = Y0 U Y1 V 10 = Y0 U Y1 V 10 = Y1 V Y0 U or 4:2:0 11 = Y0 V Y1 U 11 = Reserved If bit 28 is enabled, these bits (bits [3:2]) should be set to 01 if in 8-bit video mode and 10 if in 16-bit video mode. Note: U=C b ,V=C r 1 Video Register Update:Allow video position and scale registers to be updated simultaneously on next occurrence of vertical sync: 0 = Disable; 1 = Enable. 0 Video Enable:Video acceleration hardware: 0 = Disable; 1 = Enable. Offset 04h-07h Display Configuration Register (R/W) Reset Value = 00000000h 31 DDC Input Data (Read Only):This is the DDC input data bit for reads. 30 Red Comparator (Read Only):This is the value of the red video DAC comparator. 29 Green Comparator (Read Only):This is the value of the green video DAC comparator. 28 Blue Comparator (Read Only):This is the value of the blue video DAC comparator. 27 Flat Panel On (Read Only):This bit indicates whether the attached flat panel display is powered on or off. The bit transi- tions at the end of the power-up or power-down sequence. 0 = Off; 1 = On. 26 DAC External Voltage Reference Enable:This bit enables the use of an external voltage reference for the video DAC. When enabled, an external voltage reference should be connected to the EXTVREFIN pin. When disabled, the DAC inter- nal voltage reference will be used. 0 = Disable; 1 = Enable. 25 16-Bit Graphics Enable:This bit works in conjunction with the 16-bit Video Interface bit at F4BAR+Memory Offset 00h[29]. This bit should be set to the same value as the 16-bit Video Interface bit. 24 DDC Output Enable:This bit enables the DDC_SDA line to be driven for write data. 0 = DDC_SDA pin is input; 1 = DDC_SDA pin is output. 23 DDC Output Data:This is the DDC data bit.

Revision 4.1 201 www.national.com Register Descriptions(Continued) Geode™ CS5530 22 DDC Clock: This is the DDC clock bit. It is used to clock the DDC_SDA bit. 0 = Video data; 1 = Graphics data. 20 Video/Graphics Color Key Select:Selects whether the video or graphics data stream will be used for color/chroma key- ing. 0 = Graphics data is compared to color key; 1 = Video data is compared to color key. 19:17 Power Sequence Delay:This field selects the number of frame periods that transpire between successive transitions of the power sequence control lines. Valid values are 001h to 111h. 16:14 CRT Sync Skew: This 3-bit field represents the number of pixel clocks to skew the horizontal and vertical syncs that are sent to the CRT. This field should be programmed to 100 as the baseline. The syncs may be moved forward or backward relative to the pixel data via this register. It is used to compensate for the pipeline delay through the graphics pipeline. 13 Flat Panel Dither Enable:This bit enables flat panel dithering. It enables 24 bpp display data to be approximated with an 18-bit flat panel display. 0 = Disable; 1 = Enable. 12 XGA Flat Panel:This bit enables the FP_CLK_ EVEN output signal which can be used to demultiplex the FP_DATA bus into even and odd pixels. 0 = Standard flat panel; 1 = XGA flat panel. 0 = FP vertical sync is normally low, transitioning high during sync interval. 1 = FP vertical sync is normally high, transitioning low during sync interval. 0 = FP horizontal sync is normally low, transitioning high during sync interval. 1 = FP horizontal sync is normally high, transitioning low during sync interval. 0 = CRT vertical sync is normally low, transitioning high during sync interval. 1 = CRT vertical sync is normally high, transitioning low during sync interval. 0 = CRT horizontal sync is normally low, transitioning high during sync interval. 1 = CRT horizontal sync is normally high, transitioning low during sync interval. 0 = FP_DATA [17:0] is forced low; 1 = FP_DATA [17:0] is driven based upon power sequence control. 6 Flat Panel Power Enable:The transition of this bit initiates a flat panel power-up or power-down sequence: 0 -> 1 = Power-up flat panel; 1 -> 0 = Power-down flat panel. 5 DAC Power-down (active low):This bit must be set to power-up the video DACs. It can be cleared to power-down the video DACs when not in use. 0 = DACs are powered down; 1 = DACs are powered up. 4 Reserved: Set to 0. 3 DAC Blank Enable:This bit enables the blank to the video DACs. 0 = DACs are constantly blanked; 1 = DACs are blanked normally. 2 CRT Vertical Sync Enable:Enables the CRT vertical sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable. 1 CRT Horizontal Sync Enable:Enables the CRT horizontal sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable. 0 Display Enable:Enables the graphics display pipeline. It is used as a reset for the display control logic. 0 = Reset display control logic; 1 = Enable display control logic Offset 08h-0Bh Video X Register (R/W) Reset Value = xxxxxxxxh 31:27 Reserved: Set to 0. 26:16 V i d e oXE n dP o s i t i o n :This field represents the horizontal end position of the video window according to the following formula: Position programmed = screen position + (H_TOTAL – H_SYNC_END) – 13. 15:11 Reserved: Set to 0. 10:0 Video X Start Position:This field represents the horizontal start position of the video window according to the following formula: Position programmed = screen position + (H_TOTAL – H_SYNC_END) – 13. Table 4-22. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued) Bit Description

www.national.com 202 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Offset 0Ch-0Fh Video Y Register (R/W) Reset Value = xxxxxxxxh 31:27 Reserved: Set to 0. 26:16 V i d e oYE n dP o s i t i o n :This field represents the vertical end position of the video window according to the following for- mula: Position programmed = screen position + (V_TOTAL – V_SYNC_END) + 1. 15:11 Reserved: Set to 0. 10:0 Video Y Start Position:This field represents the vertical start position of the video window according to the following for- mula: Position programmed = screen position + (V_TOTAL – V_SYNC_END) + 1. Offset 10h-13h Video Scale Register (R/W) Reset Value = xxxxxxxxh 31:30 Reserved: Set to 0. 29:16 Video Y Scale Factor:This field represents the video window vertical scale factor according to the following formula: VID_Y_SCL = 8192 * (Ys - 1) / (Yd - 1) Where: Ys = Video Source vertical size in lines Yd = Video Destination vertical size in lines 15:14 Reserved: Set to 0. 13:0 Video X Scale Factor:This field represents the video window horizontal scale factor according to the following formula: VID_X_SCL = 8192 * (Xs - 1) / (Xd - 1) Where: Xs = Video Source horizontal size in pixels Xd = Video Destination horizontal size in pixels Offset 14h-17h Video Color Key Register (R/W) Reset Value = xxxxxxxxh 31:24 Reserved: Set to 0. 23:0 Video Color Key:This field represents the video color key. It is a 24-bit RGB value. The graphics or video data being compared may be masked prior to the compare by programming the Video Color Mask Register (F4BAR+Memory Offset 18h) appropriately. Offset 18h-1Bh Video Color Mask Register (R/W) Reset Value = xxxxxxxxh 31:24 Reserved: Set to 0. 23:0 Video Color Mask:This field represents the video color mask. It is a 24-bit RGB value. Zeroes in the mask cause the corresponding bits in the graphics or video stream being compared to be ignored. Offset 1Ch-1Fh Palette Address Register (R/W) Reset Value = xxxxxxxxh 31:8 Reserved: Set to 0. 7:0 Palette Address:The value programmed is used to initialize the palette address counter. Offset 20h-23h Palette Data Register (R/W) Reset Value = xxxxxxxxh 31:24 Reserved: Set to 0. 23:0 Palette Data:This register contains the read or write data for a Gamma RAM access. Offset 24h-27h DOT Clock Configuration Register (R/W) Reset Value = 00000000h 30 Half Clock:0 = Enable; 1 = Disable. For odd post divisors, half clock enables the falling edge of the VCO clock to be used to generate the falling edge of the post divider output to more closely approximate a 50% output duty cycle. 29 Reserved: Set to 0. Table 4-22. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued) Bit Description

Revision 4.1 203 www.national.com Register Descriptions(Continued) Geode™ CS5530 28:24 5-Bit DCLK PLL Post Divisor (PD) Value:Selects value of 1 to 31: 00000 = PD divisor of 8 01000 = PD divisor of 10 10000 = PD divisor of 9 11000 = PD divisor of 11 00001 = PD divisor of 6 01001 = PD divisor of 20 10001 = PD divisor of 7 11001 = PD divisor of 21 00010 = PD divisor of 18 01010 = PD divisor of 14 10010 = PD divisor of 19 11010 = PD divisor of 15 00011 = PD divisor of 4 01011 = PD divisor of 26 10011 = PD divisor of 5 11011 = PD divisor of 27 00100 = PD divisor of 12 01100 = PD divisor of 22 10100 = PD divisor of 13 11100 = PD divisor of 23 00101 = PD divisor of 16 01101 = PD divisor of 28 10101 = PD divisor of 17 11101 = PD divisor of 29 00110 = PD divisor of 24 01110 = PD divisor of 30 10110 = PD divisor of 25 11110 = PD divisor of 31 00111 = PD divisor of 2 01111 = PD divisor of 1* 10111 = PD divisor of 3 11111 = RSVD *See bit 11 description. 0=A d d0t oF D ;1=A d d1t oF D 22:12 N: This bit represents “N” in the equation (see Note). It is used to solve the value of FD (DCLK PLL VCO Feedback Divi- sor). N can be a value of 1 to 400. For all values of N, refer to Table 4-23. CLK_ON: 0 = PLL disable; 1 = PLL enable. If PD = 1 (i.e., bits [28:24] = 01111) the PLL is always enabled. 10 DOT Clock Select:0 = DCLK; 1 = TV_CLK. 9 Select Feedback Source:0 = DPLL; 1 = FREF . 8 Bypass PLL: Connects the input of the PLL directly to the output of the PLL: 0 = Normal Operation; 1 = Bypass PLL. If this bit is set to 1, the input of the PLL bypasses the PLL and resets the VCO control voltage, which in turn powers down the PLL. Allow 0.5 ms for the control voltage to be driven to 0V. 7:6 Reserved: Set to 0. 5 PLL Lock Indictor:0 = PLL has not locked on frequency; 1 = PLL has locked on frequency. 4:3 Reserved: Set to 0. 2:0 PLL Input Divide (ID) Value:Selects value of 2 to 9 (see Note): 000 = ID divisor of 2 100 = ID divisor of 6 001 = ID divisor of 3 101 = ID divisor of 7 010 = ID divisor of 4 110 = ID divisor of 8 011 = ID divisor of 5 111 = ID divisor of 9 Note: To calculate DCLK output frequency: Equation #1: DCLK = [CLK_14MHZ * FD] ÷ [PD *ID] Condition: 140 MHz < [DCLK * PD] < 300 MHz Where: CLK_14MHZ is pin P24 FD is derived from N see equation #2 and #3: PD is derived from bits [28:24] ID is derived from bits [2:0] Equation #2: If FD is an odd number then: FD = 2*N +1 Equation #3: If FD is an even number then: FD = 2*N +0 Where: N is derived from bits [22:12] +1 is achieved by setting bit 23 to 1. +0 s achieved by clearing bit 23 to 0. Table 4-22. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued) Bit Description

www.national.com 204 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Offset 28h-2Bh CRC Signature and TFT/TV Configuration Register (R/W) Reset Value = 00000100h 31:8 24-Bit Video Signature Data (Read Only)

7 SYNC Override:Drive VSYNC_OUT on FP_VSYNC_OUT and HSYNC_OUT on FP_HSYNC_OUT:

0 = Disable; 1 = Enable. 6 Invert FP_CLK:0 = Disable; 1 = Enable. (Applicable for TV not TFT.) 5 Invert FP_CLK_EVEN: 0 = Disable; 1 = Enable. 4:3 Reserved (Read Only) 2 Signature Free Run:0 = Disable; 1 = Enable. When high, with the signature enabled, the signature generator captures data continuously across multiple frames. This bit may be set high when the signature is started, then later set low, which causes the signature generation process to stop at the end of the current frame. 1 FP_HSYNC_OUT Delay: 0 = Disable; 1 = Enable. (Applicable for TFT not TV.) When SYNC Override (bit 7) is high, this bit (bit 1) can be set high to delay FP_HSYNC_OUT by an extra two clock cycles. When the SYNC Override (bit 7) is low, this bit should also be set low. 0 Signature Enable:0 = Disable; 1= Enable. When low the signature register is reset to 000001h and held (no capture). When high, the signature register captures the pixel data signature with each pixel clock beginning with the next vsync. Table 4-22. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued) Bit Description

Revision 4.1 205 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-23.F4BAR+Memory Offset 24h[22:12] Decode (Value of “N”) N Reg. Value 400 33A 399 674 398 4E8 397 1D0 396 3A0 395 740 394 681 393 502 392 205 391 40B 390 16 389 2D 388 5B 387 B7 386 16F 385 2DE 384 5BD 383 37B 382 6F6 381 5EC 380 3D9 379 7B2 378 765 377 6CB 376 596 375 32D 374 65A 373 4B4 372 168 371 2D0 370 5A1 369 343 368 686 367 50C 366 219 365 433 364 66 363 CD 362 19B 361 336 360 66C 359 4D8 358 1B0 357 360 356 6C0 355 580 354 301 353 602 352 404 351 8 350 11 349 23 348 47 347 8F 346 11F 345 23E 344 47D 343 FA 342 1F5 341 3EA 340 7D4 339 7A9 338 753 337 6A7 336 54E 335 29D 334 53B 333 277 332 4EF 331 1DE 330 3BC 329 778 328 6F1 327 5E2 326 3C5 325 78A 324 715 323 62B 322 456 321 AC 320 159 319 2B2 318 565 317 2CB 316 597 315 32F 314 65E 313 4BC 312 178 311 2F0 310 5E1 309 3C3 308 786 307 70D 306 61B 305 436 304 6C 303 D9 302 1B3 301 366 300 6CC 299 598 N Reg. Value 298 331 297 662 296 4C4 295 188 294 310 293 620 292 440 291 80 290 101 289 202 288 405 287 A 286 15 285 2B 284 57 283 AF 282 15F 281 2BE 280 57D 279 2FB 278 5F7 277 3EF 276 7DE 275 7BD 274 77B 273 6F7 272 5EE 271 3DD 270 7BA 269 775 268 6EB 267 5D6 266 3AD 265 75A 264 6B5 263 56A 262 2D5 261 5AB 260 357 259 6AE 258 55C 257 2B9 256 573 255 2E7 254 5CF 253 39F 252 73E 251 67D 250 4FA 249 1F4 248 3E8 N Reg. Value 247 7D0 246 7A1 245 743 244 687 243 50E 242 21D 241 43B 240 76 239 ED 238 1DB 237 3B6 236 76C 235 6D9 234 5B2 233 365 232 6CA 231 594 230 329 229 652 228 4A4 227 148 226 290 225 521 224 243 223 487 222 10E 221 21C 220 439 219 72 218 E5 217 1CB 216 396 215 72C 214 659 213 4B2 212 164 211 2C8 210 591 209 323 208 646 207 48C 206 118 205 230 204 461 203 C2 202 185 201 30A 200 614 199 428 198 50 197 A1 N Reg. Value 196 143 195 286 194 50D 193 21B 192 437 191 6E 190 DD 189 1BB 188 376 187 6EC 186 5D8 185 3B1 184 762 183 6C5 182 58A 181 315 180 62A 179 454 178 A8 177 151 176 2A2 175 545 174 28B 173 517 172 22F 171 45F 170 BE 169 17D 168 2FA 167 5F5 166 3EB 165 7D6 164 7AD 163 75B 162 6B7 161 56E 160 2DD 159 5BB 158 377 157 6EE 156 5DC 155 3B9 154 772 153 6E5 152 5CA 151 395 150 72A 149 655 148 4AA 147 154 146 2A8 N Reg. Value 145 551 144 2A3 143 547 142 28F 141 51F 140 23F 139 47F 138 FE 137 1FD 136 3FA 135 7F4 134 7E9 133 7D3 132 7A7 131 74F 130 69F 129 53E 128 27D 127 4FB 126 1F6 125 3EC 124 7D8 123 7B1 122 763 121 6C7 120 58E 119 31D 118 63A 117 474 116 E8 115 1D1 114 3A2 113 744 112 689 111 512 110 225 109 44B 108 96 107 12D 106 25A 105 4B5 104 16A 103 2D4 102 5A9 101 353 100 6A6 99 54C 98 299 97 533 96 267 95 4CF N Reg. Value 94 19E 93 33C 92 678 91 4F0 90 1E0 89 3C0 88 780 87 701 86 603 85 406 84 C 83 19 82 33 81 67 80 CF 79 19F 78 33E 77 67C 76 4F8 75 1F0 74 3E0 73 7C0 72 781 71 703 70 607 69 40E 68 1C 67 39 66 73 65 E7 64 1CF 63 39E 62 73C 61 679 60 4F2 59 1E4 58 3C8 57 790 56 721 55 643 54 486 53 10C 52 218 51 431 50 62 49 C5 48 18B 47 316 46 62C 45 458 44 B0 N Reg. Value 43 161 42 2C2 41 585 40 30B 39 616 38 42C 37 58 36 B1 35 163 34 2C6 33 58D 32 31B 31 636 30 46C 29 D8 28 1B1 27 362 26 6C4 25 588 24 311 23 622 22 444 21 88 20 111 19 222 18 445 17 8A 16 115 15 22A 14 455 13 AA 12 155 11 2AA 10 555 9 2AB 8 557 7 2AF 6 55F 5 2BF 4 57F 3 2FF 2 5FF 1 3FF N Reg. Value

www.national.com 206 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530

4.4 USB CONTROLLER REGISTERS - PCIUSB

The registers designated as PCIUSB are 32-bit registers decoded from the PCI address bits 7 through 2 and C/BE[3:0]#, when IDSEL is high, AD[10:8] select the appropriate function, and AD[1:0] are '00'. Bytes within a 32-bit address are selected with the valid byte enables. All registers can be accessed via 8-, 16-, or 32-bit cycles (i.e., each byte is individually selected by the byte enables.) Registers marked as reserved, and reserved bits within a register are not implemented and should return 0s when read. Writes have no effect for reserved r e g i s t e r s .T a b l e4 - 2 4g i v e st h eb i tf o r m a t sf o rt h eU S B controller’s PCI configuration registers. Table 4-24. PCIUSB Index xxh: USB Controller Registers Bit Description Index 00h-01h Vendor Identification Register (RO) Reset Value = 0E11h Index 02h-03h Device Identification Register (RO) Reset Value = A0F8h Index 04h-05h Command Register (R/W) Reset Value = 0000h 15:10 Reserved: Set to 0. 9 Fast Back-to-Back Enable (Read Only):USB only acts as a master to a single device, so this functionality is not needed. It is always disabled (must always be set to 0). 8 SERR#: USB asserts SERR# when it detects an address parity error: 0 = Disable; 1 = Enable. 7 Wait Cycle Control:USB does not need to insert a wait state between the address and data on the AD lines. It is always disabled (bit is set to 0). 6 Parity Error:USB asserts PERR# when it is the agent receiving data and it detects a data parity error: 0 = Disable; 1 = Enable. 5 VGA Palette Snoop Enable (Read Only):USB does not support this function. It is always disabled (bit is set to 0). 4 Memory Write and Invalidate:Allow USB to run Memory Write and Invalidate commands: 0 = Disable; 1 = Enable. The Memory Write and Invalidate Command will only occur if the cacheline size is set to 32 bytes and the memory write is exactly one cache line. If the CS5530 is being used in a GXLV processor based system, this bit must be set to 0. 3 Special Cycles:USB does not run special cycles on PCI. It is always disabled (bit is set to 0). 2 PCI Master Enable:Allow USB to run PCI master cycles: 0 = Disable; 1 = Enable. 1 Memory Space: Allow USB to respond as a target to memory cycles: 0 = Disable; 1 = Enable. 0 I/O Space:Allow USB to respond as a target to I/O cycles: 0 = Disable; 1 = Enable. Index 06h-07h Status Register (R/W) Reset Value = 0280h 15 Detected Parity Error:This bit is set whenever the USB detects a parity error, even if the Parity Error (Response) Detec- tion Enable Bit (Command Register, bit 6) is disabled. Write 1 to clear. 14 SERR# Status:This bit is set whenever the USB detects a PCI address error. Write 1 to clear. 13 Received Master Abort Status:This bit is set when the USB, acting as a PCI master, aborts a PCI bus memory cycle. Write 1 to clear. 12 Received Target Abort Status:This bit is set when a USB generated PCI cycle (USB is the PCI master) is aborted by a PCI target. Write 1 to clear. 11 Signaled Target Abort Status:This bit is set whenever the USB signals a target abort. Write 1 to clear. 10:9 DEVSEL# Timing (Read Only):These bits indicate the DEVSEL# timing when performing a positive decode. Since DEVSEL# is asserted to meet the medium timing, these bits are encoded as 01b. 8 Data Parity Reported:Set to 1 if the Parity Error Response bit (Command Register bit 6) is set, and USB detects PERR# asserted while acting as PCI master (whether PERR# was driven by USB or not). 7 Fast Back-to-Back Capable:USB does support fast back-to-back transactions when the transactions are not to the same agent. This bit is always 1. 6:0 Reserved: Set to 0. Note: The PCI Specification defines this register to record status information for PCI related events. This is a read/write register. However, writes can only reset bits. A bit is reset whenever the register is written and the data in the corresponding bit location is a 1. Index 08h Device Revision ID Register (RO) Reset Value = 00h

Revision 4.1 207 www.national.com Register Descriptions(Continued) Geode™ CS5530 Index 09h-0Bh PCI Class Code Register (RO) Reset Value = 0C0310h This register identifies this function as an OpenHCI device. The Base Class is 0Ch (Serial Bus Controller). The Sub Class is 03h (Uni- versal Serial Bus). The Programming Interface is 10h (OpenHCI). Index 0Ch Cache Line Size Register (R/W) Reset Value = 00h This register identifies the system cacheline size in units of 32-bit words. USB will only store the value of bit 3 in this register since the cacheline size of 32 bytes is the only value applicable to the design. Any value other than 08h written to this register will be read back as 00h. If the CS5530 is being used in a GXLV processor based system, this register must be set to 00h. Index 0Dh Latency Timer Register (R/W) Reset Value = 00h This register identifies the value of the latency timer in PCI clocks for PCI bus master cycles. Index 0Eh Header Type Register (RO) Reset Value = 00h This register identifies the type of the predefined header in the configuration space. Since USB is a single function device and not a PCI-to-PCI bridge, this byte should be read as 00h. Index 0Fh BIST Register (RO) Reset Value = 00h This register identifies the control and status of Built In Self Test. USB does not implement BIST, so this register is read only. Index 10h-13h Base Address Register (R/W) Reset Value = 00000000h 31:12 Base Address:POST writes the value of the memory base address to this register. 11:4 Always 0:Indicates a 4 KB address range is requested. 3 Always 0:Indicates there is no support for prefetchable memory. 2:1 Always 0:Indicates that the base register is 32-bits wide and can be placed anywhere in 32-bit memory space. 0 Always 0:Indicates that the operational registers are mapped into memory space. Index 14h-3Bh Reserved Index 3Ch Interrupt Line Register (R/W) Reset Value = 00h This register identifies which of the system interrupt controllers the devices interrupt pin is connected to. The value of this register is used by device drivers and has no direct meaning to USB. Index 3Dh Interrupt Pin Register (RO) Reset Value = 01h This register identifies which interrupt pin a device uses. Since USB uses INTA#, this value is set to 01h. Index 3Eh Min. Grant Register (RO) Reset Value = 00h This register specifies the desired settings for how long of a burst USB needs assuming a clock rate of 33 MHz. The value specifies a period of time in units of 1/4 microsecond. Index 3Fh Max. Latency Register (RO) Reset Value = 00h This register specifies the desired settings for how often USB needs access to the PCI bus assuming a clock rate of 33 MHz. The value specifies a period of time in units of 1/4 microsecond. Index 40h-43h ASIC Test Mode Enable Register (R/W) Reset Value = 00000000h Used for internal debug and test purposes only. Index 44h ASIC Operational Mode Enable Register (R/W) Reset Value = 00h 7:1 Write Only:Read as 0s. 0 Data Buffer Region 16:When set the size of the region for the data buffer is 16 bytes. Otherwise, the size is 32 bytes. Index 45h-FFh Reserved Table 4-24. PCIUSB Index xxh: USB Controller Registers (Continued) Bit Description

www.national.com 208 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530

4.5 ISA LEGACY I/O REGISTER SPACE

The bit formats for the ISA Legacy I/O Registers plus two chipset-specific configuration registers used for interrupt mapping in the CS5530 Core Logic are given in this sec- tion. These registers reside in the ISA I/O address space in the address range from 000h to FFFh and are accessed through typical input/output instructions (i.e., CPU direct R/W) with the designated I/O port address and 8-bit data. The registers are separated into the following categories:  DMA Channel Control Registers, see Table 4-25  DMA Page Registers, see T able 4-26  Programmable Interval Timer Registers, see Table 4-27  Programmable Interrupt Controller Registers, see Table 4-28  Keyboard Controller Registers, see Table 4-29  Real Time Clock Registers, see Table 4-30  Miscellaneous Registers, see Table 4-31 (includes 4D0h and 4D1h Interrupt Edge/Level Select Registers and ACPI Timer Count Register at I/O Port 121Ch) Table 4-25. DMA Channel Control Registers Bit Description I/O Port 000h (R/W) DMA Channel 0 Address Register Written as two successive bytes, byte 0, 1. I/O Port 001h (R/W) DMA Channel 0 Transfer Count Register Written as two successive bytes, byte 0, 1. I/O Port 002h (R/W) DMA Channel 1 Address Register Written as two successive bytes, byte 0, 1. I/O Port 003h (R/W) DMA Channel 1 Transfer Count Register Written as two successive bytes, byte 0, 1. I/O Port 004h (R/W) DMA Channel 2 Address Register Written as two successive bytes, byte 0, 1. I/O Port 005h (R/W) DMA Channel 2 Transfer Count Register Written as two successive bytes, byte 0, 1. I/O Port 006h (R/W) DMA Channel 3 Address Register Written as two successive bytes, byte 0, 1. I/O Port 007h (R/W) DMA Channel 3 Transfer Count Register Written as two successive bytes, byte 0, 1. I/O Port 008h (R/W) Read DMA Status Register, Channels 3:0 7 Channel 3 Request:Request pending? 0 = No; 1 = Y es. 6 Channel 2 Request:Request pending? 0 = No; 1 = Y es. 5 Channel 1 Request:Request pending? 0 = No; 1 = Y es. 4 Channel 0 Request:Request pending? 0 = No; 1 = Y es. 3 Channel 3 Terminal Count:TC reached? 0 = No; 1 = Y es. 2 Channel 2 Terminal Count:TC reached? 0 = No; 1 = Y es. 1 Channel 1 Terminal Count:TC reached? 0 = No; 1 = Y es. 0 Channel 0 Terminal Count:TC reached? 0 = No; 1 = Y es. Write DMA Command Register, Channels 3:0 7 DACK Sense: 0=A c t i v eh i g h ;1=A c t i v el o w . 6 DREQ Sense: 0 = Active high; 1 = Active low. 5 Write Selection:0 = Late write; 1 = Extended write. 4 Priority Mode:0 = Fixed; 1 = Rotating. 3 Timing Mode: 0 = Normal; 1 = Compressed. 2 Channels 3:0:0 = Disable; 1 = Enable. 1:0 Reserved: Set to 0.

Revision 4.1 209 www.national.com Register Descriptions(Continued) Geode™ CS5530 I/O Port 009h (WO) Software DMA Request Register, Channels 3:0 7:3 Reserved: Set to 0. 2 Request Type:0=R e s e t ;1=S e t . 1:0 Channel Number Request Select:00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3. I/O Port 00Ah (R/W) DMA Channel Mask Register, Channels 3:0 7:3 Reserved: Set to 0.

2 Channel Mask: 0 = Not masked; 1 = Masked

1:0 Channel Number Mask Select:00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3 I/O Port 00Bh (WO) DMA Channel Mode Register, Channels 3:0 7:6 Transfer Mode:00 = Demand; 01 = Single; 10 = Block; 11 = Cascade. 5 Address Direction:0 = Increment; 1 = Decrement. 4 Auto-initialize:0 = Disable; 1 = Enable. 3:2 Transfer Type:00 = Verify; 01 = Memory read; 10 = Memory write; 11 = Reserved. 1:0 Channel Number Mode Select:00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3. I/O Port 00Ch (WO) DMA Clear Byte Pointer Command, Channels 3:0 I/O Port 00Dh (WO) DMA Master Clear Command, Channels 3:0 I/O Port 00Eh (WO) DMA Clear Mask Register Command, Channels 3:0 I/O Port 00Fh (WO) DMA Write Mask Register Command, Channels 3:0 I/O Port 0C0h (R/W) DMA Channel 4 Address Register Not used. I/O Port 0C2h (R/W) DMA Channel 4 Transfer Count Register Not used. I/O Port 0C4h (R/W) DMA Channel 5 Address Register Memory address bytes 1 and 0. I/O Port 0C6h (R/W) DMA Channel 5 Transfer Count Register Transfer count bytes 1 and 0 I/O Port 0C8h (R/W) DMA Channel 6 Address Register Memory address bytes 1 and 0. I/O Port 0CAh (R/W) DMA Channel 6 Transfer Count Register Transfer count bytes 1 and 0. I/O Port 0CCh (R/W) DMA Channel 7 Address Register Memory address bytes 1 and 0. I/O Port 0CEh (R/W) DMA Channel 7 Transfer Count Register Transfer count bytes 1 and 0. Table 4-25. DMA Channel Control Registers (Continued) Bit Description

www.national.com 210 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 I/O Port 0D0h (R/W) Read DMA Status Register, Channels 7:4 7 Channel 7 Request:Request pending? 0 = No; 1 = Y es. 6 Channel 6 Request:Request pending? 0 = No; 1 = Y es. 5 Channel 5 Request:Request pending? 0 = No; 1 = Y es.

4 Undefined

3 Channel 7 Terminal Count:TC reached? 0 = No; 1 = Y es. 2 Channel 6 Terminal Count:TC reached? 0 = No; 1 = Y es. 1 Channel 5 Terminal Count:TC reached? 0 = No; 1 = Y es.

0 Undefined

Write DMA Command Register, Channels 7:4 7 DACK Sense: 0=A c t i v eh i g h ;1=A c t i v el o w . 6 DREQ Sense: 0 = Active high; 1 = Active low. 5 Write Selection:0 = Late write; 1 = Extended write. 4 Priority Mode:0 = Fixed; 1 = Rotating. 3 Timing Mode: 0 = Normal; 1 = Compressed. 2 Channels 7:4:0 = Disable; 1 = Enable. 1:0 Reserved: Set to 0. I/O Port 0D2h (WO) Software DMA Request Register, Channels 7:4 7:3 Reserved: Set to 0. 2 Request Type:0=R e s e t ;1=S e t . 1:0 Channel Number Request Select:00 = Illegal; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7. I/O Port 0D4h (R/W) DMA Channel Mask Register, Channels 7:0 7:3 Reserved: Set to 0. 2 Channel Mask: 0 = Not masked; 1 = Masked. 1:0 Channel Number Mask Select:00 = Channel 4; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7. I/O Port 0D6h (WO) DMA Channel Mode Register, Channels 7:4 7:6 Transfer Mode:00 = Demand; 01 = Single; 10 = Block; 11 = Cascade. 5 Address Direction:0 = Increment; 1 = Decrement. 4 Auto-initialize:0 = Disabled; 1 = Enable. 3:2 Transfer Type:00 = Verify; 01 = Memory read; 10 = Memory write; 11 = Reserved. 1:0 Channel Number Mode Select:00 = Channel 4; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7. Channel 4 must be programmed in cascade mode. This mode is not the default. I/O Port 0D8h (WO) DMA Clear Byte Pointer Command, Channels 7:4 I/O Port 0DAh (WO) DMA Master Clear Command, Channels 7:4 I/O Port 0DCh (WO) DMA Clear Mask Register Command, Channels 7:4 I/O Port 0DEh (WO) DMA Write Mask Register Command, Channels 7:4 Table 4-25. DMA Channel Control Registers (Continued) Bit Description

Revision 4.1 211 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-26. DMA Page Registers Bit Description I/O Port 081h (R/W) DMA Channel 2 Low Page Register Address bits [23:16] (byte 2). I/O Port 082h (R/W) DMA Channel 3 Low Page Register Address bits [23:16] (byte 2). I/O Port 083h (R/W) DMA Channel 1 Low Page Register Address bits [23:16] (byte 2). I/O Port 087h (R/W) DMA Channel 0 Low Page Register Address bits [23:16] (byte 2). I/O Port 089h (R/W) DMA Channel 6 Low Page Register Address bits [23:16] (byte 2). I/O Port 08Ah (R/W) DMA Channel 7 Low Page Register Address bits [23:16] (byte 2). I/O Port 08Bh (R/W) DMA Channel 5 Low Page Register Address bits [23:16] (byte 2). I/O Port 08Fh (R/W) ISA Refresh Low Page Register Refresh address. I/O Port 481h (R/W) DMA Channel 2 High Page Register Address bits [31:24] (byte 3).Note:This register is reset to 00h on any access to Port 081h. I/O Port 482h (R/W) DMA Channel 3 High Page Register Address bits [31:24] (byte 3).Note:This register is reset to 00h on any access to Port 082h. I/O Port 483h (R/W) DMA Channel 1 High Page Register Address bits [31:24] (byte 3).Note:This register is reset to 00h on any access to Port 083h. I/O Port 487h (R/W) DMA Channel 0 High Page Register Address bits [31:24] (byte 3).Note:This register is reset to 00h on any access to Port 087h. I/O Port 489h (R/W) DMA Channel 6 High Page Register Address bits [31:24] (byte 3).Note:This register is reset to 00h on any access to Port 089h. I/O Port 48Ah (R/W) DMA Channel 7 High Page Register Address bits [31:24] (byte 3).Note:This register is reset to 00h on any access to Port 08Ah. I/O Port 48Bh (R/W) DMA Channel 5 High Page Register Address bits [31:24] (byte 3).Note:This register is reset to 00h on any access to Port 08Bh.

www.national.com 212 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Table 4-27. Programmable Interval Timer Registers Bit Description I/O Port 040h Write PIT Timer 0 Counter 7:0 Counter Value Read PIT Timer 0 Status 7 Counter Output:State of counter output signal. 6 Counter Loaded:Last count written is loaded? 0 = Y es; 1 = No. 5:4 Current Read/Write Mode:00 = Counter latch command; 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB, fol- lowed by MSB. 3:1 Current Counter Mode:0-5. 0 BCD Mode: 0 = Binary; 1 = BCD (binary coded decimal). I/O Port 041h Write PIT Timer 1 Counter (Refresh) 7:0 Counter Value Read PIT Timer 1 Status (Refresh) 7 Counter Output:State of counter output signal. 6 Counter Loaded:Last count written is loaded? 0 = Y es; 1 = No. 5:4 Current Read/Write Mode:00 = Counter latch command; 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB, fol- lowed by MSB. 3:1 Current Counter Mode:0-5. 0 BCD Mode: 0 = Binary; 1 = BCD (binary coded decimal). I/O Port 042h Write PIT Timer 2 Counter (Speaker) 7:0 Counter Value Read PIT Timer 2 Status (Speaker) 7 Counter Output:State of counter output signal. 6 Counter Loaded:Last count written is loaded? 0 = Y es; 1 = No. 5:4 Current Read/Write Mode:00 = Counter latch command; 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB, fol- lowed by MSB. 3:1 Current Counter Mode:0-5. 0 BCD Mode: 0 = Binary; 1 = BCD (binary coded decimal). I/O Port 043h (R/W) PIT Mode Control Word Register 7:6 Counter Select:00 = Counter 0; 01 = Counter 1; 10 = Counter 2; 11 = Read-back command (Note 1). 5:4 Current Read/Write Mode:00 = Counter latch command (Note 2); 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB, followed by MSB. 3:1 Current Counter Mode:0-5. 0 BCD Mode: 0 = Binary; 1 = BCD (binary coded decimal). Notes:1. If bits [7:6] = 11: Register functions as Read Status Command Bit 5 = Latch Count, Bit 4 = Latch Status, Bit 3 = Select Counter 2, Bit 2 = Select Counter 1, Bit 0 = Select Counter 0, and Bit 0 = Reserved 2. If bits [5:4] = 00: Register functions as Counter Latch Command Bits [7:6] = Selects Counter, and [3:0] = Don’t care

Revision 4.1 213 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-28. Programmable Interrupt Controller Registers Bit Description I/O Port 020h / 0A0h (WO) Master / Slave PIC IWC1 7:5 Reserved: Set to 0. 4 Reserved: Set to 1. 3 Trigger Mode:0 = Edge; 1 = Level. 2 Vector Address Interval:0=8b y t ei n t e r v a l s ;1=4b y t ei n t e r v a l s . 1 Reserved: Set to 0 (cascade mode). 0 Reserved: Set to 1 (ICW4 must be programmed). I/O Port 021h / 0A1h (WO) Master / Slave PIC ICW2 (after ICW1 is written) 7:3 A[7:3]:Address lines [7:3] for base vector for interrupt controller. 2:0 Reserved: Set to 0. I/O Port 021h / 0A1h (WO) Master / Slave PIC ICW3 (after ICW2 is written) Master PIC ICW3 7:0 Cascade IRQ: Must be 04h. Slave PIC ICW3 7:0 Slave ID:Must be 02h. I/O Port 021h / 0A1h (WO) Master / Slave PIC ICW4 (after ICW3 is written) 7:5 Reserved: Set to 0. 4 Special Fully Nested Mode:0 = Disable; 1 = Enable. 3:2 Reserved: Set to 0. 1 Auto EOI:0 = Normal EOI; 1 = Auto EOI. 0 Reserved: Set to 1 (8086/8088 mode). I/O Port 021h / 0A1h (R/W) Master / Slave PIC OCW1 (except immediately after ICW1 is written) 7 IRQ7 / IRQ15 Mask:0 = Not Masked; 1 = Mask. 6 IRQ6 / IRQ14 Mask:0 = Not Masked; 1 = Mask. 5 IRQ5 / IRQ13 Mask:0 = Not Masked; 1 = Mask. 4 IRQ4 / IRQ12 Mask:0 = Not Masked; 1 = Mask. 3 IRQ3 / IRQ11 Mask:0 = Not Masked; 1 = Mask. 2 IRQ2 / IRQ10 Mask:0 = Not Masked; 1 = Mask. 1 IRQ1 / IRQ9 Mask:0 = Not Masked; 1 = Mask. 0 IRQ0 / IRQ8 Mask:0 = Not Masked; 1 = Mask. I/O Port 020h / 0A0h (WO) Master / Slave PIC OCW2 7:5 Rotate/EOI Codes: 000 = Clear rotate in Auto EOI mode 100 = Set rotate in Auto EOI mode 001 = Non-specific EOI 101 = Rotate on non-specific EOI command 010 = No operation 110 = Set priority command (bits [2:0] must be valid) 011 = Specific EOI (bits [2:0] must be valid) 111 = Rotate on specific EOI command (bits [2:0] must be valid) 4:3 Reserved: Set to 0. 2:0 IRQ Number (000-111)

www.national.com 214 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 I/O Port 020h / 0A0h (WO) Master / Slave PIC OCW3 7 Reserved: Set to 0. 6:5 Special Mask Mode: 00 = No operation 10 = Reset Special Mask Mode 01 = No operation 11 = Set Special Mask Mode 4 Reserved: Set to 0. 3 Reserved: Set to 1. 2 Poll Command: 0 = Disable; 1 = Enable. 1:0 Register Read Mode: 00 = No operation 10 = Read interrupt request register on next read of Port 20h 01 = No operation 11 = Read interrupt service register on next read of Port 20h. I/O Port 020h / 0A0h (RO) Master / Slave PIC Interrupt Request and Service Registers for OCW3 Commands Interrupt Request Register 7 IRQ7 / IRQ15 Pending:0 = Y es; 1 = No. 6 IRQ6 / IRQ14 Pending:0 = Y es; 1 = No. 5 IRQ5 / IRQ13 Pending:0 = Y es; 1 = No. 4 IRQ4 / IRQ12 Pending:0 = Y es; 1 = No. 3 IRQ3 / IRQ11 Pending:0 = Y es; 1 = No. 2 IRQ2 / IRQ10 Pending:0 = Y es; 1 = No. 1 IRQ1 / IRQ9 Pending:0 = Y es; 1 = No. 0 IRQ0 / IRQ8 Pending:0 = Y es; 1 = No. Interrupt Service Register 7 IRQ7 / IRQ15 In-Service:0=N o ;1=Y e s . 6 IRQ6 / IRQ14 In-Service:0=N o ;1=Y e s . 5 IRQ5 / IRQ13 In-Service:0=N o ;1=Y e s . 4 IRQ4 / IRQ12 In-Service:0=N o ;1=Y e s . 3 IRQ3 / IRQ11 In-Service:0=N o ;1=Y e s . 2 IRQ2 / IRQ10 In-Service:0=N o ;1=Y e s . 1 IRQ1 / IRQ9 In-Service:0=N o ;1=Y e s . 0 IRQ0 / IRQ8 In-Service:0=N o ;1=Y e s . Note: The function of this register is set with bits [1:0] in a write to 020h. Table 4-28. Programmable Interrupt Controller Registers (Continued) Bit Description

Revision 4.1 215 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-29. Keyboard Controller Registers Table 4-30. Real-Time Clock Registers Bit Description I/O Port 060h (R/W) External Keyboard Controller Data Register Keyboard Controller Data Register:All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset fea- tures are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port assert the A20M# pin or cause a warm CPU reset. I/O Port 061h (R/W) Port B Control Register Reset Value = 00x01100b 7 PERR#/SERR# Status (Read Only):Was a PCI bus error (PERR#/ SERR#) asserted by a PCI device or by CS5530? 0=N o ;1=Y e s . This bit can only be set if ERR_EN is set 0. This bit is set 0 after a write to ERR_EN with a 1 or after reset. 6 IOCHK# Status (Read Only):Is an I/O device reporting an error to the CS5530? 0 = No; 1 = Yes. This bit can only be set if IOCHK_EN is set 0. This bit is set 0 after a write to IOCHK_EN with a 1 or after reset. 5 PIT OUT2 State (Read Only):This bit reflects the current status of the PIT Counter 2 (OUT2). 4 Toggle (Read Only):This bit toggles on every falling edge of Counter 1 (OUT1). 0 = Generates an NMI if IOCHK# is driven low by an I/O device to report an error. Note that NMI is under SMI control. 1 = Ignores the IOCHK# input signal and does not generate NMI.

2 PERR#/ SERR# Enable: Generates an NMI if PERR#/ SERR# is driven active to report an error:

0 = Enable; 1 = Disable 1 PIT Counter2 (SPKR):0 = Forces Counter 2 output (OUT2) to zero. 1 = Allows Counter 2 output (OUT2) to pass to the speaker. 0 PIT Counter2 Enable:0 = Sets GATE2 input low. 1 = Sets GATE2 input high. I/O Port 062h (R/W) External Keyboard Controller Mailbox Register Keyboard Controller Mailbox Register:Accesses to this port will assert KBROMCS# if the Port 062h/066h decode is enabled through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]). I/O Port 064h (R/W) External Keyboard Controller Command Register Keyboard Controller Command Register:All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port assert the A20M# pin or cause a warm CPU reset. I/O Port 066h (R/W) External Keyboard Controller Mailbox Register Keyboard Controller Mailbox Register:Accesses to this port will assert KBROMCS# if the Port 062h/066h decode is enabled through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]). I/O Port 092h Port A Control Register (R/W) Reset Value = 02h 7:2 Reserved: Set to 0. 1 A20M# SMI Assertion:Assert A20# SMI: 0 = Enable; 1 = Disable. 0 Fast CPU Reset:WM_RST SMI is asserted to the BIOS: 0 = Disable; 1 = Enable. This bit must be cleared before the generation of another reset. Bit Description I/O Port 070h (WO) RTC Address Register 7 NMI Mask: 0 = Enable; 1 = Mask. 6:0 RTC Register Index:A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered. Note: This register is shadowed within the CS5530 and is read through the RTC Shadow Register (F0 Index BBh). I/O Port 071h (R/W) RTC Data Register A read of this register returns the value of the register indexed by the RTC Address Register plus initiates a RTCCS#. A write of this register sets the value into the register indexed by the RTC Address Register plus initiates a RTCCS#.

www.national.com 216 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Table 4-31. Miscellaneous Registers Bit Description I/O Ports 170h-177h/376h-377h Secondary IDE Registers (R/W) When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according to their configuration rather than generating standard ISA bus cycles. I/O Ports 1F0h-1F7h/3F6h-3F7h Primary IDE Registers (R/W) When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according to their configuration rather than generating standard ISA bus cycles. I/O Port 4D0h Interrupt Edge/Level Select Register 1 (R/W) Reset Value = 00h 7 IRQ7 Edge or Level Select:Selects PIC IRQ7 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 6 IRQ6 Edge or Level Select:Selects PIC IRQ6 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 5 IRQ5 Edge or Level Select:Selects PIC IRQ5 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 4 IRQ4 Edge or Level Select:Selects PIC IRQ4 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 3 IRQ3 Edge or Level Select:Selects PIC IRQ3 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 2 Reserved: Set to 0. 1 IRQ1 Edge or Level Select:Selects PIC IRQ1 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 0 Reserved: Set to 0. Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). I/O Port 4D1h Interrupt Edge/Level Select Register 2 (R/W) Reset Value = 00h 7 IRQ15 Edge or Level Select:Selects PIC IRQ15 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 6 IRQ14 Edge or Level Select:Selects PIC IRQ14 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 5 Reserved: Set to 0. 4 IRQ12 Edge or Level Select:Selects PIC IRQ12 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 3 IRQ11 Edge or Level Select:Selects PIC IRQ11 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 2 IRQ10 Edge or Level Select:Selects PIC IRQ10 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 1 IRQ9 Edge or Level Select:Selects PIC IRQ9 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 0 Reserved: Set to 0. Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). I/O Port 121Ch-121Fh (Note) ACPI Timer Count Register (RO) Reset Value = 00FFFFFCh ACPI_COUNT (Read Only): This read-only register provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled via F0 Index 83h[5], an SMI is generated when the MSB toggles. The MSB toggles every 2.343 seconds. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported is at F0 Index 87h/F7h[0]. 31:24 Reserved: Always returns 0. 23:0 Counter Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch in Silicon Revision 1.3 and above. Otherwise read at F1BAR+Offset 1Ch.

Revision 4.1 217 www.national.com Register Descriptions(Continued) Geode™ CS5530

4.6 V-ACPI I/O REGISTER SPACE

The register space designated as V-ACPI I/O does not physically exist in the CS5530. ACPI is supported in the CS5530 by virtualizing this register space, called V-ACPI. In order for ACPI to be supported, the V-ACPI VSA mod- ule must be included in the BIOS. The register descrip- tions that follow, are supplied here for reference only. F i x e dF e a t u r eS p a c er e g i s t e r sa r er e q u i r e dt ob ei m p l e - mented by all ACPI-compatible hardware. The Fixed Fea- ture registers in the VSA/ACPI solution are mapped to normal I/O space starting at offset AC00h; however, the designer can relocate this register space at compile time, hence are hereafter referred to as ACPI_BASE. Registers within V-ACPI (Virtualized ACPI) I/O space must only be accessed on their defined boundaries. For example, byte aligned registers must not be accessed via WORD I/O instructions, WORD aligned registers must not be accessed as DWORD I/O instructions, etc. The V-ACPI I/O Register Space can be broken up into major blocks:  PM Event Block 1A (PM1A_EVT_BLK)  PM Event Block 1A Control (PM1A_CNT_BLK)  Processor Register Block (P_BLK)  Command Block (CMD_BLK)  Test/Setup Block (TST/SETUP_BLK)  General Purpose Enable 0 Block (GPE0_BLK) PM1A_EVT_BLK is 32-bit aligned and contains two 16-bit registers, PM1A_STS and PM1A _EN. PM1A_CNT_BLK is 32-bit aligned and contains one 16- bit register, PM1A_CNT. PM1A_CNT contains the Fixed Feature control bits used for various power management enables and as communication flags between BIOS and the ACPI OS. P_BLK is 32-bit aligned (one register block per processor) and contains two registers P_CNT and P_LVL2. P_LVL3 is currently not supported. - P_CNT (Processor Control) - 16-bit register, Controls process duty cycle via CPU clock throttling. DUTY_WIDTH = 3 (can be widened) DUTY_OFFSET = 0 - P_LVL2 (Enter C2 Power State) - 8-bit, read only register. When read, causes the processor to enter C2 power state. CMD_BLK contains one 8-bit register SMI_CMD which interprets and processes the ACPI commands (defined in Fixed ACPI Description Table, refer to ACPI Specification, Section 5.2.5). TST/SETUP_BLK is provided by the VSA technology code and contains two registers, SETUP_IDX and SETUP_DATA for the purpose of configuring the CS5530. Specifically, this pair of registers enables system software t om a pG P I Op i n so nt h eC S 5 5 3 0t oP M 1 A _ S T Sa n d GPE0_STS register bits. GPE0_BLK has registers used to enable system software to configure GPIO (General Purpose I/O) pins to generate SCI interrupts. GPE0_BLK is a 32-bit block aligned on a 4-byte boundary. It contains two 16-bit registers, GPE0_STS and GPE0_EN, each of which must be con- figured by the BIOS POST. In order for a GPE0_STS bit to generate an SCI, the corresponding enable bit in GPE0_EN must be set. Table 4-32 give the bit formats of the V-ACPI I/O registers. Table 4-32. V-ACPI Registers Bit Description ACPI_BASE 00h-03h P_CNT — Processor Control Register (R/W) Reset Value = 00000000h 31:5 Reserved: Always 0. 4 THT_EN: Enables throttling of the clock based on the CLK_VAL field. 3 Reserved: Always 0. 2:0 CLK_VAL: Clock throttling value: CPU duty cycle = 000 = Reserved 100 = 50% 010 = 25% 110 = 75% ACPI_BASE 04h P_LVL2 — Enter C2 Power State Register (RO) Reset Value = 00h Reading this 8-bit read only register causes the processor to enter the C2 power state. Reads of P_LVL2 return 0. Writes have no effect. ACPI_BASE 05h Reserved Reset Value = 00h ACPI_BASE 06h SMI_CMD — OS/BIOS Requests Register (R/W) Reset Value = 00h Interpret and process the ACPI commands (defined in Fixed ACPI Description Table, refer to ACPI Specification, Section 5.2.5): 0x01 - ACPI_ENABLE 0x02 - ACPI_DISABLE 0x03 - S4BIOS_REQ (optional)

www.national.com 218 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 ACPI_BASE 07h Reserved Reset Value = 00h ACPI_BASE 08h-09h PM1A_STS — PM1A Status Register (R/W) Reset Value = 0000h 15 WAKE_STS: Wake Status: Set when system was in sleep state and an enabled wakeup occurs. 14:11 Reserved 10 RTC_STS: Real Time Clock Status: This bit changes to 1 if an RTC alarm causes a wake up event. This bit is only set upon wakeup from a sleep state and IRQ8 is asserted by the RTC. Refer to Table 4-35. 9 SLPBTN_STS: Sleep Button Status (Optional): This bit changes to 1 when the sleep button is pressed. If SLPBTN_EN is set, an SCI interrupt is generated. This bit must be configured to be set by a GPIO pin using SETUP_IDX values 0x10-0x17 in order to be set. Refer to Table 4-34. 8 PWRBTN_STS: Power Button Status: This bit is set when power button is pressed. If PWRBTN_EN is set, an SCI inter- rupt is asserted. This bit must be configured to be set by a GPIO pin using SETUP_IDX values 0x10-0x17 in order to be set. Refer to Table 4-34. 7:6 Reserved 5 GBL_STS: Global Status: The BIOS sets GBL_STS to 1 to release its global lock and return control to the ACPI OS. At the same time GBL_STS is set, the BIOS generates an SCI. 4 BM_STS: Bus Master Status: This bit is not supported by V-ACPI. 3:1 Reserved 0 TMR_STS: ACPI Timer Status: This bit changes to 1 whenever bit 23 of the ACPI timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch in Silicon Rev 1.3 and above) changes state. The ACPI OS is responsible for clearing TMR_STS. If TMR_EN is also set then a SCI interrupt is asserted. Note: Status bits are “sticky”. A write of a one (1) to a given bit location will reset the bit. ACPI_BASE 0Ah-0Bh PM1A_EN — PM1A Enable Register (R/W) Reset Value = 0000h 15:11 Reserved 10 RTC_EN: Real Time Clock Enable: If set, an SCI is asserted when RTC_STS changes to 1. 9 SLPBTN_EN: Sleep Button Enable (Optional): If set, an SCI is asserted when SLPBTN_STS changes to 1. 8 PWRBTN_EN: Power Button Enable: If set, an SCI is asserted when PWRBTN_STS changes to 1. 7:6 Reserved 5 GBL_EN: Global Lock Enable: If set, writing a 1 to GBL_STS causes an SCI to be asserted. 4:1 Reserved 0 TMR_EN: ACPI Timer Enable: If set, an SCI is asserted when bit 23 of the ACPI timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch in Silicon Rev 1.3 and above) changes state. ACPI_BASE 0Ch-0Dh PM1A_CNT — PM1A Control Register (R/W) Reset Value = 0000h 15:14 Reserved 13 SLP_EN (WO): Sleep Enable (Write Only): Setting this bit causes the system to enter the sleep state defined by SLP_TYPx. Reads of this bit always return zero. 12:10 SLP_TYPx: Sleep Type: Defines the type of sleep state the system enters when SLP_EN is set. 000 = Sleep State S0 (Full on) 100 = Sleep State S4 001 = Sleep State S1 101 = Sleep State S5 (Soft off) 010 = Sleep State S2 110 = Reserved 011 = Reserved 111 = Reserved 9:3 Reserved 2 GBL_RLS (WO): Global Lock Release (Write Only): Used by ACPI OS to raise an event to the BIOS software (SMI). Used by ACPI driver to indicate a release of the global lock and the setting of the pending bit in the FACS table (refer to ACPI Specification, Section 5.2.8). 1 BM_RLD: This bit is not supported by V-ACPI. 0 SCI_EN: System Controller Interrupt Enable: Selects whether power management events are SCI or SMI. Set by hard- ware based on an ACPI_ENABLE/ACPI_DISABLE written to the SMI_CMD port. Table 4-32. V-ACPI Registers (Continued) Bit Description

Revision 4.1 219 www.national.com Register Descriptions(Continued) Geode™ CS5530 ACPI_BASE 0Eh-0Fh SETUP_IDX — Setup Index Register (R/W) Reset Value = 0000h SETUP_IDX is a 16-bit register that references an internal setting in the VSA (refer to Table 4-33). A read of SETUP_IDX returns the last value written to SETUP_IDX. A write of SETUP_IDX selects the index for a corresponding write to SETUP_DATA. Writes of any undefined index values to SETUP_IDX are ignored. If the current value of SETUP_IDX is invalid, a read of SETUP_DATA returns 0. ACPI_BASE 10h-11h GPE0_STS — General Purpose Event 0 Status Register (R/W) Reset Value = 0000h 15 OEM_GPE_S15: Original Equipment Manufacturer General Purpose Event Status Bit 15: OEM defined. 14 OEM_GPE_S14: Original Equipment Manufacturer General Purpose Event Status Bit 14: OEM defined. 13 OEM_GPE_S13: Original Equipment Manufacturer General Purpose Event Status Bit 13: OEM defined. 12 OEM_GPE_S12: Original Equipment Manufacturer General Purpose Event Status Bit 12: OEM defined. 11 OEM_GPE_S11: Original Equipment Manufacturer General Purpose Event Status Bit 11: OEM defined. 10 OEM_GPE_S10: Original Equipment Manufacturer General Purpose Event Status Bit 10: OEM defined. 9 OEM_GPE_S09: Original Equipment Manufacturer General Purpose Event Status Bit 9: OEM defined. 8 OEM_GPE_S08: Original Equipment Manufacturer General Purpose Event Status Bit 8: OEM defined. 7 OEM_GPE_S07: Original Equipment Manufacturer General Purpose Event Status Bit 7: OEM defined. 6 OEM_GPE_S06: Original Equipment Manufacturer General Purpose Event Status Bit 6: OEM defined. The recommended mapping for the lid switch input is to use GPIO6. If the recommended mapping is used, bit 6 of GPE0_STS needs to be mapped to GPIO6 at boot time via SETUP_IDX and SETUP_DATA. Similarly, the lid switch input needs to be routed to GPIO6 in hardware. If this method is selected, this bit is defined as: LID_STS: Lid Status: Set when lid state changes. If LID_EN is set, a SCI interrupt is asserted. Reset by writinga1t ot h i s bit. 5 OEM_GPE_S05: Original Equipment Manufacturer General Purpose Event Status Bit 5: OEM defined. 4 OEM_GPE_S04: Original Equipment Manufacturer General Purpose Event Status Bit 4: OEM defined. 3 OEM_GPE_S03: Original Equipment Manufacturer General Purpose Event Status Bit 3: OEM defined. 2 OEM_GPE_S02: Original Equipment Manufacturer General Purpose Event Status Bit 2: OEM defined. 1 OEM_GPE_S01: Original Equipment Manufacturer General Purpose Event Status Bit 1: OEM defined. 0 OEM_GPE_S00: Original Equipment Manufacturer General Purpose Event Status Bit 0: OEM defined. Note: Each bit is set by an external event and cleared by a write of a one to that bit. The GPE0_STS bits are mapped to specific, chipset-resident GPIO signals using the SETUP_IDX and SETUP_DATA registers. Refer to Tables 4-33 through 4-35 Table 4-32. V-ACPI Registers (Continued) Bit Description

www.national.com 220 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 ACPI_BASE 12h-13h GPE0_EN — General Purpose Event 0 Enable Register (R/W) Reset Value = 0000h 15 OEM_GPE_E15: Original Equipment Manufacturer General Purpose Event Enable Bit 15: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 14 OEM_GPE_E14: Original Equipment Manufacturer General Purpose Event Enable Bit 14: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 13 OEM_GPE_E13: Original Equipment Manufacturer General Purpose Event Enable Bit 13: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 12 OEM_GPE_E12: Original Equipment Manufacturer General Purpose Event Enable Bit 12: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 11 OEM_GPE_E11: Original Equipment Manufacturer General Purpose Event Enable Bit 11: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 10 OEM_GPE_E10: Original Equipment Manufacturer General Purpose Event Enable Bit 10: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 9 OEM_GPE_E09: Original Equipment Manufacturer General Purpose Event Enable Bit 9: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 8 OEM_GPE_E08: Original Equipment Manufacturer General Purpose Event Enable Bit 8: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 7 OEM_GPE_E07: Original Equipment Manufacturer General Purpose Event Enable Bit 7: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 6 LID_STS: Lid Enable: Enables LID_STS to generate a SCI when set. 5 OEM_GPE_E05: Original Equipment Manufacturer General Purpose Event Enable Bit 5: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 4 OEM_GPE_E04: Original Equipment Manufacturer General Purpose Event Enable Bit 4: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 3 OEM_GPE_E03: Original Equipment Manufacturer General Purpose Event Enable Bit 3: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 2 OEM_GPE_E02: Original Equipment Manufacturer General Purpose Event Enable Bit 2: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 1 OEM_GPE_E01: Original Equipment Manufacturer General Purpose Event Enable Bit 1: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 0 OEM_GPE_E00: Original Equipment Manufacturer General Purpose Event Enable Bit 0: When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. Note: These are the enables for the GPE0_STS bits. When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. ACPI_BASE 14h-17h SETUP_DATA — Setup Data Register (R/W) Reset Value = 00000000h During a read operation, SETUP_DATA returns the value of the internal setting specified by the current value in SETUP_IDX (ACPI_ABASE 0Eh-0Fh) ACPI_BASE 18h-1Fh Reserved Reset Value = 00h Reserved for future V-ACPI Implementations. Table 4-32. V-ACPI Registers (Continued) Bit Description

Revision 4.1 221 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-33. SETUP_IDX Values Index Operation 0x00 No operation 0x10 Configure GPIO0 to PM1A_STS or GPE0_STS bits 0x11 Configure GPIO1 to PM1A_STS or GPE0_STS bits 0x12 Configure GPIO2 to PM1A_STS or GPE0_STS bits 0x13 Configure GPIO3 to PM1A_STS or GPE0_STS bits 0x14 Configure GPIO4 to PM1A_STS or GPE0_STS bits 0x15 Configure GPIO5 to PM1A_STS or GPE0_STS bits 0x16 Configure GPIO6 to PM1A_STS or GPE0_STS bits 0x17 Configure GPIO7 to PM1A_STS or GPE0_STS bits 0x30 Configure IRQ0 to wakeup system 0x31 Configure IRQ1 to wakeup system 0x32 Do not use – Reserved for cascade interrupt 0x33 Configure IRQ3 to wakeup system 0x34 Configure IRQ4 to wakeup system 0x35 Configure IRQ5 to wakeup system 0x36 Configure IRQ6 to wakeup system 0x37 Configure IRQ7 to wakeup system 0x38 Configure IRQ8 to wakeup system (Defaults to RTC_STS in PM1A_STS) 0x39 Configure IRQ9 to wakeup system. 0x3A Configure IRQ10 to wakeup system. 0x3B Configure IRQ11 to wakeup system 0x3C Configure IRQ12 to wakeup system 0x3D Do not use – Reserved for math coprocessor 0x3E Configure IRQ14 to wakeup system 0x3F Configure IRQ15 to wakeup system 0x40 Generate GBL_STS – Sets the GLB_STS bit and generates a SCI to the OS 0x41 Configure IRQ to be used for SCI 0x42 Enable reads of ACPI registers 0x43 Do atomic I/O sequence 0x50 Video power 0x60 Soft SMI AX = 6000 emulation 0x61 Soft SMI AX = 6001 emulation 0x62 Soft SMI AX = 6002 emulation 0x63 Soft SMI AX = 6003 emulation 0x64 Audio power control Table 4-34. GPIO Mapping (0x10-0x17) SETUP_ DATA Function xx Value 0x00 No mapping – Do not use this GPIO pin 0x08 Assign GPIOx to PWRBTN_STS bit in PM1A_STS 0x09 Assign GPIOx to SLPBTN_STS in PM1A_STS 0x10 Assign GPIOx to bit 0 in GPE0_STS register 0x11 Assign GPIOx to bit 1 in GPE0_STS register 0x12 Assign GPIOx to bit 2 in GPE0_STS register 0x13 Assign GPIOx to bit 3 in GPE0_STS register 0x14 Assign GPIOx to bit 4 in GPE0_STS register 0x15 Assign GPIOx to bit 5 in GPE0_STS register 0x16 Assign GPIOx to bit 6 in GPE0_STS register 0x17 Assign GPIOx to bit 7 in GPE0_STS register 0x18 Assign GPIOx to bit 8 in GPE0_STS register 0x19 Assign GPIOx to bit 9 in GPE0_STS register 0x1A Assign GPIOx to bit 10 in GPE0_STS register 0x1B Assign GPIOx to bit 11 in GPE0_STS register 0x1C Assign GPIOx to bit 12 in GPE0_STS register 0x1D Assign GPIOx to bit 13 in GPE0_STS register 0x1E Assign GPIOx to bit 14 in GPE0_STS register 0x1F Assign GPIOx to bit 15 in GPE0_STS register y Value (y values may be ORed together to get the desired combination of features) 0x01 Falling edge 0x02 Rising edge 0x04 Power button 0x08 Reserved Note: For GPIO mapping, a value of 0000zyxx is used where: z = a runtime/wake indicator y = the edge to be used xx = a bit in either PM1A_STS or GPE0_STS When using V-ACPI both edges of GPIO6 can be sensed. When using the CS5530, GPIO6 provides additional hardware that enables the chipset to gener- ate an SMI on both the rising and falling edges of the input signal.

www.national.com 222 Revision 4.1 Register Descriptions(Continued) Geode™ CS5530 Table 4-35. IRQ Wakeup Status Mapping (0x30-0x3F) SETUP_ DATA Function 0 Do not wakeup on IRQ activity. 0x0a Assign IRQ Wake to bit 10 in PM1A_STS register 0x10 Assign IRQ Wake to bit 0 in GPE0_STS register 0x11 Assign IRQ Wake to bit 1 in GPE0_STS register 0x12 Assign IRQ Wake to bit 2 in GPE0_STS register 0x13 Assign IRQ Wake to bit 3 in GPE0_STS register 0x14 Assign IRQ Wake to bit 4 in GPE0_STS register 0x15 Assign IRQ Wake to bit 5 in GPE0_STS register 0x16 Assign IRQ Wake to bit 6 in GPE0_STS register 0x17 Assign IRQ Wake to bit 7 in GPE0_STS register 0x18 Assign IRQ Wake to bit 8 in GPE0_STS register 0x19 Assign IRQ Wake to bit 9 in GPE0_STS register 0x1A Assign IRQ Wake to bit 10 in GPE0_STS register 0x1B Assign IRQ Wake to bit 11 in GPE0_STS register 0x1C Assign IRQ Wake to bit 12 in GPE0_STS register 0x1D Assign IRQ Wake to bit 13 in GPE0_STS register 0x1E Assign IRQ Wake to bit 14 in GPE0_STS register 0x1F Assign IRQ Wake to bit 15 in GPE0_STS register Note: When the ability to wakeup on an IRQ is desired use indexes 0x31 through 0x3F . This will allow sensing of interrupts while sleeping and waking of the system when activity occurs.The desired GPE0 Status bit will onlybe set if the system is sleeping and a wake event occurs. The system will only wake if the status bit is enabled in the corresponding enable register. IRQ8 (RTC) is assigned to the RTC_STS bit in the PM1A_STS register by default and shouldNOT be changed. For enabling and selection of the GPE0 Status bit to be set when Wake on IRQ Activity is desired, use the SETUP_DATA values listed above. Table 4-36. Commands (0x41-0x43, and 0x50) Index Function 0x41 Configure IRQ to be used for SCI:When map- ping the SCI interrupt SETUP_IDX contains the number of the IRQ to be used for the SCI. Valid values are 3-7, 9-12, and 14-15. Invalid values will not change the assignment of the SCI IRQ. The default value for the SCI IRQ is 9. 0x42 Enable Reads of ACPI Registers:Prior to the issuance of this command onlyWRITES can be performed to the V-ACPI Fixed feature registers. This command MUST be issued to enable reading of the registers. This is to prevent the User Def 1 hook on NON-ACPI systems from interfering with system functions. 0x43 Do Atomic I/O Sequence:This command allows a sequence of I/O operations to be done with no interruption. Certain SuperI/O chips must receive unlock codes with NO intervening I/O. In addition other SuperI/O chips do not allow I/O to devices while in configuration mode. This command will insure that I/O operations are completed without interruption. The address of a sequence of I/O commands is placed in the SETUP_DATA regis- ter. The command sequence will then be pro- cessed immediately. The I/O command sequence consists of two parts: the signature/length block and the I/O block. There is only one signature/length block. There may be one or more I/O blocks. The signature block consists of four DWORDs (see Table 4-37). The I/O block consists of four bytes followed by three DWORDs (see Table 4-38). 0x50 Video Power:This command will control the power to the SOFTVGA. If SETUP_DATA is writ- ten with a 0, power will be turned off. If a 1 is writ- ten, power will be turned on.

Revision 4.1 223 www.national.com Register Descriptions(Continued) Geode™ CS5530 Table 4-37. Signature/Length Block for 0x43 Byte Offset Value

0 Signature:Always 0x00000070

4 Length:The length of the entire buffer including the signature block in bytes.

8 Reserved: Set to 0

12 Reserved: Set to 0

T a b l e4 - 3 8 . I / OB l o c kf o r0 x 4 3 Byte Offset Description

0 BYTE: Operation Type:

1 = Read 2=W r i t e 3 = Read/And/Or/Write 4 = Define index and data ports In addition, values may be OR’ed in to the upper two bits of this byte to indicate that special functions are desired: 0x80 = Do not perform this operation (convert to NO-OP). 0x40 = This is an index operation.

1 BYTE: Reserved set to 0

2 BYTE: I/O Length: Determines whether a BYTE, WORD or DWORD operation is performed. 1 = BYTE operation 2 = WORD operation 3 = DWORD operation If BYTE 0 is a 4, then this field is used to indicate the size of the index write.

3 BYTE: Reserved set to 0

4 DWORD: I/O Address: This is the address in the I/O space to be used. It is always a WORD value. If this is a define index/data port operation, this DWORD contains the I/O address of the index port. If this is an index operation, other than define, this DWORD contains the value to be written to the index port.

8 DWORD: I/O Data: The meaning depends on the operation type:

Read = This is where the data read from the I/O port will be placed. Write = This is the data to write to the I/O port. Read/AND/OR/Write = This is the data that will be ANDed with the data read from the I/O port. Define index/data port - This DWORD contains the I/O address of the data port. 12 DWORD: OR Data: This field is only used in a Read/AND/OR/Write operation. It contains the data that will be OR’ed after the data read was AND’ed with the previous field. After the OR is done, the data will be re-written to the I/O port. Note: In all cases if the data called for is shorter than the field, the data will be stored or retrieved from the least significant portion of the DWORD. Table 4-39. Audio Soft SMI Emulation (0x60-0x63) Soft SMI AX SETUP_IDX SETUP_DATA 0x6000 0x60 BP register value 0x6001 0x61 BP register value 0x6002 0x62 BX register value 0x6003 0x63 BX register value Note: Arbitrary registers cannot be set in ASL code before issuing a soft SMI. These commands provide an I/O interface to allow AUDIO Soft SMIs to be emulated. Table 4-40. Audio Power Control (0x64) Data Value Action

0 Power codec off and mute output

1 Power codec off, do not mute (allows CD to play)

2 Power codec on and un-mute output

3 Power codec on only

Note: This command allows control of power to the audio codec as well as control of amplifier muting.

www.national.com 224 Revision 4.1 Geode™ CS5530

5.0 Electrical Specifications

This section provides information on testing modes, elec- trical connections, absolute maximum ratings, recom- mended operating conditions, and DC/AC characteristics for the Geode CS5530. All voltage values in Electrical Specifications are with respect to V SS unless otherwise noted. For detailed information on the PCI bus electrical specifi- cation refer to Chapter 4 of the PCI Bus Specification, Revision 2.1.

5.1 TEST MODES

The CS5530 can be forced into different test modes. Table 5-1 summarizes the test mode selection process. Table 5-1. Test Mode Selection Mode Signal Name POR# TEST IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Test mode: X_CLK is a direct clock, stays until POR# event 0100100 T e s t U S B p a d s x101000 NAND tree test, IDDQ test, tristate control: PLL, USB pads, and DAC are all in power-down mode (see Section 5.1.1 “Nand Tree Mode” on page 225) x1xxxx1 P L L t e s t x110000 X-Bus test: Allows internal X-Bus to be driven externally 011010x B I S T f o r p a l e t t e a n d v i d e o R A M s x111000 D A C t e s t x111100 I R Q 6 = 1 a s w e l l ; U S B t e s t x100010 SCAN_MODE = 1, SCAN_ENABLE = 0, TEST_CLOCK = PAD_DCC_SDA x110010 SCAN_MODE = 1, SCAN_ENABLE = 1, TEST_CLOCK = PAD_DCC_SDA, X-BUS_DISABLE = 1 x110110 Note: x = Don’t Care

Revision 4.1 225 www.national.com Electrical Specifications(Continued) Geode™ CS5530

5.1.1 Nand Tree Mode

T h eN A N Dt r e em o d ei su s e dt ot e s ti n p u ta n db i d i r e c - tional pins which will be part of the NAND tree chain. The NAND tree chain starts on pin L24 (SUSP_3V) and the output of the chain is on pin K24 (POR#). Table 5-2 gives the pins of the NAND tree chain. The NAND tree mode is started by pulling pins D3 (TEST) and AD14 (IRQ7) from low to high. All inputs in Table 5-2 are initialized to a 1 and then toggled to a 0 at least 100 ns apart. The output waveform on pin K24 (POR#) is a clock (see Figure 5-1 on page 226). Table 5-2. NAND Tree Test Mode Pins Signal Name Pin No. SUSP_3V (NAND Input Start) L24 SUSPA# L25 PSERIAL L26 CLK_14MHZ P24 SMI# P25 INTR P26 IRQ13 R23 XIDE_DATA7 U23 XIDE_DATA6 U24 XIDE_DATA8 V24 XIDE_DATA10 V25 XIDE_DATA5 W26 XIDE_DATA9 Y25 XIDE_DATA11 Y24 XIDE_DATA4 AA26 XIDE_DATA12 AA25 XIDE_DATA3 AB26 XIDE_DATA1 AA24 XIDE_DATA13 AB25 XIDE_DATA2 AB24 XIDE_DATA0 AC26 XIDE_DATA14 AC25 XIDE_DATA15 AB23 IDE_DREQ1 AC24 IDE_DREQ0 AD26 IDE_IORDY0 AD25 IDE_IORDY1 AE26 SA14/SD14 AD24 SA15/SD15 AE25 GPIO0 AC22 GPIO1/SDATA_IN2 AE24 GPIO2 AF25 GPIO3 AF24 GPIO4/SA20 AD22 GPIO5/SA21 AC21 GPIO6/SA22 AE23 GPIO7/SA23 AF23 SA13/SD13 AE22 SA10/SD10 AC20 DRQ7 AF22 SA12/SD12 AE21 SA11/SD11 AF21 SA9/SD9 AD19 DRQ6 AE20 MEMW# AF20 MEMR# AE19 DRQ5 AD18 SA8/SD8 AF19 DRQ0 AE18 IRQ11 AF18 IRQ14 AC17 IRQ15 AD17 SBHE# AE17 IRQ12 AF17 IRQ10 AE16 IOCS16# AF16 MEMCS16# AC15 IRQ4 AE15 TC AF15 IRQ3 AC14 IRQ8# AE14 IRQ6 AF14 DRQ3 AD13 IRQ5 AE13 IRQ1 AF13 DRQ1 AD12 IORX0 AE12 SA17 AF12 IOW# AC11 SA16 AD11 SA18 AE11 IOCHRDY AF11 SA19 AD10 DRQ2 AE10 ZEROWS# AF10 SA2/SD2 AD9 SA0/SD0 AE9 SA4/SD4 AF6 SA1/SD1 AE6 SA6/SD6 AF5 SA3/SD3 AC6 IRQ9 AE5 SA5/SD5 AD5 SA7/SD7 AF4 CLK_32K AE3 OVER_CUR# W3 POWER_EN V4 USBCLK W1 BIT_CLK V2 SDAT A_IN U4 DDC_SDA M4 FP_DAT A12/SA12 L1 FP_DAT A0/SA0 K3 FP_DAT A13/SA13 K2 Signal Name Pin No. FP_DAT A14/SA14 K1 FP_DAT A2/SA2 J3 FP_DAT A1/SA1 J2 FP_DAT A3/SA3 J1 FP_DAT A15/SA15 H2 FP_DAT A16/SA_OE# H3 FP_DAT A4//SA4 H1 FP_DAT A8//SA8 G1 FP_DAT A5/SA5 G2 FP_DAT A7//SA7 G3 FP_DAT A6/SA6 G4 FP_DAT A9//SA9 F1 FP_DAT A17/MASTER# F3 FP_DAT A10//SA10 E2 FP_DAT A11/SA11 D1 FP_VSYNC C1 FP_HSYNC C2 ENA_DISP B1 TVCLK B2 PIXEL0 A1 PIXEL3 C4 PIXEL6 D5 PIXEL4 B3 PIXEL1 A2 PIXEL2 A3 PIXEL11 C5 PIXEL9 D6 PIXEL5 B4 PIXEL7 A4 HSYNC C6 VSYNC B5 PIXEL13 D7 PIXEL14 C7 PIXEL10 A5 PIXEL8 B6 VID_CLK A6 PIXEL17 C8 VID_VAL B7 PIXEL12 A7 PIXEL15 B8 PIXEL20 D9 PIXEL21 C9 PIXEL16 A8 PIXEL18 B9 PIXEL19 A9 PIXEL23 C10 VID_DATA4 D11 Signal Name Pin No.

www.national.com 226 Revision 4.1 Electrical Specifications(Continued) Geode™ CS5530 VID_DATA3 C11 PIXEL22 B11 VID_DATA0 A11 VID_DATA7 C12 VID_DATA6 B12 VID_DATA5 A12 VID_DATA1 C13 VID_DATA2 B13 PCLK A13 AD1 D14 INTD# B14 INTA# A14 INTB# D15 INTC# C15 AD3 B15 AD0 A15 AD2 C16 AD5 B16 AD7 A16 AD4 C17 AD6 B17 Signal Name Pin No. AD9 A17 AD8 D18 C/BE0# B18 AD12 A18 AD11 B19 AD10 A19 AD15 A20 AD14 B20 AD13 C20 PAR A21 C/BE1# B21 SERR# A22 PERR# B22 LOCK# C22 DEVSEL# A23 TRDY# B23 FRAME# C23 C/BE2# A24 IRDY# B24 AD17 A25 AD18 B25 Signal Name Pin No. AD16 A26 GNT# D24 AD21 C25 AD19 B26 AD22 C26 AD20 E24 AD26 D25 C/BE3# D26 AD23 E25 AD25 G24 STOP# E26 AD24 F25 AD27 F26 AD28 G25 AD29 G26 AD31 H25 AD30 J24 HOLD_REQ# H26 REQ# J25 PCICLK J26 POR# (NAND Output) K24 Signal Name Pin No. Table 5-1. Test Mode Selection (Continued) Figure 5-1. NAND Tree Output Waveform POR# TEST IRQ7 SUSP_3V SUSPA# PSERIAL 100 ns ::: ::: ::: PCICLK

Revision 4.1 227 www.national.com Electrical Specifications(Continued) Geode™ CS5530

5.2 ELECTRICAL CONNECTIONS

5.2.1 Pull-Up Resistors

Table 5-3 lists the pins that are internally connected to a 20- kohm pull-up resistor. When unused, these inputs do not require connection to an external pull-up resistor.

5.2.2 Unused Input Pins

All inputs not used by the system designer and not listed in T able 5-3 should be kept at either V SS or VDD. To pre- vent possible spurious operation, connect active-high inputs to ground through a 20-kohm (±10%) pull-down resistor and active-low inputs to VDD through a 20-kohm (±10%) pull-up resistor.

5.2.3 NC-Designated Pins

Pins designated NC should be left disconnected. Con- necting an NC pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions.

5.2.4 Power/Ground Connections and Decoupling

Testing and operating the CS5530 requires the use of standard high frequency techniques to reduce parasitic effects. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low-impedance wiring, and by using all of the V DD and VSS pins.

5.3 ABSOLUTE MAXIMUM RATINGS

Table 5-4 lists absolute maximum ratings for the CS5530. Stresses beyond the listed ratings may cause permanent damage to the device. Exposure to conditions beyond these limits may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings may also result in reduced useful life and reliability These are stress rat- ings only and do not imply that operation under any condi- tions other than those listed under Table 5-5 is possible.

5.4 RECOMMENDED OPERATING

Table 5-5 lists the recommended operating conditions for the CS5530. Table 5-3. Pins with Weak Internal Resistor Signal Name Type Ball No. Internal PU IOR# I/O AE12 PU IOW# I/O AC11 PU MEMR# I/O AE19 PU MEMW# I/O AF20 PU SBHE# I/O AE17 PU SA[19:0]/ SD[19:0] I/O AD10, AE11, AF12, AD11, AE25, AD24, AD22, AE21, AF21, AC20, AD19, AF19, AF4, AF5, AD5, AF6, AC6, AD9, AE6, AD9 PU Table 5-4. Absolute Maximum Ratings Parameter Min Max Units Comments Operating Case Temperature 110 °C Power Applied Storage Temperature –65 150 °C No Bias Supply Voltage 4.0 V Voltage On Any Pin –0.5 5.5 V Input Clamp Current, I IK –0.5 10 mA Power Applied Output Clamp Current, IOK 25 mA Power Applied Table 5-5. Recommended Operating Conditions Symbol Parameter Min Max Units Comments TC Operating Case Temperature 0 85 °C VDD Supply Voltage 3.0 3.6 V Note: For video interface specific parameters, refer to Table 5-15 "Video Interface: Setup/Hold and Delay Times" on page 235.

www.national.com 228 Revision 4.1 Electrical Specifications(Continued) Geode™ CS5530

5.5 DC CHARACTERISTICS

Table 5-6. DC Characteristics (at Recommended Operating Conditions) Symbol Parameter Min Typ Max Units Comments VIL Low Level Input Voltage All inputs except PCI –0.3 0.8 V PCI –0.5 0.3V CC VIH High Level Input Voltage All inputs except 5V tolerant and PCI 2.0 1.1V DD V 5V tolerant 2.0 5.5 PCI 0.5V CC VCC +0.5 VOL Low Level Output Voltage 4m A 0 . 4 V I OL =4m A ,N o t e1 8m A 0 . 4 I OL =8m A ,N o t e1 16 mA 0.4 I OL =1 6m A ,N o t e1 PCI 0.4 USB 0.3 R L =1 5K Ω to VDD , Note 1 VOH High Level Output Voltage 4m A 2 . 4 V I OH =– 4m A ,N o t e1 8m A 2 . 4 I OH =– 8m A ,N o t e1 16 mA 2.4 I OH =– 1 6m A ,N o t e1 PCI V CC –0.5 USB 2.8 3.6 R L =1 5K Ω to VDD , Note 1 IIL Low Level Input Leakage Current All inputs except those with internal PUs –10 10 µA V IN = VSS, See Table 5-3 Inputs with internal PUs –200 –10 IIH High Level Input Leakage Current –10 10 µA V IN =V DD VH Schmitt (smt) Trigger Hysteresis Voltage

0.5 V Note 1

VDI USB - Differential Input Sensitivity 0.2 V |(D+)-(D-)| VCM USB - Differential Common Mode Range 0.8 2.5 V Includes V DI range VSE USB - Single Ended Receiver Threshold 0.8 2.0 V C IN Input Capacitance 10 pF f = 1 MHz C OUT Output or I/O Capacitance 10 pF f = 1 MHz C CLK CLK Input Capacitance 10 pF f = 1 MHz

Revision 4.1 229 www.national.com Electrical Specifications(Continued) Geode™ CS5530 Core ICC_CORE Active ICC : PCICLK @ 33MHz 180 250 mA Note 2 ICCSM_CORE S u s p e n dM o d eICC 135 mA Note 2 ICCSS_CORE Standby ICC (Suspended and CLK Stopped) 20 mA f PCICLK =0M H z , Note 2 DAC I CC_DAC Active ICC <0.3 60 mA Min is I CC inactive, Note 2 PLL I CC_PLL Active ICC 5m A N o t e 2 Notes: 1. Pins with this buffer type are listed alphabetically in Table 2-3 "352 TBGA Pin Assignments - Sorted Alpha- betically by Signal Name" on page 18. 2. Not 100% tested. Table 5-6. DC Characteristics (at Recommended Operating Conditions) (Continued) Symbol Parameter Min Typ Max Units Comments

www.national.com 230 Revision 4.1 Electrical Specifications(Continued) Geode™ CS5530

5.6 AC CHARACTERISTICS

The following tables list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. The rising-clock- edge reference level, V REF , and other reference levels are shown in Table 5-7. Input or output signals must cross these levels during testing. Input setup and hold times are specified minimums that define the smallest acceptable sampling window for which a synchronous input signal must be stable for correct oper- ation. Note: All AC tests are at V DD = 3.0V to 3.6V , TC =0 oCt o 85oC, CL = 50 pF unless otherwise specified. Figure 5-2. Drive Level and Measurement Points for Switching Characteristics Table 5-7. Drive Level and Measurement Points for Switching Characteristics Symbol Voltage (V) VREF 1.5 VIHD 2.3 VILD 0.3 CLK OUTPUTS INPUTS VIHD VILD VREF Valid Input Valid Outputn+1Valid Outputn VREF VREF VILD VIHD Min Max Legend: A = Maximum Output Delay Specification B = Minimum Output Delay Specification C = Minimum Input Setup Specification D = Minimum Input Hold Specification TX B A CD Table 5-8. AC Characteristics of Specification Compliant Interface Signals Interface Signal Group Specification Name IDE Interface Signals ATA-4 Specification USB Interface Signals USB Specification, Version 1.0 PCI Bus Interface Signals PCI Bus Specification, Revision 2.1 ISA Bus Interface Signals Abides industry standards Note: The interface signal groups listed in T able 5-8 adhere to the timing parameters given in the corresponding specification. For details, refer to those specifications.

Revision 4.1 231 www.national.com Electrical Specifications(Continued) Geode™ CS5530 Notes: 1. Worst case duty cycle. 2. Duty cycle is a function of PLL post divider. 3. Programmable to standard video frequencies. 4. Typical jitter < 650 ps peak-to-peak. 5. CLK_14MHZ input jitter < 500 ps peak-to-peak. 6. CLK_32K jitter = period of CLK_14MHZ 7. CLK_32K output frequency = CLK_14MHZ/436.95621. 8. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 5-3. Figure 5-3. 3.3V PCICLK Waveform Table 5-9. Clock Characteristics Symbol Parameter Min Max Duty Cycle Unit Comments Output Signals tf,tLcyc,tHcyc DCLK Frequency 25 157.5 30/70 MHz Notes 1 through 5 tLcyc,tHcyc CLK_32K Frequency 32.768 50/50 kHz Notes 6 and 7 tLcyc,tHcyc CLK_14MHZ Frequency 14.31818 45/55 MHz Input Signal t cyc PCICLK Cycle Time 30 ∞ ns tHIGH PCICLK High Time 11 ns tLOW PCICLK Low Time 11 ns -- PCICLK Slew Time 1 4 V/ns Note 8

0.3 VCC

0.4 VCC

0.5 VCC

0.6 VCC tLOW

0.2 VCC

0.4 VCC , peak-to-peak

(minimum)

www.national.com 232 Revision 4.1 Electrical Specifications(Continued) Geode™ CS5530 Figure 5-4. CPU Interface Timing Table 5-10. CPU Interface Timings Symbol Parameter Min Max Unit Comments tSMI Rising PCICLK to SMI# 3 9 ns tSUSP# Rising PCICLK to SUSP# 6 9 ns tSUSP Asetup SUSPA# setup to rising PCICLK 0 ns tSUSP Ahold SUSPA# hold from rising PCICLK 1 ns -- IRQ13 Input Asynchronous input for IRQ decode. -- INTR Output Asynchronous output from IRQ decode. -- SMI# Output Asynchronous output from SMI decode. PCICLK SMI# tSMI SUSP# Valid Input tSUSPAsetup tSUSPAhold SUSPA# tSUSP

Revision 4.1 233 www.national.com Electrical Specifications(Continued) Geode™ CS5530 Figure 5-5. Audio Interface Timing Table 5-11. Audio Interface Timings Symbol Parameter Min Max Unit Comments tBITCLK Rising BIT_CLK to SYNC 5 16 ns tSDAT Rising BIT_CLK to SDATA_OUT 5 17 ns tSDATsetup SDATA_IN setup to falling BIT_CLK 15 ns tSDAThold SDATA_IN hold from falling BIT_CLK 5 ns BIT_CLK SYNC SDATA_OUT SDATA_IN tBITCLK tSDAT Valid Input tSDATsetup tSDAThold

www.national.com 234 Revision 4.1 Electrical Specifications(Continued) Geode™ CS5530

5.7 VIDEO CHARACTERISTICS

The following tables and figures describe the DC/AC char- acteristics of the CS5530 video interface. It is divided into the following categories:  Recommended Operating Conditions  Miscellaneous Operating Characteristics  Analog Output Rise/Settle Times  Setup/Hold and Delay Times Additionally, Figure 5-8 is provided showing a typical video connection diagram. Table 5-12. Video Interface: Recommended Operating Conditions Symbol Parameter Min Typ Max Units Comments AV DD Power Supply connected to AVDD1, AVDD2 and AVDD3 3.0 3.3 3.6 V R L Output Load on each of the pins IOUTR, IOUTG and IOUTB

37.5 Ohms

IOUT Output Current on each of the pins IOUTR, IOUTG and IOUTB 21 mA R SET Value of the full-scale adjust resistor connected to IREF

732 Ohms This resistor should have a

1% tolerance. VEXT REF External voltage reference con- nected to the EXTVREFIN pin 1.235 V IREF Current flow through the resistor connected to the IREF pin 2.2 mA Table 5-13. Video Interface: Miscellaneous Operating Characteristics Symbol Parameter Min Typ Max Units Comments White Level Relative to Black 16.74 17.62 18.50 mA EXTVREFIN Leakage Current 2 µA IAVDD AV DD Supply Current 60 mA Table 5-14. Video Interface: Analog Output Rise/Settle Times Symbol Parameter Min Typ Max Units Comments trise Analog Output Rise Time 2 ns Notes 1 and 2 tsettle Analog Output Settling Time 4 ns Notes 1 and 3 Notes: 1. Timing measurements are made with a 75 ohm doubly-terminated load, with VEXTREF = 1.235V and R SET = 732 ohms. 2. 10% to 90% of full-scale transition. 3. Full-scale transition: time from output minimum to maximum, not including clock and data feedthrough.

www.national.com 236 Revision 4.1 Electrical Specifications(Continued) Geode™ CS5530 Figure 5-7. VID_RDY Delays VID_CLK VID_RDY (Early) VID_RDY MinDelayE VID_RDY MaxDelayE VID_RDYMin DelayN VID_RDY MaxDelayN VID_RDY (Normal)

Revision 4.1 237 www.national.com Electrical Specifications(Continued) Geode™ CS5530 Figure 5-8. Typical Video Connection Diagram VDD AVDD IREF EXTVREFIN AVSS IOUTG IOUTR AVSS AVSS IOUTB AVSS VDD L4 L5 RSET VEXTREF One-point ground To RGBL2 C7 C8 R3 C6 Video Connector Legend Part Designator Value R1-R3 75 Ohms, 1% RSET 732 Ohms, 1% C1-C6 33 pF C7 0.1 µF , Ceramic C8 2.2 µF , Electrolytic L1-L3 (Optional) 120 Ohm Ferrite Bead L4-L5 (Optional) 600 Ohm Ferrite Bead L1C1

www.national.com 238 Revision 4.1 Geode™ CS5530

6.0 Mechanical Specifications

Mechanical dimensions for the 352-T erminal TBGA (T ape Ball Grid Array) package for the Geode CS5530 are pro- vided in this section. Table 6-1 provides the values for the dimensions given in Figure 6-1. Table 6-1. 352 TBGA Package Dimension Symbol Millimeters Minimum Nominal Maximum A- - - - 1 . 7 A1 0.5 0.6 0.7 A2 -- -- 1.0 b 0.60 0.75 0.90 D 35.0 BSC D1 31.75 BSC D2 33.4 33.6 33.8 D3 17.9 18.1 18.3 D4 15.4 15.6 15.8 E 35.0 BSC E1 31.75 BSC E2 33.4 33.6 33.8 E3 17.9 18.1 18.3 E4 15.4 15.6 15.8 e 1.27 BSC s 0.635 BSC aaa 0.15 Die Size < or = 12

Revision 4.1 239 www.national.com Mechanical Specifications(Continued) Geode™ CS5530 Figure 6-1. 352-Terminal TBGA Mechanical Package Outline A b A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1718 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF M S e S A B B A1aaa C C D EE2E3E4

0.15 C B

M0.1 CA B Note:Tie-bar feature (four corners) Non Tie-bar Type Tie-bar Type

0.15 C A

Detail "B" 0.2 0.25 Min. optional, depending upon assembly location. Detail "A" e

www.national.com 240 Revision 4.1 Geode™ CS5530 Appendix A Support Documentation A.1 REVISION HISTORY This document is a report of the revision/creation process of the data book for the Geode CS5530 I/O companion. Any revisions (i.e., additions, deletions, parameter correc- tions, etc.) are recorded in the tables below. Revision # (PDF Date) Revisions / Comments

0.0 Creation Phase

0.1 (1/18/99) First preliminary release to web while being circulated for engineering approval for a rev 1.0 release. 1.0 (3/24/99) First release to web after engineering approval. 2.0 (4/6/99) Major edit to current revision was updating the mechanical package. 3.0 (6/28/99) Changed to National Semiconductor document format. Added changes from revisions 1.0, 2.0, and 3.0 of the data book addendum. Used “General Description” from newly created Product Overview (references GXLV). 3.1(7/14/99) Added minor changes for clarification purposes. 3.2 (8/27/99) Added Geode™ technology verbiage and CS prefix. Also F3BAR+Memory Offset 10h and 12h were documented incorrectly. 4.0 (2/2/00) Many corrections to registers including reset values and notes changes. Added minor clarfications and NAND T ree Test Mode. 4.1 (4/1/00) Minor format changes. No technical changes.

Geode™ CS5530 I/O Companion Multi-Function South Bridge National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 F r a n c a i sT e l : + 3 3( 0 )14 19 18 7 9 0 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. T el: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.