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Low Input Current (100 pA), Chopper- stabilized Instrumentation Amplifier Scalable Input Span (Bipolar/Unipolar) - 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V,
2.5 V, 5 V
- External: 10 V, 100 V Wide VREF Input Range (+1 to +5 V) Fourth Order Delta-Sigma A/D Converter Easy to Use Three-wire Serial Interface Port - Programmable/Auto Channel Sequencer with Conversion Data FIFO - Accessible Calibration Registers per Channel - Compatible with SPI™ and Microwire™ System and Self Calibration Eight Selectable Word Rates - Up to 617 Sps (XIN = 200 kHz) - Single Conversion Settling - 50/60 Hz ±3 Hz Simultaneous Rejection Single +5 V Power Supply Operation - Charge Pump Drive for Negative Supply - +3 to +5 V Digital Supply Operation Low Power Consumption: 6.0 mW General Description The CS5521/22/23/24/28 are highly integrated ΔΣ ana- log-to-digital converters (ADCs) which use charge- balance techniques to achieve 16-bit (CS5521/23) and 24-bit (CS5522/24/28) performance. The ADCs come as either two-channel (CS5521/22), four-channel (CS5523/24), or eight-channel (CS5528) devices and include a low-input-current, chopper-stabilized instru- mentation amplifier. To permit selectable input spans of 25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs include a PGA (programmable gain amplifier). To ac- commodate ground-based thermocouple applications, the devices include a charge pump drive which provides a negative bias voltage to the on-chip amplifiers. These devices also include a fourth-order ΔΣ modulator followed by a digital filter which provides eight selectable output word rates. The digital filters are designed to settle to full accuracy within one conversion cycle and when operated at word rates below 30 Sps, they reject both 50 Hz and 60 Hz interference. These single-supply products are ideal solutions for measuring isolated and non-isolated, low-level signals in process control applications.
ORDERING INFORMATION
See page 53. VA+ AGND VREF+ VREF- VD+ DGND XIN XOUT NBV Latch Differential Digital Filter 4th Order ΔΣ Modulator Clock Gen. MUX AIN2+ CS5524 Shown AIN2- AIN1+ AIN1- AIN4+ AIN4- AIN3+ AIN3- A0 A1CPD Controller, Programmable Gain Setup Registers, Data FIFO & Calibration Registers Channel Scan Logic Serial Port Interface X20 SDO SDI SCLK CS JUL ‘09 DS317F8
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Table 1. Relationship between Full Scale Input, Gain Factors, and Internal Analog
CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25° C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND, NBV = -2.1 V, XIN = 32.768 kHz, CFS1-CFS0 = ‘00’, OWR (Output Word Rate) = 15 Sps, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.) Notes: 1. Applies after system calibration at any temperature within -40° C ~ +85° C. 2. Specifications guaranteed by desi gn, characterization, and/or test. 3. Specification applies to the device only and does not include any effects by external parasitic thermocouples. LSBN: N is 16 for the CS5521/23 and N is 24 for the CS5522/24/28 4. Drift over specified temperature range after calibration at power-up at 25° C. 5. Measured with Charge Pump Drive off. 6. All outputs unloaded. All input CMOS levels and the CS5521/23 do not have a low power mode. Parameter CS5521/23 CS5522/24/28 UnitMin Typ Max Min Typ Max Accuracy Resolution - - 16 - - 24 Bits Linearity Error - ±0.0015 ±0.003 - ±0.0007 ±0.0015 %FS Bipolar Offset (Note 3) - ±1± 2 - ±16 ±32 LSB N Unipolar Offset (Note 3) - ±2 ±4- ±32 ±64 LSB N Offset Drift (Notes 3 and 4) - 20 - - 20 - nV/°C Bipolar Gain Error - ±8 ±31 - ±8 ±31 ppm Unipolar Gain Error - ±16 ±62 - ±16 ±62 ppm Gain Drift (Note 4) - 1 3 - 1 3 ppm/°C Power Supplies Power Supply Currents (Normal Mode) I (Note 5)ID+ INBV 1.2 110 400 1.6 150 570 1.5 110 525 2.1 150 700 mA µA µA Power Consumption (Note 6) Normal Mode Low Power Mode Sleep N/A 7.0 N/A 500 N/A 10.1 5.5 500 14.8 7.5 mW mW µW Power Supply Rejection Positive Supplies dc NBV 120 110 120 110 dB dB
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ANALOG CHARACTERISTICS (Continued) Notes: 7. For the CS5528, the 25 mV, 55 mV and 100 mV rang es cannot be used unless NBV is powered at -1.8 to -2.5 V 8. See the section of the data sheet which discusse s input models. Chop clock is 256 Hz (XIN/128) for PGIA (programmable gain instrumentation amplifier). XIN = 32.768 kHz. 9. The maximum full scale signal can be limited by satu ration of circuitry within the internal signal path. Parameter Min Typ Max Unit Analog Input Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V NBV = AGND Range = 25 mV, 55 mV, or 100 mV (Note 7) Range = 1 V, 2.5 V, or 5 V -0.150 NBV 1.85 0.0 0.950 VA+ 2.65 VA+ V V V V CVF Current on AIN+ or AIN- (Note 8) Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V 100 300 pA nA Input Current Drift (Note 8) Range = 25 mV, 55 mV, or 100 mV - 1 - pA/°C Input Leakage for Multiplexer when Off - 10 - pA Common Mode Rejection dc 50, 60 Hz 120 120 dB dB Input Capacitance - 10 - pF Voltage Reference Input Range (VREF+) - (VREF-) 1 2.5 VA+ V VREF+ (VREF-)+1 -V A + V VREF- NBV - (VREF+)-1 V CVF Current (Note 8) - 5.0 - nA Common Mode Rejection dc 50, 60 Hz 110 130 dB dB Input Capacitance - 16 - pF System Calibration Specifications Full Scale Calibration Range (VREF = 2.5V) Bipolar/Unipolar Mode 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 0.40 1.0 2.0 32.5 71.5 105 1.30 3.25 VA+ mV mV mV V V V Offset Calibration Range Bipolar/Unipolar Mode 25 mV 55 mV 100 mV (Note 9) 1 V 2.5 V 5 V ±12.5 ±27.5 ±50 ±0.5 ±1.25 ±2.50 mV mV mV V V V
TYPICAL RMS NOISE, CS5521/23 (Notes 10 and 11) Notes: 10. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C. 11. To estimate Peak-to-Peak Noise, multiply RM S noise by 6.6 for all ranges and output rates. 12. For input ranges <100 mV and output rates ≥60 Sps, 16.384 kHz chopping frequency is used. TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 (Note 13) Notes: 13. For bipolar mode, the number of bits of Nois e Free Resolution is LOG((2XInput Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. For unipolar mode, the number of bits of Noise Free Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the CS5521/23’s output conversions are 16 bits. Noise free Resolution numbers are based upon VREF = 2.5 V and XIN = 32.768 kHz. The values will be affected directly by changes in VREF, but the effects due to changes in the XIN frequency will be minor. Output Rate (Sps) -3 dB Filter Frequency Input Range, (Bipolar/Unipolar Mode) 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 15.0 12.7 280 nV 440 nV 810 nV 5.7 µV 14 µV 28 µV 84.5 (Note 12) 70.7 11 µV 27 µV 43 µV 458 µV 1.1 mV 2.4 mV Output Rate (Sps) -3 dB Filter Frequency Input Range, (Bipolar Mode) 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 1.88 1.64 16 16 16 16 16 16 3.76 3.27 16 16 16 16 16 16 7.51 6.55 15 16 16 16 16 16 15.0 12.7 15 15 15 16 16 16 30.0 25.4 14 14 14 14 14 14 61.6 (Note 12) 50.4 12 12 12 12 12 12 8 4 . 5 ( N o t e 1 2 ) 7 0 . 7 999999 1 0 1 . 1 ( N o t e 1 2 ) 8 4 . 6 888888
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TYPICAL RMS NOISE, CS5522/24/28 (Notes 14 and 15) Notes: 14. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C. 15. To estimate Peak-to-Peak Noise, multiply RM S noise by 6.6 for all ranges and output rates. 16. For input ranges <100 mV and output rates ≥60 Sps, 16.384 kHz chopping frequency is used. TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 (Note 17) Notes: 17. For bipolar mode, the number of bits of Nois e Free Resolution is LOG((2XInput Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. For unipolar mode, the number of bits of Noise Free Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the CS5522/24/28’s output conversions are 24 bits. Noise free Resolution numbers are based upon VREF = 2.5 V and XIN = 32.768 kHz. The values will be affected directly by changes in VREF, but the effects due to changes in the XIN frequency will be minor. Output Rate (Sps) -3 dB Filter Frequency Input Range, (Bipolar/Unipolar Mode) 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 1.88 1.64 90 nV 95 nV 140 nV 1.5 µV 3 µV 6 µV 3.76 3.27 110 nV 130 nV 190 nV 2 µV 4 µV 8 µV 7.51 6.55 170 nV 200 nV 275 nV 2.5 µV 6 µV 11.5 µV 15.0 12.7 250 nV 330 nV 580 nV 4.5 µV 10 µV 20 µV 30.0 25.4 500 nV 1 µV 1.5 µV 16 µV 45 µV 85 µV 61.6 (Note 16) 50.4 2 µV 4 µV 8 µV 72 µV 195 µV 350 µV 84.5 (Note 16) 70.7 10 µV 20 µV 35 µV 340 µV 900 µV 2 mV 101.1 (Note 16) 84.6 30 µV 60 µV 105 µV 1.1 mV 3 mV 5.3 mV Output Rate (Sps) -3 dB Filter Frequency Input Range, (Bipolar Mode) 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 1.88 1.64 16 17 18 18 18 18 3.76 3.27 16 17 17 17 18 18 7.51 6.55 15 16 17 17 17 17 15.0 12.7 15 16 16 16 16 16 30.0 25.4 14 14 14 14 14 14 61.6 (Note 16) 50.4 12 12 12 12 12 12 84.5 (Note 16) 70.7 10 10 10 10 10 10 1 0 1 . 1 ( N o t e 1 6 ) 8 4 . 6 888888
5 V DIGITAL CHARACTERISTICS (TA = 25° C; VA+, VD+ = 5 V ±5%; GND = 0;
See Notes 2 and 18.)) Notes: 18. All measurements performed under static conditions. 19. I out = -100 µA unless stated otherwise. (VOH = 2.4 V @ I out = -40 µA.) 3 V DIGITAL CHARACTERISTICS (TA = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0; See Notes 2 and 18.) Parameter Symbol Min Typ Max Unit High-level Input Voltage All Pins Except XIN and SCLK XIN SCLK VIH 0.6 VD+ (VD+)-0.5 (VD+) - 0.45 V V V Low-level Input Voltage All Pins Except XIN and SCLK XIN SCLK V IL - 0.8 1.5 0.6 V V V High-level Output Voltage All Pins Except CPD and SDO (Note 19) CPD, I out = -4.0 mA SDO, Iout = -5.0 mA VOH (VA+) - 1.0 (VD+) - 1.0 (VD+) - 1.0 V V V Low-level Output Voltage All Pins Except CPD and SDO, I out = 1.6 mA CPD, Iout = 2 mA SDO, Iout = 5.0 mA VOL 0.4 0.4 0.4 V V V Input Leakage Current I in -± 1 ± 1 0 µ A 3-state Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9 - p F Parameter Symbol Min Typ Max Unit High-level Input Voltage All Pins Except XIN and SCLK XIN SCLK VIH 0.6 VD+ (VD+)-0.5 (VD+) - 0.45 V V V Low-level Input Voltage All Pins Except XIN and SCLK XIN SCLK V IL -
0.16 VD+
0.3 0.6 V V V High-level Output Voltage All Pins Except CPD and SDO, I out = -400 µA CPD, Iout = -4.0 mA SDO, Iout = -5.0 mA VOH (VA+) - 0.3 (VD+) - 1.0 (VD+) - 1.0 V V V Low-level Output Voltage All Pins Except CPD and SDO, I out = 400 µA CPD, Iout = 2 mA SDO, Iout = 5.0 mA VOL 0.3 0.4 0.4 V V V Input Leakage Current I in -± 1 ± 1 0 µ A 3-state Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9 - p F
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RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; See Note 20.) Notes: 20. All voltages with respect to ground. ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 20.) Notes: 21. No pin should go more negative than NBV - 0.3 V. 22. Applies to all pins including continuous overvo ltage conditions at the analog input (AIN) pins. 23. Transient current of up to 10 0 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. 24. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Ratio Unit Modulator Sampling Frequency f s XIN/4 Hz Filter Settling Time to 1/2 LSB (Full-scale Step) t s 1/fout s Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog VD+ VA+ 2.7 4.75 5.0 5.0 5.25 5.25 V V Analog Reference Voltage (VREF+) - (VREF-) VRef diff 1.0 2.5 VA+ V Negative Bias Voltage NBV -1.8 -2.1 -2.5 V Parameter Symbol Min Typ Max Unit DC Power Supplies (Note 21) Positive Digital Positive Analog VD+ VA+ -0.3 -0.3 +6.0 +6.0 V V Negative Bias Voltage Negative Potential NBV +0.3 -2.1 -3.0 V Input Current, Any Pin Except Supplies (Note 22 and 23) I IN -- ± 1 0 m A Output Current I OUT -- ± 2 5 m A Power Dissipation (Note 24) PDN - - 500 mW Analog Input Voltage VREF pins AIN Pins V INR VINA NBV -0.3 NBV -0.3 (VA+) + 0.3 (VA+) + 0.3 V V Digital Input Voltage V IND -0.3 - (VD+) + 0.3 V Ambient Operating Temperature T A -40 - 85 °C Storage Temperature T stg -65 - 150 °C
SWITCHING CHARACTERISTICS (TA = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF.)) Notes: 25. Device parameters are specified with a 32 .768 kHz clock; however, clocks up to 200 kHz (CS5522/24/28) or 130 kHz (CS5521/23) can be used for increased throughput. 26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 28. Applicable when SCLK is continuously running. Specifications are subject to change without notice. Parameter Symbol Min Typ Max Unit Master Clock Frequency (Note 25) External Clock or Internal Oscillator (CS5522/24/28) (CS5521/23) XIN 32.768 32.768 200 130 kHz kHz Master Clock Duty Cycle 40 - 60 % Rise Times (Note 26) Any Digital Input Except SCLK SCLK Any Digital Output t rise 1.0 100 µs µs ns Fall Times (Note 26) Any Digital Input Except SCLK SCLK Any Digital Output t fall 1.0 100 µs µs ns Start-up Oscillator Start-up Time XTAL = 32.768 kHz (Note 27) t ost -5 0 0- m s Serial Port Timing Serial Clock Frequency SCLK 0 - 2 MHz SCLK Falling to CS Falling for continuous running SCLK (Note 28) t0 100 - - ns Serial Clock Pulse Width High Pulse Width Low 250 250 ns ns SDI Write Timing CS Enable to Valid Latch Clock t 3 50 - - ns Data Set-up Time prior to SCLK rising t 4 50 - - ns Data Hold Time After SCLK Rising t 5 100 - - ns SCLK Falling Prior to CS Disable t 6 100 - - ns SDO Read Timing CS to Data Valid t 7 -- 1 5 0 n s SCLK Falling to New Data Bit t 8 -- 1 5 0 n s CS Rising to SDO Hi-Z t 9 -- 1 5 0 n s
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Figure 1. Continuous Running SCLK Timing (Not to Scale) Figure 2. SDI Write Timing (Not to Scale) Figure 3. SDO Read Timing (Not to Scale)
1.1 Analog Input
Figure 4. Multiplexer Configurations
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1.1.1 Instrumentation Amplifier
amplifier is 1.85 V to 2.65 V with NBV grounded. AIN- must stay between NBV and VA+. CFS bits in their default states (cleared to logic 0s). and input sampling currents.
30 Sps and lower, 256 Sps chopping is recommended,
tings, 4096 Hz chopping is recommended.
1.1.2 Coarse/Fine Charge Buffers
designed to accommodate rail-to-rail input signals. gain buffer amplifier is NBV to VA+. (XIN = 32.768 kHz, see Figure 6). Figure 5. Input Models for AIN+ and AIN- pins, ≤100 Figure 6. Input Models for AIN+ and AIN- pins, >100
1.1.3 Analog Input Span Considerations
the Voltage Reference section for more details. values in Table 1 must be scaled accordingly.
1.1.4 Measuring Voltages Higher than 5 V
table assume a 2.5 V VREF voltage.
- The 2.8 V limit at the output of the 20X amplifier is the differential output voltage.
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high-voltage (>5 V) measurement.
1.1.5 Voltage Reference
VREF- pin can not go below NBV. can be determined from the models shown.
1.2 Overview of ADC Register Structure
registers for the CS5523/24. Figure 7. Input Ranges Greater than 5 V Figure 8. Input Model for VREF+ and VREF- Pins
flags which indicate converter operation. tails are given in the following pages. commands (the first 8 bits into the serial port). Figure 9. CS5523/24 Register Diagram
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1.2.1 System Initialization
After power is first applied to the CS5521/22/2324/28 devices, the user should wait for the oscillator to start before attempting to com- municate with the converter. If a 32.768 kHz crys- tal is used, this may be 500 milliseconds. The initialization sequen ce should be as follows: Initialize the serial port by sending the port initial- ization sequence of 15 bytes of all 1's followed by one byte with the following bit contents '1111 110'. This sequence places the chip in the command mode where it waits for a valid command to be written. The first command should be to perform a system reset. This is accomplished by writing a logic 1 to the RS (Reset System) bit in the configu- ration register. After a rese t the RV bit is set until the configuration register is read. The user must then write a logic 0 to the RS bit to take the part out of reset mode. Any other bits written to the config- uration register at this ti me will be lost. The con- figuration register must be written again once RS= 0 to set any other bits to their desired settings. After a reset, the on-chip registers are initialized to the following states: configuration register: 000040(H) offset registers: 000000(H) gain registers: 400000(H) channel setup registers: 000000(H)
1.2.2 Command Register Quick Reference
Must be logic 0 for these commands. ters associated with respective channels. Note: These bits are ignored when reading the data register. Read from selected register. Must be logic 1 for these commands. These bits are used as pointers to the Setups. Note: The MC bit, must be logic 0 for these bits to take effect. Table 2. Command Register Quick Reference
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1.2.3 Command Register Descriptions
READ/WRITE INDIVIDUAL OFFSET CALIBRATION REGISTER Function: These commands are used to access each offset register separately. CS1 - CS0 decode the registers accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. CS[2:0] (Channel Select Bits)
000 Offset Register 1(All devices)
001 Offset Register 2 (All devices)
010 Offset Register 3 (CS5523/24/28 only)
011 Offset Register 4 (CS5523/24/28 only)
100 Offset Register 5 (CS5528 only)
101 Offset Register 6 (CS5528 only)
110 Offset Register 7 (CS5528 only)
111 Offset Register 8 (CS5528 only)
READ/WRITE INDIVIDUAL GAIN REGISTER Function: These commands are used to access each gain register separately. CS1 - CS0 decode the reg- isters accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. CS[2:0] (Channel Select Bits)
000 Gain Register 1(All devices)
001 Gain Register 2 (All devices)
010 Gain Register 3 (CS5523/24/28 only)
011 Gain Register 4 (CS5523/24/28 only)
100 Gain Register 5 (CS5528 only)
101 Gain Register 6 (CS5528 only)
110 Gain Register 7 (CS5528 only)
111 Gain Register 8 (CS5528 only)
D7(MSB) D6 D5 D4 D3 D2 D1 D0
0 CS2 CS1 CS0 R/W
D7(MSB) D6 D5 D4 D3 D2 D1 D0
0 CS2 CS1 CS0 R/W 010
READ/WRITE CONFIGURATION REGISTER Function: These commands are used to read from or write to the configuration register. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. READ/WRITE CHANNEL-SETUP REGISTER(S) Function: These commands are used to access the channel-setup registers (CSRs). The number of CSRs accessed is determined by the device being used and the number of CSRs that are being accessed (i.e. the depth bits in the configuration register determine the number of levels ac- cessed). This register is 48-bits long (4 Setups) for the CS5521/22, 96-bits long (8 Setups) for the CS5523/24, and 192-bits (16 Setups) long for the CS5528. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. D7(MSB) D6 D5 D4 D3 D2 D1 D0
0000 R / W 011
D7(MSB) D6 D5 D4 D3 D2 D1 D0
0000 R / W 101
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Function: These commands instruct the ADC to perform conversions on the physical input channel point- ed to by the pointer bits (CSRP2 - CSRP0) in the channel-setup registers. The particular type of conversion performed is determined by the states of the conversion control bits (the multiple conversion bit, the loop bit, read convert bit, and the depth pointer bits) in the configuration reg- ister. CSRP [3:0] (Channel Setup Register Pointer Bits)
0000 Setup 1 (All devices)
0001 Setup 2 (All devices)
0010 Setup 3 (All devices)
0011 Setup 4 (All devices)
0100 Setup 5 (CS5523/24/28)
0101 Setup 6 (CS5523/24/28)
0110 Setup 7 (CS5523/24/28)
0111 Setup 8 (CS5523/24/28)
1000 Setup 9 (CS5528 only)
1001 Setup 10 (CS5528 only)
1010 Setup 11 (CS5528 only)
1011 Setup 12 (CS5528 only)
1100 Setup 13 (CS5528 only)
1101 Setup 14 (CS5528 only)
1110 Setup 15 (CS5528 only)
1111 Setup 16 (CS5528 only)
D7(MSB) D6 D5 D4 D3 D2 D1 D0
1 CSRP3 CSRP2 CSRP1 CSRP0 0 0 0
Function: These commands instruct the ADC to perform a calibration on the physical input channel refer- enced which is chosen by the command byte pointer bits (CSRP3 - CRSP0). CSRP [3:0] (Channel Setup Register Pointer Bits)
0100 Setup 5 (CS5523/24/28 only)
0101 Setup 6 (CS5523/24/28 only)
0110 Setup 7 (CS5523/24/28 only)
0111 Setup 8 (CS5523/24/28 only)
CC [2:0] (Calibration Control Bits)
000 Reserved
001 Self-Offset Calibration
010 Self-Gain Calibration
011 Reserved
100 Reserved
101 System-Offset Calibration
110 System-Gain Calibration
111 Reserved
D7(MSB) D6 D5 D4 D3 D2 D1 D0
1 CSRP3 CSRP2 CSRP1 CSRP0 CC2 CC1 CC0
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Function: Part of the serial port re-initialization sequence. SYNC0 Function: End of the serial port re-initialization sequence. NULL Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. D7(MSB) D6 D5 D4 D3 D2 D1 D0 11111111 D7(MSB) D6 D5 D4 D3 D2 D1 D0 11111110 D7(MSB) D6 D5 D4 D3 D2 D1 D0 00000000
1.2.4 Serial Port Interface
of four control lines: CS , SCLK, SDI, SDO. to write to, or read from the serial port’s registers. the port can function as a three-wire interface.
8 SCLKs
8 SCLKs Clear SDO FlagSDO
24 SCLKs
Figure 10. Command and Data Word Timing
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1.2.5 Reading/Writing the Offset, Gain, and
The CS5521/22/23/24/28’s offset, gain, and config- uration registers are acces sed individually and can be read from or written to. To write to an offset, a gain, or the configuration register, the user must transmit the appropriate write command which ac- cesses the particular register and then follow that command with 24 bits of data (refer to Figure 10 for details). For example, to write 0x800000 (hexadeci- mal) to physical channel one’s gain register, the user would transmit the command byte 0x02 (hexadeci- mal) and then follow that command byte with the data 0x800000 (hexadecimal). Similarly, to read physical channel one’s gain register, the user must first transmit the command byte 0x0A (hexadeci- mal) and then read the 24 bits of data. Once an off- set, a gain, or the configuration register is written to or read from, the serial p ort returns to the command mode.
1.2.6 Reading/Writing the Channel-Setup Reg-
The CS5521/22 have two 24-bit channel-setup reg- isters (CSRs). The CS5523/24 have four CSRs, and the CS5528 has eight CSRs (refer to Table 3 for more detail on the CSRs). These registers are ac- cessed in conjunction with the depth pointer bits in the configuration register. Each CSR contains two 12-bit Setups which are programmed by the user to contain data conversion or calibration information such as: 1) state of the output latch pins 2) output word rate 3) gain range 4) polarity 5) the address of a physi cal input channel to be converted. Once programmed, they are used to determine the mode (e.g. unipolar, 15 Sps, 100 mV range etc.) the ADC will operate in when future conversions or calibrations are performed. To access the CSRs, the user must first initialize the depth pointer bits in the configuration register as these bits determine the number of CSRs to read from or write to. For example, to write CSR1 (Setup1 and Setup2), the us er would first program the configuration register’s depth pointer bits with ‘0001’ binary. This notifies the ADC’s serial port that only the first CSR is to be accessed. Then, the user would transmit the write command, 0x05 (hexadecimal) and follow that command with 24 bits of data. Similarly, to read CSR1, the user must transmit the command byte 0x0D (hexadecimal) and then read the 24 bits of data. To write more than one CSR, for instance CSR1 and CSR2 (Setup1, Setup2, Setup3, and Setup4), the user would first set the depth pointer bits in the configu- ration register to ‘0011’ binary. The user would then transmit the write CS R command 0x05 (hexadeci- mal) and follow that with the information for Setup1, Setup2, Setup 3, and Setup 4 which is 48 bits of information. Note that while reading/writing CSRs, two Setups are accessed in pairs as a single 24-bit CSR register. Even if one of the Setups isn’t used, it must be written to or read. Further note that the CSRs are accessed as a closed array – the user can not access CSR2 without accessing CSR1. This requirement means that the depth bits in the config- uration register can only be set to one of the follow- ing states when the CSRs are being read from or written to: 0001, 0011, 0101, 0111, 1001, 1011, 1101, 1111. Examples detailing the power of the CSRs are provided in the Performing Conversions and Reading the Data Conversion FIFO section. Once the CSRs are written to or read from, the serial port returns to the command mode.
Latch Outputs, A1-A0 00 *R Latch Output Pins A1-A0 mimic D23/D11-D22/D10 register bits. Table 3. Channel-Setup Registers
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1.2.6.1 Latch Outputs
The A1-A0 pins mimic the latch output, D23/D11- D22/D10, bits of the channel-setup registers. A1-A0 can be used to control external multiplexers and oth- er logic functions outside the converter. The outputs can sink or source at least 1 mA, but it is recom- mended to limit drive currents to less than 20 μA to reduce self-heating of the chip. T hese outputs are powered from VA+, hence their output voltage for a logic 1 will be limited to the VA+ supply voltage.
1.2.6.2 Channel Select Bits
The channel select, CS1-CS0, bits are used to de- termine which physical input channel will be used when a conversion is perf ormed with a particular Setup.
1.2.6.3 Output Word Rate Selection
The word rate, WR2-WR0, bits of the channel-set- up registers set the output conversion word rate of the converter when a conversion is performed with a particular Setup. The word rates indicated in Table 3 assume a master clock of 32.768 kHz, and scale linearly when usi ng other master clock fre- quencies. Upon reset the converter is set to operate with an output word rate of 15.0 Sps.
1.2.6.4 Gain Bits
The gain bits, G2-G0, of the channel-setup regis- ters set the full-scale differential input range for the ADC when a conversion is performed with a partic- ular Setup. The input ranges in the table assume a
2.5 V reference voltage, and scale linearly when
using other reference voltages.
1.2.6.5 Unipolar/Bipolar Bit
The unipolar/bipolar bit is used to determine the type of conversion, unipolar or bipolar, that will be performed with a particular Setup.
1.2.7 Configuration Register
The configuration register is 24 bits long. The fol- lowing subsections detail the bits in the configura- tion register. Table 4 summarizes the configuration register.
1.2.7.1 Chop Frequency Select
The chop frequency select (CFS1-CFS0) bits are used to set the rate at which the instrumentation amplifier’s chop switches modulate the input sig- nal. The 256 Hz rate is de sirable as it provides the lowest input CVF (sampling) current, <300 pA over -40 to 85 °C. The higher rates can be used to eliminate modulation/alia sing effects as the fre- quency of the input signal increases.
1.2.7.2 Conversion/Calibration Control Bits
The conversion/calibration control bits in the con- figuration register are used to control the particular type of conversion require d for the users applica- tions. In short, the dept h pointer (DP3-DP0) bits determine the number of Set ups that will be refer- enced when conversions are performed. The multi- ple conversion (MC) bit instructs the converter to perform conversions on the number of Setups in the channel-setup registers which are referenced by the depth pointer bits. The converter begins with Setup1 and moves sequentially through the Setups in this mode. The Loop (LP) bit instructs the con- verter to continuously perform conversions until a Stop command is sent to the converter. The read convert (RC) bit instructs the converter to wait until the conversion data is r ead before performing the next conversion or set of conversions.
1.2.7.3 Power Consumption Control Bits
The CS5522/24/28 devices provide three power consumption modes: normal, low power, and sleep. The CS5521/23 provide two power con- sumption modes: normal, and sleep. The normal (default) mode is entered after a power-on reset. In normal mode, the CS5522/ 24/28 typically con-
sume 9.0 mW. The CS5521/ 23 typically consume 6.0 mW. The low-power mode is an alternate mode in the CS5522/24/28 that reduces the consumed power to 5.5 mW. It is en tered by setting bit D8 (the low-power mode bit) in the configuration reg- ister to logic 1. Slightly degraded noise or linearity performance should be expected in the low-power mode. Note that the XI N clock should not exceed 130 kHz in low-power mode. The final two modes accommodated in all devices are referred to as the power save modes. They power down most of the analog portion of the chip and stop filter convolu- tions. The power-save modes are entered whenever the PS/R bit of the configurat ion register is set to logic 1. The particular po wer-save mode entered depends on state of bit D11 (PSS, the Power Save Select bit) in the confi guration register. If PSS is logic 0, the converters enters the standby mode re- ducing the power consump tion to 1.2 mW. If the PSS bit (bit D11) is set to logic zero, the PD bit (bit D10) must be set to one. The standby mode leaves the oscillator and the on- chip bias generator run- ning. This allows the converter to quickly return to the normal or low-power mode once the PS/R bit is set back to a logic 0. If PSS and PS/R in the config- uration register are set to logic 1, the sleep mode is entered reducing the c onsumed power to around 500 μW. Since the sleep mode disables the oscilla- tor, a 500 ms oscillator st art-up delay period is re- quired before returning to the normal or low-power mode.
1.2.7.4 Charge Pump Disable
The pump disable (PD) bit permits the user to turn off the charge pump drive thus enabling the user to reduce the radiation of digital interference from the CPD pin when the charge pump is not being used.
1.2.7.5 Reset System Control Bits
The reset system (RS) bit permits the user to per- form a system reset. A system reset can be initiated at any time by writing a logic 1 to the RS bit in the configuration register. After a system reset cycle is complete, the reset valid (R V) bit is set indicating that the internal logic was properly reset. The RV remains set until the configuration register is read. Note that the user must write a logic 0 to the RS bit to take the part out of the reset mode. No other bits in the configuration regist er can be written at this time. A subsequent write to the configuration reg- ister is necessary to write to any other bits in this register. Once reset, the on-chip registers are ini- tialized to the following states.
1.2.7.6 Data Conversion Error Flags
The oscillation detect (OD) and overflow (OF) bits in the configuration register are flag bits used to in- dicate that the ADC performed a conversion on an input signal that was no t within the conversion range of the ADC. For c onvenience, the OD and OF bits are also in the data conversion word of the CS5521/23. The OF bit is set to logic 1 when the input signal is: 1) more positive than full scale 2) more negative than zero in unipolar mode, or 3) more negative than negative full scale in bipo- lar mode. The OF flag is cleared to logic 0 when a conversion occurs which is not out of range. The OD bit is set to logic 1 any time that an oscil- latory condition is detected in the modulator. This does not occur under normal operating conditions, but may occur when the input is extremely over- ranged. The OD flag will be cleared to logic 0 when the modulator becomes stable. configuration register: 000040(H) offset registers: 000000(H) gain registers: 400000(H) channel setup registers: 000000(H)
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1.R indicates the bit value after the part is reset. 4,096 Hz Amplifier chop frequency. 16,384 Hz Amplifier chop frequency. 1,024 Hz Amplifier chop frequency. D19 Not Used, NU 0 R Must always be logic 0. R Perform single-Setup conversions. MC bit is ignored during calibrations. ister by issuing only one command with MSB = 1. 1) are continuously performed. R Don’t wait for user to finish reading data before starting new conversions. during calibrations. Refer to Calibration Protocol for details. CS5524 has four CSRs, and the CS5528 has 8 CSRs. 2.When the chip is placed in standby mode, the PD bit (bit D10) should be set to 1. R Standby Mode (Oscillator active, allows quick power-up). Sleep Mode (Oscillator inactive). For PD = 1, the CPD pin goes to a Hi-Z output state. Activate a Reset cycle. To return to Normal Operation write bit to zero. No reset has occurred or bit has been cleared (read only). R Bit is clear when an oscillation condition has not occurred (read only). Bit is set when an oscillatory condition is detected in the modulator. R Bit is clear when an overrange condition has not occurred (read only). ative than the negative full scale (bipolar mode). D3-D0 Not Used, NU 0000 R Must always be logic 0. Table 4. Configuration Register
1.3 Calibration
to calculate output words for the ±100 mV range. cuitry of the chip will remain. zero or one (b0 corresponds to bit MSB-1, N=22). Refer to Table 5 for details.
1.3.1 Self Calibration
Table 5. Offset and Gain Registers The gain register span is from 0 to (4-2-22). After Reset the (MSB-1) bit is 1, all other bits are 0.
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VREF- pin as shown in Figure 12.
2.5 V range is an exception because the external
curacy, except for the 2.5 V range.
1.3.2 System Calibration
Figure 11. Self Calibration of Offset (Low Ranges) Figure 12. Self Calibration of Offset (High Ranges) Figure 13. Self Calibration of Gain (All Ranges) Figure 14. System Calibration of Offset (Low Ranges)
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The variables are defined below. V0 = First calibration voltage V1 = Second calibration voltage (greater than V0) Ru = Result of any uncalibrated conversion Ru0 = Result of uncalibrated conversion V0 (24-bit integer or 2’s complement) Ru1 = Result of uncalibrated conversion of V1 (24-bit integer or 2’s complement) Rc = Result of any conversion Rc0 = Desired calibrated result of converting V0 (24-bit integer or 2’s complement) Rc1 = Desired calibrated result of converting V1 (24-bit integer or 2’s complement) Co = Offset calibration register value (24-bit 2’s complement) Cg = Gain calibration register value (24-bit integer)
1.3.3 Calibration Tips
Calibration steps are performed at the output word rate selected by the WR2-WR0 bits of the configu- ration register. Since higher word rates result in conversion words with mo re peak-to-peak noise, calibration should be pe rformed at lower output word rates. Also, to minimize digital noise near the device, the user should wait for each calibration step to be completed be fore reading or writing to the serial port. For maximum accuracy, calibrations should be per- formed for offset and gain (selected by changing the G2-G0 bits of the desired Setup). Note that only one gain range can be calibrated per physical chan- nel. If factory calibration of the user’s system is performed using the system calibration capabilities of the CS5521/22/23/24/28, the offset and gain reg- ister contents can be read by the system microcon- troller and recorded in EEPROM. These same calibration words can then be uploaded into the off- set and gain registers of the converter when power is first applied to the system, or when the gain range is changed.
1.3.4 Limitations in Calibration Range
System calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet. For gain calibration the full-scale input signal can be reduced to the point in which the gain register reaches its upper limit of (4-2 -22 decimal) or FFFFFF (hexadecimal). Under nominal condi- tions, this occurs with a full-scale input signal equal to about 1/4 the nominal full scale. With the converter’s intrinsic gain error, this full-scale input signal may be higher or lower. In defining the min- imum Full Scale Calibration Range (FSCR) under ANALOG CHARACTERISTICS, margin is retained to accommodate the intrinsic gain error. Alterna- tively the input full-scale signal can be increased to a point in which the modulator reaches its 1’s den- sity limit of 80 percent, which under nominal con- dition occurs when the full-scale input signal is 1.5 times the nominal full scale. With the chip’s intrin- sic gain error, this fu ll-scale input signal may be higher or lower. In de fining the maximum FSCR, margin is again incorporated to accommodate the intrinsic gain error. In addition, for full-scale inputs greater than the nominal full-scale value of the range selected, there is some voltage at which var- ious internal circuits ma y saturate due to limited amplifier headroom. This is most likely to occur in the 100 mV range.
1.4 Performing Conversions and Reading
The CS5521/22/23/24/28 offers various modes of performing conversions. The sections that follow detail the differences between the conversion modes. The sections also provide examples illus- trating how to use the c onversion modes with the channel-setup registers and to acquire conversions for further processing. While reading, note that the CS5521/22 have a FIFO which is four words deep. The CS5523/24 have a FIFO which is eight words deep and the CS5528 has a FIFO which is sixteen
conversion words deep. Fu rther note that the type of conversion(s) performed and the way to access the resulting data from the FIFO is determined by the MC (multiple convers ion), the LP (loop), the RC (read convert), and the DP (depth pointer) bits in the configuration register.
1.4.1 Conversion Protocol
The CS552x offer six different conversion modes, which can be categorized into two main types of conversions: one-Setup co nversions, which refer- ence only one Setup, and multiple-Setup conver- sions, which reference any number of Setups. The converter can be instruct ed to perform single con- versions or repeated c onversions (with or without wait) in either of these modes, using the MC, LP, and RC bits in the Configuration Register. The MC bit controls whether the part will do one-Setup or multiple-Setup conversions . The LP bit controls whether the part will pe rform a single or repeated conversion set. When doing repeated conversion sets, the RC bit controls whether or not the convert- er will wait for the data from the current conversion set to be read before beginning the next conversion set. The sections that follow further detail the vari- ous conversion modes.
1.4.1.1 Single, One-Setup Conversion
(LP = 0 MC = 0 RC = X) In this conversion mode, the ADC will perform a single conversion, referencing only one Setup, and return to command mode after the data word has been fully read. The 8-bit command word contains the CSRP bits, which inst ruct the converter which Setup to use when performing the conversion. To perform a single, one-Setup conversion, the MC and LP bits in the Confi guration Register must be set to '0'. Then, the 8-bit command word that refer- ences the desired Setup must be sent to the convert- er. The ADC will then perform a single conversion on the referenced Setup, and SDO will fall to indi- cate that the conversion is complete. Thirty-two SCLKs are then needed to read the conversion word from the data register. The first 8 SCLKs are used to clear the SDO fl ag. During the last 24 SCLKs, the data word will be output from the con- verter on the SDO line. The part returns to com- mand mode immediately af ter the data word has been read, where it waits for the next command to be issued.
1.4.1.2 Repeated One-Setup Conversions with-
(LP = 1 MC = 0 RC = 0) In this conversion mode, the ADC will repeatedly perform conversions, refe rencing only one Setup. The 8-bit command word contains the CSRP bits, which instruct the conver ter which Setup to use when performing the convers ion. Note that in this mode, the part will c ontinually perform conver- sions, and the user need not read every conversion as it becomes available. Although conversions can be read whenever they are needed, they must be read within one conversion cycle (defined by the referenced Setup), as the data word will be over- written when new conversion data becomes avail- able. The SDO line rises and falls to indicate the availability of new conve rsion data. When new data is available, the cu rrent conversion data will be lost, or in the case that the user has only read a part of the conversion wo rd, the remainder of the conversion word will be corrupted. To perform repeated, one -Setup conversions with no wait, the MC bit must be set to '0', the LP bit must be set to '1', and the RC bit must be set to '0' in the Configuration Register. Then, the 8-bit com- mand word that references the desired Setup must be sent to the converter. The ADC will then begin performing conversions on the referenced Setup, and SDO will fall to indicate when a conversion is complete, and data is available. Thirty-two SCLKs are then needed to read the conversion word from the data register. The first 8 SCLKs are used to clear the SDO flag. During the last 24 SCLKs, the data word will be output from the converter on the
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SDO line. If, during the first 8 SCLKs, "00000000" is provided on SDI, the converter will remain in this conversion mode, and continue to perform conversions on the selected Setup. To exit this conversion mode, "11111111" must be provid- ed on SDI during the first 8 SCLKs. If the user de- cides to exit, 24 more SCLKs are required to read the final conversion word from the data register and return to command mode.
1.4.1.3 Repeated One-Setup Conversions with
(LP = 1 MC = 0 RC = 1) In this conversion mode, the ADC will repeatedly perform conversions, refe rencing only one Setup. The 8-bit command word contains the CSRP bits, which instruct the converter which Setup to use when performing the conversion. Note that in this mode, every conversion word must be read. The part will wait for the current conversion word to be read before performing the next conversion. To perform repeated, one -Setup conversions with wait, the MC bit must be set to '0', the LP bit must be set to '1', and the RC bit must be set to '1' in the Configuration Register. Then, the 8-bit command word that references the desired Setup must be sent to the converter. The ADC will then begin per- forming conversions on the referenced Setup, and SDO will fall to indicate when a conversion is com- plete, and data is available. Thirty-two SCLKs are then needed to read the conversion word from the data register. The first 8 SCLKs are used to clear the SDO flag. During the last 24 SCLKs, the data word will be output from the converter on the SDO line. If, during the fi rst 8 SCLKs, "00000000" is provided on SDI, the convert er will remain in this conversion mode, and continue to perform conver- sions on the selected Setup after each data word is read. To exit this conversion mode, "1111 1111" must be provided on SDI during the first 8 SCLKs. If the user decides to ex it, 24 more SCLKs are re- quired to read the final conversion word from the data register and return to command mode.
1.4.1.4 Single, Multiple-Setup Conversions
(LP = 0 MC = 1 RC = X) In this conversion mode, the ADC will perform sin- gle conversions, referenci ng multiple Setups, and return to command mode after the data for all con- versions have been read. The CSRP bits in the command word are ignored in this mode. Instead, the Depth Pointer (DP3-DP0 ) bits in the Configu- ration Register are accessed to determine the num- ber of Setups to reference when collecting the data. The number of Setups referenced will be equal to (DP3-DP0) + 1, and will be accessed in order, be- ginning with Setup1. To perform single, multiple-Setup conversions, the MC bit must be set to '1', and the LP bit must be set to '0' in the Configuration Register. Then, the 8-bit command word to start a conversion must be sent to the converter. Because the CSRP bits of the command word are ignored in this mode, a "start convert" command referencing any of the available Setups will begin the c onversions. The ADC will then perform conversions using the appropriate number of Setups (as dictated by the DP bits in the Configuration Register), beginning with Setup1. The SDO line will fall after the final conversion to indicate that the data is ready. Eight SCLKs, plus
24 SCLKs for each Setup referenced are required to
read the conversion words from the data FIFO. The first 8 SCLKs are used to clear the SDO flag. Ev- ery 24 bits thereafter cons ist of the data words of each Setup that was referenced, until all of the data has been read from the pa rt. The data word from Setup1 is output first, fo llowed by the data word from Setup2, and so on for the appropriate number of Setups. The part returns to command mode im- mediately after the final da ta word has been read, and waits for the next command to be issued.
1.4.1.5 Repeated Multiple-Setup Conversions
(LP = 1 MC = 1 RC = 0) In this conversion mode, the ADC will repeatedly perform conversions, referencing multiple Setups. The CSRP bits in the command word are ignored in this mode. Instead, the Depth Pointer (DP3-DP0) bits in the Configurati on Register are accessed to determine the number of Setups to reference when collecting the data. The number of Setups refer- enced will be equal to (DP3-DP0) + 1, and will be accessed in order, beginning with Setup1. Note that in this mode, the part will continually perform con- versions, looping back to Setup1 when finished with each set, and the user need not read every con- version set as it becomes available. The SDO line rises and falls to indicat e the availability of new conversion data sets. When new data is available, the current conversion data set will be lost, or in the case that the user has only read a part of the conver- sion set, the remainder of the conversion set will be corrupted. To perform repeated, multiple-Setup conversions with no wait, the MC bit must be set to '1', the LP bit must be set to '1', and the RC bit must be set to '0' in the Configuration Register. Then, the 8-bit command word to start a conversion must be sent to the converter. Because the CSRP bits of the command word are ignored in this mode, a "start convert" command referencing any of the available Setups will begin the conversions. The ADC will then perform conversions using the appropriate number of Setups (as dictated by the DP bits in the Configuration Register), beginning with Setup1. The SDO line will fall after the final conversion to indicate that the data is ready. Eight SCLKs, plus read the conversion words from the data FIFO. The first 8 SCLKs are used to clear the SDO flag. Ev- ery 24 bits thereafter consist of the data words of each Setup that was referenced, until all of the data has been read from the part. If, during the first 8 SCLKs, "00000000" is provided on SDI, the con- verter will remain in this conversion mode, and continue to perform co nversions on the desired number of Setups. To ex it this conversion mode, "1111 1111" must be provi ded on SDI during the first 8 SCLKs. If the user decides to exit, 24 more SCLKs for each referenced Setup are required to read the final conversion data set from the FIFO and return to command mode.
1.4.1.6 Repeated Multiple-Setup Conversions
(LP = 1 MC = 1 RC = 1) In this conversion mode, the ADC will repeatedly perform conversions, referencing multiple Setups. The CSRP bits in the command word are ignored in this mode. Instead, the Depth Pointer (DP3-DP0) bits in the Configurati on Register are accessed to determine the number of Setups to reference when collecting the data. The number of Setups refer- enced will be equal to (DP3-DP0) + 1, and will be accessed in order, beginning with Setup1. Note that in this mode, every conversion data set must be read. The part will wait for the current conversion data set to be read before performing the next set of conversions. To perform repeated, multiple-Setup conversions with wait, the MC bit must be set to '1', the LP bit must be set to '1', and the RC bit must be set to '1' in the Configuration Register. Then, the 8-bit com- mand word to start a conversion must be sent to the converter. Because the CSRP bits of the command word are ignored in this mode, a "start convert" command referencing any of the available Setups will begin the conversions. The ADC will then per- form conversions using the appropriate number of Setups (as dictated by the DP bits in the Configura- tion Register), beginning with Setup1. The SDO line will fall after the final conversion to indicate that the data is ready. Eight SCLKs, plus 24
38 DS317F8
SCLKs for each Setup referenced are required to read the conversion words from the data FIFO. The first 8 SCLKs are used to clear the SDO flag. Ev- ery 24 bits thereafter consist of the data words of each Setup that was referenced, until all of the data has been read from the part . If, during the first 8 SCLKs, "0000 0000" is provided on SDI, the con- verter will remain in this conversion mode, and be- gin performing the next set of conversions. To exit this conversion mode, "1111 1111" must be pro- vided on SDI during the first 8 SCLKs. If the user decides to exit, 24 more SCLKs for each referenced Setup are required to read the final conversion data set from the FIFO and return to command mode.
1.4.2 Calibration Protocol
To perform a calibration, the user must send a com- mand byte with its MSB=1, its pointer bits (CSRP3-CSRP0) set to address the desired Setup to be calibrated, and the a ppropriate calibration bits (CC2-CC0) set to choose the type of calibration to be performed. Pr oper calibration assumes that the CSRs have been previously initialized because the information concerning th e physical channel, its filter rate, gain range, and polarity, comes from the channel-setup register being addressed by the pointer bits in the command byte. Once the CSRs are initialized, all future calibra- tions can be performed with one command byte. Once a calibration cycle is complete, SDO falls and the results are stored in either the gain or offset reg- ister for the physical channel being calibrated. Note that if additional calibrations are performed on the same physical channel re ferenced by a different Setup with different filter rates, gain ranges, or con- version modes, the last cal ibration results will re- place the effects from th e previous calibration as only one offset and gain re gister is available per physical channel. One fi nal note is that only one calibration is performed with each command byte. To calibrate all the chan nels additional calibration commands are necessary.
1.4.3 Example of Using the CSRs to Perform
Conversions and Calibrations Any time a calibration co mmand is issued (CB=1 and proper CC2-CC0 bits set) or any time a normal conversion command is issued (CB=1, CC2=CC1=CC0=0, MC=0), the bits D6-D3 (or CSRP3 - CSRP0) in the command byte are used as pointers to address one of the Setups in the chan- nel-setup registers (CSRs). Five example situations that a user might encounter when acquiring a con- version or calibrating th e converter follow. These examples assume that th e user is using a CS5528 (16 Setups) and that its CSRs are programmed with the following physical channel order: Example 1: The configuration register has the following bits as shown: DP3-DP0 = ‘XXXX’, MC = 0, L = 0, RC = X. The command issued is ‘1111 0000’. These settings instruct the converter to convert the 15th Setup once, as CPB3 - CPB0 = ‘1110’ (which happens to be physical channel 6 in this example). SDO falls after physical channel 6 is converted. To read the conversion results, 32 SCLKs are then re- quired. Once acquired, the serial port returns to the command mode. Example 2: The configuration register has the following bits as shown: DP3-DP0 = ‘XXXX’, MC = 0, LP = 1, RC = 1. The command byte issued is ‘1001 1000’. These settings instruct th e converter to repeatedly convert the fourth Se tup as CPB3-CPB0 = ‘0011’ (which happens to be physical channel 2 in this ex- ample). SDO falls after phys ical channel 2 is con- verted. To read the c onversion results 32 SCLKs are required. The first 8 SCLKs are needed to clear the SD0 flag. If ‘0000 0000’ is provided to the SDI pin during the first 8 SCLKs, the conversion is per- formed again on physical channel 2. The converter will remain in data mode until ‘1111 1111’ is pro- vided during the first 8 SCLKs following the fall of
SD0. After ‘1111 1111’ is provided, 24 additional SCLKs are required to tran sfer the last 3 bytes of conversion data before the serial port will return to the command mode. Example 3: The configuration register has the following bits as shown: DP3-DP = ‘0101’, MC = 1, LP = 0, RC = X. The command issued is ‘1XXX X000’. These settings instruct th e converter to perform a single conversion on six Setups once. The order in which the channels are converted is 6, 1, 6, 2, 6, and 3. SDO falls after physical channel 3 is converted. To read the 6 conversion results 8 SCLKs are re- quired to clear the SD0 flag. Then 144 additional SCLKs are required to r ead the conversion data from the FIFO. Again, the order in which the data is provided is the same as the order in which the channels are converted. After the last 3 bytes of the conversion data corresponding to physical channel 3 is read, the serial port automatically returns to the command mode where it will remain until the next valid command byte is received. Example 4: The configuration register has the following bits as shown: DP3-DP0 = ‘1001’, MC = 1, LP = 1, RC = 0. The command byte issued is ‘1XXX X000’. These settings instruct the convert- er to repeatedly perf orm multiple-setup conver- sions using ten Setups. The order in which the channels are converted is: 6, 1, 6, 2, 6, 3, 6, 4, 6, 5. SDO falls after physical channel 5 is converted. To read the 10 conversion results 8 SCLKs with SDI = 0 are required to cl ear the SD0 flag. Then 240 more SCLKs are require d to read the conver- sion data from the FIFO. The order in which the data is provided is the sa me as the order in which the channels are converted. The first 3 bytes of data correspond to the first Setup which in this example is physical channel 6; the next 3 bytes of data cor- respond to the second Setup which in this example is physical channel 1; and, the last 3 bytes of data corresponds to 10th Setup which here is physical channel 5. Since the Set ups are converted in the background, while the data is being read, the user must finish reading the conversion data FIFO be- fore it is updated with new conversions. To exit this conversion mode the user must provide ‘1111 1111’ to SDI during the first 8 SCLKs. If a byte of 1’s is provided, the serial port returns to the command mode only after the conversion data FIFO is emptied (in this case 10 conversions are performed). Note that in this example physical channel 6 is converted five times. Each conversion could be with the same or different filter rates de- pending on the setting of Setups 1, 3, 5, 7 and 9. Note that there is only one offset and one gain reg- ister per physical channel. Therefore, any physical channel can only be calibrated for the gain range selected during calibrat ion. Specifying a different gain range in the Setup other than the range that was calibrated will result in a gain error. Example 5: The configuration register has the following bits as shown: DP3-DP0 = ‘XXXX’, MC = X, LP = X, RC = X. The command issued is ‘1010 1101’. These settings instruct th e converter to perform a system offset calibration of the 6th Setup (which is physical channel 3 in th is example). During cali- bration, the serial port remains in the command mode. Once the calibration is completed, SDO falls. To perform addi tional calibrations, more commands have to be issued. Notes: 1)The configuration register must be written before channel-setup registers (CSRs) because the depth information contained in the configuration regis- ter defines how many of the CSRs to use. 2) The CSRs need to be written regardless of single conversion or multiple single conversion mode. 3) When single-Setup conversions (MC = 0) are de- sired, the channel address is embedded in the command byte. In the multiple-Setup conversion mode (MC = 1), channels are selected in a pre- programmed order based on information con- tained in the CSRs and the depth bits (DP3-DP0)
40 DS317F8
of the configuration register. suing only one command byte. modified version of it has to be issued again. in command mode, once it is in command mode.
1.5 Conversion Output Coding
scriptions section for more details. Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28
1.5.1 Conversion Data FIFO Descriptions
CS5521/23 (EACH 16-BIT CONVERSIONS) CS5522/24/28 (EACH 24-BIT CONVERSION LEVELS) Conversion Data Bits [23:8 for CS5521/23; 23:0 for CS5522/24/28] These bits depict the latest output conversion. OD (Oscillation detect Flag Bit) 0 Bit is clear when oscillatory condition in m odulator does not exist (bit is read only). 1 Bit is set any time an oscillatory condition is detec ted in the modulator. This does not occur under normal operation conditions, but may occur when the input is extremely overranged. The OD flag will be cleared to logic 0 when the modulator becomes stable. OF (Over-range Flag Bit) 0 Bit is clear when over-range condition has not occurred (bit is read only). 1 Bit is set when input signal is more positive than t he positive full scale, more negative than zero (unipolar mode) or when the input is more negative than the negative full scale (bipolar mode). CI (Channel Indicator Bits) [1:0] These bits indicate which physical input channel was converted.
00 Physical Channel 1 (CS5521/23 only)
01 Physical Channel 2 (CS5521/23 only)
10 Physical Channel 3 (CS5523 only)
11 Physical Channel 4 (CS5523 only)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 M S B 1 4 1 3 1 2 1 1 1 09 87654 D 1 1 D 1 0 D 9D 8D 7D 6 D 5 D 4D 3D 2D 1D 0 3 2 1 LSB 1 1 1 0 CI1 CI0 OD OF D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 M S B 2 22 12 01 91 8 1 7 1 61 51 41 31 2 D 1 1 D 1 0 D 9D 8D 7D 6 D 5 D 4D 3D 2D 1D 0 11 10 9 8 7 6 5 4 3 2 1 LSB
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1.6 Digital Filter
Figure 18. The filters are optimized to settle to full word rates at or below 15.0 Sps. ner frequency moves to 25.4 Hz.
1.7 Clock Generator
should be minimized to reduce stray capacitance. with a 100 kHz “tuning fork” type crystal. ating temperature ranges (i .e. -10° C to +60° C).
15 Sps
Figure 18. Filter Response (Normalized to Output Word Figure 19. Typical Linearity Error for CS5521/23 Figure 20. Typical Linearity Error for CS5522/24/28
1.8 Power Supply Arrangements
plifier’s NBV (negative bias voltage) pin. signals with magnitudes down to ±100 mV. gain register to achieve optimum gain scaling.
1 AGND
18 AIN2+
17 AIN2-16 A16 A0
Figure 21. CS5522 Configured to use on-chip charge pump to supply NBV
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18 AIN2+17 AIN2-16 A16 A0
Figure 22. CS5522 Configured for ground-referenced Unipolar Signals Figure 23. CS5522 Configured for Single Supply Bridge Measurement
1.8.1 Charge Pump Drive Circuits
an internal regulator loop referenced to VA+. resistive divider as illustrated in Figure 25.
5 V ranges) the NBV voltage should not be more
pacitors in parallel can be used.
1.9 Digital Gain Scaling
Figure 24. Charge Pump Drive Circuit for VD+ = 3 V Figure 25. Alternate NBV Circuits
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verter stays constant but the number of codes af- fected is doubled because the code size has been reduced by half. The converter input range s are specified with a voltage reference of 2.5 V. The device can be op- erated with the reference tied directly to the +5 V supply. When this is done, the input span of the in- put ranges is doubled; the 25 mV range actually be- comes a 50 mV range. The gain register can be set to 2.0 (shift contents le ft one bit) and the input range will be scaled back to 25 mV. Since the gain register can actually be as great as 4-2 -22 decimal, one could scale the input span on the 25 mV range to accept an analog full-scale span of about 6.25 mV. This is useful for ratiometric bridge mea- surement of low-level differential outputs. The gain register can also be scaled manually to a value lower than 1.0. It is not recommended to use the devices with the gain register scaled lower than 0.6. This can enable the converter to accept a 40 mV input signal on the 25 mV range when using a voltage reference of 2.5 V. Caution though in scaling the gain register below 1.0 on the 100 mV, 2.5 and 5 volt ranges as the analog signal path into the converter may saturate before the expected full-scale code output is produced by the converter. Note that digital gain scaling will directly influence the number of digital output codes affected by noise. The effects can be analytically determined by calculating the size of the codes (V/Count) which result from a give n gain scaling condition and relating the amount of noise in the converter relative to the determined code size. The evalua- tion board for the converter is a useful tool to aid the assessment of noise performance with various voltage reference values, input range settings, and gain register settings. The evaluation board sup- ports noise analysis through data capture and noise histogram analysis.
1.10 Getting Started
The CS5521/22/23/24/28 have many features. From a software programmer’s perspective, what should be done first? To begin, a 32.768 kHz crys- tal takes approximately 500 ms to start-up. To ac- commodate for this, it is recommended that a software delay greater than 500 ms precede the processor’s ADC initializ ation code before any registers are accessed in the ADC. This delay time is dependent on the star t-up delay of the clock source. If a CMOS clock source with no start-up delay is being used to drive the ADC, then this de- lay is not necessary. Once the oscillator is started, the following se- quence of instructions should be performed to guarantee the converter begins proper operation: 1) After power is applied, initialize the serial port using the serial port synchronization sequence. 2) Write a ‘1’ to the reset bit (RS) of the configu- ration register to reset the converter. 3) Read the configuration register to determine if the reset valid bit (RV) is set to ‘1’. If the RV bit is not set, the conf iguration register should be read again. 4) When the RV bit has been set to ‘1’, reset the RS bit back to ‘0’ by writing 0x000000 to the configuration register. Note that while the RS bit is set to ‘1’ all other register bits in the ADC will be reset to their default state, and the RS bit must be set to ‘0’ for normal operation of the converters. Once the RS bit has been set to ‘0’, the ADC is placed in the command state were it waits for a val- id command to execute. The next step is to load the configuration register a nd then the channel setup registers with conditions that you have decided. If you need to do a factory calibration, perform offset and gain calibrations for each channel that is to be used. Then off-load the offset and gain register contents into EEPROM. These registers can then
be initialized to these c onditions when the instru- ment is used in normal operation. Once calibration is ready, input the command to start conversions in the mode you have selected via the configuration register bits. Monitor the SDO pin for a flag that the data is ready and read conversion data.
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1.11 PCB Layout
The CS5521/22/23/24/28 should be placed entirely over an analog ground plane with both the AGND and DGND pins of the device connected to the an- alog plane. Place the analog-digital plane split im- mediately adjacent to the digital portion of the chip. If separate digital (VD+) and analog (VA+) sup- plies are used, it is r ecommended that a diode be placed between them (the cathode of the diode should point to VA+). If the digital supply comes up before the analog supply, the ADC may not start up properly.
- PIN DESCRIPTIONS 81 3 CS5521 CS5522 VREF+ Voltage Reference InputAGNDAnalog Ground VREF- Voltage Reference InputVA+Positive Analog Supply AIN2+ Differential Analog InputAIN1+Differential Analog Input AIN2- Differential Analog InputAIN1-Differential Analog Input A1 Logic OutputNBVNegative Bias Voltage SCLK Serial Clock InputA0Logic Output VD+ Positive Digital SupplyCPDCharge Pump Drive DGND Digital GroundSDISerial Data Input SDO Serial Data OutputCSChip Select XOUT Crystal OutXINCrystal In 81 7 CS5523 CS5524 VREF+ Voltage Reference InputAGNDAnalog Ground VREF- Voltage Reference InputVA+Positive Analog Supply AIN2+ Differential Analog InputAIN1+Differential Analog Input AIN2- Differential Analog InputAIN1-Differential Analog Input AIN4+ Differential Analog InputAIN3+Differential Analog Input AIN4- Differential Analog InputAIN3-Differential Analog Input A1 Logic OutputNBVNegative Bias Voltage SCLK Serial Clock InputA0Logic Output VD+ Positive Digital SupplyCPDCharge Pump Drive DGND Digital GroundSDISerial Data Input SDO Serial Data OutputCSChip Select XOUT Crystal OutXINCrystal In 81 7 CS5528 VREF+ Voltage Reference InputAGNDAnalog Ground VREF- Voltage Reference InputVA+Positive Analog Supply AIN3+ Single-ended Analog InputAIN1+Single-ended Analog Input AIN4+ Single-ended Analog InputAIN2+Single-ended Analog Input AIN7+ Single-ended Analog InputAIN5+Single-ended Analog Input AIN8+ Single-ended Analog InputAIN6+Single-ended Analog Input A1 Logic OutputNBVNegative Bias Voltage SCLK Serial Clock InputA0Logic Output VD+ Positive Digital SupplyCPDCharge Pump Drive DGND Digital GroundSDISerial Data Input SDO Serial Data OutputCSChip Select XOUT Crystal OutXINCrystal In
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2.1 Clock Generator
XIN; XOUT - Crystal In; Crystal Out. A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device.
2.2 Control Pins and Serial Data I/O
CS - Chip Select. When active low, the port will recognize SCLK. When hi gh the SDO pin will output a high impedance state. CS should be changed when SCLK = 0. SDI - Serial Data Input. SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SDO - Serial Data Output. SDO is the serial data output. It will output a high impedance state if CS =1 . SCLK - Serial Clock Input. A clock signal on this pin determines the input/ output rate of the data for the SDI/SDO pins respectively. This input is a Sc hmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. A0, A1 - Logic Outputs. The logic states of A0-A1 mimic the states of the D22/D10-D23/ D11 bits of the channel-setup register. Logic Output 0 = AGND, and Logic Output 1 = V A+.
2.3 Measurement and Reference Inputs
AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- - Differential Analog Input. Differential input pins into the CS5522 and CS5524 devices. AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ - Single-Ended Analog Input. Single-ended input pins into the CS5528. VREF+, VREF- - Voltage Reference Input. Fully differential inputs whic h establish the voltage refere nce for the on-chip modulator.
NBV - Negative Bias Voltage. Input pin to supply the negative supply voltage for the 20X gain instrumentation amplifier and coarse/fine charge buffers. May be tied to AGND if AIN+ and AIN- inputs are centered around +2.5 V; or it may be tied to a negative supply voltage (-2.1 V typical) to allow the amplifier to handle low level signals more negative th an ground. When using the CS5528 in either the 25 mV , 55 mV or 100 mV range, the analog inputs are expect ed to be ground referenced; therefore, NBV must be between - 1.8 to -2.5 to ensure proper operation. CPD - Charge Pump Drive. Square wave output used to provide energy for the charge pump.
2.4 Power Supply Connections
V A+ - Positive Analog Power. Positive analog supply voltage. Nominally +5 V . VD+ - Positive Digital Power. Positive digital supply voltage. Nominally +3.0 V or +5 V . AGND - Analog Ground. Analog Ground. DGND - Digital Ground. Digital Ground.
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- SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connect s the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB belo w the first code transition and the other endpoint is located 1/ 2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width fr om the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(V REF+) - (VREF-)} - 3/2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above the voltage on the AIN- pin.). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset the voltage on the AIN- pin) . When in bipolar mode (U/B bit = 0). Units are in LSBs.
- ORDERING INFORMATION 5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Number Bits Channels Linearity Error (Max) Package Temperature Range CS5521-ASZ 16 ±0.003% 20-pin 0.2" Plastic SSOP (Lead Free) -40°C to +85°C CS5522-ASZ 24 ±0.0015% CS5523-ASZ 16 ±0.003% 24-pin 0.2" Plastic SSOP (Lead Free)CS5524-ASZ 24 ±0.0015% CS5528-ASZ 8 Model Number Package MSL Rating* Peak Reflow Temp Max Floor Life CS5521-ASZ 20-pin 0.2" Plastic SSOP (Lead Free) 3 260 °C 7 Days CS5522-ASZ CS5523-ASZ 24-pin 0.2" Plastic SSOP (Lead Free)CS5524-ASZ CS5528-ASZ
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- PACKAGE DIMENSION DRAWINGS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion /intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-150 Controling Dimension is Millimeters. 20L SSOP PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion /intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-150 Controling Dimension is Millimeters. 24L SSOP PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW
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- REVISION HISTORY Revision Date Changes F8 JUL 2009 Leaded (Pb) and PDIP-packaged devices removed from ordering information. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUS- TOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.