CS5509

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Technical content

Features

 Delta-sigma A/D Converter - 16-bit, No Missing Codes - Linearity Error: ±0.0015%FS  Differential Input - Pin-selectable Unipolar/Bipolar Ranges - Common Mode Rejection 105 dB @ dc 120 dB @ 50, 60 Hz Either 5V or 3.3V Digital Interface  On-chip Self-calibration Circuitry  Output Update Rates up to 200/second  Ultra Low Power: 1.7 mW

Description

The CS5509 is a single-supply, 16-bit, serial-output CMOS A/D converter. The CS5509 uses charge-bal- anced (delta-sigma) techniques to provide low-cost, high-resolution measurements at output word rates up to 200 samples per second. The on-chip digital filter offe rs superior line rejection at 50Hz and 60Hz when the device is operated from a 32.768 kHz clock (output word rate = 20 Sps). The CS5509 has on-chip self-calibration circuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors. Low power, high resolution, and small package size make the CS5509 an ideal solution for loop-powered transmitters, panel meters, weigh scales, and battery powered instruments.

ORDERING INFORMATION

CS5509-ASZ -40 °C to +85 °C 16-pin SOIC Lead Free I Differential 4th order delta-sigma modulator VD+ VA+VREF+ VREF- AIN- 8 AIN+ 7 Calibration SRAM Serial Interface Logic Digital Filter XIN XOUT CONV Calibration µC OSC CAL3

6 BP/UP

SEP ‘09 DS125F3

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Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5509's source impedance requirements. Refer to the text section Analog Input Impedance Considerations. 2. Specifications guaranteed by design, characterization and/or test. 3. Applies after calibration at the temperature of interest. 4. Total drift over the specified temperature range since calibration at power-up at 25 °C. 5. The input is different ial. Therefore, GND ≤ Signal + Common Mode Voltage ≤ VA+. 6. The CS5509 can accept input voltages up to the VA+ analog supply. In unipolar mode the CS5509 will output all 1's if the dc input magnitude ((AIN+) - (AIN-)) exceeds ((VREF+) - (VREF-)) and will output all 0's if the input becomes more negative than 0 Volts. In bipolar mode the CS5509 will output all 1's if the dc input magnitude ((AIN+) - (AIN-)) exceeds ((VREF+) - (VREF-)) and will output all 0's if the input becomes more negative in magnitude than -((VREF+) - (VREF-)). 7. All outputs unloaded. A ll inputs CMOS levels. * Refer to the Specification Definitions immediately following the Pin Description Section. ANALOG CHARACTERISTICS (TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; VREF+ = 2.5V, VREF- = 0V; fCLK = 32.768 kHz; Bipolar Mode; Rsource = 40 Ω with a 10 nF to GND at AIN; AIN- = 2.5V; unless oth- erwise specified.) (Notes 1 and 2) Parameter* Min Typ Max Unit Accuracy Linearity Error f CLK = 32.768 kHz fCLK = 165 kHz fCLK = 247.5 kHz fCLK = 330 kHz 0.0015 0.0015 0.0015 0.005 0.003 0.003 0.003 0.0125 ± %FS ± %FS ± %FS ± %FS Differential Nonlinearity - ±0.25 ±0.5 LSB Full-scale Error (Note 3) - ±0.25 ±2 LSB Full-scale Drift (Note 4) - ±0.5 - LSB Unipolar Offset (Note 3) - ±0.5 ±2 LSB Unipolar Offset Drift (Note 4) - ±0.5 - LSB Bipolar Offset (Note 3) - ±0.25 ±1 LSB Bipolar Offset Drift (Note 4) - ±0.25 - LSB Noise (Referred to Output) - 0.16 - LSB rms Analog Input Analog Input Range Unipolar Bipolar (Notes 5 and 6) 0 to +2.5 ±2.5 V V Common Mode Rejection dc fCLK = 32.768 kHz 50, 60 Hz (Note 2) 120 105 dB dB Input Capacitance - 15 - pF DC Bias Current (Note 1) - 5 - nA Power Supplies DC Power Supply Currents I Total IAnalog IDigital 350 300 450 µA µA µA Power Dissipation (Note 7) - 1.7 2.25 mW Power Supply Rejection - 80 - dB

Notes: 8. All measurements are performed under static conditions. Specifications are subject to change without notice DYNAMIC CHARACTERISTICS Parameter Symbol Ratio Unit Modulator Sampling Frequency fs fclk/2 Hz Output Update Rate (CONV = 1) fout fclk/1622 Hz Filter Corner Frequency f-3dB fclk/1928 Hz Settling Time to 1/2 LSB (FS Step) ts 1/fout s 5V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ±5%; GND = 0) (Notes 2 and 8) Parameter Symbol Min Typ Max Unit High-level Input Voltage XIN All Pins Except XIN VIH 3.5 2.0 V V Low-level Input Voltage XIN All Pins Except XIN VIL 1.5 0.8 V V High-level Output Voltage (Note 9) VOH (VD+) -1.0 - - V Low-level Output Voiltage I out = 1.6 mA V OL -- 0 . 4 V Input Leakage Current Iin -± 1 ± 1 0 µ A 3-State Leakage Current IOZ -- ± 1 0 µ A Digital Output Pin Capacitance Cout -9- p F 3.3V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; GND = 0) (Notes 2 and 8) Parameter Symbol Min Typ Max Unit High-level Input Voltage XIN All Pins Except XIN VIH

0.7 VD+

0.6 VD+

V V Low-level Input Voltage XIN All Pins Except XIN VIL

0.3 VD+

0.16 VD+

V V High-level Output Voltage (Note 9) VOH (VD+) -0.3 - - V Low-level Output Voltage I out = 1.6 mA V OL -- 0 . 3 V Input Leakage Current Iin -± 1 ± 1 0 µ A 3-state Leakage Current IOZ -- ± 1 0 µ A Digital Output Pin Capacitance Cout -9- p F

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Notes: 10. Specified using 10% and 90% points on waveform of interest. 11. An internal power-on-reset is activated whenever power is applied to the device. 12. Oscillator start-up time varies wit h the crystal parameters. This specification does not apply when using an external clock source. 13. The wake-up period begins once the oscillator starts; or when using an external fclk, after the power-on reset time elapses. 14. Calibration can also be initiated by pulsing CAL high while CONV=1. 15. Conversion time will be 1622/f clk if CONV remains high continuously. 5V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ±5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Note 2) Parameter Symbol Min Typ Max Unit Master Clock Frequency Internal Oscillator External Clock XIN fclk 30.0 32.768 53.0 330 kHz kHz Master Clock Duty Cycle 40 - 60 % Rise Times Any Digital Input (Note 10) Any Digital Output t rise 1.0 µs ns Fall Time Any Digital Input (Note 10) Any Digital Output tfall 1.0 µs ns Start-Up Power-On Reset Period (Note 11) tres -1 0- m s Oscillator Start-up Time XTAL = 32.768 kHz (Note 12) tosu -5 0 0- m s Wake-up Period (Note 13) twup - 1800/fclk -s Calibration CONV Pulse Width (CAL = 1) (Note 14) tccw 100 - - ns CONV and CAL High to Start of Calibration tscl -- 2/fclk+200 ns Start of Calibration to End of Calibration tcal - 3246/fclk -s Conversion CONV Pulse Width tcpw 100 - - ns CONV High to Start of Conversion tscn -- 2/fclk+200 ns Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk -- s Hold Time BP/UP stable after DRDY falls tbuh 0-- n s Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk -s

3.3V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Note 2) Parameter Symbol Min Typ Max Unit Master Clock Frequency Internal Oscillator External Clock XIN fclk 30.0 32.768 53.0 330 kHz kHz Master Clock Duty Cycle 40 - 60 % Rise Times Any Digital Input (Note 10) Any Digital Output t rise 1.0 µs ns Fall Time Any Digital Input (Note 10) Any Digital Output tfall 1.0 µs ns Start-Up Power-On Reset Period (Note 11) tres -1 0- m s Oscillator Start-up Time XTAL = 32.768 kHz (Note 12) tosu -5 0 0- m s Wake-up Period (Note 13) twup - 1800/fclk -s Calibration CONV Pulse Width (CAL = 1) (Note 14) tccw 100 - - ns CONV and CAL High to Start of Calibration tscl -- 2/fclk+200 ns Start of Calibration to End of Calibration tcal - 3246/fclk -s Conversion CONV Pulse Width tcpw 100 - - ns CONV High to Start of Conversion tscn -- 2/fclk+200 ns Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk -- s Hold Time BP/UP stable after DRDY falls tbuh 0-- n s Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk -s

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Figure 1. Calibration Timing (Not to Scale) Figure 2. Conversion Timing (Not to Scale)

Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high sooner than 2 fclk + 200 ns after CS goes low. 17. SDATA transitions on the falling edge of SCLK. Note th at a rising SCLK must occur to enable the serial port shifting mechanism before falling edges can be recognized. 18. If CS is returned high before all data bits are output, the SDATA output will complete the current data bit and then go to high impedance. 5V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ±5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Note 2) Parameter Symbol Min Typ Max Unit Serial Clock fsclk 0- 2 . 5 M H z Serial Clock Pulse Width High Pulse Width Low tph tpl 200 200 ns ns Access Time CS Low to data valid (Note 16) tcsd -6 0 2 0 0 n s Maximum Delay Time (Note 17) SCLK falling to new SDATA bit tdd -1 5 0 3 1 0 n s Output Float Delay CS High to output Hi-Z (Note 18) SCLK falling to Hi-Z tfd1 tfd2 160 150 300 ns ns 3.3V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Note 2) Parameter Symbol Min Typ Max Unit Serial Clock fsclk 0 - 1.25 MHz Serial Clock Pulse Width High Pulse Width Low tph tpl 200 200 ns ns Access Time CS Low to data valid (Note 16) tcsd -1 0 0 2 0 0 n s Maximum Delay Time (Note 17) SCLK falling to new SDATA bit tdd -4 0 0 6 0 0 n s Output Float Delay CS High to output Hi-Z (Note 18) SCLK falling to Hi-Z tfd1 tfd2 320 150 500 ns ns

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Figure 3. Timing Relationships (Not to Scale)

Notes: 19. All voltages with respect to ground. 20. The CS5509 can be operated with a reference voltage as low as 100 mV; but with a corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and GND. Notes: 21. No pin should go more positive than (VA+) + 0.3 V. 22. VD+ must always be less than (VA+) + 0.3 V, and can never exceed +6.0 V. 23. Applies to all pins including continuous overvo ltage conditions at the analog input (AIN) pin. 24. Transient currents of up to 100 mA will not caus e SCR latch-up. Maximum input current for a power supply pin is ± 50 mA. 25. Total power dissipation, including all input currents and output currents. *WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19) Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog VD+ VA+ 3.15 4.75 5.0 5.0 5.5 5.5 V V Analog Reference Voltage (Note 20) (VREF+) - Analog Input Voltage (Note 6) Unipolar Bipolar VAIN VAIN -((VREF+) - (VREF-)) (VREF+) - (VREF-) (VREF+) - (VREF-) V V ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Min Typ Max Unit DC Power Supplies Ground (Note 21) Positive Digital (Note 22) Positive Analog GND VD+ VA+ -0.3 -0.3 -0.3 (VD+)-0.3 6.0 6.0 V V V Input Current, Any Pin Except Supplies (Notes 23 and 24) I in -- ± 1 0 m A Output Current Iout -- ± 2 5 m A Power Dissipation (Total) (Note 25) - - 500 mW Analog Input Voltage AIN and VREF pins VINA -0.3 - (VA+)+0.3 V Digital Input Voltage VIND -0.3 - (VD+)+0.3 V Ambient Operating Temperature TA -40 - 85 °C Storage Temperature Tstg -65 - 150 °C

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The CS5509 is a low power, 16-bit, monolithic CMOS A/D converter desi gned specifically for measurement of dc signals. The CS5509 includes a delta-sigma charge-balan ce converter, a voltage reference, a calibration microcontroller with SRAM, a digital filter and a serial interface. The CS5509 is optimized to operate from a 32.768 kHz crystal but can be driven by an external clock whose frequency is between 30kHz and 330kHz. When the digital filter is operated with a 32.768 kHz clock, the filter has zeros precisely at 50 and 60 Hz line frequencies and multiples thereof. The CS5509 uses a "start convert" command to start a convolution cycle on the digital filter. Once the filter cycle is completed, the output port is up- dated.When operated wi th a 32.768kHz clock the ADC converts and updates its output port at 20 samples/sec.The output port operates in a synchro- nous externally-clocked interface format. THEORY OF OPERATION Basic Converter Operation The CS5509 A/D converter has three operating states. These are stand-by, calibration, and conver- sion. When power is first applied, an internal pow- er-on reset delay of about 10 ms resets all of the logic in the device. The os cillator must then begin oscillating before the device can be considered functional. After the power-on reset is applied, the device enters the wake-up period for 1800 clock cycles after clock is present. This allows the delta- sigma modulator and other circuitry (which are op- erating with very low cu rrents) to reach a stable bias condition prior to entering into either the cali- bration or conversion states. During the 1800 cycle wake-up period, the device can accept an input command. Execution of this command will not oc- cur until the complete wa ke-up period elapses. If no command is given, the device enters the standby state. Calibration After the initial applic ation of power, the CS5509 must enter the calibration state prior to performing accurate conversions. Du ring calibration, the chip executes a two-step proces s. The device first per- forms an offset calibrati on and then follows this with a gain calibration. The two calibration steps determine the zero reference point and the full scale reference point of the converter's transfer function. From these points it calibrates the zero point and a gain slope to be used to properly scale the output digital codes when doing conversions. The calibration state is entered whenever the CAL and CONV pins are high at the same time. The state of the CAL and CONV pins at power-on are recog- nized as commands, but will not be executed until the end of the 1800 clock cycle wake-up period. If CAL and CONV become active (high) during the 1800 clock cycle wake-up ti me, the converter will wait until the wake-up pe riod elapses before exe- cuting the calibration. If the wake-up time has elapsed, the converter will be in the standby mode waiting for instruction and will enter the calibration cycle immediately if CAL and CONV become ac- tive. The calibration last s for 3246 clock cycles. Calibration coefficients are then retained in the SRAM (static RAM) for use during conversion. The state of BP/UP is ignored during calibration but should remain stable throughout the calibration period to minimize noise. When conversions are performed in unipolar mode or in bipolar mode, the converter uses the same cal- ibration factors to compute the digital output code. The only difference is that in bipolar mode the on- chip microcontroller o ffsets the computed output word by a code value of 8000H. This means that the bipolar measurement range is not calibrated from full scale positive to full scale negative. Instead it is calibrated from the bipolar zero scale point to full scale positive. The slope factor is then extended be- low bipolar zero to accom modate the negative in-

put signals. The converter can be used to convert both unipolar and bipolar signals by changing the BP/UP pin. Recalibration is not required when switching between unipolar and bipolar modes. At the end of the calibration cycle, the on-chip mi- crocontroller checks the logic state of the CONV signal. If the CONV input is low the device will en- ter the standby mode where it waits for further in- struction. If the CONV signal is high at the end of the calibration cycle, the converter will enter the conversion state and perf orm a conversion on the input channel. The CAL signal can be returned low any time after calibrati on is initiated. CONV can also be returned low, but it should never be taken low and then taken back high until the calibration period has ended and the converter is in the standby state. If CONV is taken low and then high again with CAL high while the converter is calibrating, the device will interrupt the current calibration cy- cle and start a new one. If CAL is taken low and CONV is taken low and then high during calibra- tion, the calibration cycle will continue as the con- version command is disregarded. The state of BP/UP is not important during calibrations. If an "end of calibration" signal is desired, pulse the CAL signal high while l eaving the CONV signal high continuously. Once the calibration is complet- ed, a conversion wi ll be performe d. At the end of the conversion, DRDY will fall to indicate the first valid conversion after th e calibration has been completed. Conversion The conversion state can be entered at the end of the calibration cycle, or whenever the converter is idle in the standby mode. If CONV is taken high to initiate a calibration cycle ( CAL also high), and re- mains high until the calibration cycle is completed (CAL is taken low after CONV transitions high), the converter will begin a conversion upon comple- tion of the calibration period. The BP/UP pin is not a latc hed input. The BP/UP pin controls how the output word from the digital filter is processed. In bipolar mode the output word computed by the digital filter is offset by 8000H (see Understanding Converter Calibration). BP/UP can be changed after a conversion is started as long as it is stable for 82 clock cycles of the conversion period prior to DRDY falling. If one wishes to in- termix measurement of bipolar and unipolar signals on various input signals, it is best to switch the BP/UP pin immediately after DRDY falls and leave BP/UP stable until DRDY falls again. The digital filter in the CS5509 has a Finite Im- pulse Response and is designed to settle to full ac- curacy in one conversion time. If CONV is left high, the CS5509 will perform con- tinuous conversions. The conversion time will be 1622 clock cycles. If conve rsion is initiated from the standby state, there may be up to two XIN clock cycles of uncertainty as to when conversion actual- ly begins. This is because the internal logic oper- ates at one half the external clock rate and the exact phase of the internal clock may be 180° out of phase relative to the XI N clock. When a new con- version is initia ted from the standby state, it will take up to two XIN clock cycles to begin. Actual conversion will use 1624 clock cycles before DRDY goes low to indicate that the serial port has been updated. See the Seri al Interface Logic sec- tion of the data sheet for information on reading data from the serial port. In the event the A/D conversion command (CONV going positive) is issued during the conversion state, the current conversion will be terminated and a new conversion will be initiated. Voltage Reference The CS5509 uses a differen tial voltage reference input. The positive input is VREF+ and the nega- tive input is VREF-. Th e voltage between VREF+ and VREF- can range from 1 volt minimum to 3.6 volts maximum. The gain slope will track changes

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dating ratiometric applications. the voltage between the VREF+ and VREF- pins. and minus the magnitude of the voltage reference. stay within the supply voltages VA+ and GND. nal magnitude stays within the supply voltages. this noise will be filtered out by the digital filter. and bipolar measurement modes. cal, and CMR at 50 and 60Hz of 120dB typical. time by recalibrating the converter. to settle to its final value. signal and reference inputs. Table 1. Output Coding

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CS5509 running at 32.768kHz. Table 2. Filter Notch Attenuation (XIN = 32.768 kHz) (XIN/2) and multiples thereof may also be aliased. Figure 6. Filter Magnitude Plot to 260 Hz Figure 7. Filter Magnitude Plot to 50 Hz Figure 8. Filter Phase Plot to 50 Hz

to prevent aliasing. Spec tral components greater than one half the output word rate on the VREF in- puts (VREF+ and VREF-) may also be aliased. Fil- tering of the reference voltage to remove these spectral components from the reference voltage is desirable. Crystal Oscillator The CS5509 is designed to be operated using a 32.768kHz "tuning fork" type crystal. One end of the crystal should be conne cted to the XIN input. The other end should be attached to XOUT. Short lead lengths should be us ed to minimize stray ca- pacitance. Over the industrial te mperature range (-40 to +85 °C) the on-chip gate oscillator will oscillate with other crystals in the range of 30kHz to 53 kHz. The chip will operate with external clock frequen- cies from 30kHz to 330kHz over the industrial tem- perature range. The 32.768 kHz crystal is normally specified as a time-keeping crystal with tight spec- ifications for both initia l frequency and for drift over temperature. To maintain excellent frequency stability, these crystals are specified only over lim- ited operating temperatur e ranges (i.e. -10 °C to +60 °C) by the manufactur ers. Applications of these crystals with the CS5509 does not require tight initial tolerance or low tempco drift. There- fore, a lower cost crystal with looser initial toler- ance and tempco will generally be adequate for use with the CS5509. Also check with the manufactur- er about wide temperat ure range a pplication of their standard crystals. Generally, even those crys- tals specified for limited temperature range will op- erate over much larger ranges if frequency stability over temperature is not a requirement. The frequen- cy stability can be as bad as ±3000 ppm over the operating temperature range and still be typically better than the line frequency (50 Hz or 60Hz) sta- bility over cycle-to-cycle during the course of a day. Serial Interface Logic The digital filter in th e CS5509 takes 1624 clock cycles to compute an output word once a conver- sion begins. At the end of the conversion cycle, the filter will atte mpt to update the serial port. Two clock cycles prior to the update DRDY will go high. When DRDY goes high just prior to a port up- date it checks to see if the port is either empty or unselected (CS = 1). If the port is empty or unse- lected, the digital filter will update the port with a new output word. When new data is put into the port DRDY will go low. Reading Serial Data SDATA is the output pin for the serial data. When CS goes low after new data becomes available (DRDY goes low), the SDATA pin comes out of Hi-Z with the MSB data bit present. SCLK is the input pin for the serial clock. If the MSB data bit is on the SDATA pin, the firs t rising edge of SCLK enables the shifting mechanism. This allows the falling edges of SCLK to shift subsequent data bits out of the port. Note that if the MSB data bit is out- put and the SCLK signal is high, the first falling edge of SCLK will be ignored because the shifting mechanism has not become activated. After the first rising edge of SCLK , each subsequent falling edge will shift out the serial data. Once the LSB is present, the falling edge of SCLK will cause the SDATA output to go to Hi-Z and DRDY to return high. The serial port register will be updated with a new data word upon the completion of another con- version if the serial port has been emptied, or if the CS is inactive (high). CS can be operated async hronously to the DRDY signal. The DRDY signal need not be monitored as long as the CS signal is taken low for at least two XIN clock cycles plus 200ns prior to SCLK being toggled. This ensures that CS has gained control over the serial port.

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Power Supplies and Grounding The analog and digital supply pins to the CS5509 are brought out on separate pins to minimize noise coupling between the analog and digital sections of the chip. In the digital section of the chip the supply current flows into the VD+ pin and out of the GND pin. As a CMOS device , the CS5509 requires that the supply voltage on the VA+ pin always be more positive than the voltage on any other pin of the de- vice. If this requirement is not met, the device can latch-up or be damaged. In all circumstances the VA+ voltage must remain more positive than the VD+ or GND pins; VD+ mu st remain more posi- tive than the GND pin. Figure 9a illustrates th e System Connection Dia- gram for the CS5509. Note that all supply pins are bypassed with 0.1 µF capacitors and that the VD+ digital supply is derived from the VA+ supply. Fig- ure 9b illustrates the CS5509 operating from a +5V analog supply and +3.3V digital supply. When using separate supplies for VA+ and VD+, VA+ must be established first. VD+ should never become more positive than VA+ under any operat- ing condition. Remember to investigate transient power-up conditions, when one power supply may have a faster rise time.

Figure 9a. System Connection Diagram Using a Single Supply CS5509 +5V Analog Supply VD+VA+ VREF+ VREF- GND 0.1 µF 0.1 µF Analog Signal AIN+ AIN- SCLK SDATA XIN XOUT 16DRDY CAL 3 1CS CONV 2 6BP/UP 32.768 kHz 10Ω Voltage Reference Optional Clock Source Serial Data Interface Control Logic

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Figure 9b. System Connection Diagram Using Split Supplies CS5509 +5V Analog Supply VD+VA+ VREF+ VREF- GND 0.1 µF 0.1 µF Analog Signal AIN+ AIN- SCLK SDATA XIN XOUT 16DRDY CAL 3 1CS CONV 2 6BP/UP 32.768 kHz Voltage Reference Optional Clock Source Serial Data Interface Control Logic +3.3V to +5V Digital Supply Note: VD+ must never be more positive than VA+

PIN DESCRIPTIONS* * Pinout applies to both PDIP and SOIC Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 4, 5. A gate inside the chip is connect ed to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the device into a lower powered state (a pproximately 70% power reduction). Serial Output I/O CS - Chip Select, Pin 1. This input allows an external device to access the serial port. DRDY - Data Ready, Pin 16. Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new output word has been placed into the serial port. DRDY will return high af ter all data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the CS pin is inactive (high). SDATA - Serial Data Output, Pin 15. SDATA is the output pin of the se rial output port. Data from th is pin will be output at a rate determined by SCLK. Data is output MSB first and advances to th e next data bit on the falling edges of SCLK. SDATA will be in a high im pedance state when not transmitting data. SCLK - Serial Clock Input, Pin 14. A clock signal on this pin determin es the output rate of the data from the SDATA pin. This pin must not be allowed to float. 8 9

16 DRDY

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CAL - Calibrate, Pin 3. When taken high the same time that the CONV pin is taken high the c onverter will perform a self-calibration which includes cali bration of the offset and gain scale factors in the converter. CONV - Convert, Pin 2. The CONV pin initiates a calibrati on cycle if it is ta ken from low to high while the CAL pin is high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If CONV is held high (CAL low) the convert er will do continuous conversions. BP/UP - Bipolar/Unipolar, Pin 6. The BP/UP pin selects the conversion mode of th e converter. When high the converter will convert bipolar input signals; when low it will convert unipolar input signals. Measurement and Reference Inputs AIN+, AIN- - Differential Analog Inputs, Pins 7, 8. Analog differential inputs to the delta-sigma modulator. VREF+, VREF- - Differential Voltage Reference Inputs, Pins 9, 10. A differential voltage referenc e on these pins operates as the voltage reference for the converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts. Power Supply Connections V A+ - Positive Analog Power, Pin 11. Positive analog supply volta ge. Nominally +5 volts. VD+ - Positive Digital Power, Pin 13. Positive digital supply voltage. No minally +5 volts or +3.3 volts. GND - Ground, Pin 12. Ground.

The deviation of a code from a straight line which connect s the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB belo w the first code transition and the other endpoint is located 1/ 2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width fr om the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (V REF-)} - LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition fro m the ideal ( LSB above the voltage on the AIN- pin.) when in unipolar mode (BP/UP low). Units are in LSBs. Bipolar Offset the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs

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0.095 0.1052.41 2.67 0.008 0.0150.203 0.381 0.398 0.42010.11 10.67 0.0200.0130.510.33 0.016 0.0350.41 0.89 8°0°0° 8° MILLIMETERS INCHES MIN MAX MAXMINpins 0.4100.3909.91 10.4116 0.5100.49012.45 12.9520 0.6100.59014.99 15.5024 0.7100.69017.53 18.0328 0.0120.0050.127 0.300 1.14 0.040 DIM E E b L D e A A c 0.292 0.2987.42 7.57 D EE1 e A Ab 1 c L µ µ 1.40 0.055 A 2 see table above NOM 2.54 0.280 10.41 0.46 NOM 10.16 12.70 15.24 17.78 7.49 1.27 2.29 2.542.41 NOM 0.100 0.011 0.410 0.018 NOM 0.400 0.500 0.600 0.700 0.295 0.050 0.1000.090 0.095

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Peak Relfow Temp MSL Rating* Maximum Floor Life CS5509-ASZ (lead free) 260 °C 3 7 Days

24 DS125F3

REVISION HISTORY

F1 Aug ‘97 First “final” release. F2 Aug ‘05 Added lead-free device ordering info. Added legal notice. Added MSL data. F3 Jul ‘09 Removed PDIP and leaded (Pb) devices from ordering information. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD- ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.