CS5451 ETC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Features
/G108Synchronous Sampling /G108On-chip 1.2 V Reference (25 ppm/°C typ) /G108Power Supply Configurations: – VA+ = +3 V; VA- = -2 V; VD+ = +3 V – Supply tolerances ±10% /G108Power Consumption – 20 mW Typical at VD+ = +3 V /G108Simple Four-wire Serial Interface /G108Charge Pump Driver output generates negative power supply. /G108Ground-Referenced Bipolar Inputs
Description
The CS5451 is a highly integrated Delta-Sigma (∆Σ) An- alog-to-Digital Converter (ADC) developed for the Power Measurement Industry. The CS5451 combines six ∆Σ ADCs, decimation filters, and a serial interface on a sin- gle chip. The CS5451 interfaces directly to a current transformer or shunt to measure current, and resistive divider or transformer to measure voltage. The product features a serial interface for communication with a mi- cro-controller or DSP. The product is initialized and fully functional upon reset, and includes a Voltage Reference. ORDERING INFORMATION: CS5451-BS -40 °C to +85°C 28-pin SSOP VREFIN VREFOUT IIN1+ IIN1- VIN1+ VIN1- VIN2+ VIN2- VIN3+ VIN3- IIN2+ IIN2- IIN3+ IIN3- VA+ VD+ AGND SE FSO SDO SCLK Voltage Reference Serial Interface RESET 4th Order ∆Σ Modulator 2nd Order ∆Σ Modulator Decimation Filter Decimation Filter 4th Order ∆Σ Modulator 2nd Order ∆Σ Modulator Decimation Filter Decimation Filter 4th Order ∆Σ Modulator 2nd Order ∆Σ Modulator Decimation Filter Decimation Filter x1, 20 x1, 20 x1, 20 GAIN CPD OWRS XIN DGNDVA- CLOCK Pulse Output Regulator JUL ‘01 DS458PP4
2 DS458PP4
marks and service marks can be found at http://www.cirrus.com.
- CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (TA = -40 °C to +85 °C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V; VA- = -2 V ±10%; External VREF+ = 1.2 V; XIN = 4.000 MHz; AGND, DGND = 0.0V.)(See Notes 1 and 2) Notes: 1. Specifications guaranteed by design, characterization, and/or test. 2. Analog signals are relative to AGND and digital signals to DGND unless otherwise noted. 3. Effective Input Impedance (EII) varies with clock frequency (XIN) and Input Capacitance (IC) EII = 1/(IC*XIN/4) Parameter Symbol Min Typ Max Unit Accuracy (All Channels) Total Harmonic Distortion THD 74 - - dB Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB Common Mode + Signal on Input VA- - VA+ V Input Sampling Rate - XIN/4 - Hz Analog Inputs (Current Channels) Differential Input Voltage Range Gain=20 [ For example: (v IIN1+) - (vIIN1-) ] Gain=1 IIN - ±40 ±800 mV mV Bipolar Offset Gain=20 Gain=1 VOS VOS 0.500 mV mV Crosstalk (Channel-to-Channel) (50, 60 Hz) - - -120 dB Input Capacitance Gain = 20 Gain = 1 IC IC pF pF Effective Input Impedance (Note 3) Gain=20 Gain=1 EII EII 500 600 kΩ kΩ Noise (Referred to Input) 0-60 Hz Gain=20 Gain=1 0-1 kHz Gain=20 Gain=1 0-2 kHz Gain=20 Gain=1 2.5 3.75 µVrms µVrms µVrms µVrms µVrms µVrms Analog Inputs (Voltage Channels) Differential Input Voltage Range [ For example: (vVIN1+) - (vVIN1-) ] VIN - ±800 - mV Bipolar Offset Gain=1 VOS - 20 25 mV Crosstalk to any other channel at full-scale (50, 60 Hz) - - -120 dB Input Capacitance IC - - 0.2 pF Effective Input Impedance (Note 3) EII - 3 4 M Ω Noise (Referred to Input) 0-60 Hz 0-1 kHz 0-2 kHz µV rms µVrms µVrms Dynamic Characteristics High Rate Filter Output Word Rate OWRS = “0” OWRS = “1” OWR OWR XIN/2048 XIN/1024 Hz Hz
4 DS458PP4
ANALOG CHARACTERISITCS (continued) Notes: 4. All outputs unloaded. All inputs CMOS level. 5. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3V, AGND = DGND = 0V, VA- = -2V (using charge-pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB): DIGITAL CHARACTERISTICS (TA = -40 °C to +85 °C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V; VA- = -2 V ±10%; AGND, DGND = 0.0 V) (See Note 6) Notes: 6. All measurements performed under static conditions. 7. For OWRS and GAIN pins, input leakage current is 30 µA (Max). Parameter Symbol Min Typ Max Unit Reference Output Output Voltage REFOUT 1.15 - 1.25 V Temperature Coefficient - 20 50 ppm/ °C Load Regulation (Output Current 1 µA Source or Sink) ∆V R -6 1 0 m V Power Supply Rejection PSRR 60 - - dB Reference Input Input Voltage Range VREF+ 1.15 1.2 1.25 V Input Capacitance - - 10 pF Input CVF Current - - 1 µA Power Supplies Power Supply Currents I ID+ PSCA PSCD mA mA Power Consumption (Note 4) PC - - 27 mW Power Supply Rejection (DC) (see Note 5) (50, 60 Hz) PSRR PSRR dB dB Parameter Symbol Min Typ Max Unit High-Level Input Voltage V IH 0.6 VD+ - VD+ V Low-Level Input Voltage V IL 0.0 - 0.8 V High-Level Output Voltage I out = -5.0 mA V OH (VD+) - 1.0 - - V Low-Level Output Voltage I out = 5.0 mA V OL -- 0 . 4 V Input Leakage Current (Note 7) I in -± 1 ± 1 0 µ A 3-State Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9 - p F PSRR 20 106.07 Veq log⋅=
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0.0 V) ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0.0 V; See Note 8.) Notes: 8. All voltages with respect to AGND. 9. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. 10. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. 11. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog Negative Analog VD+ VA+ VA- 2.7 2.7 -2.2 3.0 3.0 -2.0 3.5 3.5 -1.8 V V V Voltage Reference Input VREF+ - 1.2 - V Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog Negative Analog VD+ VA+ VA- -0.3 -0.3 -2.5 +3.5 +3.5 -0.3 V V V Input Current, Any Pin Except Supplies (Note 9 and 10) I IN -- ± 1 0 m A Output Current I OUT -- ± 2 5 m A Power Dissipation (Note 11) PDN - - 500 mW Analog Input Voltage All Analog Pins V INA VA- - 0.3 - (VA+) + 0.3 V Digital Input Voltage All Digital Pins V IND -0.3 - (VD+) + 0.3 V Ambient Operating Temperature T A -40 - 85 °C Storage Temperature T stg -65 - 150 °C
6 DS458PP4
Notes: 12. Device parameters are specified with a 4.000 MHz clock, OWRS = 1.
- Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
Figure 1. Serial Port Timing
vider or transformer to measure voltage. ers, and three channels assigned for voltage input. The device outputs data on a serial output port.
2.1 Theory of Operation
Figure 2. Typical Connection Diagram
8 DS458PP4
2.2 Performing Measurements
Table 1. Nominal Relationship for Differential Input
2.3 High Rate Digital Filters
XIN/8 Hz and decimates to XIN/2048 Hz. at XIN/8 Hz and decimates to XIN/1024 Hz.
2.4 Serial Interface
96 SCLKs
Figure 3. Serial Port Data Transfer
SCLK is not active during FSO high.
2.5 System Initialization
is forced low with a minimum pulse width of 50 ns.
2.6 Analog Inputs
±800 mV on the Voltage Channels.
2.7 Voltage Reference
V reference between the VREFIN and AGND pins. ternal reference can be used.
2.8 Power Supply
Figure 4. Close-up of One Data Frame
10 DS458PP4
the VA- level to -2/3 of VA+ level. Pump Drive for External Loads.
2.9 PCB Layout
Figure 5. Generating VA- with a Charge Pump
- PIN DESCRIPTION Clock Generator XIN - Master Clock Input Control Pins and Serial Data I/O SE - Serial Port Enable When SE is low, the output pins of the serial port are 3-stated. SDO - Serial Port Output Data will be at a rate determined by SCLK. FSO - Frame Signal Output Framing signal output for data transfer from SDO pin. SCLK - Serial Clock Output A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined by XIN frequency and state of OWRS input pin. RESET - Reset When reset is taken low, all internal registers are set to their default states. GAIN - Input Gain Control Sets input gain for current channels. A logic high sets internal gain to 1, a logic low level sets the gain to 20. If no connection is made to this pin, it will default to logic low level (through internal 200K resistor to DGND). OWRS - Output Word Rate Select When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200K resistor to DGND). 14 15 28Serial Clock Output SCLK VD+ Digital Supply Serial Data Output SDO DGND Digital Ground Frame Sync FSO CPD Charge Pump Drive Serial Port Enable SE XIN Master Clock Current Input Gain GAIN RESET Reset Analog Ground AGND OWRS Output Word Rate Select Reference Input VREFIN VIN1+ Differential Voltage Input 1 Reference Output VREFOUT VIN1- Differential Voltage Input 1 Positive Analog Supply VA+ IIN1+ Differential Current Input 1 Negative Analog Supply VA- IIN1- Differential Current Input 1 Differential Voltage Input 3 VIN3+ VIN2+ Differential Voltage Input 2 Differential Voltage Input 3 VIN3- VIN2- Differential Voltage Input 2 Differential Current Input 3 IIN3+ IIN2+ Differential Current Input 2 Differential Current Input 3 IIN3- IIN2- Differential Current Input 2
12 DS458PP4
Measurement and Reference Input IIN(1-3)+, IIN(1-3)- - Differential Current Inputs Differential analog input pins for current channels. VIN(1-3)+, VIN(1-3)- - Differential Voltage Inputs Differential analog input pins for voltage channels. VREFOUT - Voltage Reference Output The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 1.2 V and is referenced to the AGND pin on the converter. VREFIN - Voltage Reference Input The voltage input to this pin establishes the voltage reference for the on-chip modulator. Power Supply Connections V A+ - Positive Analog Supply The positive analog supply is nominally +3 V ±10% relative to AGND. V A- - Negative Analog Supply The negative analog supply is nominally -2 V ±10% relative to AGND. AGND - Analog Ground The analog ground pin for input signals. VD+ - Positive Digital Supply The positive digital supply is nominally +3 V ±10% relative to DGND. DGND - Digital Ground The digital ground is typically at the same level as AGND. CPD - Charge Pump Drive This output pin drives the external charge pump circuitry to create a negative supply voltage.
- PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-150 28L SSOP PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW