CS5106

CS5106 CHERRY | Alldatasheet

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Features

Multi-Feature, Synchronous plus Auxiliary PWM Controller CS5106

Description

The CS5106 is a fixed frequency, current mode controller with one single NFET driver and one dual FET, synchronous driver. The syn- chronous driver allows for increased efficiency of the main iso- lated power stage and the single driver allows the designer to devel- op auxiliary supplies for controller power as well as secondary side house keeping. In addition, because the synchronous drivers have programmable FET non-over- lap, the CS5106 is an ideal con- troller for soft-switched converter topologies. The CS5106 is specifically designed for isolated topologies where speed, flexibility, reduced size and reduced component count are requirements. The controller con- tains the following features: Undervoltage Shutdown, Overvoltage Shutdown, Programmable Frequency, Programmable Synchronous Non- Overlap Time, Master/Slave Clocking with Frequency Range Detection, Enable, Output Undervoltage Protection with Timer, 20mA 5V Output, 80ns PWM propagation delay, and Controlled Hiccup Mode. The CS5106 has junction tempera- ture and supply ranges of -40ûC to 125ûC and 9V to 16V respectively and is available in the 24 lead SSOP package. Applications Diagram

24 Lead SSOP

Rev. 10/27/98 48V to 3.3V Forward Converter with Synchronous Rectifiers Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ¨

Lead Symbol Lead Name VMAX VMIN ISOURCE ISINK UVSD Undervoltage Shutdown Input 6V -0.3V 1mA N/A OVSD Overvoltage Shutdown Input 6V -0.3V 1mA N/A V 5REF 5V Reference Output 6V -0.3V 150mA 25mA OAM Error Amp Minus Input 6V -0.3V 250µA 1.2mA OAOUT Error Amp Output 6V -0.3V 300µA 100mA OUVDELAY Output Overcurrent Timer Capacitor 6V -0.3V 15µA N/A I LIM1 Auxiliary Primary Side Current Limit Input 6V -0.3V 10µA N/A RAMP1 Auxiliary Primary Side Current Ramp Input 6V -0.3V 10µA N/A VFB1 Auxiliary Voltage Feedback Input 6V -0.3V 5µA 100µA VSS Bootstrapped Power Input 20V -0.3V 2µA 0.5A Peak 300mA DC VCC Main Power Input 20V -0.3V See Note 1 0.5A Peak 300mA DC GATE1 Auxiliary FET Driver Output 20V -0.3V 0.5A Peak 0.5Peak 100mA DC 100mA DC Gnd Ground 0V 0V 0.5A Peak N/A 300mA DC GATE2 Synchronous FET Driver Output 20V -0.3V 0.5A Peak 0.5APeak 100mA DC 100mA DC GATE2B Synchronous FET Driver Output B 20V -0.3V 0.5A Peak 0.5A Peak 100mA DC 100mA DC VFB2 Synchronous Voltage Feedback Input 6V -0.3V 10µA 100µA RAMP2 Synchronous Primary Side Current Ramp Input 6V -0.3V 10µA N/A ILIM2 Synchronous Primary Side Current Limit Input 6V -0.3V 10µA N/A DLYSET Gate Non-Overlap Programming Input 2.5V -0.3V 125µA N/A FADJ Frequency Programming Input 2.5V -0.3V 125µA N/A SYNC OUT Clock Master Output 6V -0.3V 50mA 100mA SYNCIN Clock Slave Input 6V -0.3V N/A 1mA PROGRAM Enable Programming Input 16V -0.3V 30µA N/A ENABLE Enable Input 16V -0.3V 300µA N/A Note 1: Current out of VCC is not limited. Care should be taken to prevent shorting VCC to Ground.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: TJ = -40¡C to 125¡C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless other- wise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k½. n VSS Supply Current Measure current into VSS when 16.00 23.00 mA V5REF ILOAD=0mA. 9V ² VSS ² 13V. Measure current into VSS when 16.00 25.00 mA V5REF ILOAD=0mA. 13V < VSS ² 16V. Measure current into VSS when 16.00 30.00 mA V5REF ILOAD=0mA. 16V < VSS ² 20V. n Low VCC Supply Current Float VSS. Set VCC=7V & measure 1.50 3.50 mA VCC current while V5REF ILOAD=0mA. n VSS TO VCC DIODE Diode ON Voltage Measure V SS - VCC. 0.20 0.75 1.00 V n Reference 5V Internal Voltage Reference Measure V REF voltage when 4.85 5.00 5.15 V IREF=0 and IREF=20 mA. PWM1,2 goes low. n Low VCC Lockout VCC Turnon Threshold Voltage V CC increasing until ICC > 3.5mA 7.00 7.25 7.50 V V5REF ILOAD = 0mA VCC Turnoff Threshold Voltage V CC decreasing until ICC < 3.5mA 6.30 6.70 7.10 V V5REF ILOAD = 0mA Hysteresis Turnon - Turnoff 0.40 0.55 0.70 V n Clock Operating Frequency1 Measure frequency from SYNC OUT. 485.0 512.0 540.0 kHz SYNCIN Input Impedance Measure input impedance. 7.00 15.00 k½ SYNCOUT Output Low Voltage R LOAD = 2k½ to V5REF 1.00 1.50 V SYNCOUT Output High R LOAD = 2k½ to Gnd 3.50 4.20 V Voltage SYNCIN Detect Frequency Verify SYNC OUT = SYNCIN, 425.0 555.0 kHz RLOAD = 2k½ to Gnd Max. Low SYNC Rej. Frequency Verify SYNC OUT = FCLK when 340.0 kHz RLOAD = 2k½ to Gnd. Min. High SYNC Rej. Frequency Verify SYNC OUT = FCLK when 690 kHz RLOAD = 2k½ to Gnd. SYNCIN Input Threshold Functional Testing 0.90 1.85 2.90 V Voltage Verify FCLK from 1.0V to 2.8V. Main PWM Clock Pulse (GBD) - CLPH1 Width One Shot Pulse Width 80.0 100.0 120.0 ns Aux PWM Clock Pulse (GBD) -CLPH2 Width One Shot Pulse Width 80.0 100.0 120.0 ns n Bias Supply Error Amplifier Output Low Voltage V SS > 12.6V. Measure OAOUT 43.0 85.0 mV voltage when sinking 1.0 mA. Output High Voltage V SS < 11.4V. Measure OAOUT 4.55 4.75 V voltage when sourcing 150µA. current when OAOUT = 0.5V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: TJ = -40¡C to 125¡C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless other- wise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k½. n Bias Supply Error Amplifier: continued current when OAOUT = 2.5V. VSS Set Point Adjust V SS until OAOUT goes low. 11.60 12.25 12.80 V Large Signal Gain (GBD) 15.00 V/mV Unity Gain Bandwidth (GBD) 1.00 MHz Common Mode Input Range (GBD) 1.00 2.00 V n V SS Voltage VSS Reset Voltage Toggle ENABLE between Gnd & V CC, then adjust VSS from 2.0V-0.8V until OAOUT goes high. 1.00 1.40 1.80 V n Undervoltage Lockout Threshold Voltage until GATE 1, 2 goes high. Voltage until GATE 1, 2 goes low. Hysteresis Turnon - Turnoff 0.20 0.27 0.40 V UVSD Input Bias Current Set UVSD=0V. Measure Current 0.20 0.50 µA out of UVSD lead. n Overvoltage Lockout until GATE 1, 2 goes low. OVSD Input Bias Current Set OVSD=0V. Measure Current out 0.20 0.50 µA of OVSD lead. n ENABLE & PROGRAM ENABLE Lead Output Current Measure current out of 100.0 266.0 500.0 µA ENABLE when ENABLE = 0V. PROGRAM Lead Output Measure current out of 20.0 60.0 100.0 µA Current PROGRAM when PROGRAM = 0V. PROGRAM Threshold ENABLE = Gnd. Adjust 1.20 1.40 1.60 V Voltage PROGRAM from 1.0V - 1.8V until GATE 1, 2 goes high. ENABLE Threshold Voltage PROGRAM = Gnd. 1.20 1.40 1.60 V Adjust ENABLE from 1.0V - 1.8V until GATE 1, 2 goes high. n Output Undervoltage Delay OUVDELAY Charging Set OUVDELAY = 1V, V FB1 = 4.4V 7.50 10.00 12.50 µA Current Measure OUVDELAY I CHARGE. OUVDELAY Latchoff Voltage Toggle ENABLE between Gnd & V CC, 4.80 5.00 5.20 V then adjust OUVDELAY from 4.7V - 5.3V until GATE 1, 2, goes low. OUVDELAY Set Current OUVDELAY = VOCLO + 50mV 0.50 1.00 mA Measure current into OUVDELAY. V FB1 Charge Threshold V SS=1V. Toggle ENABLE between 4.05 4.22 4.40 V Gnd & VCC, adjust VFB1 from 3.8V - 4.6V until GATE 1, 2 goes low. VFB2 Charge Threshold V SS = 1V. Toggle ENABLE between 3.90 4.15 4.35 V Gnd & VCC, adjust VFB2 from 3.8V - 4.6V until GATE 1, 2 goes low.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS5106 Electrical Characteristics: TJ = -40¡C to 125¡C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless other- wise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k½. n Current Limit Circuits Voltage GATE1 goes low. Voltage GATE1 skips 2-cycles with reference to SYNCOUT. ILIM1 Input Bias Current Set I LIM1=0V. Measure current 0.50 5.00 µA out of ILIM1 lead. Threshold V GATE2 goes low. Threshold Voltage GATE2 skips 2-cycles with reference to SYNCOUT. ILIM2 Input Bias Current Set I LIM 2= 0V. Measure current out 0.50 5.00 µA of ILIM2 lead. n Voltage Feedback Control until GATE1 goes low. Measure VRAMP1. RAMP1 Input Bias Current Set RAMP1 = 0V. Measure Current 0.50 5.00 µA out of RAMP1 lead. RAMP2 Offset Voltage V FB2 = 0V. Adjust RAMP2 from 0.08 0.13 0.20 V 0V-3V until GATE2 goes low. Measure V RAMP2. RAMP2 Input Bias Current Set RAMP2 = 0V. Measure Current out of RAMP2 lead. 0.50 5.00 µA VFB1 Input Impedance Measure input impedance. 60.0 120.0 220.0 k½ VFB2 Input Impedance Measure Input impedance. 60.0 120.0 220.0 k½ n Gate1,2,2B Output Voltages V SS = 12V. VCC = VSS - VDON GATE1 Low State PROGRAM = 0V. Measure GATE1 0.15 0.80 V voltage when sinking 1mA. GATE2 Low State PROGRAM = 0V. Measure GATE2 0.18 0.80 V voltage when sinking 1mA. GATE2B Low State PROGRAM = 0V. Measure GATE2B 0.18 0.80 V voltage when sinking 1mA. GATE2B High State Measure V CC - GATE2B voltage 1.65 2.00 V when sourcing 1mA. GATE2 High State Measure V CC - GATE2 voltage 1.65 2.00 V when sourcing 1mA. GATE1 High State Measure V CC - GATE1 voltage 1.65 2.00 V when sourcing 1mA. n Propagation Delays ILIM1 Delay to Output GATE1 Measure delay from I LIM1 going 80.0 120.0 ns high to GATE1 going low. ILIM2 Delay to Output GATE2 Measure delay from I LIM2 going 80.0 100.0 ns high to GATE2 going low. RAMP1 Delay to Output GATE1 Measure delay from RAMP1 going 80.0 115.0 ns high to GATE1 going low. RAMP2 Delay to Output GATE2 Measure delay from RAMP2 going 80.0 100.0 ns high to GATE2 going low.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: TJ = -40¡C to 125¡C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless other- wise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k½. PACKAGE LEAD # LEAD SYMBOL FUNCTION n GATE 2, 2B Non-Overlap Delay GATE2 Turn-on Delay Measure delay from GATE2B going low 20.0 45.0 70.0 ns from GATE2B @1.7V to GATE2 going high @1.7V. GATE2B Turn-on Delay Measure delay from GATE2 going low 20.0 45.0 70.0 ns from GATE2 @1.7V to GATE2B going high @1.7V. n GATE 1, 2, 2B Rise & Fall Times V SS=12V,VCC=VSS-VDON GATE1 Rise Time Measure GATE1 Rise Time from 50.0 80.0 ns 90% to 10%. CLOAD = 150pF. GATE1 Fall Time Measure GATE1 Fall Time from 10% to 90%. CLOAD = 150pF. 30.0 60.0 ns GATE2 Rise Time Measure GATE2 Rise Time from 90% to10%. CLOAD = 50pF. 50.0 80.0 ns GATE2 Fall Time Measure GATE2 Fall Time from 10% to 90%. CLOAD = 50pF. 15.0 30.0 ns GATE2B Rise Time Measure GATE2B Rise Time from 90% to10%. CLOAD = 50pF. 50.0 80.0 ns GATE2B Fall Time Measure GATE2B Fall Time from 10% to 90%. CLOAD = 50pF. 15.0 30.0 ns 1 UVSD Undervoltage shutdown lead. Typically this lead is connected through a resistor divider to the main high voltage (VIN) line. If the voltage on this lead is less than 5V then a fault is initiated such that GATE1, GATE2 and GATE2B go low. 2 OVSD Overvoltage shutdown lead. Typically this lead is connected through a resistor divider to the main high voltage (V IN) line. If the voltage on this lead exceeds 5V then a fault is initiated such that GATE1, GATE2 and GATE2B go low. 3V 5REF 5V reference output lead. Capable of 20mA nominal output. If this lead falls to 4.5V, a fault is initiated such that GATE1, GATE2 and GATE2B go low. 4 OAM Auxiliary error amplifier minus input. This lead is compared to 1.2V nominal on the auxiliary error amp plus lead and represents the VSS voltage divided by ten. 5 OAOUT Auxiliary error amplifier output lead. Source current 300µA max. 6 OUVDELAY Output undervoltage timing capacitor lead. If the controlled output voltages of either the main or the auxiliary supply are such that either V FB1 or VFB2 is greater that 4.1V nominal, then capacitor from OUVDELAY to ground will begin charging. If the over voltage duration is such that the OUVDELAY voltage exceeds 5V, then a fault will be initiated such that GATE1, GATE2 and GATE2B will go low. LIM1 Pulse by pulse over current protection lead for the auxiliary PWM. A voltage exceeding 1.2V nominal on ILIM1 will cause GATE1 to go low. A voltage exceeding 1.4V nominal on ILIM1 will cause GATE1 to go low for at least two clock cycles. 8 RAMP1 Current Ramp Input Lead for the Auxiliary PWM. A voltage which is linear with respect to current in the primary side of the auxiliary trans former is usually represented on this lead. A voltage exceeding V FB1 - 0.13 on RAMP1 will cause GATE1 to go low.

PACKAGE LEAD # LEAD SYMBOL FUNCTION Package Lead Description: continued 9V FB1 Voltage Feedback Lead for the Auxiliary PWM. A voltage which represents the auxiliary power supply output voltage is fed to this lead. A voltage less than RAMP1+0.13 on V FB1 will cause GATE1 to go low. 10 V SS VSS power/feedback input lead. See VCC for description of power operation. In addition, this lead is fed to a divide by ten resistor divider and compared to 1.2V nominal at the positive side of the error amplifier. 11 V CC VCC power input lead. This input runs off a Zener referenced supply until VSS > VCC. Then an internal diode which runs between VSS and VCC turns on and all main power is derived from VSS. 12 GATE1 Auxiliary PWM gate drive lead. This output normally drives the FET which drives the auxiliary transformer. 13 Gnd Ground lead. 14 GATE2 Synchronous PWM gate drive lead. This output normally drives the FET which drives the main transformer. 15 GATE2B Synchronous PWM gate drive lead. This output normally drives the FET for the gate drive transformer used for synchronous rectification. 16 V FB2 Voltage feedback lead for the synchronous PWM. A voltage which represents the main power supply output voltage is fed to this lead. A voltage less than RAMP2+0.13 on V FB2 will cause GATE2 to go low and GATE2B to go high. 17 RAMP2 Current ramp input lead for the synchronous PWM. A voltage which is linear with respect to current in the primary side of the main trans former is usually represented on this lead. A voltage exceeding V FB2 - 0.13 on RAMP2 will cause GATE2 to go low and GATE2B to go high. 18 I LIM2 Pulse by pulse over current protection lead for the synchronous PWM. A volt- age exceeding 1.2V nominal on ILIM2 will cause GATE2 to go low and GATE2B to go high. A voltage exceeding 1.4V nominal on ILIM2 will cause GATE2 to go low and GATE2B to go high for at least two clock cycles. 19 DLYSET GATE2, GATE2B non-overlap time adjustment lead. A 27k½ resistor from DLYSET to ground sets the non-overlap time to 45ns nominal. 20 FADJ Frequency adjustment lead. A 27k½ resistor from FADJ to ground sets the clock frequency to 512kHz nominal. 21 SYNC OUT Clock output lead. This is a 50% duty cycle, 1V to 5V pulse whose rising edge is in phase with GATE1. This signal can be used to synchronize other power supplies.

22 SYNC

IN Clock synchronization lead. The internal clock frequency can be adjusted +10%, -15% by the onset of positive edges of an external clock occurring on the SYNC IN lead. If the external clock frequency is out side the internal clock fre- quency by +25%, -35% the external clock is ignored and the internal clock free runs. 23 PROGRAM ENABLE programming input. See ENABLE for programming states. PRO- GRAM has at least 20µA min. of available source current. 24 ENABLE PWM enable input. If PROGRAM is HIGH then a LOW on ENABLE will allow GATE1, GATE2 and GATE2B to switch. If PROGRAM is LOW then a HIGH on ENABLE will allow GATE1, GATE2 and GATE2B to switch. If ENABLE is left floating, it will pull up to a HIGH level. ENABLE has at least 100µA (min) of available source current.

V V V V V V V V V V V OUVDELAY OAOUT OAM VSS Aux. Error Amp A1 1.2V + 45k VCC D1 Output Undervoltage Timer V 5REF 100k RUN1 RUN 2G6 VREFOK VFB1 SYNCIN PROGRAM ENABLE UVSD SYNCOUT DYLSET FADJ RAMP2 GATE2 GATE2B ILIM2 VFB2 VREFOK RUN 1 VSS G8 FREQ TOO LOW Aux.PWM Comparator V REFOK Comparator Main PWM Comparator Sync Detection Main 2nd Current Threshold Comparator Aux. 2nd Current Threshold Comparator Aux. Current Limit Comparator Main Current Limit Comparator C11 1.2V V Skip Two Clock Pulses SET CLOCK SET CLOCK Skip Two Clock Pulses G15 C17C16 Skip2B G14 G18 1.4V GATE1 Gnd ILIM1 RSFF QR S TPERIOD DRIVER C10 C12 C13 OSC IFSET CLK1 CLK2 IDSET SYNCIN SYNCOUT OVSD G13 C14 G16G17 C15 DELAY DELAY G12 RUN2 RUN2 1.7V + DRIVER Reset Dominant G11G10 VREFENABLE VREF=5V VCC RSFF RQ S Set Dominant Over Voltage Comparator VSS Restart Comparator Reset Dominant RSFF Q S R Reset Dominant RSFF Q S R -C4 +C7 Skip2B ENABLE Comparator Under Voltage Comparator R DRIVER TFF Q + 0.13V0.13V + START STOP R RUN1 + 1.5V Fault Latch C3+ FREQ TOO HIGH 1.4V 4.5 7.4/6.8V 1.4V RAMP1 1.4V Q Theory of Application Powering the IC The IC has one supply, VCC, and one Ground lead. If VSS is used for a bootstrapped supply the diode between VSS and VCC is forward biased, and the IC will derive its power from VSS. The internal logic monitors the supply voltage, VCC. During abnormal operating conditions, all GATE drivers are held in a low state. The CS5106 requires 1.5mA nominal of startup current. Startup Assume the part is enabled and there are no over voltage or under voltage faults present. Also, assume that all auxil- iary and main regulated output voltages start at 0V. An 8V, Zener referenced supply is typically applied to V CC. When VCC exceeds 7.5V, the 5V reference is enabled and the OSC begins switching. If the V5REF lead is not exces- sively loaded such that V5REF < 4.5V nominal, ÔVREFOKÕ goes ÔhighÕ and ÔRUN1Õ will go ÔhighÕ, releasing GATE1 from its low state. After GATE1 is released, it begins switching according to conditions set by the auxiliary con- trol loop and the auxiliary supply, V SS begins to rise. When VSS > VCC + V(D1), P1 turns on and ÔRUN2Õ goes ÔhighÕ, releasing GATE2 and GATE2B from their low state. GATE2 and GATE2B begin switching according to condi- tions set by the main control loop and the main regulated output begins to rise. See startup waveforms in Figure 1. Soft Start Soft start for the auxiliary power supply is accomplished by placing a capacitor between OAOUT and Ground. The error amplifier has 200µA of nominal of source current and is ideal for setting up a Soft Start condition for the auxiliary regulator. Care should be taken to make sure that the soft start timing requirements are not in conflict with any tran- sient load requirements for the auxiliary supply as large capacitors on OAOUT will slow down the loop response. Also, the Soft start capacitor must be chosen such that dur- ing start or restart, both outputs will come into regulation before the OUVDELAY timer trips. Soft Start for the main supply is accomplished by charging soft start capacitor C6 through D5 and R7 at start up. After the main supply has come into regulation C6 continues to charge and is discon- nected from the feedback loop by D8. Theory of Operation

RQJC typ 23 ûC/W RQJA typ 117 ûC/W Rev. 10/27/98 © 1999 Cherry Semiconductor Corporation Package Specification PACKAGE DIMENSIONS IN mm (INCHES) D Lead Count Metric English Max Min Max Min 24 Lead SSOP 8.50 7.90 .335 .311 PACKAGE THERMAL DATA CS5106

Ordering Information

CS5106LSWR24 24 Lead SSOP (tape & reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Seating Plane 0.65 (.026) BSC 0.38 (.015) 0.22 (.009) D 0.25 (.010) 0.05 (.002) 1.88 (.074) 1.03 (.041) 0.77 (.030) 8.20 (.323) 7.40 (.291) 0.20 (.008) 0.09 (.004) 5.60 (.220) 5.00 (.197) See DETAIL A Parting Line DETAIL A REF: JEDEC MO-150 SSOP (SW); 5.3mm Body