CS51033

CS51033 CHERRY | Alldatasheet

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Features

3.3VIN 1.5VOUT @3Amp 0.1µF VC PGnd Gnd 100µF 1µF 1N4148 1N4148 CS 0.1µF C4C0 1N5821 4.7µH CIN 100µF 1N5818 Gnd RA 1.5k RB 300 NOTE: Capacitors C2, C3 and C4 are low ESR tantalum caps used for noise reduction. RG 10Ω RC 10Ω .1µF 100µF 100µF 0.1µF 100 0.01µF I 1A Totem Pole Output Driver I High Speed Oscillator (700kHz max) I No Stability Compensation Required I Lossless Short Circuit Protection I 2% Precision Reference I Programmable Soft Start Package Options CS51033 Fast PFET Buck Controller Does Not Require Compensation CS51033

Description

The CS51033 is a switching con- troller for use in DC-DC converters. It can be used in the buck topology with a minimum number of exter- nal components. The CS51033 con- sists of a 1.0A power driver for con- trolling the gate of a discrete P- channel transistor, fixed frequency oscillator, short circuit protection timer, programmable soft start, pre- cision reference, fast output voltage monitoring comparator, and output stage driver logic with latch. The high frequency oscillator allows the use of small inductors and output capacitors, minimizing PC board area and systems cost. The programmable soft start reduces current surges at start up. The short circuit protection timer significantly reduces the PFET duty cycle to approximately 1/30 of its normal cycle during short circuit conditions. The CS51033 is available in 8L SO and 8L PDIP plastic packages. Typical Application Diagram 1VGATE PGnd COSC Gnd VC CS VCC VFB

8 Lead SO Narrow & PDIP

A Company ® Rev. 2/13/98 Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com

Lead Temperature Soldering PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS51033 Absolute Maximum Ratings Electrical Characteristics: Specifications apply for 3.135 ≤ VCC ≤ 3.465V, 3V ≤ VC ≤ 16V, -40°C ≤ TA ≤ 125°C, -40°C ≤ TJ ≤ 125°C, unless otherwise specified. I Oscillator V FB = 1.2V Frequency C OSC = 470pF 160 200 240 kHz Charge Current 1.4V < V COSC < 2V 110 µA Discharge Current 2.7V > V COSC > 2V 660 µA Maximum Duty Cycle 1 – (t OFF/tON) 80.0 83.3 % I Short Circuit Timer V FB = 1.0V; CS = 0.1µF; VCOSC = 2V Charge Current 1V < V CS < 2V 175 264 325 µA Fast Discharge Current 2.55V > V CS > 2.4V 40 66 80 µA Slow Discharge Current 2.4V > V CS > 1.5V 4 6 10 µA Start Fault Inhibit Time 0.70 0.85 1.40 ms Valid Fault Time 2.6V > V CS > 2.4V 0.2 0.3 0.45 ms GATE Inhibit Time 2.4V > V CS > 1.5V 9 15 23 ms Duty Cycle 2.5 3.1 4.6 % I CS Comparator V FB = 1V Fault Enable CS Voltage 2.5 V Max. CS Voltage V FB = 1.5V 2.6 V Fault Detect Voltage V CS when GATE goes high 2.4 V Fault Inhibit Voltage Minimum V CS 1.5 V Hold Off Release Voltage V FB = 0V 0.4 0.7 1.0 V Regulator Threshold V CS = 1.5V 0.725 0.866 1.035 V Voltage Clamp I VFB Comparator V COSC = VCS = 2V Regulator Threshold Voltage T J = 25°C (Note 1) 1.225 1.250 1.275 V TJ = -40 to 125°C 1.210 1.250 1.290 V Fault Threshold Voltage T J = 25°C (Note 1) 1.12 1.15 1.17 V TJ = -40 to 125°C 1.10 1.15 1.19 V Threshold Line Regulation 3.135V ≤ VCC ≤ 3.465 6 15 mV Input Bias Current V FB = 0V 1 4 µA Voltage Tracking (Regulator Threshold Voltage - 70 100 120 mV Fault Threshold Voltage) Input Hysteresis Voltage 4 20 mV

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS51033 Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION Electrical Characteristics: Specifications apply for 3.135 ≤ VCC ≤ 3.465V, 3V ≤ VC ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise specified. 8L SO Narrow & PDIP 1V GATE Driver pin to gate of external PFET. 2 PGnd Output power stage ground connection. OSC Oscillator frequency programming capacitor. 4 Gnd Logic ground. FB Feedback voltage input. 6V CC Logic supply voltage. 7 CS Soft start and fault timing capacitor. C Driver supply voltage. I Power Stage V C = 10V; VFB = 1.2V GATE DC Low Saturation V COSC = 1V; 200mA Sink 1.2 1.5 V Voltage GATE DC High Saturation V COSC = 2.7V; 200mA Source; VC = VGATE 1.5 2.1 V Voltage Rise Time C GATE = 1nF; 1.5V < VGATE < 9V 25 60 ns Fall Time C GATE = 1nF; 9V > VGATE > 1.5V 25 60 ns I Current Drain ICC 3.135V < VCC < 3.465V, Gate switching 3.5 6.0 mA IC 3V < VC < 16V, Gate non-switching 2.7 4.0 mA Note1: Guaranteed by design not 100% tested in production.

R S 2.5V1.5V 1.25V 1.15V Q G1A1 RG VCC 2.4V 2.5V1.5V IC 7IC VCC IT Q IT IT Fault Comp -A4 0.7V 2.3VQR QS Slow Discharge Comparator Slow Discharge Flip-Flop CS Charge Sense Comparator CS Comparator Oscillator Comparator V FB Comparator VGATE Flip-Flop Hold Off Comp Control Scheme The CS51033 monitors the output voltage to determine when to turn on the PFET. If VFB falls below the internal ref- erence voltage of 1.25V during the oscillator’s charge cycle, the PFET is turned on and remains on for the duration of the charge time. The PFET gets turned off and remains off dur- ing the oscillator’s discharge cycle time with the maximum duty cycle to 80%. It requires 7mV typical, and 20mV maxi- mum ripple on the V FB pin is required to operate. This method of control does not require any loop stability com- pensation. Startup The CS51033 has an externally programmable soft start fea- ture that allows the output voltage to come up slowly, pre- venting voltage overshoot on the output. At startup, the voltage on all pins is zero. As V CC rises, the VC voltage along with the internal resistor RG keeps the PFET off. As VCC and VC continue to rise, the oscillator capacitor (COSC ) and the Soft start/Fault Timing capacitor (CS) charges via internal current sources. COSC gets charged by the current source IC and CS gets charged by the IT source combination described by: ICS = IT - ( + ) The internal Holdoff Comparator ensures that the external PFET is off until VCS > 0.7V preventing the GATE flip-flop (F2) from being set. This allows the oscillator to reach its operating frequency before enabling the drive output. Soft start is obtained by clamping the VFB comparator’s (A6) ref- erence input to approximately 1/2 of the voltage at the CS pin during startup, permitting the control loop and the out- put voltage to slowly increase. Once the CS pin charges above the Holdoff Comparator trip point of 0.7V, the low IT IT Theory of Operation Circuit Description Figure 1: Block Diagram for CS51033

Applications Information: continued D = From this, the maximum duty cycle DMAX is 53%, this occurs when VIN is at its minimum while the minimum duty cycle DMIN is 0.35%. 2) Switching Frequency and on and off time calculations. F SW= 200KHz. The switching frequency is determined by COSC, whose value is determined by : COSC = 95 ≅ 470pF Fsw × (1-() -() T = = 5µs TON(MAX) = 5µs × 0.53 = 2.65µs TON(MIN) = 5µs × 0.35 = 1.75µs TOFF(MAX) = 5µs − 0.7µs = 4.3µs 3) Inductor selection Pick the inductor value to maintain continuous mode opera- tion down to 0.3 Amps. The ripple current ∆I = 2 × I OUT(MIN) = 2 × 0.3A = 0.6A. LMIN == ≅ 15µH The CS51033 will operate with almost any value of inductor. With larger inductors the ripple current is reduced and the regulator will remain in a continuous conduction mode for lower values of load current. A smaller inductor will result in larger ripple current. The core must not saturate with the maximum expected current, here given by: I 4) Output Capacitor The output capacitor limits the output ripple voltage. The CS51033 needs a maximum of 15mV of output ripple for the feedback comparator to change state. If we assume that all the inductor ripple current flows through the output capaci- tor and that it is an ideal capacitor (i.e. zero ESR), the mini- mum capacitance needed to limit the output ripple to 50mV peak to peak is given by: CO = = ≅ 11.4µF The minimum ESR needed to limit the output voltage ripple to 50mV peak to peak is: ESR = = = 55m Ω The output capacitor should be chosen so that its ESR is at least half of the calculated value and the capacitance is at least ten times the calculated value. It is often advisable to use several capacitors in parallel to reduce the ESR. Low impedance aluminum electrolytic, tantalum or organic semiconductor capacitors are a good choice for an output capacitor. Low impedance aluminum are the cheapest but are not available in surface mount at present. Solid tantalum chip capacitors are available from a number of suppliers and offer the best choice for surface mount applications. The capacitor working voltage should be greater than the output voltage in all cases. 5) V FB Divider The input bias current to the comparator is 4µA. The resistor divider current should be considerably higher than this to ensure that there is sufficient bias current. If we choose the divider current to be at least 250 times the bias current this gives a divider current of 1mA and simplifies the calcula- tions. = R1+R2 = 1.5KΩ Let R2 = 1K Rearranging the divider equation gives: R1 = R2 6) Divider bypass capacitor Crr Since the feedback resistors divide the output voltage by a factor of 4, i.e. 5V/1.25V= 4 it follows that the output ripple is also divided by four. This would require that the output ripple be at least 60mV (4 × 15mV) to trip the feedback com- pactor. We use a capacitor Crr to act as an ac short so that the output ripple is not attenuated by the divider network. The ripple voltage frequency is equal to the switching fre- quency so we choose Crr so that: X C = is negligible at the switching frequency. In this case FSW is 200kHz if we allow XC = 3Ω then: C = ≅ 0.265µF 7) Soft start and Fault timing capacitor CS. CS performs several important functions. First it provides a dead time for load transients so that the IC does not enter a fault mode every time the load changes abruptly. Secondly it disables the fault circuitry during startup, it also provides soft start by clamping the reference voltage during startup 2πf3 2πfC 1.5V 1.25 VOUT 1.25 1.5V 1mA R1 + R2 50 × 10-3 0.6A 0.6A 8 × FSW × ∆V IOUT + ∆I 2.1V × 4.3µs 0.6A VOUT + VD × ΤOFF(MAX) FSW 30 × 10 3 FSW FSW 3 × 10 6 VOUT VIN

to rise slowly and finally it controls the Hiccup short circuit protection circuitry. This function reduces the PFET's duty cycle to 2% of the C S period. The most important consideration in calculating CS is that it’s voltage does not reach 2.5V (the voltage at which the fault detect circuitry is enabled) before V FB reaches 1.15V otherwise the power supply will never start. If the VFB pin reaches 1.15V the fault timing comparator will discharge CS and the supply will not start. For the VFB volt- age to reach 1.15V the output voltage must be at least 4 × 1.15 = 4.6V. If we choose an arbitrary startup time of 200µs we calculate the value of C S from: T = CS(min) = = 0.02µF Use 0.1µf. The fault time out time is the sum of the slow discharge time the fast discharge time and the recharge time and is obviously dominated by the slow discharge time. The first parameter is the slow discharge time, it is the time for the C S capacitor to discharge from 2.4V to 1.5V and is given by: TSLOWDISCHARGE = Where IDISCHARGE is 6µA typical. TSLOWDISCHARGE = CS × 1.5V × 105 The fast discharge time occurs when a fault is first detected. The CS capacitor is discharged from 2.5V to 2.4V. TFASTDISCHARGE = Where IFASTDISCHARGE is 66µA typical. TFASTDISCHARGE = CS × 1515 The recharge time is the time for CS to charge from 1.5V to 2.5V. TCHARGE = Where ICHARGE is 264µA typical. TCHARGE = CS × 3787 The fault time out time is given by: TFAULT = CS × (3787 + 1515 + 1.5 × 105) TFAULT = CS × 1.55 × 105 For this circuit TFAULT = 0.1 × 10-6 × 1.55 × 105 = 0.0155 A larger value of CS will increase the fault time out time but will also increase the soft start time. 8) Input Capacitor. The input capacitor reduces the peak currents drawn from the input supply and reduces the noise and ripple voltage on the V CC and VC pins. This capacitor must also ensure that the VCC remains above the UVLO voltage in the event of an output short circuit. CIN should be a low ESR capacitor of at least 100µf. A ceramic surface mount capacitor should also be connected between V CC and ground to prevent spikes. 9) MOSFET Selection The CS51033 drive a P-channel MOSFET. The V GATE pin swings from Gnd to VC. The type of PFET used depends on the operating conditions but for input voltages below 7V a logic level FET should be used. Choose a PFET with a continuous drain current (Id) rating greater than the maximum output current. R DS(on) should be less than RDS < = 167m Ω The Gate-to-Source voltage VGS and the Drain-to Source Breakdown Voltage should be chosen based on the input supply voltage. The power dissipation due to the conduction losses is given by: P D = OUT2 × RDS(on) × D The power dissipation due to the switching losses is given by: PD = 0.5 × VIN × IOUT × (TRr + TF) × FSW Where tr =Rise Time and tf= Fall Time. 10) Diode Selection. The flyback or catch diode should be a Schottky diode because of it’s fast switching ability and low forward volt- age drop. The current rating must be at least equal to the maximum output current. The breakdown voltage should be at least 20V for this 12V application. The diode power dissipation is given by: P D = IOUT × VD × (1-DMIN) 0.6V IOUT(max) CS × (2.5V-1.5V) ΙCHARGE CS × (2.5V - 2.4V) ΙFASTDISCHARGE CS × (2.4V-1.5V) ΙDISCHARGE 200µs × 264µA 2.5V CS × 2.5V ICHARGE Applications Information: continued

8 © 1999 Cherry Semiconductor CorporationRev. 2/13/98

Ordering Information

CS51033YDR8 8L SO Narrow (tape & reel) CS51033YN8 8L PDIP Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Package Specification Thermal Data 8L SO Narrow 8L PDIP RΘJC typ 45 52 ˚C/W RΘJA typ 165 100 ˚C/W D Lead Count Metric English Max Min Max Min 8L SO Narrow 5.00 4.80 .197 .189 8L PDIP 10.16 9.02 .400 .355 PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA Surface Mount Narrow Body (D); 150 mil wide Plastic DIP (N); 300 mil wide 0.39 (.015) MIN. 1.14 (.045) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. .203 (.008) .356 (.014) REF: JEDEC MS-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022) 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) D 0.25 (0.10) 0.10 (.004) 1.75 (.069) MAX 1.27 (.050) 0.40 (.016) REF: JEDEC MS-012 0.25 (.010) 0.19 (.008)