CS51031 CHERRY | Alldatasheet
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Features
0.1mF RA 1.5kW RB 2.5kW CO 100mF ´ 2 MP1 5V - 12V L 4.7mH CRR 0.1mF CIN 47mF VO 3.3V @ 3A MBRS360 IRF7416 VGATE 20W RVCC 10W CVCC 100mF .01mF 100 n 1A Totem Pole Output Driver n High Speed Oscillator (700kHz max) n No Stability Compensation Required n Lossless Short Circuit Protection n VCC Monitor n 2% Precision Reference n Programmable Soft Start Package Options CS51031 Fast PFET Buck Controller Does Not Require Compensation CS51031
Description
The CS51031 is a switching con- troller for use in DC-DC converters. It can be used in the buck topology with a minimum number of exter- nal components. The CS51031 con- sists of a V CC monitor for control- ling the state of the device, 1.0A power driver for controlling the gate of a discrete P-channel transis- tor, fixed frequency oscillator, short circuit protection timer, pro- grammable soft start, precision ref- erence, fast output voltage monitor- ing comparator, and output stage driver logic with latch. The high frequency oscillator allows the use of small inductors and output capacitors, minimizing PC board area and systems cost. The programmable soft start reduces current surges at start up. The short circuit protection timer significantly reduces the duty cycle to approximately 1/30 of its cycle during short circuit conditions. The CS51031 is available in 8L SO and 8L PDIP plastic packages. Typical Application Diagram 1VGATE PGnd COSC Gnd VC CS VCC VFB
8 Lead SO Narrow & PDIP
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ¨ Rev. 2/13/98
Lead Temperature Soldering PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS51031 Absolute Maximum Ratings Electrical Characteristics: Specifications apply for 4.5 ² VCC ² 16V, 3V ² VC ² 16V, -40¡C ² TJ ² 125¡C, unless otherwise specified. n Oscillator V FB = 1.2V Frequency C OSC = 470pF 160 200 240 kHz Charge Current 1.4V < V COSC < 2V 110 µA Discharge Current 2.7V > V COSC > 2V 660 µA Maximum Duty Cycle 1 Ð (t OFF/tON) 80.0 83.3 % n Short Circuit Timer V FB = 1.0V; CS = 0.1µF; VCOSC = 2V Charge Current 1V < V CS < 2V 175 264 325 µA Fast Discharge Current 2.55V > V CS > 2.4V 40 66 80 µA Slow Discharge Current 2.4V > V CS > 1.5V 4 6 10 µA Start Fault Inhibit Time 0V < V CS < 2.5V 0.70 0.85 1.40 ms GATE Inhibit Time 2.4V > V CS > 1.5V 9 15 23 ms Fault Duty Cycle 2.5 3.1 4.6 % n CS Comparator V FB = 1V Fault Enable CS Voltage 2.5 V Max. CS Voltage V FB = 1.5V 2.6 V Fault Detect Voltage V CS when GATE goes high 2.4 V Fault Inhibit Voltage Minimum V CS 1.5 V Hold Off Release Voltage V FB = 0V 0.4 0.7 1.0 V Regulator Threshold V CS = 1.5V 0.725 0.866 1.035 V Voltage Clamp n VFB Comparators V COSC = VCS = 2V Regulator Threshold Voltage T J = 25¡C (note 1) 1.225 1.250 1.275 V TJ = -40 to 125¡C 1.210 1.250 1.290 V Fault Threshold Voltage T J = 25¡C (note 1) 1.12 1.15 1.17 V TJ = -40 to 125¡C 1.10 1.15 1.19 V Threshold Line Regulation 4.5V ² V CC ² 16V 6 15 mV Input Bias Current V FB = 0V 1 4 µA Voltage Tracking (Regulator Threshold Voltage - 70 100 120 mV Fault Threshold Voltage) Input Hysteresis Voltage 4 20 mV
Electrical Characteristics: Specifications apply for 4.5 ² VCC ² 16V, 3V ² VC ² 16V, -40¡C ² TJ ² 125¡C, unless otherwise specified. Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION 8L SO Narrow & PDIP 1V GATE Driver pin to gate of external PFET. 2 PGnd Output power stage ground connection. OSC Oscillator frequency programming capacitor. 4 Gnd Logic ground. FB Feedback voltage input. 6V CC Logic supply voltage. 7 CS Soft start and fault timing capacitor. C Driver supply voltage. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT n Power Stage V CC = VC = 10V; VFB = 1.2V GATE DC Low Saturation V COSC = 1V; 200mA Sink 1.2 1.5 V Voltage GATE DC High Saturation V COSC = 2.7V; 200mA Source; VC = VGATE 1.5 2.1 V Voltage Rise Time C GATE = 1nF; 1.5V < VGATE < 9V 25 60 ns Fall Time C GATE = 1nF; 9V > VGATE > 1.5V 25 60 ns n VCC Monitor Turn On Threshold 4.200 4.400 4.600 V Turn Off Threshold 4.085 4.300 4.515 V Hysteresis 65 130 200 mV n Current Drain I CC 4.5V < VCC < 16V, Gate switching 4.5 6.0 mA IC 3V < VC < 16V, Gate non-switching 2.7 4.0 mA Shutdown ICC VCC = 4, 500 900 µA Note 1: Guaranteed by design not 100% tested in production.
R S 2.5V1.5V 1.25V 1.15V Q G1A1 RG VCC 3.3V VCCOK 2.4V VREF = 3.3V 2.5V1.5V IC 7IC VREF VCC IT Q IT IT Fault Comp -A4 0.7V 2.3VQR QS Slow Discharge Comparator Slow Discharge Flip-Flop CS Charge Sense Comparator CS Comparator Oscillator Comparator V FB Comparator VGATE Flip-Flop Hold Off Comp Control Scheme The CS51031 monitors and the output voltage to determine when to turn on the PFET. If VFB falls below the internal reference voltage of 1.25V during the oscillatorÕs charge cycle, the PFET is turned on and remains on for the dura- tion of the charge time. The PFET gets turned off and remains off during the oscillatorÕs discharge time with the maximum duty cycle to 80%. It requires 7mV typical, and 20mV maximum ripple on the V FB pin is required to oper- ate. This method of control does not require any loop sta- bility compensation. Startup The CS51031 has an externally programmable soft start fea- ture that allows the output voltage to come up slowly, pre- venting voltage overshoot on the output. At startup, the voltage on all pins is zero. As V CC rises, the VC voltage along with the internal resistor RG keeps the PFET off. As VCC and VC continue to rise, the oscillator capacitor (COSC ) and the Soft start/Fault Timing capacitor (CS) charges via internal current sources. COSC gets charged by the current source IC and CS gets charged by the IT source combination described by: ICS = IT - ( + ). The internal Holdoff Comparator ensures that the external PFET is off until VCS > 0.7V, preventing the GATE flip-flop (F2) from being set. This allows the oscillator to reach its operating frequency before enabling the drive output. Soft start is obtained by clamping the V FB comparatorÕs (A6) reference input to approximately 1/2 of the voltage at the CS pin during startup, permitting the control loop and the output voltage to slowly increase. Once the CS pin charges above the Holdoff Comparator trip point of 0.7V, the low feedback to the V FB Comparator sets the GATE flip-flop during COSC Õs charge cycle. Once the GATE flip-flop is set, VGATE goes low and turns on the PFET. When VCS exceeds IT IT Theory of Operation Circuit Description Figure 1: Block Diagram for CS51031
Applications Information: continued where VSAT = Rds(on) ´ IOUT max. and Rds(on)is the value at TJ 100ûC. If VF = 0.60V and VSAT = 0.60V then the above equation becomes: DMAX = = 0.62 DMIN = = 0.40 2) Switching frequency and on and off time calculations Given that fSW = 200kHz and DMAX = 0.80 T = = 5µs TON(max) = T ´ DMAX = 5µs ´ 0.62 @ 3µs TON(min) = T ´ DMIN = 5µs ´ 0.40 = 2µs TOFF(max) = TON(min) = 5µs - 2µs = 3µs 3) Oscillator Capacitor Selection The switching frequency is set by COSC, whose value is given by: COSC in pF = 95 ´ 10-6 Fsw 1+ - () 4) Inductor selection The inductor value is chosen for continuous mode opera- tion down to 0.3Amps. The ripple current ÆI = 2 ´ IOUTmin = 2 ´ 0.3A = 0.6A. Lmin = = =28µH This is the minimum value of inductor to keep the ripple current to <0.6A during normal operation. A smaller inductor will result in larger ripple current. Ripple current at a minimum off time is ÆI = = =0.4A The core must not saturate with the maximum expected current, here given by: IMAX = IOUT + ÆI/2 = 3A+0.4A/2 = 3.2A 5) Output capacitor The output capacitor and the inductor form a low pass fil- ter. The output capacitor should have a low ESL and ESR. Low impedance aluminum electrolytic, tantalum or organ- ic semiconductor capacitors are a good choice for an out- put capacitor. Low impedance aluminum are less expen- sive. Solid tantalum chip capacitors are available from a number of suppliers and are the best choice for surface mount applications. The output capacitor limits the output ripple voltage. The CS51031 needs a maximum of 20mV of output ripple for the feedback comparator to change state. If we assume that all the inductor ripple current flows through the output capacitor and that it is an ideal capacitor (i.e. zero ESR), the minimum capacitance needed to limit the output ripple to 50mV peak to peak is given by: C = = = 7.5µF The minimum ESR needed to limit the output voltage rip- ple to 50mV peak to peak is: ESR = = = 83m½ The output capacitor should be chosen so that its ESR is less than 83m½. During the minimum off time, the ripple current is 0.4A and the output voltage ripple will be: ÆV=ESR ´ ÆI = 83m½ ´ 0.4 = 33mV. 6) V FB divider The input bias current to the comparator is 4µA. The resis- tor divider current should be considerably higher than this to ensure that there is sufficient bias current. If we choose the divider current to be at least 250 times the bias current this permits a divider current of 1mA and simplifies the calculations. = R1 + R2 = 5k½ Let R2 = 1K Rearranging the divider equation gives: R1 = R2 1.25 VOUT 1.25 1mA R1 + R2 50 ´ 10-3 0.6A ÆV ÆI 0.6A ÆI 8 ´ fSW ´ ÆV 5.6V ´ 2µs 28µH (VOUT + VF) ´ TOFF(min) LMIN 5.6V ´ 3µs 0.6A (VOUT + VD) ´ TOFF(max) ÆI 30 ´ 10 3 Fsw Fsw 3 ´ 10 6 fSW 5.6 13.8 5.6
Applications Information: continued 7) Divider bypass Capacitor Crr Since the feedback resistors divide the output voltage by a factor of 4, i.e. 5V/1.25V= 4, it follows that the output ripple is also divided by four. This would require that the output ripple be at least 60mV (4 ´ 15mV) to trip the feedback com- parator. We use a capacitor Crr to act as an AC short . The ripple voltage frequency is equal to the switching fre- quency so we choose Crr = 1nF. 8) Soft start and Fault timing capacitor CS. CS performs several important functions. First it provides a delay time for load transients so that the IC does not enter a fault mode every time the load changes abruptly. Secondly it disables the fault circuitry during startup, it also provides soft start by clamping the reference voltage during startup, allowing it to rise slowly, and, finally it controls the hiccup short circuit protection circuitry. This reduces the duty cycle to approximately 0.035 during short circuit conditions. An important consideration in calculating CS is that itÕs voltage does not reach 2.5V (the voltage at which the fault detect circuitry is enabled) before V FB reaches 1.15V other- wise the power supply will never start. If the VFB pin reaches 1.15V, the fault timing comparator will discharge CS and the supply will not start. For the VFB voltage to reach 1.15V the output voltage must be at least 4 ´ 1.15 = 4.6V. If we choose an arbitrary startup time of 900µs, the value of C S is: t Startup= CSmin = = 950nF @ 0.1µF The fault time is the sum of the slow discharge time the fast discharge time and the recharge time. It is dominated by the slow discharge time. The first parameter is the slow discharge time, it is the time for the C S capacitor to discharge from 2.4V to 1.5V and is given by: tSlowDischarge(t) = Where IDischarge is 6µA typical. tSlowDischarge(t) = CS ´ 1.5 ´ 105 The fast discharge time occurs when a fault is first detect- ed. The CS capacitor is discharged from 2.5V to 2.4V. tFastDischarge(t) = Where I FastDischarge is 66µA typical. tFastDischarge(t) = CS ´ 1515 The recharge time is the time for CS to charge from 1.5V to 2.5V. tCharge(t) = Where ICharge is 264µA typical. tCharge(t) = CS ´ 3787 The fault time is given by: tFault = CS ´ (3787 + 1515 + 1.5 ´ 105) tFault = CS ´ (1.55 ´ 105) For this circuit tFault = 0.1 ´ 10-6 ´ 1.55 ´ 105 = 15.5µS A larger value of CS will increase the fault time out time but will also increase the soft start time. 9) Input Capacitor The input capacitor reduces the peak currents drawn from the input supply and reduces the noise and ripple voltage on the V CC and VC pins. This capacitor must also ensure that the VCC remains above the UVLO voltage in the event of an output short circuit. A low ESR capacitor of at least 100µF is good. A ceramic surface mount capacitor should also be connected between V CC and ground to filter high frequency noise. 10) MOSFET Selection The CS51031 drives a P-channel MOSFET. The VGATE pin swings from Gnd to VC. The type of PFET used depends on the operating conditions but for input voltages below 7V a logic level FET should be used. A PFET with a continuous drain current (I D) rating greater than the maximum output current is required. The Gate-to-Source voltage VGS and the Drain-to Source Breakdown Voltage should be chosen based on the input supply voltage. The power dissipation due to the conduction losses is given by: P D = IOUT2 ´ RDS(ON) ´ D where RDS(ON) is the value at TJ = 100ûC. The power dissipation of the PFET due to the switching loss- es is given by: PD = 0.5 ´ VIN ´ IOUT ´ (tr ) ´ fSW Where tr = Rise Time. 11) Diode Selection The flyback or catch diode should be a Schottky diode because of itÕs fast switching ability and low forward volt- age drop. The current rating must be at least equal to the maximum output current. The breakdown voltage should be at least 20V for this 12V application. The diode power dissipation is given by: P D = IOUT ´ VD ´ (1 - Dmin) CS ´ (2.5V - 1.5V) ICharge CS ´ (2.5V - 2.4V) IFastDischarge CS ´ (2.4V - 1.5V) IDischarge 900µs ´ 264µA 2.5V CS ´ 2.5V ICharge
8L PDIP; 300 mil wide 8 © 1999 Cherry Semiconductor CorporationRev. 2/13/98
Ordering Information
CS51031YDR8 8L SO Narrow (tape & reel) CS51031YN8 8L PDIP 0.39 (.015) MIN. 1.14 (.045) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. .203 (.008) .356 (.014) REF: JEDEC MS-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Package Specification Thermal Data 8L SO Narrow 8L PDIP RQJC typ 45 52 ûC/W RQJA typ 165 100 ûC/W D Lead Count Metric English Max Min Max Min 8L SO Narrow 5.00 4.80 .197 .189 8L PDIP 10.16 9.02 .400 .355 PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA 8L SO Narrow; 150 mil wide 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) D 0.25 (0.10) 0.10 (.004) 1.75 (.069) MAX 1.27 (.050) 0.40 (.016) REF: JEDEC MS-012 0.25 (.010) 0.19 (.008)