CS51022A

CS51021A ONSEMI | Alldatasheet

Document overview

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• PDF pages: 11

Technical content

Features

• 75 /C0109A Max. Startup Current
• Fixed Frequency Current Mode Control
• 1.0 MHz Switching Frequency
• Undervoltage Protection Monitor
• Overvoltage Protection Monitor with Programmable Hysteresis
• Programmable Dual Threshold Overcurrent Protection with Delayed Restart
• Programmable Soft Start
• Accurate Maximum Duty Cycle Limit
• Programmable Slope Compensation
• Leading Edge Current Sense Blanking
• 1.0 A Sink/Source Gate Drive
• Bidirectional Synchronization (CS51021A/3A)
• 50 ns PWM Propagation Delay
• 100 /C0109A Max Sleep Current (CS51022A/4A)
• Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. x = Specific Device Code A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or /C0071= Pb−Free Package SOIC−16 D SUFFIX CASE 751B VFBISET CS5102xAG AWLYWW COMPRTCT SSOV LGNDUV VREFSLOPE VCCSLEEP or SYNC PGNDISENSE VCGATE PIN CONNECTIONS AND MARKING DIAGRAMS http://onsemi.com TSSOP−16 DTB SUFFIX CASE 948F CS51 022A ALYW/C0071 /C0071 11 6 See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

Figure 1. Typical Application Diagram, 36−72 V to 5.0 V, 5.0 A DC−DC Converter damage may occur and reliability may be affected. *The maximum package power dissipation must be observed.

1. 60 second maximum above 183 °C.

CS51021A, CS51022A, CS51023A, CS51024A http://onsemi.com ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40 °C < TA < 85°C, −40°C < TJ < 150°C, 3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 k/C0087, CT = 390 pF) Characteristic Test Conditions Min Typ Max Unit Under Voltage Lockout START Threshold (CS51021A/2A) − 7.95 8.25 8.8 V START Threshold (CS51023A/4A) − 12.4 13 13.4 V STOP Threshold − 7.4 7.7 8.2 V Hysteresis (CS51021A/2A) − 0.50 0.75 1.00 V Hysteresis (CS51023A/4A) − 4.0 5.0 6.0 V ICC @ Startup (CS51021A/2A) VCC < UVSTART Threshold − 40 75 /C0109A ICC @ Startup (CS51023A/4A) VCC < UVSTART Threshold − 45 75 /C0109A ICC Operating (CS51021A/3A) − − 7.0 9.0 mA ICC Operating (CS51022A/4A) − − 6.0 8.0 mA ICC Operating Includes 1.0 nF Load − 7.0 12 mA Voltage Reference Initial Accuracy TA = 25°C, IREF = 2.0 mA, VCC = 14 V, (Note 2) 4.95 5.0 5.05 V Total Accuracy 1.0 mA < IREF < 10 mA 4.9 5.0 5.15 V Line Regulation 8.2 V < VCC < 18 V, IREF = 2.0 mA − 6.0 20 mV Load Regulation 1.0 mA < IREF < 10 mA − 6.0 15 mV NOISE Voltage (Note 2) − 50 − /C0109V OP Life Shift T = 1000 Hours, (Note 2) − 4.0 20 mV FAULT Voltage Force VREF 0.90 × VREF 0.93 × VREF 0.95 × VREF V OK Voltage Force VREF 0.94 × VREF 0.96 × VREF 0.985 × VREF V OK Hysteresis Force VREF 75 165 250 mV Current Limit Force VREF −20 − − mA Error Amplifier Initial Accuracy TA = 25°C, IREF = 2.0 mA, VCC = 14 V, VFB = COMP , (Note 2) 2.465 2.515 2.565 V Reference Voltage VFB = COMP 2.440 2.515 2.590 V VFB Leakage Current VFB = 0 V − −0.2 −2.0 /C0109A Open Loop Gain 1.4 V < COMP < 4.0 V, (Note 2) 60 90 − dB Unity Gain Bandwidth (Note 2) 1.5 2.5 − MHz COMP Sink Current COMP = 1.5 V, VFB = 2.7 V 2.0 6.0 − mA COMP Source Current COMP = 1.5 V, VFB = 2.3 V −0.2 −0.5 − mA COMP High Voltage VFB = 2.3 V 4.35 4.8 5.0 V COMP Low Voltage VFB = 2.7 V 0.4 0.8 1.2 V PS Ripple Rejection FREQ = 120 Hz, (Note 2) 60 85 − dB ILIM(SET) Clamp (Note 2) 0.95 1.0 1.15 V 2. Guaranteed by design, not 100% tested in production.

CS51021A, CS51022A, CS51023A, CS51024A http://onsemi.com ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40 °C < TA < 85°C, −40°C < TJ < 150°C, 3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 k/C0087, CT = 390 pF) Characteristic UnitMaxTypMinTest Conditions Oscillator Accuracy RT = 12 k, CT = 390 pF 230 255 280 kHz Voltage Stability Delta Frequency 8.2 V < VCC < 20 V − 2.0 3.0 % Temperature Stability TMIN < TA < TMAX, (Note 3) − 8.0 − % Min Charge & Discharge Time (Note 3) 0.333 − − /C0109s Duty Cycle Accuracy RT = 12 k, CT = 390 pF 70 77 83 % Peak Voltage (Note 3) − 3.0 − V Valley Voltage (Note 3) − 1.5 − V Valley Clamp Voltage 10 k Resistor to ground on RTCT 1.2 1.4 1.6 V Discharge Current − 0.8 1.0 1.2 mA Discharge Current TA = 25°C, Note 3 0.925 1.0 1.075 mA Synchronization (CS51021A/3A) Input Threshold − 1.0 1.5 2.7 V Output Pulsewidth − 160 260 400 ns Output High Voltage ISYNC = 100 /C0109A 3.5 4.3 4.8 V Input Resistance (Note 3) 35 70 140 k/C0087 Drive Delay SYNC to GATE RESET 80 120 150 ns Output Drive Current 1.0 k Load 1.25 2.0 3.5 mA SLEEP (CS51022A/4A) SLEEP Input Threshold Active High 1.0 1.5 2.7 V SLEEP Input Current VSLEEP = 4.0 V 11 25 46 /C0109A ICC @ SLEEP VCC ≤ 15 V − 50 100 /C0109A GATE Driver HIGH Voltage Measure VC − GATE, VC = 10 V, 150 mA Load − 1.5 2.2 V LOW Voltage Measure GATE − PGND, 150 mA SINK − 1.2 1.5 V HIGH Voltage Clamp VC = 20 V, 1.0 nF 11 13.5 16 V LOW Voltage Clamp Measured at 10 mA Output Current − 0.6 0.8 V Peak Current VC = 20 V, 1.0 nF, (Note 3) − 1.0 − A UVL Leakage VC = 20 V measured at 0 V − −1.0 −50 /C0109A RISE Time Load = 1.0 nF, 1.0 V < GATE < 9.0 V, VC = 20 V, TA = 25°C − 60 100 ns FALL Time Load = 1.0 nF, 9.0 V > GATE > 1 .0 V, VC = 20 V − 15 40 ns SLOPE Compensation Charge Current SLOPE = 2.0 V −63 −53 −43 /C0109A COMP Gain Fraction of slope voltage added to ISENSE, (Note 3) 0.095 0.100 0.105 V/V Discharge Voltage SYNC = 0 V − 0.1 0.2 V 3. Guaranteed by design, not 100% tested in production.

CS51021A, CS51022A, CS51023A, CS51024A http://onsemi.com ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40 °C < TA < 85°C, −40°C < TJ < 150°C, 3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 k/C0087, CT = 390 pF) Characteristic UnitMaxTypMinTest Conditions Current Sense OFFSET Voltage (Note 4) 0.09 0.10 0.11 V Blanking Time − − 55 160 ns Blanking Disable Voltage Adjust VFB 1.8 2.0 2.2 V Second Current Threshold Gain − 1.21 1.33 1.45 V/V ISENSE Input Resistance − − 5.0 − k/C0087 Minimum On Time GATE High to Low 30 70 110 ns Gain (Note 4) 0.78 0.80 0.82 V/V OV & UV Voltage Monitors OV Monitor Threshold − 2.4 2.5 2.6 V OV Hysteresis Current − −10 −12.5 −15 /C0109A UV Monitor Threshold − 1.38 1.45 1.52 V UV Monitor Hysteresis − 25 75 100 mV SOFT START (SS) Charge Current SS = 2.0 V −70 −55 −40 /C0109A Discharge Current SS = 2.0 V 250 1000 − /C0109A Charge Voltage, VSS − 4.4 4.7 5.0 V Discharge Voltage, VSS − 0.25 0.27 0.30 V 4. Guaranteed by design, not 100% tested in production. PACKAGE PIN DESCRIPTION PIN # PIN SYMBOL FUNCTION

16 Lead SO Narrow

1 GATE External power switch driver with 1.0 A peak capability. 2 ISENSE Current sense amplifier input. 3 SYNC (CS51021A/3A) Bi−directional synchronization. Locks to the highest frequency. 3 SLEEP (CS51022A/4A) Active high chip disable. In sleep mode, V REF and GATE are turned off. 4 SLOPE Additional slope to the current sense signal. Internal current source charges the external capacitor. 5 UV Undervoltage protection monitor. 6 OV Overvoltage protection monitor. 7 RTCT Timing resistor RT and capacitor CT determine oscillator frequency and maximum duty cycle, DMAX. 8 ISET Voltage at this pin sets pulse−by−pulse overcurrent threshold, and second threshold (1.33 times higher) with Soft Start retrigger (hiccup mode). 9 VFB Feedback voltage input. Connected to the error amplifier inverting input. 10 COMP Error amplifier output. Frequency compensation network is usually connected between COMP and V FB pins. 11 SS Charging external capacitor restricts error amplifier output voltage during the start or fault conditions (hiccup). 12 LGND Logic ground. 13 VREF 5.0 V reference voltage output. 14 VCC Logic supply voltage. 15 PGND Output power stage ground connection. 16 VC Output power stage supply voltage.

Figure 2. Block Diagram

Figure 3. Typical Waveforms 75 /C0109A of startup current. connected to the negative input of the PWM comparator. external power switch on at the beginning of each cycle. on again at the beginning of the next oscillator cycle. that ignores the first 55 ns of each switching period. VI(SENSE) is voltage at the ISENSE pin. VSLOPE is voltage at the SLOPE pin. repeating for as long as the fault condition persists. error amplifier output voltage is clamped by the SS Clamp.

CS51021A, CS51022A, CS51023A, CS51024A http://onsemi.com Synchronization A bi−directional synchronization is provided to synchronize several controllers. When SYNC pins are connected together, the converters will lock to the highest switching frequency. The fastest controller becomes the master, producing a 4.3 V , 200 ns pulse train. Only one, the highest frequency SYNC signal, will appear on the SYNC line. Sleep The sleep input is an active high input. The CS51022A/4A is placed in sleep mode when SLEEP is driven high. In sleep mode, the controller and MOSFET are turned off. Connect to GND for normal operation. The sleep mode operates at VCC ≤ 15 V . Oscillator and Duty Cycle Limit The switching frequency is set by RT and CT connected to the RTCT pin. CT charges and discharges between 3.0 V and 1.5 V . The maximum duty cycle is set by the ratio of the on time, tON, and the whole period, T = tON + tOFF. Because the timing capacitor’s discharge current is trimmed, the maximum duty cycle is well defined. It is determined by the ratio between the timing resistor RT and the timing capacitor CT. Refer to figures 6 and 7 to select appropriate values for RT and CT. fSW /C00431 TSW ;T SW /C0043tCH /C0041tDIS 2500Frequency (kHz) RT (k/C0087) 2000 1500 1000 500 100 10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 35 40 45 50 5 5 RT (k/C0087) Duty Cycle (%) 5 6 8 7 1. CT = 47 pF 2. CT = 100 pF 3. CT = 150 pF 4. CT = 220 pF 5. CT = 390 pF 6. CT = 470 pF 7. CT = 560 pF 8. CT = 680 pF 1. CT = 47 pF 2. CT = 100 pF 3. CT = 150 pF 4. CT = 220 pF 5. CT = 390 pF 6. CT = 470 pF 7. CT = 560 pF 8. CT = 680 pF Figure 6. Frequency vs. RT for Discrete Figure 7. Duty Cycle vs. RT for Discrete Device Package Shipping† CS51021AED16 SOIC−16

48 Units / Rail

2500 Tape & ReelCS51021AEDR16G SOIC−16

(Pb−Free) CS51022ADBG TSSOP−16* 48 Units / Rail CS51022ADBR2G TSSOP−16* 2500 Tape & Reel CS51022AED16 SOIC−16

2500 Tape & ReelCS51022AEDR16G SOIC−16

(Pb−Free) CS51023AED16 SOIC−16

2500 Tape & ReelCS51023AEDR16G SOIC−16

(Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free.

CS51021A, CS51022A, CS51023A, CS51024A http://onsemi.com PACKAGE DIMENSIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 16 9 SEATING PLANE F JM R X 45/C0095 G

8 PLP−B−

−A− M0.25 (0.010) B S −T− D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 SOIC−16 D SUFFIX CASE 751B−05 ISSUE J PACKAGE THERMAL DATA Parameter SOIC−16 Unit R/C0113JC Typical 28 °C/W R/C0113JA Typical 115 °C/W

CS51021A, CS51022A, CS51023A, CS51024A http://onsemi.com ÇÇÇ ÇÇÇ ÇÇÇ DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. /C0095/C0095/C0095/C0095SECTION N−N SEATING PLANE IDENT. PIN 1 1 8 16 9 DETAIL E J B C D A K H G ÉÉ ÉÉ DETAIL E F M L 2X L/2 −U− SU0.15 (0.006) T SU0.15 (0.006) T SUM0.10 (0.004) V ST 0.10 (0.004) −T− −V− −W− 0.25 (0.010) 16X REFK N N TSSOP−16 CASE 948F−01 ISSUE A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 CS51021/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.