CS51021ED16

CS51021 CHERRY | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

Features

VIN (36V to 72V) 51k 0.01µF 470pF 6.98k, 6.98k, PGND 200K,1% 0.1µF 100p 62 IRF6345 100 1µF 680pF 10K 180 MOC81025 2K,1% 100µF 100µF SGND VOUT (5V/5A) 22K 5.1K0.1µF 1000pF SYNC/SLEEP 2.49K,1% 51K 10K 0.01µF 2K, 1% 330pF MBRB2060CT 100pF BA521 10K BAS21 18V22µF11V FZT688 4700pF 24.3K 100 TL431 4:1 100:1 2:5 UV OV VREF RTCT ISET LGnd CSS VFB COMP SYNC/ SLEEP PGnd SLOPE VC VCC GATE ISENSE CS51021/51022 I 75µA Max. Startup Current I Fixed Frequency Current Mode Control I 1MHz Switching Frequency I Undervoltage Protection Monitor I Overvoltage Protection Monitor with Programmable Hysteresis I Programmable Dual Threshold Overcurrent Protection with Delayed Restart I Programmable Soft Start I Accurate Maximum Duty Cycle Limit I Programmable Slope Compensation I Leading Edge Current Sense Blanking I 1A Sink/Source Gate Drive I Bidirectional Synchronization (CS51021/23) I 50ns PWM Propagation Delay I 100µA Max Sleep Current (CS51022/24) Package Options CS51021/22/23/24 Enhanced Current Mode PWM Controller CS51021/CS51023 CS51022/CS51024

Description

Typical Application Diagram SS VREF OV SLEEP or SYNC VFB RTCT VCC SLOPE ISET PGndISENSE COMP LGndUV VCGATE

16 Lead SO Narrow

Device Sleep/Synch V CC Start/Stop CS51021 Synch 8.25V/7.7V CS51022 Sleep 8.25V/7.7V CS51023 Synch 13V/7.7V CS51024 Sleep 13V/7.7V A Company ® 36-72V to 5V, 5A DC-DC Convertor Rev. 2/22/99 Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com Consult factory for other package options.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS51021/22/23/24 Absolute Maximum Ratings I Under Voltage Lockout START Threshold (CS51021/22) 7.95 8.25 8.8 V START Threshold (CS51023/24) 12.4 13 13.4 V STOP Threshold 7.4 7.7 8.2 V Hysteresis (CS51021/22) 0.50 0.75 1.00 V Hysteresis (CS51023/24) 4 5 6 V I CC @ Startup (CS51021/22) V CC < UVSTART Threshold 40 75 µA ICC @ Startup (CS51023/24) V CC < UVSTART Threshold 45 75 µA ICC Operating (CS51021/23) 7 9 mA ICC Operating (CS51022/24) 6 8 mA IC Operating Includes 1nF Load 7 12 mA I Voltage Reference Initial Accuracy T A = 25C, IREF = 2mA, VCC = 14V (Note1) 4.95 5 5.05 V Total Accuracy 1mA<I REF<10mA 4.9 5 5.15 V Line Regulation 8.2V < V CC < 18V, IREF = 2mA 6 20 mV Load Regulation 1mA < I REF < 10mA 6 15 mV NOISE Voltage (Note 1) 50 uV OP Life Shift T=1000 Hours (Note 1) 4 20 mV FAULT Voltage Force V REF .92 × VREF .95 × VREF .97 × VREF V OK Voltage Force V REF .94 × VREF .96 × VREF .98 × VREF V OK Hysteresis Force V REF 50 105 160 mV Current Limit Force V REF -20 mA I Error Amplifier Initial Accuracy T A=25°C, IREF = 2mA, VCC = 14V, 2.465 2.515 2.565 V VFB = COMP (Note 1) Reference Voltage V FB = COMP 2.440 2.515 2.590 V VFB Leakage Current V FB = 0V -0.2 -2 µA Open Loop Gain 1.4V < COMP < 4V (Note 1) 60 90 dB Unity Gain Bandwidth (Note 1) 1.5 2.5 MHz COMP Sink Current COMP = 1.5V, V FB = 2.7V 2 6 mA COMP Source Current COMP = 1.5V, V FB = 2.3V -0.2 -0.5 mA Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < TA < 85°C, -40°C < TJ < 150°C, 3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: -40°C < TA < 85°C, -40°C < TJ < 150°C, 3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF, unless otherwise stated I Error Amplifier continued COMP High Voltage V FB = 2.3V 4.35 4.8 5 V COMP Low Voltage V FB = 2.7V 0.4 0.8 1.2 V PS Ripple Rejection FREQ = 120Hz (Note 1) 60 85 dB SS Clamp, VCOMP VSS=2.5V, VFB = 0V, ISET = 2V 2.4 2.5 2.6 V ILIM(SET) Clamp (Note 1) 0.95 1 1.15 V I Oscillator Accuracy R T = 12k, CT = 390pF 230 255 280 kHz Voltage Stability Delta Frequency 8.2V < V CC < 20V 2 3 % Temperature Stability T MIN < TA < TMAX (Note1) 8 % Min Charge & Discharge Time (Note1) 0.333 µs Duty Cycle Accuracy R T = 12k, CT = 390pF 70 77 83 % Peak Voltage (Note 1) 3 V Valley Voltage (Note 1) 1.5 V Valley Clamp Voltage 10k Resistor to ground on R TCT 1.2 1.4 1.6 V Discharge Current 0.8 1 1.2 mA Discharge Current T A=25°C (Note 1) 0.925 1 1.075 mA I Synchronization (CS51021/23) Input Threshold 1.0 1.5 2.7 V Output Pulsewidth 160 260 360 ns Output High Voltage I SYNC = 100µA 3.5 4.3 4.8 V Input Resistance (Note 1) 35 70 140 k Ω Drive Delay SYNC to GATE RESET 80 120 150 ns Output Drive Current 1k Load 1.25 2 3.5 mA I SLEEP (CS51022/24) SLEEP Input Threshold Active High 1.0 1.5 2.7 V SLEEP Input Current V SLEEP = 4V 11 25 46 µA ICC @ SLEEP V CC ≤ 15V 50 100 µA I GATE Driver HIGH Voltage Measure V C-GATE, VC = 10V, 150mA Load 1.5 2.2 V LOW Voltage Measure GATE-PGnd, 150mA SINK 1.2 1.5 V HIGH Voltage Clamp V C = 20V, 1nF 11 13.5 16 V LOW Voltage Clamp Measured at 10mA Output Current 0.6 0.8 V Peak Current V C = 20V, 1nF (Note 1) 1 A UVL Leakage V C = 20V, measured at 0V -1 -50 µA RISE Time Load = 1nF, 1V < GATE < 9V, 60 100 ns VC = 20V, TA = 25˚C FALL Time Load = 1nF, 9V > GATE > 1V, V C = 20V 15 40 ns

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS51021/22/23/24 Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < TA < 85°C, -40°C < TJ < 150°C, 3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF. Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION I SLOPE Compensation Charge Current SLOPE = 2V -63 -53 -43 µA COMP Gain Fraction of slope voltage added 0.095 0.100 0.105 V/V to I SENSE (Note 1) Discharge Voltage SYNC = 0V 0.1 0.2 V I Current Sense OFFSET Voltage (Note 1) 0.09 0.10 0.11 V Blanking Time 55 160 ns Blanking Disable Voltage Adjust V FB 1.8 2 2.2 V Second Current Threshold Gain 1.21 1.33 1.45 V/V I SENSE Input Resistance 5 k Ω Minimum On Time GATE High to Low 30 70 110 ns Gain (Note 1) 0.78 0.80 0.82 V/V I OV & UV Voltage Monitors OV Monitor Threshold 2.4 2.5 2.6 V OV Hysteresis Current -10 -12.5 -15 µA UV Monitor Threshold 1.38 1.45 1.52 V UV Monitor Hysteresis 25 75 100 mV I SOFT START (SS) Charge Current SS = 2V -70 -55 -40 µA Discharge Current SS = 2V 250 1000 µA Charge Voltage, V SS 4.4 4.7 5 V Discharge Voltage, VSS 0.25 0.27 0.30 V Note 1: Guaranteed by Design, not 100% tested in production. 16L PDIP & SO Narrow 1 GATE External power switch driver with 1.0A peak capability. SENSE Current sense amplifier input. 3 SYNC Bi-directional synchronization. Locks to the highest frequency. (CS51021/23) 3 SLEEP Active high chip disable. In sleep mode, V REF and GATE are (CS51022/24) turned off. 4 SLOPE Additional slope to the current sense signal. Internal current source charges the external capacitor. 5 UV Undervoltage protection monitor. 6 OV Overvoltage protection monitor.

Package Pin Description: continued PACKAGE PIN # PIN SYMBOL FUNCTION 4.75V VREF DISABLE 1.33 55µA VREF = 5V OSC Discharge Latch 2.5V PWM Comp S R Q E/A START STOP+- ISET Clamp SS Clamp 12.5µA OV Monitor UV Monitor ∑ +– 0.1V 0.1 VREF 53µA VREF_OK Vcc_OK SS Monitor VFB Monitor 1.45V 55ns Blank 0.8 10k 20k VREF 13.5V VISense 2.5V 4.3V 200ns FAULT ZD1D4 4.7V SS PGnd VC GATE ISENSE SLOPE COMP VFB OV ISET VREF VCC LGnd SYNC RTCT UV SLEEP 2nd Threshold Figure 1: CS51021/22/23/24 Block Diagram Block Diagram 16L PDIP & SO Narrow 7R TCT Timing resistor RT and capacitor C T determine oscillator frequen- cy and maximum duty cycle, DMAX. 8I SET Voltage at this pin sets pulse-by-pulse overcurrent threshold, and second threshold (1.33 times higher) with Soft Start retrigger (hic- cup mode). 9V FB Feedback voltage input. Connected to the error amplifier invert- ing input. 10 COMP Error amplifier output. Frequency compensation network is usu- ally connected between COMP and VFB pins.

11 SS Charging external capacitor restricts error amplifier output volt-

age during the start or fault conditions (hiccup). 12 LGnd Logic ground. 13 V REF 5.0V reference voltage output. 14 V CC Logic supply voltage. 15 PGnd Output power stage ground connection. 16 V C Output power stage supply voltage.

Figure 2: Typical Waveforms Powering the IC The IC has two supply and two ground pins. VC and PGnd pins provide high speed power drive for the exter- nal power switch. V CC and LGnd pins power the control portion of the IC. The internal logic monitors the supply voltage, V CC. During abnormal operating conditions, the output is held low. The CS51021/22/23/24 requires only 75µA of startup current. Voltage Feedback The output voltage is monitored via the V FB pin and is compared with the internal 2.5V reference. The error amplifier output minus one diode drop is divided by 3 and connected to the negative input of the PWM compara- tor. The positive input of the PWM comparator is connect- ed to the modified current sense signal. The oscillator turns the external power switch on at the beginning of each cycle. When current sense ramp voltage exceeds the reference side of PWM comparator, the output stage latch- es off. It is turned on again at the beginning of the next oscillator cycle. Current Sense and Protection The current is monitored at the I SENSE pin. The CS51021/22/23/24 has leading edge blanking circuitry that ignores the first 55ns of each switching period. Blanking is disabled when V FB is less than 2V so that the minimum on-time of the controller does not have an addi- tional 55ns of delay time during fault conditions. For the remaining portion of the switching period, the current sense signal, combined with a fraction of the slope com- pensation voltage, is applied to the positive input of the PWM comparator where it is compared with the divided by three error amplifier output voltage. The pulse-by- pulse overcurrent protection threshold is set by the volt- age at the I SET pin. This voltage is passed through the ISET Clamp and appears at the non-inverting input of the PWM comparator, limiting its dynamic range according to the following formula: Overcurrent Threshold= 0.8 × V I(SENSE) +0.1V + 0.1 VSLOPE where VI(SENSE) is voltage at the ISENSE pin and VSLOPE is voltage at the SLOPE pin. During extreme overcurrent or short circuit conditions, the slope of the current sense signal will become much steeper than during normal operation. Due to loop propa- gation delay, the sensed signal will overshoot the pulse- by-pulse threshold eventually reaching the second over- current protection threshold which is 1.33 times higher than the first threshold and is described by the following equation: 2nd Threshold = 1.33 × V I(SET) Exceeding the second threshold will reset the Soft Start capacitor CSS and reinitiate the Soft Start sequence, repeat- ing for as long as the fault condition persists. Soft Start During power up, when the output filter capacitor is dis- charged and the output voltage is low, the voltage across the Soft Start capacitor (V SS) controls the duty cycle. An internal current source of 55µA charges CSS. The maxi- mum error amplifier output voltage is clamped by the SS Clamp. When the Soft Start capacitor voltage exceeds the error amplifier output voltage, the feedback loop takes over the duty cycle control. The Soft Start time can be esti- mated with the following formula: t SS = 9 × 104 × CSS The Soft Start voltage, VSS, charges and discharges between 0.25V and 4.7V. Slope Compensation DC-DC converters with current mode control require a current sense signal with slope compensation to avoid instability at duty cycles greater than 50%. Slope capacitor C S is charged by an internal 53µA current source and is discharged during the oscillator discharge time. The slope compensation voltage is divided by 10 and is added to the current sense voltage, V I(SENSE). The signal applied to the Theory of Operation 4.3V 200ns TCH TDIS VIN VSLOPE IS + 0.1 SLOPE IS 55ns Blanking PWM COMP SLOPE RTCT SYNC IS VDS GATE VCOMP

CS51021EDR16 16L SO Narrow (tape & reel) CS51022ED16 16L SO Narrow CS51022EDR16 16L SO Narrow (tape & reel) CS51023ED16 16L SO Narrow CS51023EDR16 16L SO Narrow (tape & reel) CS51024ED16 16L SO Narrow CS51024EDR16 16L SO Narrow (tape & reel) Rev. 2/22/99

Ordering Information

Thermal Data 16L SO Narrow RΘJC typ 28 ˚C/W RΘJA typ 115 ˚C/W D Lead Count Metric English Max Min Max Min 16L SO Narrow 10.00 9.80 .394 .386 PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA © 1999 Cherry Semiconductor Corporation Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Surface Mount Narrow Body (D); 150 mil wide 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) D 0.25 (0.10) 0.10 (.004) 1.75 (.069) MAX 1.27 (.050) 0.40 (.016) REF: JEDEC MS-012 0.25 (.010) 0.19 (.008)