CS5101 ONSEMI | Alldatasheet
Document overview
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- PDF pages: 9
Technical content
Features
- 1.5 A Peak Output (Grounded Totem Pole)
- 8.0 V to 75 V Gate Drive V oltage
- 8.0 V to 45 V Supply V oltage
- 300 ns Propagation Delay
- 1.0% Error Amplifier Reference V oltage
- Lossless Turn On and Turn Off
- Sleep Mode: < 100 /C0109A
- Overcurrent Protection with Dedicated Differential Amp
- Synchronization to External Clock
- External Power Switch Drain V oltage Monitor
- Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb −Free Package http://onsemi.com PDIP−14 N SUFFIX CASE 646 MARKING DIAGRAMS AND PIN ASSIGNMENTS SO−16WB DW SUFFIX CASE 751G SO−16WB See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
IS−COMP IS+RAMP CS5101 AWLYYWWG IS+RAMP 1 16 IS−COMP IS COMPVFB PGNDAGND PGNDDGND VGVREF VCVCC VDSYNC PDIP−14 CS5101EN14 AWLYYWWG
Figure 1. Application Diagram
- 60 second maximum above 183 °C
http://onsemi.com ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 85°C, −40°C ≤ TJ ≤ 150°C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Error Amplifier Input Voltage Initial Accuracy VFB = VCOMP, VCC = 15 V, T = 25°C, Note 3 1.98 2.00 2.02 V Input Voltage VFB = VCOMP, includes line and temp 1.94 2.00 2.06 V Input Bias Current VFB = 0 V , IVFB flows out of pin − − 500 nA Open Loop Gain 1.5 V < VCOMP < 3.0 V 60 70 − dB Unity Gain Bandwidth 1.5 V < VCOMP < 3.0 V, Note 3 0.7 1.0 − MHz Output Sink Current VCOMP = 2.0 V, VFB = 2.2 V 2.0 8.0 − mA Output Source Current VCOMP = 2.0 V, VFB = 1.8 V 2.0 6.0 − mA VCOMP High VFB = 1.8 V 3.3 3.5 3.7 V VCOMP Low VFB = 2.2 V 0.85 1.0 1.15 V PSRR 10 V < VCC < 45 V, VFB = VCOMP, Note 3 60 70 − dB Voltage Reference Output Voltage Initial Accuracy VCC = 15 V, T = 25°C, Note 3 4.9 5.0 5.1 V Output Voltage 0 A < IREF < 8.0 mA 4.8 5.0 5.2 V Line Regulation 10 V < VCC < 45 V, IREF = 0 A − 10 60 mV Load Regulation 0 A < IREF < 8.0 mA − 20 60 mV Current Limit VREF = 4.8 V 10 50 − mA VREF−OK FAULT V VSYNC = 5.0 V, VREF = VLOAD 4.10 4.40 4.60 V VREF−OK V VSYNC = 5.0 V, VREF = VLOAD 4.30 4.50 4.80 V VREF−OK Hysteresis − 40 100 250 mV Current Sense Amplifier IS COMP High V IS+ = 5.0 V, IS− = IS COMP 4.7 5.0 5.3 V IS COMP Low V IS+ = 0 V, IS− = IS COMP 0.5 1.0 1.3 V Source Current IS+ = 5.0 V, IS− = 0 V 2.0 10 − mA Sink Current IS− = 5.0 V, IS+ = 0 V 10 20 − mA Open Loop Gain 1.5 V ≤ VCOMP ≤ 4.5 V, RL = 4.0 k/C0087 60 80 − dB CMRR Note 3 60 80 − dB PSRR 10 V < VCC < 45 V, Note 3 60 80 − dB Input Offset Voltage VIS+ = 2.5 V, VIS− = VISCOMP −8.0 0 8.0 mV Input Bias Currents VIS+ = VIS− = 0 V, IIS flows out of pins − 20 250 nA Input Offset Current (IS+, IS−) − −250 0 250 nA Input Signal Voltage Range Note 3 −0.3 − VCC − 4.0 V RAMP/SYNC Generator RAMP Sink Current VSYNC = 0 V, VRAMP = 2.5 V 1.0 4.0 − mA RAMP Peak Voltage VSYNC = 5.0 V 3.3 3.5 3.7 V RAMP Valley Voltage VSYNC = 0 V 1.4 1.5 1.6 V RAMP Dynamic Range VRAMPDR = VRAMPPK − VRAMPVY 1.7 2.0 2.3 V RAMP Sleep Threshold Voltage VRAMP @ VREF < 2.0 V 0.3 0.6 1.0 V SYNC Threshold VSYNC @ VRAMP > 2.5 V 2.3 2.5 2.7 V SYNC Input Bias Current VSYNC = 0 V, ISYNC flows out of pin − 1.0 20 /C0109A 3. Guaranteed by design. Not 100% tested in production.
http://onsemi.com ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 85°C, −40°C ≤ TJ ≤ 150°C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Output Stage VG, High VSYNC = 5.0 V, IVG = 200 mA, VC − VG − 1.6 2.5 V VG, Low VSYNC = 0 V, IVG = 200 mA − 0.9 1.5 V VG Rise Time Switch VSYNC High, CG = 1.0 nF, VCC = 15 V, measure 2.0 V to 8.0 V − 30 75 ns VG Fall Time Switch VSYNC Low, CG = 1.0 nF, VCC = 15 V, measure 8.0 V to 2.0 V − 40 100 ns VG Resistance to GND Remove supplies, VG = 10 V − 50 100 k/C0087 VD Resistance to GND Remove supplies, VD = 10 V 500 1500 − /C0087 General ICC, Operating VSYNC = 5.0 V − 12 18 mA ICC in UVL VCC = 6.0 V − 300 500 /C0109A ICC in Sleep Mode High VRAMP = 0 V, VCC = 45 V − 80 200 /C0109A ICC in Sleep Mode Low VRAMP = 0 V, VCC = 10 V − 20 50 /C0109A IC, Operating High VSYNC = 5.0 V, VFB = VIS− = 0 V, VC = 75 V − 4.0 8.0 mA IC, Operating Low VSYNC = 5.0 V, VFB = VIS− = 0 V, VC = 8.0 V − 3.0 6.0 mA UVLO Start Voltage − 7.4 8.0 9.2 V UVLO Stop Voltage − 6.4 7.0 8.3 V UVLO Hysteresis − 0.8 1.0 1.2 V Leading Edge, tDELAY VSYNC = 2.5 V to VG = 8.0 V − 280 − ns Trailing Edge, tDELAY VSYNC = 2.5 V to VG = 2.0 V − 750 − ns PACKAGE PIN DESCRIPTION PACKAGE LEAD # LEAD SYMBOL FUNCTIONPDIP−14 SO −16WB 1 1 SYNC Synchronization input. 2 2 VCC Logic supply (10 V to 45 V). 3 3 VREF 5.0 V voltage reference. 4 − LGND Logic level ground (analog and digital ground tied). 5 6 VFB Error amplifier inverting input. 6 7 COMP Error amplifier output and compensation. 7 8 RAMP RAMP programmable with the external capacitor. 8 9 IS+ Current sense amplifier non −inverting input. 9 10 IS− Current sense amplifier inverting input. 10 11 IS COMP Current sense amplifier compensation and output. 11 12, 13 PGND Power ground. 12 14 VG External power switch gate drive. 13 15 VC Output power stage supply voltage (8.0 V to 75 V). 14 16 VD External FET DRAIN voltage monitor. − 5 AGND Analog ground. − 4 DGND Digital ground.
http://onsemi.com Device Package Shipping† CS5101EN14 PDIP−14
25 Units / RailCS5101EN14G PDIP−14
(Pb−Free) CS5101EDW16 SOIC−16WB
47 Units / RailCS5101EDW16G SOIC−16WB
(Pb−Free) CS5101EDWR16 SOIC−16WB 1000 / Tape & ReelCS5101EDWR16G SOIC−16WB (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. CIRCUIT DESCRIPTION Figure 2. Block Diagram
5.0 V OK
5.0 V −
The VFB voltage is monitored by the error amplifier EA. power switch, usually an N−FET, turns on. comparator is latched by the RS latch, LATCH. Figure 3. Waveforms for CS5101. The Number to Application Diagram on Page 2. VSY, gate G2 output goes high, resetting the latch at time t3. power switch (an N−FET) is turned off. cycle of the secondary pulse VSY. than 100 /C0109A, and the IC is in SLEEP mode. condition the supply current is reduced to less than 500 /C0109A. current cycle has finished and the RS latch is reset. VREF voltage is within the specification limits of REF_OK.
Figure 4. CS5101 Bench Test on DIP−14 Package
8.0 V − 45 V
http://onsemi.com PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 B A DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L N 0.015 0.039 0.38 1.01 /C0095/C0095 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. F HG D K C SEATING PLANE N −T− 14 PL M0.13 (0.005) L M J 0.290 0.310 7.37 7.87
http://onsemi.com PACKAGE DIMENSIONS SOIC−16WB CASE 751G−03 ISSUE C D 14X B16X SEATING PLANE SAM0.25 B ST 16 9 h X 45/C0095 MBM0.25 H8X E B A e T A L C /C0113 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0 7 /C0095/C0095 PACKAGE THERMAL DATA Parameter PDIP−14 SOIC−16WB Unit R/C0113JC Typical 23 48 °C/W R/C0113JA Typical 105 85 °C/W ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 CS5101/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative