CS5101 CHERRY | Alldatasheet

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Technical content

Features

n 1.5A Peak Output (Grounded Totem Pole) n 8V to 75V Gate Drive Voltage n 8V to 45V Supply Voltage n 300ns Propagation Delay n 1% Error Amplifier Reference Voltage n Lossless T urn On and T urn Off n Sleep Mode: < 100µA n Overcurrent Protection with Dedicated Differential Amp n Synchronization to External Clock n External Power Switch Drain Voltage Monitor Package Options 16L SO Wide 14L PDIP CS5101 Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters 1SYNC VCC VREF DGnd VFB COMP RAMP VC PGnd IS- IS+ IS COMP VD VG PGndAGnd 1SYNC VCC VREF LGnd VFB COMP RAMP VC PGnd IS- IS+ IS COMP VD VG CS5101

Description

The CS5101 is a bipolar monolithic secondary side post regulator (SSPR) which provides tight regula- tion of multiple output voltages in AC-DC or DC-DC converters. Leading edge pulse width modula- tion is used with the CS5101. The CS5101 is designed to operate over an 8V to 45V supply voltage CC) range and up to a 75V drive voltage (VC). The CS5101 features include a totem pole output with 1.5A peak output current capability, externally pro- grammable overcurrent protection, an on chip 2% precision 5V refer- ence, internally compensated error amplifier, externally synchronized switching frequency, and a power switch drain voltage monitor. It is available in a 14 lead plastic DIP or a 16 lead wide body SO package. Application Diagram Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ¨ Rev. 3/31/97

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS5101 Absolute Maximum Ratings Lead Temperature Soldering Electrical Characteristics: -40¡C ² TA ² 85¡C; -40¡C ² TJ ² 150¡C; 10V < VCC < 45V; 8V < VC <75V unless otherwise specified. n Error Amplifier Input Voltage Initial Accuracy V FB = VCOMP; VCC = 15V; 1.98 2.00 2.02 V T = 25¡C (Note 1) Input Voltage V FB = VCOMP, includes line and temp 1.94 2.00 2.06 V Input Bias Current V FB = 0V; IVFB flows out of pin 500 nA Open Loop Gain 1.5V < V COMP < 3.0V 60 70 dB Unity Gain Bandwidth 1.5V < V COMP < 3.0V; (Note 1) 0.7 1.0 MHz Output Sink Current V COMP = 2.0V; VFB = 2.2V 2 8 mA Output Source Current V COMP = 2.0V; VFB = 1.8V 2 6 mA VCOMP High V FB = 1.8V 3.3 3.5 3.7 V VCOMP Low V FB = 2.2V 0.85 1.0 1.15 V PSRR 10V < V CC < 45V; 60 70 dB VFB = VCOMP (Note 1) n Voltage Reference Output Voltage Initial Accuracy V CC = 15V; T = 25¡C (Note 1) 4.9 5.0 5.1 V Output Voltage 0A < I REF < 8mA 4.8 5.0 5.2 V Line Regulation 10V < V CC < 45V; IREF = 0A 10 60 mV Load Regulation 0A < I REF < 8mA 20 60 mV Current Limit V REF = 4.8V 10 50 mA VREF_OK FAULT V V SYNC = 5V; VREF = VLOAD 4.10 4.40 4.60 V VREF_OK V V SYNC = 5V; VREF = VLOAD 4.30 4.50 4.80 V VREF_OK Hysteresis 40 100 250 mV n Current Sense Amplifier IS COMP High V IS + = 5V; ISÐ = IS COMP 4.7 5.0 5.3 V IS COMP Low V IS + = 0V; ISÐ = IS COMP 0.5 1.0 1.3 V Source Current IS + = 5V; ISÐ = 0V 2.0 10 mA Sink Current IS - = 5V; IS+ = 0V 10 20 mA Open Loop Gain 1.5V ² V COMP ² 4.5V; RL = 4k½ 60 80 dB CMRR (Note 1) 60 80 dB PSRR 10V < V CC < 45V, (Note 1) 60 80 dB Unity Gain Bandwidth 1.5V ² V COMP ² 4.5V; RL = 4k½ (Note 1) 0.5 0.8 MHz

Electrical Characteristics: continued PARAMETER TEST CONDITIONS MIN TYP MAX UNIT n Current Sense Amplifier: continued Input Offset Voltage V IS+ = 2.5V; VIS- = VISCOMP -8 0 8 mV Input Bias Currents V IS+ = VIS- = 0V; IIS flows out of pins 20 250 nA Input Offset Current (IS+, IS-) -250 0 250 nA Input Signal Voltage Range (Note 1) -0.3 V CC-4.0 V n RAMP/SYNC Generator Ramp Source Current Initial V SYNC = 5V, VRAMP = 2.5V ; T = 25¡C 0.18 0.20 0.22 mA Accuracy (Note 1) Ramp Source Current V SYNC = 5V; VRAMP = 2.5V 0.16 0.20 0.24 mA Ramp Sink Current V SYNC = 0V; VRAMP = 2.5V 1.0 4.0 mA RAMP Peak Voltage V SYNC = 5V 3.3 3.5 3.7 V RAMP Valley Voltage V SYNC = 0V 1.4 1.5 1.6 V RAMP Dynamic Range V RAMPDR = VRAMPPK Ð VRAMPVY 1.7 2.0 2.3 V RAMP Sleep Threshold Voltage V RAMP @ VREF < 2.0V 0.3 0.6 1.0 V SYNC Threshold V SYNC @ VRAMP > 2.5V 2.3 2.5 2.7 V SYNC Input Bias Current V SYNC = 0V; ISYNC flows out of pin 1 20 µA n Output Stage VG, High V SYNC = 5V; IVG = 200mA, VC Ð VG 1.6 2.5 V VG, Low V SYNC = 0V; IVG = 200mA 0.9 1.5 V VG Rise Time Switch V SYNC High; CG = 1nF; 30 75 ns VCC = 15V; measure 2V to 8V VG Fall Time Switch V SYNC Low; CG = 1nF 40 100 ns VCC = 15V; measure 8V to 2V VG Resistance to Gnd Remove supplies; V G = 10V 50 100 k½ VD Resistance to Gnd Remove supplies; V D = 10V 500 1500 ½ n General ICC, Operating V SYNC = 5V 12 18 mA ICC in UVL V CC = 6V 300 500 µA ICC in Sleep Mode High V RAMP = 0V; VCC = 45V 80 200 µA ICC In Sleep Mode Low V RAMP = 0V; VCC = 10V 20 50 µA IC, Operating High V SYNC = 5V; VFB = VISÐ = 0V; 4 8 mA VC = 75V IC, Operating Low V SYNC = 5V; VFB = VISÐ = 0V; VC = 8V 3 6 mA UVLO Start Voltage 7.4 8.0 9.2 V UVLO Stop Voltage 6.4 7.0 8.3 V UVLO Hysteresis 0.8 1.0 1.2 V Leading Edge, t DELAY VSYNC = 2.5V to VG = 8V 280 ns Trailing Edge, tDELAY VSYNC = 2.5V to VG = 2V 750 ns Note 1: Guaranteed by design. Not 100% tested in production.

CS5101 PACKAGE PIN # PIN SYMBOL FUNCTION Package Pin Description 14L PDIP 16L SO Wide 1 1 SYNC Synchronization input. 22 V CC Logic supply (10V to 45V). 33 V REF 5.0V voltage reference. 4 LGnd Logic level ground (Analog and digital ground tied). 56 V FB Error amplifier inverting input. 6 7 COMP Error amplifier output and compensation. 7 8 RAMP RAMP programmable with the external capacitor. 8 9 IS+ Current sense amplifier non-inverting input. 9 10 IS- Current sense amplifier inverting input. 10 11 IS COMP Current sense amplifier compensation and output. 11 12, 13 PGnd Power ground. 12 14 V G External power switch gate drive. 13 15 V C Output power stage supply voltage (8V to 75V). 14 16 V D External FET DRAIN Voltage Monitor. 5 AGnd Analog Ground. 4 DGnd Digital Ground. Circuit Description COMP RAMP LGnd SYNC LATCH Q VREF PGnd IS COMP VD VC VG IS REF_OKG1 I = 200mA VFB 2.5V 2V Q3 Ð SYNC VCC_OK Ð VCC S R PWM Ð 4.5V/4.4V 1.65V Ð RAMP Ð Ð Ð EA Ð BUF Ð IS+ IS- 1.5V 0.7V Ð SLEEP VCC Ð REF UVLOK 0.7V8V/7V 2.4V 24.6k VCC 10k 10k 5V5V Ð Ð + Ð Ð Ð Ð Ð Ð VCC VC Q Block Diagram

external power switch, usually an N-FET, turns on. comparator is latched by the RS latch, LATCH. Figure 1. Waveforms for CS5101. The number to the left of each curve refers to a node on the Application Diagram. and the external power switch (an N-FET) is turned off. less than 100µA, and the IC is in SLEEP mode. the supply current is reduced to less than 500µA. after the current cycle has finished and the RS latch is reset. REF voltage is within the specification limits of REF_OK.

14 L PDIP

0.1mF 0.1mF 1mF 1nF 10kR6 10k 100k 100k 2.2k SW SPST 8V – 45V CS5101 bench test Circuit Description: continued

CS5101EDWR16 16L SO Wide (tape & reel) D Lead Count Metric English Max Min Max Min 14L PDIP 19.69 18.67 .775 .735 16L SO Wide 10.50 10.10 .413 .398

Ordering Information

Rev. 3/31/97 Thermal Data 16L SOIC 14L PDIP RQJC typ 23 48 ûC/W RQJA typ 105 85 ûC/W Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA PATENTS PENDING CS5101 © 1999 Cherry Semiconductor Corporation Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Plastic DIP (N); 300 mil wide 0.39 (.015) MIN. 1.14 (.045) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. .203 (.008) .356 (.014) REF: JEDEC MS-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022) 1.27 (.050) BSC 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) D 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) REF: JEDEC MS-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 0.10 (.004) Surface Mount Wide Body (DW); 300 mil wide