CS43198

CS43198 CIRRUS | Alldatasheet

Document overview

• Manufacturer or author: Cirrus Logic, Inc.
• PDF pages: 137

Technical content

Copyright  Cirrus Logic, Inc. 2015–2017 (All Rights Reserved) http://www.cirrus.com 130-dB, 32-Bit High-Performance DAC with Pseudodifferential Outputs System Features

• Enhanced  oversampling DAC architecture — 32-bit resolution — Up to 384-kHz sampling rate — Low clock jitter sensitivity — Auto mute detection
• Integrated high performance outputs — 130-dB dynamic range (A-weighted) — –115-dB total harmonic distortion + noise (THD+N) — 110-dB interchannel isolation — Up to 2-V rms pseudodifferential stereo analog output
• Headphone detection — Headphone plug-in detection — Popguard ® technology eliminates pop noise
• Integrated PLL 19.2-, 12-/24-, and 13-/26-MHz system MCLK rates — Reference clock sourced from XTI/MCLK pin — System clock output
• Mono Mode (differential) support 2C control—up to 1 MHz
• Wideband Flatness Mode Support
• Direct Stream Digital (DSD®) path — Up to 256•Fs DSD — Patented DSD processor – On-chip 50-kHz filter to meet Scarlet Book Super Audio Compact Disk (SACD) recommendations – Matched PCM and DSD analog output levels – Nondecimating volume control with 0.5-dB step size and soft ramp – DSD and Pulse-code modulation (PCM) mixing for alerts — Dedicated DSD and DoP pin interface
• Direct DSD path support
• Serial audio input path — Programmable Hi-Fi digital filter — Five selectable digi tal filter responses – Low-latency Mode minimizes pre-echo – 110 dB of stopband attenuation — Supports sample rates from 32 to 384 kHz 2S, right-justified, left-justified, TDM, and DSD-over-PCM (DoP) interface — Master or slave operation — Volume control with 0.5-dB step size and soft ramp — 44.1 kHz deemphasis and inverting feature
• 40-pin 5mm × 5mm QFN or 42-ball CSP package options

Applications

• Smart phones, tablets, portable media players, laptops, digital headphones, powered speakers, AVR, home theater systems, Blu-ray/DVD/SACD players, and pro audio VCP_FILT+ Multibit Modulator Multibit Modulator Interpolation Filt er and Volume Control DSD Processor Interpolation Filt er and Volume Control Control Por t Level Transl atorRegi ster/Hardwar e Configur ation PLL XTI/MCLK DoP to DSD Engine Analog Supply (VA,VCP) +1.8VFILT+ Level Translator Popguard® Circui try ASP FLYN_VCP FLYP_VA XTAL OSCXTO VCP_FILT+ VCP_FILT- FLYN_VA -VA Char ge Pump Interrupt Sources Internal Voltage Reference AO UTA REFA XSP/DSD Audio Interface MU X MU XMU X FILT- FLYP_VCP VA -VA Digital Audi o Bus FLYC_VCP Battery Supply (VP) VCP_FILT- ADR SDA SCL RESET CLKOUT Digital LDOs Digital Core Interface Supply (VL) +1.8V Internal Supply (VD) +1.8VTSO DAC and Filter VCP_FILT+ VCP_FILT- AO UTB REFB DAC and Filter VA -VA HPDETECT HP_DETECT SCLK1 LRCK1 SDIN1 DSDCLK/SCLK2 DSDB/LRCLK2 DSDA/SDIN2 DS1156F1 OCT ’17 CS43198

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The CS43198 is a high-performance, 32-bit resolution, stereo audio DAC that supports up to 384-kHz sampling frequency with pseudodifferential analog outputs. The advanced 32-bit oversampled multibit modulator with mismatch shaping technology eliminates distortion due to on-chip component mismatch. Proprietary digital-interpolation filters support five selectable filter responses with pseudo-linear phase and ultralow latency to minimize pre-echos and ringing artifacts. An on-chip programmable filter is available for further response customization. Other features include volume control with 0.5-dB steps, wideband flatness mode support, and digital deemphasis for 44.1-kHz sample rate. The patented on-chip DSD processor preserves audio integrity by allowing signal processing such as volume control and 50-kHz Scarlet Book recommended filtering to be applied directly to the DSD stream without an intermediate decimation stage. Additional features like volume matching and channel mixing enable seamless transition between DSD and PCM playback paths. Direct DSD Mode is also provided to bypass the DSD processor. The CS43198 accepts I2S, right-justified, left-justified, and TDM-format PCM data at sample rates from 32 to 384 kHz. The industry-standard high-speed I2C interface capable of up to 1-MHz operation provides easy configuration control. An integrated PLL allows for maximum clocking flexibility in any system. Popguard® technology eliminates output transients upon power-up or power-down events. The CS43198 is available in a commercial-grade 42-ball WLCSP or 40-pin QFN package for operation from –10°C to +70°C.

Table 3-5. Analog Output Characteristics for Direct DSD Mode 15 Table 3-6. Wideband Flatness Mode Analog Output Table 3-7. Combined DAC Digital, On-Chip Analog and Table 3-8. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics (Wideband Flatness Mode) . . . . 18 Table 3-10. DSD Combined Digital and On-Chip Analog Filter Table 3-11. Digital Interface Specifications and Characteristics 19 Table 3-15. Power-Supply Rejection Ratio (PSRR) Table 3-20. I

5.11 Sequences for Enabling and Disabling Mono Mode

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1 Pin Assignments and Descriptions

1.1 40-Pin QFN (Top-Down, Through-Package View) Figure 1-1. Top-Down (Through-Package) View—QFN 40-Pin Diagram Top-Down (Through Package ) View 40-Pin QFN Package 1211 13 14 15 16 17 18 19 20 3940 38 37 36 35 34 33 32 31 DSDB/LRCK2 RESET VCP FLYP_VCP FLYC_VCP HP_DETECT VCP_FILT+ SCL SDIN1 TSO VD FILT+ FILT– VA GNDA –VA FLYP_VA DSDA/SDIN2 SDA LRCK1 XTI/MCLK XTO GNDD SCLK1 CLKOUT DSDCLK/SCLK2 REFA AOUTA GNDCP AOUTB REFB VCP_FILT– INT VP VL ADR GNDCP FLYN_VCP FLYN_VA GNDCP

1.2 42-Ball WLCSP (Top-down, Through-Package View) 1.2 42-Ball WLCSP (Top-dow n, Through-Package View) Figure 1-2. Top-Down (Through-Package) View—42-Ball WLCSP Package VL SCLK1 XTO XTI/MCLK DSDA/ SDIN2 SDIN1 DSDCLK/ SCLK2 CLKOUT LRCK1 SDA SCL TSO DSDB/ LRCK2 ADR GNDD RESET INT VD VP VCP TSI FILT+ FILT– VA FLYP_VCP VCP_FILT+ REFB REFA GNDA –VA FLYC_VCP GNDCP GNDCP HP_DETECT TSI FLYP_VA FLYN_VCP VCP_FILT– AOUTB AOUTA GNDCP FLYN_VA A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 F1 F2 F3 F4 F5 F6 G1 G2 G3 G4 G5 G6 Charge Pump Analog I/O Digital I/OGround Power Supplies Test

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1.3 Pin Descriptions

Table 1-1. Pin Descriptions Pin Name QFN Pin # WLCSP Ball Power Supply I/O Pin Description Internal Connection Digital I/O Driver Digital I/O Receiver ADR 30 C2 VL I Address Bit (I²C). In I²C Mode, ADR is a chip address pin. — — — CLKOUT 33 B2 VL O CLK Output. Single-ended clock output sourced from PLL or buffered crystal. Weak pull-down CMOS output SCLK1 34 A2 VL I/O Serial Audio Input Bit Clock 1. Serial bit clock for audio data on the SDIN pins. Weak pull-down CMOS output Hysteresis on CMOS input LRCK1 38 B3 VL I/O Serial Audio Input Left/Right Clock. Word-rate clock for the audio data on the SDIN pins. Weak pull-down CMOS output Hysteresis on CMOS input SDIN1 2 A6 VL I Serial Audio Input Data Port. Audio data serial input pin 1. Weak pull-down — Hysteresis on CMOS input DSDA/ SDIN2 40 A5 VL I DSD Data Input A/Serial Data In 2. DSD audio or PCM audio data serial input pin 2. Weak pull-down — Hysteresis on CMOS input DSDB/ LRCK2 29 C1 VL I/O DSD Data Input B/Serial Audio Input Left/Right Clock 2. DSD audio data serial input pin or word rate clock for the audio data on the SDIN2 pin. Weak pull-down CMOS output Hysteresis on CMOS input DSDCLK/ SCLK2 32 B1 VL I/O DSD Clock Input/Serial Audio Input Bit Clock 2. DSD clock input. Serial bit clock for audio data on the SDIN2 pin. Weak pull-down CMOS output Hysteresis on CMOS input INT 27 C5 VP O Interrupt. When pulled up, works as system interrupt pin. Open drain, active low programmable. —C M O S open-drain output RESET 28 C4 VP I System Reset. The device enters system reset when enabled. — — Hysteresis on CMOS input SDA 39 B4 VL I/O Serial Control Data I/O (I²C). In I²C Mode, SDA is the control I/O data line. —C M O S open-drain output Hysteresis on CMOS input SCL 1 B5 VL I Software Clock (I²C). Serial control interface clock used to clock control data bits into and out of the CS43198. — — Hysteresis on CMOS input XTI/MCLK 37 A4 VL I Crystal/Oscillator Input/MCLK In. Crystal or digital clock input for the master clock. Weak pull-down — Hysteresis on CMOS input XTO 36 A3 VL O Crystal/Oscillator Output. Crystal output. Weak pull-down CMOS output FILT+ FILT– VA O Positive/Negative Voltage Reference. Positive/negative reference voltage for DAC. —— — HP_ DETECT 22 F4 VP I Headphone Detect. Can be configured to be debounced on unplugged and plugged events before it is presented as a noninterrupt status bit (HPDETECT). —H i - Z — AOUTB AOUTA VCP_ FILT± O Audio Output. Refer to analog specification table for full-scale output level. —— — REFB REFA VCP_ FILT± I Output Reference. Reference for analog output. — — — VL 31 A1 N/A I Logic Power. Input/Output power supply, typically +1.8 V. — — — VD 4 C6 N/A I Internal Digital Power. Internal digital power supply, typically +1.8 V. —— — VA 7 D6 N/A I Analog Power. Power supply for the internal analog section. — — — VCP 25 D2 N/A I Charge Pump Supply. Provides charge pump voltage to the analog output circuit. —— — Digital I/O Analog I/O Power Supplies

VP 26 D1 N/A I Battery supply. Provides voltage to the headphone Class H circuit. —— — GNDD 35 C3 N/A I Digital and I/O Ground. Ground for the I/O and core logic. GNDA, GNDCP, GNDD must be connected to a common ground area under the chip. —— — GNDA 8 E5 N/A I Analog Ground. Ground reference for the internal analog section. GNDA, GNDCP, GNDD must be connected to a common ground area under the chip. —— — GNDCP 19, 12, F2, F3, N/A I Charge Pump Ground. Ground reference for the charge pump section. GNDA, GNDCP, GNDD must be connected to a common ground area under the chip. —— — VCP_FILT+ VCP_FILT– VCP/ VP I/O Inverting Charge Pump Filter Connection. Power supply from the inverting charge pump that provides the positive/negative rail for the analog output. When operating in external VCP_FILT mode, these pins can directly take in supply voltage. —— — –VA 9 E6 VA O VA Negative Charge Pump Output. Negative charge pump output for DAC rail. It is derived from VA. —— — FLYP_VA FLYN_VA VA O –VA Charge Pump Cap Positive/Negative Node. Positive/ negative nodes for the DAC negative charge pump’s flying capacitor. —— — FLYP_VCP 24 E1 VCP/ VP O –VCP Charge Pump Cap Positive Node. Positive node for the analog output negative charge pump’s flying capacitor. —— — FLYC_VCP 23 F1 VCP/ VP 1 O –VCP Charge Pump Cap Center Node. Center node for the analog output negative charge pump’s flying capacitor. —— — FLYN_VCP 20 G1 VCP_ FILT± O –VCP Charge Pump Cap Negative Node. Negative node for the analog output negative charge pump’s flying capacitor. —— — TSO 3 B6 N/A I/O Test Output. —— — TSI — D3, F5 Test Input. —— — 1.The power supply is determined by ADPT_PWR setting (see Section 4.3.1). VP is used if ADPT_PWR = 001 (VP_LDO Mode) or when necessary for ADPTPWR = 111 (Adapt-to-Signal Mode). Table 1-1. Pin Descriptions (Cont.) Pin Name QFN Pin # WLCSP Ball Power Supply I/O Pin Description Internal Connection Digital I/O Driver Digital I/O Receiver Ground Charge Pump Test

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1.4 Electrostatic Discharge (ESD) Protection Circuitry

Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the substrate (GND), as well as the interrelations between some domains. Note that this figure represents the structure for the internal protection devices and that additional protections can be implemented as part of the integration into the board. Figure 1-3. Composite ESD Topology Table 1-2 shows the individual ESD domains and lists the pins associated with each domain. ESD-sensitive device. The CS43198 is manufactured on a CMOS process. Therefore, it is generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while handling and storing this device. This device is qualified to current JEDEC ESD standards. Table 1-2. ESD Domains ESD Domain Signal Name (See * in Topology Figures for Pad) Topology VL/GNDD ADR DSDCLK/SCLK2 SCL SDA DSDB/LRCK2 DSDA/SDIN2 SDIN1 LRCK1 SCLK1 CLKOUT XTI/MCLK XTO VL GNDD Substrate VD VA –VA VP VCP_FILT+ GNDCP VCP_FILT– VCP GNDA VP/GNDCP Domain VP/VCP_FILT– Domain VCP_FILT+/VCP_FILT– Domain VL GNDD Substrate

VA/–VA FLYN_VA FLYP_VA FILT+ FILT– VP/GNDCP RESET INT VP/VCP_FILT– FLYP_VCP FLYC_VCP HP_DETECT VCP_FILT+/ VCP_FILT– FLYN_VCP AOUTA AOUTB REFA REFB Table 1-2. ESD Domains (Cont.) ESD Domain Signal Name (See * in Topology Figures for Pad) Topology VA –VA GNDA Substrate VP VCP_FILT+ GNDCP VCP_FILT– Substrate VP/GNDCP Domain VP/VCP_FILT– Domain VCP_FILT+/VCP_FILT– Domain

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2 Typical Connection Diagram

Figure 2-1. Typical Connection Diagram All external passive component values shown are nominal. Key for Capacitor Types Required: * Use low ESR, X7R/X5R capacitors If no type symbol is shown next to a capacitor, any type may be used. ** Use C0G capacitors. Analog Signal Conditioning GNDD GNDA VA +1.8 V VL FLYN_VA FLYP_VA 2.2 µF -VA OUTA OUTB HPREFA Headphone Connector 12 3 2.2 µF 0.1 µF HPREFB FLYN_VCP FLYP_VCP CLKOUTAudio Devices XTI / MCLK XTOSee Clocking Configuration FILT- FILT+ 15 µF Battery (3.0 V—5.25 V) 2.2 µFFLYC_VCP VP +1.8 V 2.2 µF 2.2 µF 4.7 µF RESET RP_I VL ADR SDA SCL VD0.1 µF 15 µF* Clocking Configuration XTALExternal MCLK System Clock XTI/MCLK XTO * 0.1 µF AOUTA REFA AOUTB REFB HP_DETECT VCP_FILT+ GNDCP VCP VCP_FILT– See VCP_FILT Configuration VCP_FILT Configuration EXT_VCPFILT = 1EXT_VCPFILT = 0 VCP_FILT+ GNDCP VCP +1.8 V VCP_FILT– 2.2 µF 2.2 µF 2.2 µF VCP_FILT+ GNDCP VCP +1.8 V VCP_FILT– 2.2 µF* 2.2 µF* 2.2 µF* +3.0V -3.0V 2.2 µF FLYN_VCP FLYP_VCP FLYC_VCP* 2.2 µF FLYN_VCP FLYP_VCP 2.2 µFFLYC_VCP NC XTI/MCLK XTO SCLK1 LRCK1 SDIN1 DSDCLK/SCLK2 DSDB/LRCLK2 DSDA/SDIN2 PCM / DoP Digital Audio Source DoP / DSD Digital Audio Source CS43198

Figure 2-2. Typical Connection Diagram (Mono Mode) Note: 1. The value for RP_I can be determined by the interrupt pin specification in Table 3-11. All external passive component values shown are nominal. Key for Capacitor Types Required: * Use low ESR, X7R/X5R capacitors If no type symbol is shown next to a capacitor, any type may be used. ** Use C0G cap acitors. Analog Signal Conditioning GNDD GNDA VA +1.8 V VL FLYN_VA FLYP_VA 2.2 µF -VA OUTA OUTB HPREFA 2.2 µF 0.1 µF HPREFB FLYN_VCP FLYP_VCP CLKOUTAudio Devices XTI / MCLK XTOSee Clocking Configuration FILT- FILT+ 15 µF Battery (3.0 V—5.25 V) 2.2 µFFLYC_VCP VP +1.8 V 2.2 µF 2.2 µF 4.7 µF RESET RP_I VL ADR SDA SCL VD0.1 µF 15 µF* Clocking Configuration XTALExternal MCLK System Clock XTI/MCLK XTO * 0.1 µF AOUTA REFA AOUTB REFB HP_DETECT VCP_FILT+ GNDCP VCP VCP_FILT– See VCP_FILT Configuration VCP_FILT Configuration EXT_VCPFILT = 1EXT_VCPFILT = 0 VCP_FILT+ GNDCP VCP +1.8 V VCP_FILT– 2.2 µF 2.2 µF 2.2 µF VCP_FILT+ GNDCP VCP +1.8 V VCP_FILT– 2.2 µF* 2.2 µF* 2.2 µF* +3.0V -3.0V 2.2 µF FLYN_VCP FLYP_VCP FLYC_VCP* 2.2 µF FLYN_VCP FLYP_VCP 2.2 µFFLYC_VCP NC XTI/MCLK XTO SCLK1 LRCK1 SDIN1 DSDCLK/SCLK2 DSDB/LRCLK2 DSDA/SDIN2 PCM / DoP Digital Audio Source DoP / DSD Digital Audio Source XLR 2 3 CS43198

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3 Characteristics and Specifications

Table 3-1 defines parameters as they are characterized in this section. Table 3-1. Parameter Definitions Parameter Definition Dynamic range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwi dth. A signal-to-noise ratio measurement over the specified bandwidth made with a –60-dB signal; 60 dB is added to resulting measurement to refer the measurement to full scale. This technique ensures that distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17–1991, and the Electronic Industries Association of Japan, EIAJ CP–307. Dynamic range is expressed in decibel units. Gain drift The change in gain value with temperature, expressed in ppm/°C units. Idle channel noise The rms value of the signal with no input applied (properly back-terminated analog input, digital zero, or ze ro modulation input). Measured over the specified bandwidth. Interchannel gain mismatch The gain difference between left and right channel pairs. Interchannel gain mismatch is expressed in decibel units. Interchannel phase mismatch The phase difference between left and right channel pairs at 997-Hz sine wave input. Interchannel phase mismatch is ex- pressed in degree units (with respect to 997-Hz sine wave input). Interchannel isolation A measure of cross talk between the left and right channel pairs. Interchannel isolation is measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Interchannel isolation is expressed in decibel units. Load resistance and capacitance The recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. The load capacitance effectively moves the band-limiting pole of the amp in the output stage. Increasing load ca- pacitance beyond the recommended value can cause the internal op-amp to become unstable. Output offset voltage The DC offset voltage present at the amplifier’s output when its input signal is in a mute state. The offset exists due to CMOS process limitations and is proportional to analog volume settings. When measuring the offset out of the headphone amplifier, the headphone amplifier is ON. Total harmonic distortion + noise (THD+N) The ratio of the rms sum of distortion and noise spectral components across the specified bandwidth (typically 20 Hz–20 kHz) relative to the rms value of the signal. THD+N is measured at –1 and –20 dBFS for the analog input and at 0 and –20 dB for the analog output, as suggested in AES17–1991 Annex A. THD+N is expressed in decibel units. Turn-on time Turn-on time is measured from when the PDN_HP = 0 ACK signal is received to when the signal appears on the HP output. Table 3-2. Recommended Operating Conditions Test conditions (unless otherwise specified): GNDD = GNDA = 0 V, all voltages with respect to ground. Parameters 1 1.Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. Symbol Minimum Maximum Units DC power supply Analog VA 1.66 1.94 V Charge pump VCP 1.66 1.94 V Filtered charge pump 2 2.If +1dB_EN = 1, the minimum VCP_FILT+ voltage becomes 3.0 V, and the maximum VCP_FILT– voltage becomes –3.0 V. EXT_VCPFLT = 1 VCP_FILT+ 2.85 3.15 V VCP_FILT– –3.15 –2.85 V Battery supply HV_EN = 0, EXT_VCPFILT = 0 HV_EN = 1, EXT_VCPFILT = 0 EXT_VCPFILT = 1 VP 3.0 3.3 3.3 5.25 5.25 5.25 V V V Digital Interface VL 1.66 1.94 V Digital Internal VD 1.66 1.94 V External voltage applied to pin 3,4 3.The maximum over/undervoltage is limited by the input current. 4.Table 1-1 lists the power supply domain in which each CS43198 pin resides. HP_DETECT pin VCP_FILT± domain pins 5 VL domain pins VA domain pins VP domain pins 5.VCP_FILT± is specified in Table 3-16. VINHI VVCPF VVL VVA VVP –0.3 – VCP_FILT– –0.3 – VCP_FILT– –0.3 –0.3 –0.3 VP + 0.3 0.3 + VCP_FILT+ VL + 0.3 VA + 0.3 VP + 0.3 V V V V V Ambient temperature T A –10 +70 C

Table 3-3. Absolute Maximum Ratings Test conditions (unless otherwise specified): GNDD = GNDA= GNDCP = 0 V; all voltages with respect to ground. Parameters Symbol Minimum Maximum Units DC power supply Analog Battery Charge pump Filtered charge pump (positive) Filtered charge pump (negative) Digital interface Digital internal VA VP VCP VCP_FILT+ VCP_FILT– VL VD –0.3 –0.3 –0.3 –0.3 –3.3 –0.3 –0.3 2.33 6.3 2.33 3.3 0.3 2.33 2.33 V V V V V V V Input current 1.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins do not cause SCR latch-up. Iin —± 1 0 m A Ambient operating temperature (power applied) T A –50 +115 °C Storage temperature Tstg –65 +150 °C Caution: Stresses beyond “Absolute Maximum Ratings” levels may cause permanent damage to the device. These levels are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Table 3-2, “Recommended Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3-4. Analog Output Characteristics (HV_EN = 1) 1 Test conditions (unless otherwise specified): Fig. 2-1 shows CS43198 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; ASP_M/Sb = 1; typical, min/max performance data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK = 44.1-kHz mode); PDN_XTAL = 0, MCLK_INT = 1, PLUS_1DB = 0, and MCLK_SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz); Volume = 0 dB; when testing in DSD processor mode, DSD_ZERODB = 1; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external impedance on REFx. PCM and DSD Processor Mode Parameter 2,3,4 Minimum Typical Maximum Units AOUTx RL = 10 k CL = 200 pF OUT_FS = 11 Volume = 0 dB +1dB_EN = 0,5 unless otherwise specified Dynamic range (defined in Table 3-1) 24-bit, 32-bit, DSD 16-bit A-weighted Unweighted A-weighted Unweighted 124 121 130 127 dB dB dB dB THD+N (defined in Table 3-1) 24-bit, 32-bit 16-bit DSD 0 dB –20 dB –60 dB 0 dB –20 dB –60 dB 0 dB –20 dB –60 dB –115 –97 –67 –94 –74 –34 –108 –97 –67 –109 –61 –88 –28 –101 –61 dB dB dB dB dB dB dB dB dB Idle channel noise (A-weighted) (defined in Table 3-1) 24-bit, 32-bit, DSD — 0.55 — µV Full-scale output voltage 4.66 4.90 5.14 Vpp Interchannel isolation 6(defined in Table 3-1) 217 Hz 1 kHz 20 kHz 120 120 100 dB dB dB AOUTx R L = 10 k CL = 200 pF OUT_FS = 11 Volume = 0 dB +1dB_EN = 1, unless otherwise specified THD+N (defined in Table 3-1) 24-bit, 32-bit, DSD 0 dB — –105 — dB Full-scale output voltage 5.42 5.70 5.99 Vpp

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RL = 600  CL = 200 pF OUT_FS = 11 Volume = 0 dB +1dB_EN = 0, unless otherwise specified Dynamic range (defined in Table 3-1) 24-bit, 32-bit, DSD 16-bit A-weighted Unweighted A-weighted Unweighted 124 121 130 127 dB dB dB dB THD+N (defined in Table 3-1) 24-bit, 32-bit 16-bit DSD 0 dB –20 dB –60 dB 0 dB –20 dB –60 dB 0 dB –20 dB –60 dB –115 –97 –67 –94 –74 –34 –108 –97 –67 –109 –61 –88 –28 –101 –61 dB dB dB dB dB dB dB dB dB Idle channel noise (A-weighted) (defined in Table 3-1) 24-bit, 32-bit, DSD — 0.55 — µV Full-scale output voltage 4.66 4.90 5.14 Vpp Output power — 5 — mW Interchannel isolation (defined in Table 3-1) 217 Hz 1 kHz 20 kHz 120 120 100 dB dB dB AOUTx R L = 600  CL = 200 pF OUT_FS = 11 Volume = 0 dB +1dB_EN = 1, unless otherwise specified THD+N (defined in Table 3-1) 24-bit, 32-bit, DSD 0 dB — –105 — dB Full-scale output voltage 5.42 5.70 5.99 Vpp Output power — 6.8 — mW Other characteristics for AOUTx Interchannel gain mismatch (defined in Table 3-1)— ± 0 . 1 — d B Interchannel phase mismatch (defined in Table 3-1) — — ±0.01 ° Output offset voltage: Mute (defined in Table 3-1) — ±50 ±100 µV Gain drift (defined in Table 3-1) — ±100 — ppm/°C Load resistance (R L)6 0 0 — —  Load capacitance (CL)— — 1 n F Turn-on time (defined in Table 3-1)— — 1 2 m s Click/pop during PDN_HP enable or disable A-weighted — ±50 ±100 µV 1.This table also applies to external VCP_FILT supply mode: CS43198 power up procedure is per description in Section 5.12.1; EXT_VCPFILT = 1; VCP_FILT+ and VCP_FILT– comply to Table 3-2 when EXT_VCPFILT = 1; in this mode, HV_EN must be set to 1. 2.One LSB of triangular PDF dither is added to PCM data. 3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table. 4.DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index. 5.The volume must be configured as indicated to achieve specified output characteristics. Table 3-4. Analog Output Characteristics (HV_EN = 1) 1 (Cont.) Test conditions (unless otherwise specified): Fig. 2-1 shows CS43198 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; ASP_M/Sb = 1; typical, min/max performance data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK = 44.1-kHz mode); PDN_XTAL = 0, MCLK_INT = 1, PLUS_1DB = 0, and MCLK_SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz); Volume = 0 dB; when testing in DSD processor mode, DSD_ZERODB = 1; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external impedance on REFx. PCM and DSD Processor Mode Parameter 2,3,4 Minimum Typical Maximum Units

6.Output test configuration. Symbolized component values are specified in the test conditions. Table 3-5. Analog Output Characteristics for Direct DSD Mode 1 Test conditions (unless otherwise specified): Fig. 2-1 shows CS43198 connections; input test signal is a 0-dB SACD, full-scale 997-Hz sine wave (unless specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; HV_EN = 1; typical, min/max performance data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; PDN_XTAL = 0, MCLK_INT = 1, and MCLK_ SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz); DSD_EN = 1; DIR_DSD = 1; O U T _ F S=1 1 ; V o l u m e=0 d B ; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external impedance on REFx. 1.This table also applies to external VCP_FILT supply mode: CS43198 power up procedure is per description in Section 5.12.1; EXT_VCPFILT=1; VCP_ FILT+ and VCP_FILT– comply to Table 3-2 when EXT_VCPFILT=1; in this mode, HV_EN must be set to 1. Direct DSD Mode Parameter 2,3 2.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table. 3.DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index. Minimum Typical Maximum Units AOUTx RL = 600  or 10 k CL = 200 pF 64•Fs, High Gain DSD_SPEED = 00 DSD_DIRECT_MC = 0 DSD_DIRECT_GAIN = 1, unless otherwise specified Dynamic range (defined in Table 3-1) DSD A-weighted Unweighted 111 108 116 113 dB dB THD+N (defined in Table 3-1) DSD 0 dB –20 dB –60 dB –105 –91 –53 –99 –85 –48 dB dB dB Full-scale output voltage 3.61 3.8 3.99 Vpp AOUTx R L = 600  or 10 k CL = 200 pF 64•Fs, Low Gain No Magnitude Compensation DSD_SPEED = 00 DSD_DIRECT_GAIN = 0 DSD_DIRECT_MC = 0, unless otherwise specified Dynamic range (defined in Table 3-1) DSD A-weighted Unweighted 106 105 112 110 dB dB THD+N (defined in Table 3-1) DSD 0 dB –20 dB –60 dB –107 –90 –50 –101 –84 –45 dB dB dB Full-scale output voltage 2.71 2.85 2.99 Vpp AOUTx R L = 600  or 10 k CL = 200 pF 64•Fs, Low Gain With Magnitude Compensation DSD_SPEED = 00 DSD_DIRECT_MC = 1, unless otherwise specified Dynamic range (defined in Table 3-1) DSD A-weighted Unweighted 107 103 111 107 dB dB THD+N (defined in Table 3-1) DSD 0 dB –20 dB –60 dB –98 –78 –47 –92 –72 –43 dB dB dB Full-scale output voltage 2.71 2.85 2.99 Vpp AOUTx R L = 600  or 10 k CL = 200 pF 128•Fs, High Gain DSD_SPEED = 01 DSD_DIRECT_GAIN = 1, unless otherwise specified Dynamic range (defined in Table 3-1) DSD A-weighted Unweighted 110 106 116 112 dB dB THD+N (defined in Table 3-1) DSD 0 dB –20 dB –60 dB –101 –92 –52 –95 –84 –46 dB dB dB Full-scale output voltage 3.61 3.8 3.99 Vpp AOUTx R L = 600  or 10 k CL = 200 pF 128•Fs, Low Gain DSD_SPEED = 01 DSD_DIRECT_GAIN = 0, unless otherwise specified Dynamic range (defined in Table 3-1) DSD A-weighted Unweighted 105 103 112 109 dB dB THD+N (defined in Table 3-1) DSD 0 dB –20 dB –60 dB –104 –90 –49 –98 –84 –43 dB dB dB Full-scale output voltage 2.71 2.85 2.99 Vpp Test Load AOUTA CLA REFA RLA Measurement Device +AOUTB REFB CH1 CH2 CLB RLB

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Table 3-6. Wideband Flatness Mode Analog Output Characteristics 1 Test conditions (unless otherwise specified): Fig. 2-1 shows CS43198 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; ASP_M/Sb = 1; typical, min/max performance data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–90 kHz; ASP_SPRATE = 0110 (LRCK = 192-kHz mode); PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz); Volume = 0 dB; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external impedance on REFx. 1.This table also applies to external VCP_FILT supply mode: CS43198 power up procedure is per description in Section 5.12.1; EXT_VCPFILT = 1; VCP_FILT+ and VCP_FILT– comply to Table 3-2 when EXT_VCPFILT = 1; in this mode, HV_EN must be set to 1. Wideband Flatness Mode Parameter 2,3 2.One LSB of triangular PDF dither is added to PCM data. 3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table. Minimum Typical Maximum Units AOUTx RL = 600  CL = 200 pF OUT_FS = 11 Volume = 0 dB +1dB_EN = 0 HV_EN = 1, unless otherwise specified Dynamic range (defined in Table 3-1) 24-bit, 32-bit A-weighted 122 128 — dB THD+N (20 Hz–20 kHz, defined in Table 3-1) 24-bit, 32-bit 0 dB –20 dB –60 dB –112 –97 –67 –106 –61 dB dB dB Idle channel noise (A-weighted) (defined in Table 3-1) 24-bit, 32-bit — 0.69 — µV Full-scale output voltage 4.66 4.90 5.14 Vpp Output power — 5 — mW Interchannel isolation (defined in Table 3-1) 217 Hz 1 kHz 20 kHz 120 120 110 dB dB dB AOUTx R L = 600  CL = 200 pF OUT_FS = 11 Volume = 0 dB +1dB_EN = 1 HV_EN = 1, unless otherwise specified THD+N (20 Hz–20 kHz, defined in Table 3-1) 24-bit, 32-bit 0 dB — –105 –99 dB Full-scale output voltage 5.42 5.7 5.99 Vpp Output power — 6.8 — mW Other characteristics for AOUTx Interchannel gain mismatch (defined in Table 3-1)— ± 0 . 1 — d B Interchannel phase mismatch (defined in Table 3-1) — — ±0.01 ° Output offset voltage: Mute (defined in Table 3-1) — ±50 ±100 µV Gain drift (defined in Table 3-1) — ±100 — ppm/°C Load resistance (R L)6 0 0 — —  Load capacitance (CL)— — 1 n F Turn-on time (defined in Table 3-1)— — 1 2 m s Click/pop during PDN_HP enable or disable A-weighted — ±50 ±100 µV Table 3-7. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics Test conditions (unless specified otherwise): The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Single-Speed Mode refers to 32-, 44.1-, and 48-kHz sample rates. Double-Speed Mode refers sample rates. MCLK_INT is an integer multiple of Fs; HPF disabled; no DC offset applied; group delay does not include serial port delay. Parameter Minimum Typical Maximum Units Fast Roll-Off (FILTER_SLOW_FASTB =0 ) Single-Speed Mode 1 Passband 2 to –0.01-dB corner to –3-dB corner attenuation @ Fs/2 8.44 3 0.4535 0.482 Fs Fs dB Passband ripple 10 Hz to –0.01-dB corner 5 –0.01 — +0.01 dB Stopband 0.547 — — Fs Stopband attenuation 6 110 — — dB Group delay (linear phase) PHCOMP_LOWLATB = 1 — 39.5/Fs 7 —s Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 6.3/Fs 8 —s Deemphasis error 9 (Relative to 1 kHz) Fs = 44.1 kHz — — ±0.3 dB

(FILTER_SLOW_FASTB =0 ) Double-Speed Mode 1 Passband 2 to –0.01-dB corner to –3-dB corner attenuation @ Fs/2 7.77 0.227 0.48 Fs Fs dB Passband ripple 10 Hz to –0.01-dB corner –0.01 — 0.01 dB Stopband 0.583 — — Fs Stopband attenuation 6 80 — — dB Group delay (linear phase) PHCOMB_LOWLATB = 1 — 22.3/Fs — s Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 7.5/Fs — s Fast Roll-Off (FILTER_SLOW_FASTB =0 ) Quad-Speed Mode 1 Passband 2 to –0.01-dB corner to –3-dB corner attenuation @ Fs/2 9.44 0.114 0.46 Fs Fs dB Passband ripple 10 Hz to –0.01-dB corner –0.01 — 0.01 dB Stopband 0.583 — — Fs Stopband attenuation 6 80 — — dB Group delay (linear phase) PHCOMB_LOWLATB = 1 — 20.7/Fs — s Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 11.3/Fs — s Slow Roll-Off (FILTER_SLOW_FASTB =1 ) Single-Speed Mode 1 Passband 2 to –0.01-dB corner to –3-dB corner attenuation @ Fs/2 6.45 10 0.417 0.482 Fs Fs dB Passband ripple 10 Hz to –0.01-dB corner 5 –0.01 — +0.01 dB Stopband 0.583 — — Fs Stopband attenuation 6 64 — — dB Group delay (linear phase) PHCOMB_LOWLATB = 1 — 34.5/Fs 11 —s Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 5.6/Fs 12 —s Deemphasis error 9 (Relative to 1 kHz) Fs = 44.1 kHz — — ±0.3 dB Slow Roll-Off (FILTER_SLOW_FASTB =1 ) Double-Speed Mode 1 Passband 2 to –0.01-dB corner to –3-dB corner attenuation @ Fs/2 0.208 0.458 Fs Fs dB Passband ripple 10 Hz to –0.01-dB corner –0.01 — 0.01 dB Stopband 0.792 — — Fs Stopband attenuation 6 70 — — dB Group delay (linear phase) PHCOMB_LOWLATB = 1 — 22.3/Fs — s Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 6.7/Fs — s Slow Roll-Off (FILTER_SLOW_FASTB =1 ) Quad-Speed Mode Passband 2 to –0.01-dB corner to –3-dB corner attenuation @ Fs/2 7.00 0.104 0.43 Fs Fs dB Passband ripple 10 Hz to –0.01-dB corner –0.01 — 0.01 dB Stopband 0.792 — — Fs Stopband attenuation 6 75 — — dB Group delay (linear phase) PHCOMB_LOWLATB = 1 — 20.7/Fs — s Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 10.6/Fs — s Nonoversampling (NOS) (NOS =1 ) Single-Speed Mode 1 Passband 2 to –0.01-dB corner to –3-dB corner 0.026 0.443 Fs Fs Passband droop 10 Hz to 20 kHz — — 3.2 13 dB Group delay — 2.7/Fs — s Nonoversampling (NOS) (NOS =1 ) Double-Speed Mode 1 Passband 2 to –0.01-dB corner to –3-dB corner 0.0246 0.446 Fs Fs Passband droop 10 Hz to 20 kHz — — 0.73 dB Group delay — 4.5/Fs — s Nonoversampling (NOS) (NOS =1 ) Quad-Speed Mode 1 Passband 2 to –0.01-dB corner to –3-dB corner 0.026 0.405 Fs Fs Passband droop 10 Hz to 20 kHz — — 0.17 dB Group delay — 8.4/Fs — s Table 3-7. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics (Cont.) Test conditions (unless specified otherwise): The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Single-Speed Mode refers to 32-, 44.1-, and 48-kHz sample rates. Double-Speed Mode refers sample rates. MCLK_INT is an integer multiple of Fs; HPF disabled; no DC offset applied; group delay does not include serial port delay. Parameter Minimum Typical Maximum Units

18 DS1156F1

Octuple-Speed Mode 1 Passband 2 to –0.01-dB corner to –3-dB corner 0.0299 0.263 Fs Fs Passband droop 10 Hz to 20 kHz — — 0.04 dB Group delay — 17/Fs — s 1. Filter response is by design. 2. Response is clock-dependent and scales with Fs. 3. 8.5 dB for 32-kHz sample rate. 4. 0.454 Fs for 32-kHz sample rate. 5. Filter ripple specification is invalid with deemphasis enabled. 6. For Single-Speed Mode, the measurement bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the measurement bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the measurement bandwidth is from stopband to 1.34 Fs. 7. 39/Fs for 32-kHz sample rate. 8. 5.9/Fs for 32-kHz sample rate. 9. Deemphasis is available only in 44.1 kHz. 10. 6.5 dB for 32-kHz sample rate. 11. 34/Fs for 32-kHz sample rate. 12. 5.2/Fs for 32-kHz sample rate. 13. 3.9 dB for 32-kHz sample rate (passband droop 10 Hz to 15 kHz). Table 3-8. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics (Wideband Flatness Mode) Test conditions (unless specified otherwise): The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Wideband Flatness Mode refers to Fs = 192 kHz sample rates. PCM_WBF_EN = 1. MCLK_ INT is an integer multiple of Fs; HPF disabled; no DC offset applied; group delay does not include serial port delay. Parameter Minimum Typical Maximum Units Wideband Flatness Mode 1 1. Filter response is by design and may require calibration. Passband 2 2. Response is clock-dependent and scales with Fs. to –0.003-dB corner to –3-dB corner attenuation @ Fs/2 0.417 0.46 Fs Fs dB Passband ripple 10 Hz to –0.003-dB corner –0.003 — 0.003 dB Stopband 0.583 — — Fs Stopband attenuation 3. The measurement bandwidth is from stopband to 1.34 Fs. 80 — — dB Group delay — 20.7/Fs — s Table 3-9. DAC High-Pass Filter (HPF) Characteristics Test conditions (unless specified otherwise): Gains are all set to 0 dB; TA = +25°C. Parameter 1 Minimum Typical Maximum Units Passband 2 2.For PCM Single-Speed Mode, N = 1. For PCM Double-Speed Mode, N = 2. For PCM Quad-Speed Mode, N = 4. For PCM Octuple-Speed Mode, N = 8. For DSD 64 x Fs Mode, N = 1. For DSD 128 x Fs Mode, N = 1. –0.05-dB corner –3.0-dB corner 0.195 x 10-3/N 19.5 x 10-6/N Fs Fs Passband ripple (0.417x10-3/N Fs to 0.417/N Fs; normalized to 0.417/N Fs) 2 — — 0.01 dB Phase deviation @ 0.453x10-3/N Fs 2 —2 . 4 5 — ° Filter settling time 3 3.Required time for the magnitude of the DC component present at the output of the HPF to reach 5% of the applied DC signal. — 24500 × N / Fs 2 —s Table 3-7. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics (Cont.) Test conditions (unless specified otherwise): The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Single-Speed Mode refers to 32-, 44.1-, and 48-kHz sample rates. Double-Speed Mode refers sample rates. MCLK_INT is an integer multiple of Fs; HPF disabled; no DC offset applied; group delay does not include serial port delay. Parameter Minimum Typical Maximum Units

Table 3-10. DSD Combined Digital and On-Chip Analog Filter Response 1 Test conditions (unless specified otherwise): Digital gains are all set to 0 dB; TA = +25°C; PDN_XTAL = 0, MCLK_INT = 1, DSD_EN = 1, and MCLK_SRC_ SEL = 00 (crystal frequency fXTAL = 22.5792 MHz). 1.Filter response is by design. Parameter Minimum Typical Maximum Units DSD Processor Mode DIR_DSD = 0 Passband to –3-dB corner — 50 — kHz Frequency response 20 Hz to 20 kHz –0.05 — 0.05 dB Roll-off 27 — — dB/Oct Direct DSD Mode, 64•Fs, Low Gain, DSD_SPEED = 00, DSD_DIRECT_GAIN = 0, DIR_DSD = 1 Passband to –0.1-dB corner to –3-dB corner 7.8 kHz kHz Frequency response 20 Hz to 20 kHz –0.67 — 0 dB Direct DSD Mode, 64•Fs, Low Gain With Magnitude Compensation, DSD_SPEED = 00, DSD_DIRECT_GAIN = 0, DSD_DIRECT_MC = 1, DIR_DSD = 1 Passband to –0.1-dB corner to –3-dB corner kHz kHz Frequency response 20 Hz to 20 kHz 0 — 0.06 dB Direct DSD Mode, 64•Fs, High Gain, DSD_SPEED = 00, DSD_DIRECT_GAIN = 1, DIR_DSD = 1 Passband to –0.1-dB corner to –3-dB corner 7.5 kHz kHz Frequency response 20 Hz to 20 kHz –0.71 — 0 dB Direct DSD Mode, 128•Fs, Low Gain, DSD_SPEED = 01, DSD_DIRECT_GAIN = 0, DIR_DSD = 1 Passband to –0.1-dB corner to –3-dB corner 7.8 kHz kHz Frequency response 20 Hz to 20 kHz –0.67 — 0 dB Direct DSD Mode, 128•Fs, High Gain, DSD_SPEED = 01, DSD_DIRECT_GAIN = 1, DIR_DSD = 1 Passband to –0.1-dB corner to –3-dB corner kHz kHz Frequency response 20 Hz to 20 kHz –0.18 — 0 dB Table 3-11. Digital Interface Specifications and Characteristics Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; parameters can vary with VL and VP; typical performance data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; min/max performance Parameters 1 1.See Table 1-1 for serial and control-port power rails. Symbol Minimum Maximum Units Input leakage current 2,3 2.Specification is per pin. 3.Includes current through internal pull-up or pull-down resistors on pin. LRCK1, DSDB/LRCK2 SDIN1, SCLK1, DSDA/SDIN2, DSDCLK/SCLK2 SDA, SCL INT, RESET Iin — ±100 ±100 µA µA nA nA Internal weak pull-down — 550 2450 k  Input capacitance —— 1 0 p F INT current sink (VOL = 0.3 V maximum) — 825 — µA VL Logic (non-I2C) High-level output voltage (I OH = –100 µA) Low-level output voltage High-level input voltage Low-level input voltage VOH VOL VIH VIL 0.9•VL 0.7•VL 0.1•VL 0.3•VL V V V V VL Logic (I 2C only) Hysteresis voltage (Fast Mode and Fast Mode Plus) Low-level output voltage High-level input voltage Low-level input voltage VHYS VOL VIH VIL 0.05•VL 0.7•VL 0.2•VL 0.3•VL V V V V HP_DETECT 4 4.The HP_DETECT input circuit allows the HP_DETECT signal to be as low of a voltage as VCP_FILT– and as high as VP. Section 4.4.1 provides configuration details. High-level input voltage Low-level input voltage VIH VIL 0.93•VP 2.0 V V HP_DETECT current to VCP_FILT– 4 IHP_DETECT 1.00 2.91 µA RESET pulse width low — 1000 — µs

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Table 3-12. CLKOUT Characteristics Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL = VD = 1.8 V; CL = 60 pF; PLL reference input must meet the phase-noise mask specified in Fig. 4-12; TA = +25°C; Output jitter is measured from 100 Hz to half of the output frequency. Parameters Symbol Minimum Typical Maximum Units CLKOUT output frequency f CLKOUT 2.8224 5.6448 7.5264 11.2896 3.072 6.144 8.192 12.288 MHz MHz MHz MHz CLKOUT output duty cycle — 40 50 60 % CLKOUT output TIE jitter (RMS) CLKOUT_SRC_SEL = 01 t JIT —5 0 0— p s Table 3-13. PLL Characteristics Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL = VD = 1.8 V; PLL reference input must meet the phase-noise mask specified in Fig. 4-12; TA = +25°C. Parameters Symbol Minimum Typical Maximum Units PLL output frequency f out 22.5792 24 24.576 MHz PLL lock time tLock — 620 1000 µs PLL reference clock input — — 11.2896 22.5792 12.2880 24.5760 9.6000 19.2000 12.0000 24.0000 13.0000 26.000 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz PLL reference clock input jitter — — — 50 ps Table 3-14. Crystal Characteristics Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL = VD = 1.8 V; TA = +25°C Parameters 1 1.Refer to Section 5.3 for supported crystal options. Symbol Minimum Typical Maximum Units Crystal oscillator frequency f XTAL 22.57 22.5792/ 24.576 24.58 MHz Crystal load capacitance C L_XTAL 5—8 p F Equivalent series resistance esr XTAL —— 1 0 0  Startup time t XTAL_pup —— 6 . 5 m s Shunt capacitance C O —— 0 . 8 p F Maximum drive level — 200 — — µW Table 3-15. Power-Supply Rejection Ratio (PSRR) Characteristics Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; input test signal held low (all zero data); GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; VL = VA = VD = 1.8 V, VP = 3.6 V; When testing PSRR, PCM input test signal held low (all zero data); TA = +25°C; PCM_AMUTE = 0. Parameter 1 Minimum Typical Maximum Units AOUTx PSRR with 100-mVpp signal AC coupled to VA supply 217 Hz 1 kHz 20 kHz dB dB dB AOUTx PSRR with 100-mVpp signal AC coupled to VCP supply 217 Hz 1 kHz 20 kHz dB dB dB AOUTx PSRR with 100-mVpp signal AC coupled to VP supply 217 Hz 1 kHz 20 kHz 100 100 dB dB dB

1.PSRR test configuration: Typical PSRR can vary by approximately 6 dB below the indicated values. Table 3-16. DC Characteristics Test conditions (unless otherwise specified): Fig. 2-1 shows CS43198 connections; GNDD = GNDA = 0 V; all voltages with respect to ground. Parameters Minimum Typical Maximum Units VCP_FILT (No load connected to AOUTx) EXT_VCPFILT = 0 VP_LDO Mode VCP_FILT+ pin (HV_EN = 1) VCP_FILT+ pin (HV_EN = 0) VCP_FILT– pin (HV_EN = 1) VCP_FILT– pin (HV_EN = 0) 3.0 2.6 –3.0 –2.6 V V V V VCP Mode VCP_FILT+ pin VCP_FILT– pin VCP –VCP V V Other DC characteristics FILT+ voltage — –0.35 — V FILT– voltage — 0.35 — V Analog output current limiter on threshold. — 120 160 mA VD power-on reset threshold POR) Up Down 1.15 0.950 V V Table 3-17. Power Consumption Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; performance data taken with VA = VCP = VD = VL = 1.8 V; VP = 3.6 V; TA = +25°C; ASP_SPRATE = 0001(44.1-kHz mode); MCLK_INT= 1 (22.5792 MHz); MCLK_SRC_SEL = 00; +1dB_EN = 1; all other fields are set to defaults; no signal on any input; control port inactive; all serial ports are set to Slave or Master Mode as indicated, input clock/data are held low unless active; test load is RL = 600  and CL = 1 nF for AOUTx; measured values include currents consumed by the DAC and do not include current delivered to external loads unless specified otherwise (e.g., from AOUTx outputs); see Fig. 2-1. Use Cases Typical Current (µA) Total Power (µW)POUT iVCP iVA iVD iVL iVP 1O f f 1 1.Off configuration: Clock/data lines held low; RESET = LOW; VA = VD = VL = 0 V, VCP = 0 V, VP = 3.6 V. —0 0 0 0 6 1 1

2 Standby 2

2.Standby configuration: Clock/data lines held low; RESET = HIGH; VA = VD = VL = 1.8 V, VCP = 1.8 V, VP = 3.6 V; HP_DETECT_CTRL = 11 (enabled); HPDETECT_PLUG_INT_MASK=0 (unmasked); PDN_XTAL = 1, MCLK_SRC_SEL = 10 (RCO selected as MCLK source). HPDETECT enabled — 0 0 256 0 32 576 3 A Playback External MCLK = 22.5792 MHz, I 2S/DoP Stereo AOUT Quiescent 3 SDIN, ASP_M/Sb = 0); PDN_XTAL = 1. 3808 7835 2786 0 28 26074 Table 3-18. Serial-Port Interface Characteristics Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL = 1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH thresholds (see Table 3-11). Parameters 1,2,3,4 Symbol Minimum Typical Maximum Units FSYNC frame rate Fs (See Section 4.8.5) kHz FSYNC high period 5 tHI:FSYNC 1/fSCLK — (n–1)/f SCLK s Operational Amplifier OUT GND Power DAC OUT GND PWR DUT+5 V +5 V ++–– OUT Analog Generator Analog Analyzer Analog Test Equipment Analog Output PSRR

22 DS1156F1

FSYNC duty cycle xSP_5050 = 1 — 45 — 55 % FSYNC delay time after SCLK launching edge 6 tD:CLK–FSYNC ——1 0 n s SCLK frequency f SCLK —— f MCLK_INT MHz SCLK high period 7 tHI:SCLK 1/(2•fSCLK) – 1/fMCLK_INT —1 / ( 2 • f SCLK) + 1/fMCLK_INT ns SDIN setup time before SCLK latching edge 6 tSU:SDI 10 — — ns SDIN hold time after SCLK latching edge 6 tH:SDI 5— — n s Slave Mode FSYNC setup time before SCLK latching edge 6 tSU:FSYNC 10 — — ns FSYNC hold time after SCLK latching edge 6 tH:FSYNC 5— — n s SCLK frequency f SCLK —— 2 4 . 5 8 M H z SCLK high period t HI:SCLK 16 — — ns SCLK low period t LO:SCLK 16 — — ns SDIN setup time before SCLK latching edge 8 tSU:SDI 10 — — ns SDIN hold time after SCLK latching edge 6 tH:SDI 5— — n s 1.Output clock frequencies follow the internal master clock (MCLK_INT) frequency proportionally. Any deviation of the clock source from the nominal supported rates are directly imparted to the output clock rate by the same factor (e.g., +100-ppm offset in the frequency of MCLK_INT becomes a +100-ppm offset in LRCK/FSYNC and SCLK). 2.I2S interface timing 3.TDM interface timing (shown with xSP_FSD = 010, xSP_LCHI = 1) 4.Applies to Master and Slave Modes, unless specified otherwise. 5.Maximum LRCK duty cycle is equal to frame length, in SCLK periods, minus 1. Maximum duty cycle occurs when LRCK high (xSP_LCHI) is set to 768 SCLK periods and LRCK period (xSP_LCPR) is set to 769 SCLK periods. 6.Data may be latched/launched on either the rising or falling edge of SCLK. 7.SCLK duty cycle in Master Mode depends on Master Mode clock configuration, and can vary by up to 1 MCLK_INT period. 8.Data is latched/launched on the rising or falling edge of SCLK as determined by xSP_SCPOL_OUT, xSP_SCPOL_IN, and xSP_FSD bits. See the SCLK launching specs in Table 3-18. Table 3-19. DSD Switching Characteristics Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL = 1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH thresholds (see Table 3-11). Parameter 1,2 Symbol Minimum Typical Maximum Units DSDCLK duty cycle — 40 — 60 % DSDCLK pulse width low t SCLKL 40 — — ns DSDCLK pulse width high t SCLKH 40 — — ns Table 3-18. Serial-Port Interface Characteristics (Cont.) Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL = 1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH thresholds (see Table 3-11). Parameters 1,2,3,4 Symbol Minimum Typical Maximum Units SCLK (CPOL = 1 ) SDIN tSU:SDI tH:SDI LRCK/FSYNC tD: CLK–FSYNC 1/Fs ... ... fSCLK = N · Fs tSU :FSYNC tH:FSYNC tLO:SCLK tHI:SCLK SCLK (CPOL = 0) ... 1/fSCLK ... ... ... ... ... SCLK SDIN tSU :SD I tH: SD I LRCK/FSYNC tD :C LK- FSYN C 1/fSC LK Don’t Care Frame location 0 Frame location N -1 1/Fs ... ... ... fSC LK = N · Fs tSU :FSYNC tH: FSYN C tH I:FSYN C tLO: SCLK tH I:SC L K

DSDCLK frequency (64× oversampled) (128× oversampled) (256x oversampled) —1 . 0 2 4 2.048 4.096 2.8224 5.6448 11.2897 f MCLK_INT/8 fMCLK_INT/4 fMCLK_INT/2 MHz MHz MHz DSDA/DSDB valid to DSDCLK rising setup time t SDLRS 10 — — ns DSDCLK rising to DSDA or DSDB hold time t SDH 10 — — ns DSD clock to data transition (Phase Modulation Mode) (64× oversampled) (128× oversampled) tDPM –20 –10 ns ns 1.Serial audio input interface timing 2.Phase modulation mode serial audio input interface timing Table 3-20. I2C Slave Port Characteristics Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to ground; VL = 1.8 V; inputs: Logic 0 = GNDA = 0 V, Logic 1 = VL; TA = +25°C; SDA load capacitance equal to maximum value of CB = 400 pF; minimum SDA pull-up resistance, RP(min).1 Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS43198 with the specified load capacitance. Parameter 2 Symbol 3 Minimum Maximum Units SCL clock frequency fSCL —1 0 0 0 k H z Clock low time tLOW 500 — ns Clock high time tHIGH 260 — ns Start condition hold time (before first clock pulse) t HDST 260 — ns Setup time for repeated start t SUST 260 — ns Rise time of SCL and SDA Standard Mode Fast Mode Fast Mode Plus tRC — 1000 300 120 ns ns ns Fall time of SCL and SDA Standard Mode Fast Mode Fast Mode Plus t FC — 300 300 120 ns ns ns Setup time for stop condition t SUSP 260 — ns SDA setup time to SCL rising t SUD 50 — ns SDA input hold time from SCL falling 4 tHDDI 0— n s Output data valid (Data/Ack) 5 Standard Mode Fast Mode Fast Mode Plus tVDDO — 3450 900 450 ns ns ns Bus free time between transmissions t BUF 500 — ns SDA bus capacitance SCL frequency = 1 MHz, V L = 1.8 V SCL frequency ≤ 400 kHz CB — 340 400 pF pF SCL/SDA pull-up resistance 1 VL = 1.8 V R P 350 — Ω Pulse width of spikes to be suppressed t PS —5 0 n s Switching time between RCO and MCLK_INT 6 — 150 — µs Power-up delay (delay before I2C can communicate after RESET released) tPUD 1500 — µs Table 3-19. DSD Switching Characteristics (Cont.) Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL = 1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH thresholds (see Table 3-11). Parameter 1,2 Symbol Minimum Typical Maximum Units DSDCLK DSDA, DSDB tSDLRS tSDH tSCLKL tSCLKH DSDCLK (128•Fs) DSDCLK (64•Fs) DSDA, DSDB tDPM tDPM

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1.The minimum RP value (resistor shown in Fig. 2-1) is determined by using the maximum level of VL, the minimum sink current strength of its respective output, and the maximum low-level output voltage VOL. The maximum RP value may be determined by how fast its associated signal must transition (e.g., the lower the value of RP, the faster the I2C bus is able to operate for a given bus load capacitance). See I²C bus specification referenced in Section 13. 2.All timing is relative to thresholds specified in Table 3-11, VIL and VIH for input signals, and VOL and VOH for output signals. 3.I²C control-port timing 4.Data must be held long enough to bridge the transition time, t F, of SCL. 5.Time from falling edge of SCL until data output is valid. 6.Upon setting MCLK_SRC_SEL and sending the I2C stop condition, the switching of RCO and other MCLK_INT sources occurs. A least wait time as specified is required after changing MCLK_SRC_SEL and sending the I2C stop condition before the next I2C transaction is initiated. tBUF tLOW Stop tHDDI tSUD tSUST tRC tHDST tHIGH tHDST tFC tSUSP Start Repeated Start Stop SDA SCL tVDDO

4 Functional Description

This section describes the general theory of operation of the CS43198, tracing the signal and control flow through the various blocks within the device. It comprises the following sections:

• Section 4.1, “Overview”
• Section 4.2, “Analog Outputs”
• Section 4.3, “Class H Output”
• Section 4.4, “Headphone Presence Detect”
• Section 4.5, “Clocking Architecture”
• Section 4.6, “Clock Output and Fractional-N PLL”
• Section 4.7, “Filtering Options”
• Section 4.8, “Audio Serial Port (ASP)”
• Section 4.9, “DSD Interface”
• Section 4.10, “DSD and PCM Mixing”
• Section 4.11, “Standard Interrupts”
• Section 4.12, “Control Port Operation”
• Section 4.13, “Programmable Filter”

4.1 Overview

4.1.1 Analog Outputs

The analog output block includes separate pseudodifferential output. An on-chip inverting charge pump creates a positive and negative voltage equal to the input, allowing an adaptable, full-scale output swing centered around ground. The resulting internal supply can be ±VCP, or ±VP_LDO (either ±3.0 V with HV_EN = 1 or ±2.6 V with HV_EN = 0).

4.1.2 Headphone Detection

The CS43198 detects the presence of a headphone and notifies the application processor to wake up through an interrupt event.

4.1.3 Audio Interfaces and Supported Formats

There are two serial input ports on the CS43198, the audio serial port (ASP) and the auxiliary serial port (XSP). The ASP on the CS43198 supports I2S, TDM, and DoP (DSD over PCM) formats up to a 384-kHz sample rate. The XSP on the CS43198 supports the DoP format up to a 352.8-kHz sample rate. The CS43198 also has a dedicated DSD interface to support up to a 256•Fs DSD stream. The DSD interface shares pins with the XSP.

4.1.4 System Clocking

The CS43198 internal MCLK can be sourced from three options:

• Direct MCLK/crystal mode. The internal MCLK is provid ed through XTI/MCLK pin directly or generated by crystal oscillator.
• PLL mode. A PLL reference CLK is provided by externally through XTI/MCLK. The PLL is configured, and output is used as the internal MCLK.
• RCO mode. An internal RCO is used as the intern al MCLK. This mode can support HP detection and I2C communication. DAC playback function is not supported. The clock output is provided for audio applications that require high quality audio rate system clock. This clock output can be sourced from the following two options:

26 DS1156F1

• The clock generated by the CS43198 crystal oscillator.
• Output of the internal Fractional-N PLL that refers to MCLK input. See Section 4.6.1 for supported frequencies. The internal MCLK is used to generate serial port clocks. See Table 4-6 for supported LRCK combinations.

4.1.5 System Interrupts

The CS43198 includes an open-drain interrupt output (INT pin). Interrupt mask registers control whether an event associated with an interrupt status/mask bit pair triggers the assertion of INT. All types of interrupt are described in Section 4.10.

4.1.6 System Reset

The CS43198 offers two types of reset options:

• Asserting RESET . If RESET is asserted, all registers and state machines are immediately set to their default values/ states. No operation can begin until RESET is deasserted. Before normal operation can begin, RESET must be asserted at least once after the VP supply is first brought up.
• Power-on reset (POR). If the VD supply is lower than the POR threshold specified in Table 3-16, all registers and state machines are set to their default values/states. The POR releases the reset when the VD supply goes above the POR threshold. When the VD supply is turned on, the VL and VA supplies must also be turned on at the same time.

4.1.7 Power Down

The CS43198 has a register to power down individual components on the chip. Before any change can be applied to an individual component (except PLL), the block must be powered down first. For the PLL, changes can be applied after PLL_ START is cleared. The PDN_HP bit is responsible for enabling or disabling the signal chain playback operation. Setting PDN_HP disables signal chain playback operation. All the necessary components for playback operation need to be powered up and configured properly before PDN_HP is cleared. PDN_HP needs to be set before making any changes to the playback signal chain setup, except the following functions:

• Volume and mute related functions
• PCM filter settings (see Section 7.5.2) Before ASP, XSP, or DSDIF can be safely powered down, PDN_HP must be asserted, and PDN_DONE_INT must be present. For XTAL or PLL used as the source of internal MCLK, PDN_HP needs to be set first and MCLK source needs to be properly switched away before PDN_XTAL or PDN_PLL is set. If PLL output is only used as the source of CLKOUT, PDN_PLL can be set without PDN_HP being asserted. If the steps described above are not followed, the CS43198 enters an unresponsive state. PDN_CLKOUT does not require PDN_HP to be set before it is enabled. Recommended power-up and power-down sequences can be found in the Section 5.2.

4.2 Analog Outputs

The CS43198 provides an analog output that is derived from the digital audio input ports. This section describes the general flow of the analog outputs.

4.2.1 Analog Output Signal Flow

The CS43198 signal flow is shown in Fig. 4-1. Figure 4-1. Analog Output Signal Flow The CS43198 has 4 settings of full scale voltage, which are determined by OUT_FS[1:0]. When OUT_FS[1:0] = 11 and HV_EN = 1, the +1dB_EN bit can boost the output voltage to 2 Vrms. In any other setting combination of OUT_FS[1:0] and HV_EN, the +1dB_EN bit is ignored. The proper full scale voltage must be set first, and the digital volume settings is used to control signal levels. The CS43198 digital volume control allows independent control of the signal level in 1/2 dB increments from 0 dB (0b0000 0000) to –127 dB (0b1111 1110) by using x_VOLUME_y (where "x" is either PCM or DSD; "y" is either A or B) register. When the x_VOL_BEQA bit is set, both volumes can be changed simultaneously using x_VOLUME_A). The volume changes are implemented as dictated by PCM_SZC[1:0] and DSD_SZC in the signal control register (see changing the volume level in 1/8-dB steps, from the previous level to the new level. For PCM, when PCM_SZC[1:0] = 2, the volume level changes at an approximate rate of 1 dB/ms. The volume level also changes at a rate of 1 dB/ms for DSD. Both channels can be inverted independently by setting the INV_A and INV_B bits. Both channels can be swapped by setting the x_SWAP_CHAN bit. Channel A content can be copied to channel B by setting the x_COPY_CHAN bit. Mono mode can be enabled with proper setting of these bits. The CS43198 provides individual ramp-up and ramp-down control options (from the global soft ramp settings) for two specific scenarios. The PCM_RAMP_DOWN bit is for the scenario when the interpolation filter configuration switches (as configured by the PCM Filter Option register) during PCM playback. DSD_RAMP_UP bit is for the scenario when DSD playback recovers from detected DSD stream errors. Refer to each individual register description for setting details. The CS43198 can mute both channels simultaneously or independently. Also, it can auto-mute on both PCM stream and DSD stream when mute pattern is identified (defined in PCM_AMUTE and DSD_AMUTE). Additional signal and mute Multibit Modulator Multibit Modulator Interpolation Filter & Volume Control Interpolation Filter & Volume Control AO UTA AO UTB MUXMU X DSD Processor DoP to DSD Engine MU X Audio Source I2S REFB REFA DoP DSD  DAC and Filter DAC and Filter DAC_OVFL_INT p. 115 DSD_PRC_SRC p. 109 DIR_DSD p. 109 DSD_DIRECT_MC p. 110 DSD_DIRECT_GAIN p. 110 PCM_SZC p. 112 DSD_RAMP_UP p. 108 PCM_RAMP_DOWN p. 112 PCM_VOLUME_B p. 112 PCM_VOLUME_A p. 112 PCM_INV_A p. 113 PCM_INV_B p. 113 PCM_SWAP_CHAN p. 113 PCM_COPY_CHAN p. 113 PCM_VOL_BEQA p. 112 PCM_AMUTE p. 112 PCM_AMUTEBEQA p. 112 PCM_MUTE_A p. 112 PCM_MUTE_B p. 112 FILTER_SLOW_FASTB p. 111 PHCOMP_LOWLATB p. 111 HIGH_PASS p. 111 DEEMP_ON p. 111 MIX_PCM_PREP p. 109 MIX_PCM_DSD p. 109 +1dB_EN p. 111 OUT_FS p. 111 PCM_WBF_EN p. 111 DSD_EN p. 109 DSD_SPEED p. 109 STA_DSD_DET p. 109 INV_DSD_DET p. 109 DSD_VOLUME_B p. 107 DSD_VOLUME_A p. 108 DSD_INV_A p. 110 DSD_INV_B p. 110 DSD_VOL_BEQA p. 108 DSD_AMUTE p. 108 DSD_MUTE_A p. 108 DSD_MUTE_B p. 108 DSD_ZERODB p. 110 DSD_HPF_EN p. 110 OUT_FS p. 111 DSD_SZC p. 108 DSD_RAMP_UP p. 108 DSD_SWAP_CHAN p. 110 DSD_COPY_CHAN p. 110

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4.3 Class H Output

The CS43198 has an independent set of controls for the DSD processor path as shown in Fig. 4-1. The DSD processor also offers the control bit SIGCTL_DSDEQPCM, which maps the PCM_x setting to DSD_x setting, once enabled. As a result, some of the DSD_x register settings are ignored. The registers affected are DSD_RAMP_UP, DSD_VOL_BEQA, DSD_SZC, DSD_AMUTE, DSD_AMUTE_BEQA, DSD_MUTE_A, DSD_MUTE_B, DSD_INV_A, DSD_INV_B, DSD_ The CS43198 supports Direct DSD Mode up to a speed of 128•Fs. When enabled, DSD input data is sent directly to the digital-to-analog conversion interface for a pure DSD conversion. In this mode, the full-scale DSD and PCM levels are not matched, the dynamic range performance may be reduced, DC offset may be present in the output, the volume control is inactive, and the 50-kHz lowpass filter is not available. The user has selection of different internal filter configurations. Refer to Section 7.4.8 for details on the filter configuration control register.

4.2.2 Wideband Flatness Mode

The CS43198 specifically optimizes for wideband flatness playback, which is enabled by PCM_WBF_EN bit. This mode should only be enabled when PCM plays back at 192 kHz. When operating in other speeds or modes, this bit should be properly disabled. If wideband flatness mode enabled, the filter spec complies to Table 3-8. There is no option for filter roll-off or phase response in this mode. NOS filter mode should be disabled for proper operation. Note that wideband flatness mode can only be enabled or disabled when PDN_HP is set.

4.2.3 Mono Mode

The CS43198 supports mono (differential) mode playback. Mono mode allows driving a differential interconnect such as a XLR connector or implementing a stereo differential headphone utilizing two CS43198 devices. Fig. 2-2 shows a typical connection of the CS43198 to a XLR connector in mono mode. Fig. 4-2 shows the Class H operation. Figure 4-2. Class H Operation The CS43198 outputs use Cirrus Logic two-mode Class H technology. This prevents unnecessarily wasting energy during low power passages of program material or when the program material is played back at a low volume level. The internal charge pump is the central component of the two-mode Class H technology implemented in the CS43198. The charge pump receives its input voltage from the voltage present on the VCP or VP pin. From this input voltage, the charge pump creates the differential rail voltages supplied to the output stages. The charge pump can supply two sets of differential rail voltages: ±VCP and ±VP_LDO. VCP Class H Control Step-down/Inverting Charge Pump VCP_FILT––VCP –VP _LDO V VCP_FILT++VCP +VP _ LDO VVP ADPT_PWR p. 114

HV_EN setting, as shown in Fig. 4-3, determines the VP_LDO voltage as shown in Table 4-1. HV_EN = 1 setting is required to support the 1.7-V full-scale voltage. In this setting, minimum VP is required to be higher than 3.3 V. When HV_ EN = 0, the max output voltage is 1.4-V RMS full-scale voltage. In this setting, minimum VP is required to be higher than 3V . Figure 4-3. Internal LDO Configuration Table 4-2 shows the nominal signal and volume level ranges when the output is set to the adapt modes explained in Section 4.3.1. If the signal level is greater than the maximum value of this range, then clipping can occur.

4.3.1 Power Supply Control Options

This section describes the two types of operation: standard Class AB and adapt-to-output signal. The set of rail voltages supplied to the amplifier output stages depends on the ADPT_PWR (see p. 114) setting.

4.3.1.1 Standard Class AB Operation (ADPT_PWR = 001 or 010)

If ADPT_PWR is set to 001 or 010, the rail voltages supplied to the amplifiers are held to ±VP_LDO or ±VCP, respectively. The rail voltages supplied to the output stages are held constant, regardless of the output signal level. The CS43198 outputs simply operate in a traditional Class AB configuration.

4.3.1.2 Adapt-to-Output Signal (ADPT_PWR = 111)

If ADPT_PWR is set to 111, the rail voltage sent to the output stages is based solely on whether the signal sent to the amplifiers would cause the amplifiers to clip when operating on the lower set of rail voltages at certain threshold values.

• If it would cause clipping, the control logic instructs the charge pump to provide the next higher set of rail voltages to the amplifiers.
• If it would not cause clipping, the cont rol logic instructs the charge pump to provide the lower set of rail voltages to the amplifiers, eliminating the need to advise the CS43198 of volume settings external to the device.
• Note that for Direct DSD Mode, ADPT_PWR = 111 mode is not supported. Table 4-1. VP_LDO Voltage Per HV_EN Setting HV_EN VP_LDO Voltage 02 . 6 V 13 . 0 V Table 4-2. Class H Supply Modes Mode Class H Supply Level Signal 1 or Volume Level Range 2,3, 1.In adapt-to-signal, the volume level ranges are approximations but are within –0.5 dB from the values shown. 2.Relative to digital full scale with output gain set to 0 dB. 3.In fixed modes, clipping can occur if the signal level exceeds the maximum of this range due to setting the supply too low. 0 ±VP_LDO V, internally regulated from VP  –11 dB 1 ±VCP < –11 dB VP VP_LDOInternal LDO HV_EN p. 114

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4.3.2 Power-Supply Transitions

Charge-pump transitions from the lower to the higher set of rail voltages occur on the next FLYN/FLYP clock cycle. Despite the system’s fast response time, the VCP_FILT pin’s capacitive elements prevent rail voltages from changing instantly. Instead, the rail voltages ramp up from the lower to the higher supply, based on the time constant created by the output impedance of the charge pump and the capacitor on the VCP_FILT pin (the transition time is approximately 20 µs). Fig. 4-4 shows Class H supply switching. During this charging transition, a high dv/dt transient on the inputs may briefly clip the outputs before the rail voltages charge to the full higher supply level. This transitory clipping has been found to be inaudible in listening tests. Figure 4-4. VCP_FILT Transitions When the charge pump transitions from the lower to higher set or rail voltage, there is no delay associated with the transition. +VCP Ideal Transition Actual Transition caused by VCP_FILT+ Capacitor Time +VP_LDO -VCP -VP_LDO

When the charge pump transitions from the higher to the lower set of rail voltages, there is an approximate 5.5-s delay before the charge pump supplies the lower rail voltages to the amplifiers. This hysteresis ensures that the charge pump does not toggle between the two rail voltages as signals approach the clip threshold. It also prevents clipping in the instance of repetitive high-level transients in the input signal. Fig. 4-5 shows examples of this transitional behavior. Figure 4-5. VCP_FILT Hysteresis

4.3.3 External VCP_FILT Supply Mode

To bypass the CS43198 Class-H charge-pump circuit, provide external VCP_FILT± supply with the following conditions:

• When CS43198 is operating, apply +3.0 V with ±5% accu racy to VCP_FILT+ and apply –3.0 V with ±5% accuracy to VCP_FILT–.
• When CS43198 is powered down, extern al circuits present Hi-Z state to the VCP_FILT+ pin (>1k impedance) and VCP_FILT– pin (>10k impedance). Output Level +VCP Output Stage Rail Voltage Time –VCP 5.5 s –11 dB +VP_LDO –VP_LDO –11.5 dB

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4.4 Headphone Presence Detect

• To avoid possible damage, VCP_FILT± pins must re main within the absolute maximum rating specified. Figure 4-6. External VCP_FILT Power-Up Sequence For powering up CS43198 in this mode, the recommended sequence must be followed. This assumes that the CS43198 starts from the status where VCP_FILT± pins are presented with Hi-Z. 1. Set EXT_VCPFILT and HV_EN bits. 2. Wait 8 ms after I 2C ACK. 3. Release and start to ramp external voltage on VCP_FILT± pins. 4. Wait until VCP_FILT+ pin voltage to be greater than +2.6V and VCP_FILT– to be less than –2.6 V. 5. Clear the PDN_HP bit. Figure 4-7. External VCP_FILT Power-Down Sequence For powering down in this mode, use the following recommended sequence. This assumes that the CS43198 starts from the status where VCP_FILT± pins are presented with ±3.0 V, respectively. 1. Set PDN_HP. 2. Wait 8 ms after I 2C ACK. 3. Start to shut-off external supply to VCP_FILT± pins. 4. Wait until Hi-Z mode is presented on VCP_FILT± pins. 5. Clear EXT_VCPFILT and HV_EN bits.

The CS43198 provides headphone presence-detect functionality. EXT_VCPFILT PDN_HP VCP_FILT+ VCP_FILT‐ 8 ms +3.0 V ‐3.0 V +2.6 V ‐2.6 V Hi‐Z Hi‐Z EXT_VCPFILT PDN_HP VCP_FILT+ VCP_FILT‐ 8 ms +3.0 V ‐3.0 V Hi‐Z Hi‐Z

4.4.1 Headphone Presence Detect

The CS43198 supports headphone presence-detect capability via the HP_DETECT sense pin. HP_DETECT is debounced to filter out brief events before being reported to the corresponding presence-detect status bit and generating an interrupt if appropriate.

4.4.1.1 Headphone Detect Methods

CS43198 can detect the presence or absence of a plug. For a headphone-presence detect, a sense pin is connected to a terminal on the receptacle such that, if no plug is inserted, the pin is floating. If a plug is inserted, the pin is shorted to the tip (T) terminal. The presence detect function is accomplished by having a small current source inside the CS43198 to pull up the pin if it is left floating (no plug). If a plug is inserted and the sense pin is shorted to headphone output, the sense pin is shorted to the output signal and, therefore, is pulled below a certain threshold via the output stage of the HP amp. Thus, a low level at the sense pin indicates plug inserted, and a high level at the sense pin indicates plug removed.

4.4.1.2 Headphone Detect Registers

This section describes the behavior and interaction of the headphone-detect debounce register fields. See Fig. 4-8 for reference. Figure 4-8. Headphone Detect Block Diagram

• HPDETECT_CTRL configures the oper ation of the HP detect circuit.
• HPDETECT_INV inverts the signal from the HP detect circuit.
• HPDETECT_FALL_DBC_TIME configures the HP_DETECT falling debounce time.
• HPDETECT_RISE_DBC_TIME configures the HP_DETECT rising debounce time.
• HPDETECT_PLUG_DBC shows the falling-edge-debounced version of HP_DETECT signal.
• HPDETECT_UNPLUG_DBC shows the rising-edge -debounced version of HP_DETECT signal.
• HPDETECT_PLUG_INT shows the he adphone plug-in event status.
• HPDETECT_UNPLUG_INT shows the headphone unplug event status.
• HPDETECT_PLUG_INT_MASK is the interrupt mask of headphone plug-in event status.
• HPDETECT_UNPLUG_INT_MASK is the interrupt mask of headphone unplug event status.

4.4.1.3 Headphone Detect and Interrupts Setup Instructions

The following steps are required for activation of headphone-detect debounce interrupt status: 1. Ensure the I 2C is ready to respond to control port command. 2. Clear the interrupt masks. HP_DETECT HP Detect Block No Delay HP Detect Plug/Unplug Detect HP Detect Plug/Unplug Interrupt Mask HP Detect Plug/Unplug Interrupt Status Interrupt Handler Block INT Read Clears INT FALL_DEBOUNCE RISE DEBOUNCE No Delay HP Detect Debounced Status HPDETECT_CTRL p. 114 HPDETECT_PLUG_INT p. 115 HPDETECT_UNPLUG_ INT p. 115 HPDETECT_RISE_DBC_TIME p. 115 HPDETECT_FALL_DBC_TIME p. 115 HPDETECT_INV p. 114 HPDETECT_PLUG_DBC p. 115 HPDETECT_UNPLUG_DBC p. 115 HPDETECT_PLUG_INT_ MASK p. 117 HPDETECT_UNPLUG_ INT_MASK p. 117

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4.5 Clocking Architecture

1. Write to HPDETECT_RISE_DBC_TIME and HPDETECT_FALL_DBC_TIME (see p. 114) to enable debounce for presence detect plug/unplug. 4. Set HPDETECT_CTRL to 11 to enable the HPDETECT functions. The interrupt status bits can be found in Section 7.6.1.

4.5.1 Master Clock (MCLK) Sources

The MCLK is required by the CS43198 to operate any functionality associated with control, serial-port operation, or data conversion. Depending on the setting of MCLK_SRC_SEL (see p. 97), the MCLK can be provided by one of following methods:

• Sourced from a crystal oscillator between XTI/MCLK and XTO pins (see Fig. 4-9), then used directly as MCLK_INT
• Externally sourced through the XTI/MCLK input pin (see Fig. 4-10)
• PLL reference clock is provided through the XTI/MCLK input pin (see Fig. 4-10), then use internal PLL to convert into MCLK_INT
• Use internal RCO as MCLK. This mode can support HP detection and I 2C communication. DAC playback and headphone impedance measurement functions are not supported. Figure 4-9. System Clocking—Crystal Mode Figure 4-10. System Clocking—External MCLK Mode If XTAL is used, the supported crystal characteristics and frequencies are listed in Table 3-14. Based on the crystal selection, XTAL_IBIAS must be set properly before powering up. The XTAL_IBIAS information can be found in Section 5.3. PDN_XTAL is cleared to start the crystal oscillator. PDN_XTAL is set to power down the crystal oscillator. The XTAL_READY_INT and XTAL_ERROR_INT status bits indicate the status of crystal operation after power-up. At tXTAL_pup after the crystal oscillator is powered up, if the crystal is started successfully and ready to be used, XTAL_READY_INT is set; if the crystal is started unsuccessfully, XTAL_ERROR_INT is set. The two bits are mutually exclusive when set. Both status bits have corresponding interrupt status bits and interrupt mask bits. To be informed on the crystal status at tXTAL_ pup after power-up, unmask both interrupts before powering up the crystal. XTAL XTI/MCLK XTO External MCLK System Clock XTI/MCLK XTO

When the MCLK is supplied to the device through the XTI/MCLK pin, it must comply with the phase-noise mask shown in Fig. 4-11. Its frequency must be one of the nominal MCLK_INT frequencies (22.5792 or 24.576 MHz), and its duty cycle must be between 45% to 55%. Figure 4-11. MCLK Phase Noise Mask Without PLL When the PLL reference clock is supplied to the device through the XTI/MCLK pin, it must comply with the phase-noise mask shown in Fig. 4-12. Figure 4-12. MCLK Phase Noise Mask With PLL

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4.6 Clock Output and Fractional-N PLL

Further restrictions are listed in Table 4-3. Figure 4-13. MCLK Source Switching A source to MCLK_INT, either the XTAL (or external MCLK), PLL, or the RCO, must be provided as long as CS43198 is operating; otherwise, the CS43198 will enter a non-responsive state. The only way to recover from this non-responsive state is either through a reset or POR event. Switching MCLK sources during DAC operation causes audible artifacts, but does not put the device in an unrecoverable state. In an MCLK source-switching event, the destined clock source must be present and ready before switching occurs. After POR or reset event, RCO is selected as default source of MCLK_INT.

4.5.1.1 Internal RC Oscillator

As described in Section 4.5.1, the CS43198 includes an internal RC oscillator that can be used as a clock source for peripheral circuit such as control port or charge pump. The CS43198 clock output can be used as a master clock for other data-conversion or signal-processing components, which requires synchronous timing to the CS43198. Table 4-3. MCLK Source Restrictions Internal MCLK Source MCLK_SRC_SEL MCLK _INT Restrictions Direct MCLK or XTAL 00 0 • Nominal MCLK_INT frequency = 24.576 MHz

• All specified CLKOUT frequencies ( generated by PLL or XTAL) are supported
• CLKOUT outputs (/2, /3, /4, /8 divide) optionally 1 • Nominal MCLK_INT frequency = 22.5792 MHz
• All specified CLKOUT frequencies ( generated by PLL or XTAL) are supported
• CLKOUT outputs (/2, /3, /4, /8 divide) optionally PLL 01 0 • Nominal MCLK_INT frequency = 24.576 MHz
• PDN_PLL = 0 and PLL properly configured to generate 24.576 MHz given reference input frequency on XTI/MCLK pin
• Only MCLK_INT on CLKOUT is supported on CLKOUT pin
• CLKOUT outputs (/2, /3, /4, /8 divide) optionally 1 • Nominal MCLK_INT frequency = 22.5792MHz
• PDN_PLL = 0 and PLL properly configured to generate 22.5792 MHz given reference input frequency on XTI/MCLK pin
• Only MCLK_INT on CLKOUT is supported on CLKOUT pin
• CLKOUT outputs (/2, /3, /4, /8 divide) optionally Internal PLL XTI/MCLK Internal MCLK CLKOUT÷ CLKOUT_SEL p. 101 PDN_PLL p. 98 CLKOUT_DIV p. 101 MCLK_INT p. 97

The CLKOUT output is enabled by clearing PDN_CLKOUT. Figure 4-14. CLKOUT Source Selection Once enabled, CLKOUT is generated either from the internal crystal oscillator output (when used) or from the integrated fractional-N PLL; it can be selected by CLKOUT_SEL. CLKOUT_DIV can be used to set /2, /3, /4, or /8 to divide the selected clock source to targeted frequency.

4.6.1 Fractional-N PLL

The CS43198 has an integrated fractional-N PLL to support the clocking requirements of various applications. This PLL can be enabled or disabled by clearing or setting PDN_PLL bit. The input reference clock for the PLL is signal on XTI/ MCLK pin (crystal-generated or external-feed).

4.6.2 Fractional-N PLL Internal Interface

Fig. 4-15 shows how PLL operation can be configured. Figure 4-15. Fractional-N PLL Use Eq. 4-1 to calculate the PLL output frequency. Equation 4-1. PLL Output Frequency Equation PLL_REF source must be in range below: PLL_REF Source PLL_REF_PREDIV Input Minimum Maximum MCLK/XIN pin 9.6 MHz 26 MHz XTI/MCLK PLL_OUT CLKOUT÷ CLKOUT_DIV CLKOUT_SEL p. 101 PLLXTI/MCLK PLL_OUT PLL_DIV_INT p. 99 PLL_DIV_FRAC_0 p. 99 PLL_DIV_FRAC_1 p. 99 PLL_DIV_FRAC_2 p. 99 PLL_MODE p. 100 PLL_REF_ PREDIV p. 100 PDN_PLL p. 98 PLL_START p. 99 PLL_OUT_ DIV p. 100 PLL_OUT = PLL_REF PLL_REF_PREDIV × PLL_OUT_DIV PLL_DIV_INT + PLL_DIV_FRAC or 1, selected by PLL_Mode ×500 512

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Table 4-4 lists common settings with XTAL input as PLL reference. Table 4-5 lists common settings with MCLK input as PLL reference. Note that in Table 4-4 and Table 4-5:

• The PLL_OUT_DIV value must be even.
• PLL_OUT frequencies are at 22.5792 or 24.576 MHz. CL KOUT frequencies can be obtained by configuring the CLK_OUT_DIV value:
• PLL_ERROR_INT constantly monitors the PLL error stat us after PLL_START is set, assuming the PLL reference input is stable and accurate.

4.6.2.1 Powering Up the PLLs

To power up the PLL, use the following default sequence: 1. Enable the PLL by clearing PDN_PLL. 2. Configure PLL_REF_PREDIV. 3. Configure PLL_OUT_DIV. 4. Configure the three fractional factor registers, PLL_DIV_FRAC. 5. Set the integer factor, PLL_DI V_INT, to the desired value. 6. Configure PLL_MODE and PLL_CAL_RATIO. Table 4-4. PLL Configuration for Typical Use Case (XTAL as the PLL Reference) XTAL (MHz) PLL_REF_PREDIV (Divide-by Value) PLL_REF_PREDIV (Setting) PLL_ DIV_INT PLL_DIV_FRAC PLL_OUT_DIV PLL_ MODE PLL OUT (MHz) PLL_CAL_ RATIO 22.5792 8 0x3 0x44 0x06 F700 0x08 0 24.576 139 24.576 8 0x3 0x49 0x80 0000 0x0A 1 22.5792 118 Table 4-5. PLL Configuration for Typical Use Case (XIN/MCLK as the PLL Reference) XIN/MCLK (MHz) PLL_REF_PREDIV (Divide-by Value) PLL_REF_PREDIV (Setting) PLL_DIV_INT PLL_DIV_FRAC PLL_OUT_DIV PLL_ MODE PLL_OUT (MHz) PLL_CAL_ RATIO 11.2896 4 0x2 0x40 0x00 0000 0x08 1 22.5792 128 40 x 2 0x44 0x06 F700 0x08 0 24.576 139 22.5792 8 0x3 0x44 0x06 F700 0x08 0 24.576 139 12.000 4 0x2 0x49 0x80 0000 0x0A 0 22.5792 120 40 x 2 0x40 0x00 0000 0x08 0 24.576 131 24.000 8 0x3 0x49 0x80 0000 0x0A 0 22.5792 120 8 0x3 0x40 0x00 0000 0x08 0 24.576 131 12.288 4 0x2 0x49 0x80 0000 0x0A 1 22.5792 118 40 x 2 0x40 0x00 0000 0x08 1 24.576 128 24.576 8 0x3 0x49 0x80 0000 0x0A 1 22.5792 118 9.600 4 0x2 0x49 0x80 0000 0x08 0 22.5792 151 40 x 2 0x50 0x00 0000 0x08 0 24.576 164 19.200 8 0x3 0x49 0x80 0000 0x08 0 22.5792 151 8 0x3 0x50 0x00 0000 0x08 0 24.576 164 13.000 4 0x2 0x45 0x79 7680 0x0A 1 22.5792 111 40 x 2 0x3C 0x7E A940 0x08 1 24.576 121 26.000 8 0x3 0x45 0x79 7680 0x0A 1 22.5792 111 8 0x3 0x3C 0x7E A940 0x08 1 24.576 121 PLL_OUT CLK_OUT_DIV (2) CLK_OUT_DIV (3) CLK_OUT_DIV (4) CLK_OUT_DIV (8)

4.7 Filtering Options

1. After properly unmasked (cl earing PLL_READY_INT_MASK and PLL_ERROR_INT_MASK), PLL_READY_INT, and PLL_ERROR_INT are used to monitor if PLL has been successfully started. 8. Turn on the PLL by setting PLL_START.

4.6.2.2 Powering Down the PLL

1. Clear PLL_START to stop the PLL operation. 2. For further power saving, set PDN_PLL to disable the PLL block.

To accommodate the increasingly complex requirements of digital audio systems, the CS43198 incorporates selectable filters in different playback modes. For PCM/TDM mode, the following interpolation filtering options can be selected:

• Fast roll-off and slow roll-off interpolation filter options.
• In each option above, both low-latency and normal ph ase-compensation filtering options can be used.
• Nonoversampling (NOS) mode is provided, which minimizes th e internal digital processing. Once NOS mode is set, the settings on the above two options are ignored. The combination of the options results in five different filter combinations. The specifications for each filter can be found in Table 3-7, and response plots can be found in Section 9. These filters have been designed to accommodate a variety of musical tastes and styles. The PCM filter option register (see Section 7.5.2) is used to select filter options. When in octuple-speed mode, the filter options above are not available and the internal digital processing is minimized. See the specification in Table 3-7 for filter characteristics. The DSD processor mode uses a decimation-free DSD processing technique that allows for features such as matched PCM level output, DSD volume control, and 50-kHz on-chip filter. In Direct DSD Mode, the DSD stream directly controls the DAC elements for minimal processing. Since there is no 50-kHz on-chip filter in the signal path, external filter designs must be compliant with SACD requirements.

4.8 Audio Serial Port (ASP)

The independent, highly configurable ASPs and auxiliary serial ports (XSPs) communicate audio data from other system devices, such as applications processors. Both ports can be configured to support common audio interfaces, TDM/I2S and left-justified (LJ). ASP supports both PCM and DoP stream playback. XSP can only support DoP stream playback. For DAC playback, only one port needs to be enabled. Both ports are enabled only in specific application, such as PCM notification mixing with DSD/DoP content. Details regarding this application setup can be found in Section 4.11. In this section, the reference to both ports is generalized as “xSP” to explain the common settings between the two ports.

4.8.1 Master and Slave Timing

Each serial port can operate as either the master of timing or as a slave to another device’s timing. If xSP_M/S is set, the serial port acts as a clock master. If xSP_M/S is cleared, the serial port acts as a clock slave.

• In Master Mode, xSP_SCLK and xSP_LRCK ar e outputs derived from the internal MCLK.
• In Slave Mode, xSP_SCLK and xSP_LRCK are inputs. Al though the CS43198 does not generate the interface timings in Slave Mode, the expected LRCK and SCLK format must be programmed in the same way as in Master Mode (see Table 3-18).
• In both modes, the serial port sample rate register (x SP_SPRATE) must be set per audio content before enabling the serial port.

40 DS1156F1

• When using ASP for PCM playback, the au dio serial port sample bit size register (ASP_SPSIZE) must be set per audio content before enabling the ASP.
• When using XSP or ASP for DoP playba ck, the serial port sample bit size register (XSP_SPSIZE or ASP_SPSIZE) must be set per audio content before enabling the XSP or ASP. Note that the XSP_SPSIZE or ASP_SPSIZE must reflect the length of both DSD marker bits together with audio bits.

4.8.2 Power-Up, Power-Down, and Tristate

The xSP has separate power-down and tristate controls (PDN_xSP and xSP_3ST) for input data paths, which minimizes power consumption if the input port is not used. xSP master/slave operation is controlled only by the xSP_M/S setting, irrespective of the PDN_xSP and xSP_3ST settings.

• PDN_xSP. If a serial port’s SDIN functionality is not required, xSP can be powered down by setting PDN_xSP, which powers down the input data path and clocks of the serial port.
• xSP_3ST. In Master Mode, setting xSP_3ST tri-states the SCLK and LRCK clocks. Before setting an xSP_3ST bit, the associated serial port must be powered down and must not be powered up until the xSP_3ST bit is cleared. In Slave Mode, xSP_3ST does not affect the functionality of SCLK and LRCK clocks, given both pins are input pins.

4.8.3 I/O

The ASP port is associated with SDIN1, SCLK1, and LRCK1. The XSP port is associated with SDIN2, SCLK2, and LRCK2, which are shared with DSD interface:

• SCLKx—Serial data shift clock
• LRCKx—Toggles at extern al sample rate (Fsext). LRCK (left/right, I²S) identifies each channel’s (left or right) location in the data word when I²S format is used. LRCK identifies the start of each serialized data word. FSYNC (frame sync clock, TDM) identifies the start of each TDM frame.
• SDINx—Serial data input

4.8.4 High-Impedance Mode

Serial ports can be placed on a clock bus that allows multiple masters without the need for external buffers. xSP_3ST bits place the internal buffers for the respective serial-port interface signals in a high-impedance state, allowing another device to transmit clocks without bus contention. When the CS43198 serial port is a timing slave, its SCLK and LRCK I/Os are always inputs and are thus unaffected by the xSP_3ST control. Fig. 4-16 shows the busing for CS43198 master timing serial-port use case. Figure 4-16. Serial Port Busing when Master Timed

4.8.5 Clock Generation and Control

The CS43198 has a flexible serial port clock generation subsystem that allows independent clocking of the two serial ports. When operating as a master port, the serial port provides a bit clock (xSP_SCLK) and a left-right/frame sync signal (xSP_ LRCK/FSYNC). Note: x = XSP or ASP Transmitting Device #1 (DAC) Transmitting Device #2 x_ SCLK, x_ LRCK x_3ST Receiving Device

Fig. 4-17 and Fig. 4-18 show the serial port clocking architecture. Figure 4-17. xSP SCLK and MCLK Architecture As shown in Fig. 4-17, the master-mode SCLK output for each serial port is derived from the internal MCLK. The SCLK output can be configured to various frequencies to accommodate many sample rates, sample sizes, and channel counts. The SCLK is output of a fractional divide from the internal MCLK input, where N is the numerator and M is the denominator. Note: Depending on the chosen fractional divide configuration, the SCLK duty cycle can vary by one MCLK period. Input and output SCLK polarity controls (xSP_SCPOL_IN and xSP_SCPOL_OUT) are also available. As shown in Fig. 4-17, if Master Mode is used, both polarity controls affect the SCLK used by the serial port module. For example, both polarity controls must be set (xSP_SCPOL_IN = xSP_SCPOL_OUT = 1) to invert the SCLK output and output data on the falling edge. In typical use cases, the values of xSP_SCPOL_IN equals xSP_SCPOL_OUT in each serial port. See Fig. 4-20 for example waveforms showing the various settings of the SCLK polarity controls. Likewise, input and output LRCK polarity controls (xSP_LCPOL_IN and xSP_LCPOL_OUT) are available. In Master Mode, both LRCK polarity controls affect the LRCK used by the serial-port module as shown in Fig. 4-18. In typical-use cases, the value of xSP_LCPOL_IN equals xSP_LCPOL_OUT in each serial port. Figure 4-18. xSP LRCK Architecture As shown in Fig. 4-19, xSP_LCPR determines the LRCK/FSYNC period, in units of SCLK periods. The LRCK period effectively sets the length of the frame and the number of SCLK periods per Fs. Frame length may be programmed in single SCLK period multiples from a minimum of 16 SCLK:Fs up to 1536 SCLK:Fs. N M Internal MCLK IN N[13:0] M[13:0] SCLK To LRCK SCLK to Serial Port ASP_SCPOL_IN p. 103/ XSP_SCPOL_IN p. 105 ASP_M/SB p. 103/ XSP_M/SB p. 105 ASP_SCPOL_OUT p. 103/ XSP_SCPOL_OUT p. 105 ASP_M_LSB p. 101/XSP_M_LSB p. 104 ASP_M_MSB p. 102/XSP_M_MSB p. 104 ASP_N_LSB p. 101/XSP_N_LSB p. 103 ASP_N_MSB p. 101/XSP_N_MSB p. 104 LRCK to Serial Port ASP_LRCK/FSYNC IN PER OUT HI LR GEN EN From SCLK x_M/S = 1 (master) & PDN_x = 0 (enabled ) 5050 DELAY ASP_5050 p. 103/XSP_5050 p. 105 ASP_FSD p. 103/XSP_FSD p. 106 ASP_LCPOL_IN p. 103/ XSP_LCPOL_IN p. 105 ASP_M/SB p. 103/ XSP_M/SB p. 105 ASP_LCPOL_OUT p. 103/ XSP_LCPOL_OUT p. 105 ASP_LCHI_LSB p. 102/XSP_LCHI_LSB p. 104 ASP_LCHI_MSB p. 102/XSP_LCHI_MSB p. 104 ASP_LCPR_LSB p. 102/XSP_LCPR_LSB p. 105 ASP_LCPR_MSB p. 102/XSP_LCPR_MSB p. 105

42 DS1156F1

The LRCK-high width (xSP_LCHI) controls the number of SCLK periods for which the LRCK signal is held high during each frame. Like the LRCK period, the LRCK-high width is programmable in single SCLK periods, from a minimum of one period to a maximum of the LRCK period minus one (and an absolute maximum of 768 SCLK periods). That is, LRCK-high width must be less than the LRCK period. Figure 4-19. xSP LRCK Period, High Width As shown in Fig. 4-20, if Serial Port 50/50 Mode is enabled (xSP_5050 = 1), the LRCK high duration must be programmed to the LRCK period divided by two (rounded down to the nearest integer when the LRCK period is odd). When the serial port is in 50/50 Mode, setting the LRCK high duration to a value other than half of the period results in erroneous operation. Figure 4-20. xSP_LRCK Period, High Width, 50/50 Mode SCLK LRCK Falling Edge Rising Edge xSP _LCPR xSP_LCHI ... ... ... ... ... ... SCLK LRCK Falling Edge Rising Edge xSP_LCPR xSP _LCHI SCLK LRCK Falling Edge Rising Edge xSP_LCPR xSP _LCHI Even xSP _LCPR Odd xSP _LCPR xSP _LCPR count clock is absent xSP_LCHI ... ... ... ... ... ... ... ... ... ... ... ...

Fig. 4-21 shows how LRCK frame start delay (xSP_FSD) controls the number of SCLK periods delay from the LRCK synchronization edge to the start of frame data. Figure 4-21. LRCK FSD and SCLK Polarity Example Diagram Table 4-6. Serial Port Clock Generation—Supported Configurations for 32 bits and 2 Channels Frequency (MHz) LRCK/FSYNC Rate (kHz) SCLKs per LRCK Frame xSP_N[15:0] xSP_M[15:0]xSP_LCPR + 1 xSP_LCPR[10:0] 22.5792 32.000 64 63 40 441 44.100 64 63 1 8 48.000 64 63 20 147 88.200 64 63 1 4 96.000 64 63 40 147 176.400 64 63 1 2 192.000 64 63 80 147 352.800 64 63 1 1 24.576 32.000 64 63 1 12 44.100 64 63 147 1280 48.000 64 63 1 8 88.200 64 63 147 640 96.000 64 63 1 4 176.400 64 63 147 320 192.000 64 63 1 2 352.800 64 63 147 160 384.000 64 63 1 1 LRCK Channel location (xSP_RX_CHn) = 0 FSD = 000 FSD = 001 FSD = 010 N-1N-2N-3N-4N-5 FSD = 011 FSD = 100 0.5 1.5 2.5 FSD = 101 End of frame 2 ... ... ... ... ... ... ... 3456789 ... ... Channel location (xSP_RX_CHn) = 0 N-1N-2N-3N-4N-5 End of frame 2 ...3456789 ... Channel location (xSP_RX_CHn) = 0 N-1N-2N-3N-4N-5 End of frame 2 ...3456789 Channel location (xSP_RX_CHn) = 0 N-1N-2N-3N-4N-5 End of frame 2 ...3456789 ...SCLK SDIN SDIN SCLK SDIN SCLK SCLK SDIN SCPOL _IN = 0 SCPOL_OUT = 0 SCPOL _IN = 1 SCPOL_OUT = 0 SCPOL _IN = 0 SCPOL_OUT = 1 SCPOL _IN = 1 SCPOL_OUT = 1

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4.8.6 Channel Location and Size

Each serial-port channel has a programmable location offset (xSP_RX_CHn). Channel location is programmable in single SCLK period resolution. When set to the minimum location offset, the channel transmits or receives on the first SCLK period of a new frame. Channel size is programmable in byte resolution from 8 to 32 bits using xSP_RX_CHn_RES. Channel size and location must not be programmed such that channel data extends beyond the frame boundary. Size and location must not be programmed such that data from a given SCLK period is assigned to more than one channel. The example in Fig. 4-22 shows channel location and size. Figure 4-22. Example Channel Location and Size

4.8.7 Frame Start Phase

The serial port can start a frame when xSP_LRCK/FSYNC is high or low, depending on xSP_STP. In typical TDM use cases, a frame starts when FSYNC is high (xSP_STP = 1). Table 4-7. Serial Port Clock Generation—Supported Configurations for 32-bits and 4-Channels Frequency (MHz) LRCK/FSYNC Rate (kHz) SCLKs per LRCK Frame xSP_N[15:0] xSP_M[15:0]xSP_LCPR + 1 xSP_LCPR[10:0] 22.5792 32.000 128 127 80 441 44.100 128 127 1 4 48.000 128 127 40 147 88.200 128 127 1 2 96.000 128 127 80 147 176.400 128 127 1 1 24.576 32.000 128 127 1 6 44.100 128 127 147 640 48.000 128 127 1 4 88.200 128 127 147 320 96.000 128 127 1 2 176.400 128 127 147 160 192.000 128 127 1 1 Slot 0 SCLK Slot 1 Slot 30 Slot 31 247 248 255 70 7 07 0 First SCLK latching edge of a new frame after frame sync Traditional ‘Slot’ N 23 Ch. M MSB Ch. M LSB 0 15 Ch. M MSB Ch. M LSB 0 7 Ch. M MSB 0Channel Size = 00 Channel Size = 01 Channel Size = 10 Channel Location (xSP_RX_CHn) = N TDM Channel M Data Don’t Care 31 Ch. M MSB Ch. M LSB 0Channel Size = 11 Don’t Care Don’t Care

• If xSP_STP = 0, the frame begins when LRCK/FSYNC transitions from high to low. See Fig. 4-23 for an example in 50/50 mode. The TDM Mode behaves similarly. Figure 4-23. Example 50/50 Mode (ASP_STP = 0)
• If xSP_STP = 1, the frame begins when LRCK/FSYNC transitions from low to high. See Fig. 4-24 for an example in 50/50 mode. TDM mode is similar. Figure 4-24. Example 50/50 Mode (ASP_STP = 1) 4.8.8 50/50 Mode In typical two-channel I2S operation (50/50 Mode, xSP_5050 = 1), the LRCK duty cycle is 50%, and each channel is transferred during one of the two LRCK phases. In this mode, each serial port channel can be independently programmed to output when LRCK/FSYNC is high or low; this is called the channel-active phase. If the active-phase control bit (xSP_RX_CHn_AP) is set, the respective channel is output when LRCK/FSYNC is high. If xSP_RX_CHn_AP is cleared, the respective channel is output if LRCK/FSYNC is low. Examples of each setting of xSP_ RX_CHn_AP are shown in Fig. 4-23 and Fig. 4-24. In 50/50 Mode, the channel location (see Section 4.8.6) is calculated within the channel-active phase. If there are N bits in a frame, the location of the last bit of each active phase is equal to (N/2) – 1. Note: If xSP_5050 is set, xSP_LCHI must be programmed to half of xSP_LCPR for a 50% duty cycle. Also, only two channels can be enabled for the corresponding serial port. LRCK ... ... xSP _STP = 0 Channel y Channel z xSP _CHy_LOC = 0, xSP_CHy_AP = 0 xSP _CHz_LOC = 0, xSP_CHz_AP = 1 SDIN Note: This diagram assumes xSP _FSD = 0. Channel location index (xSP_CHy_LOC, xSP_CHz_LOC) 0 1 2 N/ 2 N/ 2 N/ 2 -3... 0 1 2 N/ 2 N/ 2 N/ 2 -3... Next Sample Previous Sample LRCK Next Sample Previous Sample SDIN ... ...xSP_STP = 1 Channel location index (xSP _CHy_LOC , xSP_CHz _LOC) 0 1 2 N/2 N/2 N/2 -3... 0 1 2 N/2 N/2 N/2 -3... Channel z xSP _CHz_LOC = 0, xSP_CHz_AP = 1 Channel y xSP _CHy_LOC = 0, xSP_CHy_AP = 0 Note: This diagram assumes xSP _FSD = 0.

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4.8.9 Serial Port Status

Each serial port has five status bits. Each bit is sticky and must be read to be cleared. The status bits have associated mask bits to mask setting the INT pin when the status bit sets. A brief description of each status bit is shown in Table 4-8.

4.8.10 Serial Port Clock Pin Status

There are various control bits available that affect the output state of the serial port clock and data pins. Table 4-9 summarizes the possible states depending on these bit settings.

4.8.11 DoP (DSD over PCM) Mode

DoP is a protocol for packetizing DSD data into a PCM frame for transmission over an existing I2S interface. The ASP or XSP can accept DSD data in DoP format. To use the DoP interface in Slave Mode, if MCLK_INT = 22.5792 MHz, the DoP interface clocks are required to be synchronous to MCLK_INT. Table 4-8. Serial Port Status Name Description Register Reference Request Overload Set when too many input buffers request processing at the same time. If all channel size and location registers are properly configured to non-overlapping values, this error status must never set. ASP_OVFL_INT p. 116 XSP_OVFL_INT p. 116 LRCK Error Logical OR of LRCK early and LRCK late (see below). ASP_ERROR_INT p. 116 XSP_ERROR_INT p. 116 LRCK Early Set when the number of SCLK periods pe r LRCK phase (high or low) is less than the expected count as determined by xSP_LCPR and xSP_LCHI. Note: The Rx LRCK early interrupt status is set during the first receive LRCK early event. Subsequent receive LRCK early events are not indicated until after valid LRCK transitions are detected. ASP_EARLY_INT p. 116 XSP_EARLY_INT p. 116 LRCK Late Set when the number of SCLK periods per LRCK phase (high or low) is greater than the expected count as determined by xSP_LCPR and xSP_LCHI. ASP_LATE_INT p. 116 XSP_LATE_INT p. 116 No LRCK Set when the number of SCLK periods counted exceeds twice the value of LRCK period (xSP_LCPR) without an LRCK edge. The Tx No LRCK interrupt status is set during the first instance of a no transmit LRCK condition. Subsequent no transmit LRCK conditions are not indicated until after valid LRCK transitions are detected. ASP_NOLRCK_INT p. 116 XSP_NOLRCK_INT p. 116 Table 4-9. xSP_SCLK and xSP_LRCK/FSYNC Pin States xSP_3ST xSP_M/S PDN_xSP xSP_SCLK Pin State xSP_LRCK/FSYNC Pin State 1 x x Hi-Z with weak pull-down Hi-Z with weak pull-down 0 0 x Hi-Z with weak pull-down Hi-Z with weak pull-down 0 1 0 Active Active 0 1 1 Inactive Inactive 1.If xSP_LCPOL_OUT is set, xSP_LRCK/FSYNC inactive output is high. If xSP_LCPOL_OUT is cleared, xSP_LRCK/FSYNC inactive output is low.

4.9 DSD Interface

Each sample is 24 bits, as shown in Fig. 4-25, where the 8 most significant bits are used for the DSD marker and alternate with each sample between 0x05/0xFA. Each channel within a sample contains the same marker. The remaining 16 lower bits are then used for the DSD data, with the first or oldest bit in Slot t0. Figure 4-25. DoP Data Sample and Stereo Stream Example Each PCM frame is assigned to a specific channel (left or right), and when used for DSD streaming, each PCM frame contains only DSD data corresponding to its assigned channel. The CS43198 unpacks the received DoP data and reforms it into a DSD stream to feed the internal DSD data paths. It includes the following features:

• 24 bits per PCM data sample
• I 2S format is supported
• DoP data is unpacketed internally for DSD playback
• Clock Master and Slave Mode
• Up to 128•Fs DSD stream — Accepts a 64•Fs DSD stream with LRCK@176.4 kHz — Accepts a 128•Fs DSD stream with LRCK@352.8 kHz To enable DoP interface on the ASP to take in DSD source: 1. Configure the ASP per clocking/format required by DoP content. 2. Configure DSD_SPEED per DoP content. Set DSD_PRC_SRC = 10 and DSD_EN = 1.

The DSD interface is enabled or disabled by PDN_DSDIF bit. When cleared, the DSD data interface is enabled. When using this interface, the DSD interface clock can be mastered by the CS43198 (DSD_M/SB=1). If set to Master Mode, DSDCLK toggles if both PDN_DSDIF and XSP_3ST bits are cleared, and DSD_EN is set. If the DSD interface clock is slaved (DSD_M/SB=0), when MCLK_INT is set as 22.5792 MHz, DSDCLK is required to be synchronous to MCLK_INT. The DSDCLK can be derived by either:

• Exporting 1/2, 1/4, or 1/8 the frequency of the CS43198 crystal to CLKOUT, or
• Sourcing MCLK_INT and DSDCLK from the same external clock source DSD Marker (8 MSB) dm7 dm6 dm5 dm4 dm3 dm2 dm1 dm0 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15

16 DSD Audio bits for one channel (oldest bit = t0)

LRCK (I2S) SDATA (DoP ) 0x05 Data Stream Example of Stereo DoP DoP Data Sample

48 DS1156F1

The DSD_EN bit, when set, is used to configure the device for processing DSD sources. DSD_PRC_SRC configures the DSD interface used for feeding into the DSD processor. DSD_SPEED specifies if a 64•Fs, 128•Fs, or 256•Fs DSD stream is provided. If PDN_DSDIF = 0 and DSD_M/SB = 1, DSD_SPEED determines the DSDCLK clock frequency generated. When configuring the DSD interface, follow these steps: 1. Configure the DSD_M/SB, DSD_ SPEED, DSD_PRC_SRC, and XSP_3ST. 2. Release PDN_DSDIF. 3. Enable DSD_EN. The DIR_DSD bit selects between two proprietary methods for DSD-to-analog conversion. The first method (DIR_ DSD = 0) uses a decimation-free DSD processing technique that allows for features such as matched PCM level output, DC offset removal, DSD volume control, and 50 kHz on-chip filter. The second method (DIR_DSD = 1) sends the DSD data directly to the on-chip digital-to-analog conversion interface (without the above mentioned features). In DIR_DSD = 1 setting, the user has selection of 2 gain settings for 64•Fs and 128•Fs modes. For 64•Fs mode low-gain settings, the user can select to magnitude compensate for the analog filter response. Refer to Section 7.4.8 for details on the filter configuration control register. The DSD_PM_EN bit selects phase modulation (data plus data inverted) as the style of data input. In this mode, the DSD_ PM_SEL bit selects whether a 2x or 1x data rate clock is used for phase-modulated data (see Fig. 4-26). Use of phase modulation mode may not directly affect the performance of the CS43198, but may lower the sensitivity of other board-level components to the DSD data signals. Note that phase modulation mode is supported only for DSD 64•Fs and DSD 128•Fs data rates. If the 2x data rate mode is used, DSD_INV_B and DSD_INV_A need to be set before the mode is enabled. After the 2x data rate mode is disabled, DSD_INV_B and DSD_INV_A need to be cleared appropriately. The CS43198 can detect overmodulation errors in the DSD data that do not comply to the SACD specification. Setting INV_DSD_DET enables detection of overmodulation errors. This condition is reported through the DSD_INVAL_A_INT and DSD_INVAL_B_INT status bits. Overmodulated DSD data is converted as received without intervention, but performance at these levels cannot be guaranteed. Setting STA_DSD_DET allows the CS43198 to mute a DSD stream that is stuck at 1 or 0. This condition is reported through the DSD_STUCK_INT status bit. See Section 7.6.4 for descriptions of the DSD error reporting bits. More information for these register bits can be found in Section 7.

4.10 DSD and PCM Mixing

The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index) at full-rated performance. When 0 dB-SACD and 0 dBFS PCM need to be level matched, DSD_ZERODB must be set. In this mode, signals of +3-dB SACD may be applied for brief periods of time; however, performance at these levels is not guaranteed. If sustained levels approaching +3-dB SACD levels are required, DSD_ZERODB must be cleared, which matches a +3-dB SACD output level. DSD_ZERODB does not affect volume in Direct DSD mode. Figure 4-26. DSD Phase Modulation Mode Diagram For mobile application, the CS43198 provides a feature for mixing in PCM notification during DSD playback, with the setup in Table 4-10. It is assumed that the DSD path has been properly configured for DSD playback. Note that the mixing feature is not applicable for Direct DSD playback. During normal DSD playback, the ASP can be shut down. At the PCM notification event, the ASP must be properly configured to receive PCM samples at 44.1 kHz. After the ASP subclocks are running, set MIX_PCM_PREP to indicate to the CS43198 that the PCM mixing event is imminent. After 1.6 ms, MIX_PCM_DSD can be safely set to initiate the mixing process. After the PCM notification mixing is complete, clear both MIX_PCM_DSD and MIX_PCM_PREP at the same time. If desired, the ASP can be shut down to save power. Table 4-10. Mixing Configurations Supported by the CS43198 PCM Input Configuration DSD Input Configuration I2S or TDM on ASP 44.1 kHz Master DSD on DSD IF 2.8224, 5.6448, or

11.2896 MHz on

1.The ASP/XSP subclocks and DSDCLK are required to be synchronous. Slave 1 Master DoP on XSP 176.4 or 352.8 kHz Master Slave 1 Slave 1 DSDA, DSDB D1D0 D2 DSDCLK DSD Normal Mode (128•Fs or 256•Fs) D1 D1 D2D0 DSDCLK = BCKD DSDA, DSDB (64•Fs or 128•Fs) DSD Phase Modulation Mode (64•Fs, 128•Fs, or 256•Fs) DSDCLK = BCKA (DSD_PM_EN = 0) (DSD_PM_EN = 1) (DSD_PM_SEL = 0) (DSD_PM_SEL = 1)

50 DS1156F1

4.11 Standard Interrupts

When mixing, use both PCM and DSD volume controls to attenuate the signal content on both paths (e.g., at least –6-dB attenuation on each) to avoid clipping on the mixing product. Use PCM_VOLUMEx to adjust the PCM path and DSD_ VOLUMEx to adjust the DSD path. All the signal path settings apply to both path’s individual settings. Figure 4-27. PCM and DSD Mixing Signal Flow The interrupt output pin, INT, is used to signal the occurrence of events within the device’s interrupt status registers. Events can be masked individually by setting corresponding bits in the interrupt mask registers. Table 4-11 lists interrupt status and mask registers. The configuration of mask bits determines which events cause the immediate assertion of INT:

• When an unmasked interrupt status event is detected, the status bit is set, and INT is asserted.
• When a masked interrupt status event is detecte d, the interrupt status bit is set, but INT is not affected. Once INT is asserted, it remains asserted until all status bits that are unmasked and set have been read. Interrupt status bits are sticky and read-to-clear. Once set, they remain set until the register is read and the associated interrupt condition is not present. If a condition is still present and the status bit is read, although INT is deasserted, the status bit remains set. To clear status bits set due to the initiation of a block, all interrupt status bits must be read after the corresponding module is enabled and before normal operation begins. Otherwise, unmasking these previously set status bits causes assertion of INT. Interrupt source bits are set when edge-detect interrupts is detected, and they remain set until the register is read and the condition that caused the bit to assert is no longer present. Fig. 4-28 shows sticky-bit behavior. Figure 4-28. Example of Rising-Edge-Sensitive, Sticky, Interrupt-Status-Bit Behavior Table 4-11. Interrupts Events and Register Bit Fields Interrupt Register Bit Fi eld Interrupt Mask Field DAC overflow DAC_OVFL_INT DAC_OVFL__INT_MASK HP unplug detect HPDETECT_UNPLUG _INT HPDETECT_UNPLUG_INT_MASK HP plug detect HPDETECT_PLUG_INT HPDETECT_PLUG_INT_MASK XTAL is ready XTAL_READY _INT XTAL_READY_INT_MASK XTAL error detected XTAL_ERR OR_INT XTAL_ERROR_INT_MASK DSD Processor Interpolation Filter & Volume Control DoP to DSD Engine MU X ASP XSP/ DSD Audio Interface Multibit Modulator PCM DSD MIX_PCM_PREP p. 109 MIX_PCM_DSD p. 109 PCM_VOLUME_B p. 112 PCM_VOLUME_A p. 112 DSD_VOLUME_B p. 107 DSD_VOLUME_A p. 108 Raw signal feeding status register bit Status register bit ___ INT Register read signal Status read value Read Source 0 11 0 001 Poll cycle Interrupt service Extra read for present state Interrupt service Extra read for present state Poll cycle Poll cycle

4.12 Control Port Operation

The control port is used to access control registers and on-chip memory locations, allowing the device to be configured for desired operational modes and formats. Control port operation may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, control port pins must remain static if no operation is required. The control port operates using a I2C interface with the CS43198 acting as a slave device. Device communication must not begin until tPUD (refer to Table 3-20) after power conditions are ready and RESET is released.

4.12.1 I 2C Control Port Operation

The I2C control port operates completely asynchronously with the audio sample rates. However, to avoid interference problems, the I2C control-port pins must remain static if no operation is required. The control-port uses the I2C interface, with the chip acting as a slave device. The I2C control port can operate in the following modes:

• Standard Mode (SM), with a bit rate of up to 100 kbit/s
• Fast Mode (FM), with a bit rate of up to 400 kbit/s
• Fast Mode Plus (FM+), with a bit rate of up to 1 Mbit/s SDA is a bidirectional data line. Data is clocked into and out of the CS43198 by the SCL clock. Fig. 4-29, Fig. 4-30, and Fig. 4-31 show signal timings for read and write cycles. A Start condition is defined as a falling transition of SDA while SCL is high. A stop condition is defined as a rising transition of SDA while SCL is high. All other transitions of SDA must occur while SCL is low. Note that when HP_IN_LP is set, only SM and FM modes are supported. To configure the last two bits of I2C address, CS43198 detects the ADR resistor connection type and measures the resistance upon a device power up (POR event) or after a hardware reset event (RESET deasserted). Based on the detected resistance, the I2C address is latched and cannot be changed until the next hardware reset event. The I2C address configuration is not ready until tPUD after the hardware reset event. During this period, the CS43198 does not respond to any user-issued I2C command. After configuration, the IC tristates the ADR pin and becomes high impedance internally to avoid a constant bias current. ASP overload ASP_OVLD_I NT ASP_OVLD_INT_MASK ASP error ASP_ERR_INT ASP_ERR_INT_MASK ASP late ASP_LATE_INT ASP_LATE_INT_MASK ASP early ASP_EARLY_INT ASP_EARLY_INT_MASK ASP no LRCK ASP_NOLRCK_INT ASP_NOLRCK_INT_MASK XSP overload XSP_OVLD_I NT XSP_OVLD_INT_MASK XSP error XSP_ERR_INT XSP_ERR_INT_MASK XSP late XSP_LATE_INT XSP_LATE_INT_MASK XSP early XSP_EARLY_INT XSP_EARLY_INT_MASK XSP no LRCK XSP_NOLRCK_INT XSP_NOLRCK_INT_MASK PLL is ready PLL_READY_INT PLL_READY_INT_MASK PLL error detected PLL_ERROR_INT PLL_ERROR_INT_MASK Power down done PDN_DONE_INT PDN_DONE_INT_MASK DSD stuck Error DSD_STUCK_INT DSD_STUCK_INT_MASK DSD channel A invalid error DSD_I NVAL_A_INT DSD_INVAL_A_INT_MASK DSD channel B invalid error DSD_I NVAL_B_INT DSD_INVAL_B_INT_MASK DSD channel A silence pattern detected DS D_SILENCE_A_INT DSD_SILENCE_A_INT_MASK DSD channel B silence pattern detected DS D_SILENCE_B_INT DSD_SILENCE_B_INT_MASK DSD rate error detected DSD_ RATE_INT DSD_RATE_INT_MASK DoP marker detected DOP_MRK_D ET_INT DOP_MRK_DET_INT_MASK DoP engine on DOP_ON_INT DOP_ON_INT_MASK Table 4-11. Interrupts Events and Register Bit Fields (Cont.) Interrupt Register Bit Fi eld Interrupt Mask Field

52 DS1156F1

To directly connect the ADR pin and ground, the last two bits of the I2C address are configured as the default 00. For the other options, use a resistor (with 5% accuracy) as suggested in the Table 4-12. If the operation is a write, the 3 bytes after the chip address are the memory address pointer (MAP) that select the address of the register to be read or written to next. The byte following the MAP is the control byte. Bit[0] of the control byte, INCR, selects whether autoincrementing is to be used (INCR = 1), allowing successive reads or writes of consecutive registers. Bits[2:1] of the control byte indicate the size of the data for the autoincrement to be acted on. Table 4-13 explains the format for the I2C control byte. Each byte transferred on the I2C bus is separated by an acknowledge (ACK) bit. The CS43198 acknowledges each input byte read from the host, and the host must acknowledge each byte transmitted from the CS43198. For write operations, the data bytes following the MAP byte are written to the CS43198 register addresses pointed to by the last received MAP address, plus however many autoincrements have occurred. Fig. 4-29 shows a write pattern with autoincrementing. Figure 4-29. Control Port Timing, I2C Writes with Autoincrement (8-bit Data Access) Table 4-12. I2C Address Configurations Connection Type Resistor Value ( ) Last Two Bits of I 2C Address Pull-up to VL 0 11 Pull-up to VL 4990 10 Pull-down to GND 4990 01 Pull-down to GND 0 00 (Default)Table 4-13. I2C Control-Byte Format Bit Name Description 7:3 — Reserved Default: 0 2:1 SIZE Register access width. Specifie s the width of the register access. 00 8-bit (1 byte) 01–11 Reserved 0 INCR Setting this bit allows the MAP address to autoincrement. The MAP address automatically increments every SIZE + 1 bytes accessed consecutively.

0 Disabled

1 Enabled

(WRITE ) MAP BYTE High (23:16) START STOPACK SDA SDA Source Master Master Master Pull-up Slave Slave Pull-up ACKR/W = 0 Slave AD0 AD1 4 5 6 7 8 9 17 180 1 2 3 7 6 5 4 3 2 1 0 ACK MAP BYTE Mid (15:8) MAP BYTE Low (7:0) ACK ACK CONTROL BYTE 7 6 5 4 3 2 1 0 37 3835 INCR = 1 SIZE = 00 Empty 7 0 7 0 7 0 16 26 27 25 39 40 41 42 43 44 7 0 7 0 DATA BYTE 1 DATA BYTE N Master Master Master Master M Slave Slave Slave Slave MAP ADDRESS MAP ADDRESS + ( N–1) ACK ACK Addr = 01100

For read operations, the contents of the register pointed to by the last received MAP address (plus however many autoincrements have occurred if INCR was previously set) are output in the next byte. Fig. 4-30 shows a read pattern following the write pattern in Fig. 4-29. Notice how read addresses are based on the MAP bytes from Fig. 4-29. Figure 4-30. Control Port Timing, I2C Reads with Autoincrement (8-Bit Data Access) To generate a read address not based on the last received MAP address, an aborted write operation can be used as a preamble (see Fig. 4-31). Here, a write operation is aborted (after the ACK for the control byte) by sending a Stop condition. Figure 4-31. Control Port Timing, I2C Reads with Preamble and Autoincrement (8-Bit Data Access) SCL CHIP ADDRESS (READ) START SDA SDA Source Master Pull-up Slave Pull-up ACKR/W = 1 AD0 AD1 4 5 6 7 8 9 17 0 1 2 3 7 6 5 4 3 2 1 0 ACK NACK 7 0 7 0 DATA BYTE 1 DATA BYTE N M MSlave STOP MAP ADDRESS MAP ADDRESS + (N–1 ) Addr = 01100 SCL CHIP ADDRESS (WRITE ) MAP BYTE High (23:16) START STOP ACK SDA SDA Source Master Master Master Pull-up Slave Slave Pull-up ACKR/W = 0 Addr = 01100 AD0 AD1 4 5 6 7 8 9 17 180 1 2 3 7 6 5 4 3 2 1 0 ACK MAP BYTE Mid (15:8) MAP BYTE Low (7:0) ACK ACK CONTROL BYTE 7 6 5 4 3 2 1 0 37 3835 INCR = 1 SIZE = 00 Empty 7 0 7 0 7 0 16 26 27 25 39 40 41 42 43 44 7 0 7 0 DATA BYTE 1 DATA BYTE N Master Master Slave Slave Slave MSlave START R/W = 1 AD0 AD1 7 6 5 4 3 2 1 0 ACK ACK M NACK STOP Master 4 5 6 7 8 9 0 1 2 3 16 17 Slave CHIP ADDRESS (READ) MAP ADDRESS MAP ADDRESS + (N-1) Addr = 01100

54 DS1156F1

4.13 Programmable Filter

In the CS43198, there are a series of programmable filters which is open for user's customization. The filter coefficients can be programmed for altering frequency response or other characteristics to fit the design intention. The filter runs at the input sample rate as set by xSP. This feature is intended to be used for normal PCM playback under single-, double-, and quad-speed settings. (If operating at 192 kHz, MCLK_INT is required to be at 24.576 MHz.) For WBF mode and impedance measurement mode, the filter should be properly turned off. The filter series are composed of 1 first-order IIR system (FOS) and 3 second-order IIR system (SOS), which effectively is a seventh-order system. FOS and SOS structures are illustrated as in Fig. 4-32 and Fig. 4-33, respectively. Any filter stage can be chosen to be either utilized or bypassed through coefficient settings. Each stage is represented by filter coefficients, which is accessed through I2C writes. The filter coefficients are located in register address 0x09 000C to 0x09 0041. Each coefficient is comprised of a most-significant byte, a least-significant byte, and a sign byte. Figure 4-32. First-Order IIR System Figure 4-33. Second-Order IIR System The filter can only be programmed when PDN_HP is set. Program the filter coefficients when PDN_HP is cleared will result in non-expected behavior. To properly enable each filter's coefficients, after the coefficients is programmed in control port, user enable the control port filter coefficients through registers Programmable Filter Control 1 and Programmable Filter Control 2. When user not using the programmable filters, the filter should be disabled properly. Z‐1 ‐a1 X[n] Y[n] + + Z‐1 X[n] Y[n] Z‐1 ‐a2 ‐a1

5 Applications

This section provides recommended application procedures and instruction sequences for standard CS43198 operations.

5.1 PLL Clocking

Data-path logic is in the MCLK_INT domain, where MCLK_INT is expected to be 22.5792 or 24.576 MHz. For clocking scenarios in which the external system MCLK provided to CS43198 is neither 22.5792 nor 24.576 MHz, the PLL must be turned on to provide the desired internal MCLK. At start up, the system uses RCO as the internal MCLK for PLL programming over I2C and switches to the PLL output after it settles. PLL start-up time is a maximum of 1 ms.

5.2 Power Sequencing

Note the following for power-up sequencing on the CS43198:

• VP must be powered up first.
• All other supplies can come up in any order before RESET is released. Note the following for power-down sequencing on the CS43198:
• After RESET is asserted, VA/VCP/VL/VD can be removed in any order.
• VP must be powered down last.

5.3 Crystal Tuning

The CS43198 uses an external crystal as the source for internal MCLK. Refer to Table 3-14 for the load capacitance that is supported by CS43198. Table 5-1 lists supported crystals that meet the requirements for CS43198 and also shows also shows the XTAL_IBIAS settings for different crystals. The crystal setting register (0x20052) must be set appropriately based on the crystal used. The frequency at which the crystal eventually oscillates can be calculated using the formula below: Fosc= 1/(2*π*sqrt[Lm*(Cm (C0+CL))/(Cm+C0+CL)]) , where Lm = motional inductance of crystal Cm = motional capacitance of crystal C0 = shunt capacitance CL = load capacitance Trace capacitance and pad capacitance (approximately 0.5 pF) must also be taken into account while calculating the value of the load capacitors. Below are the steps to tune the crystal to the correct frequency: 1. Select load capacitor values that match the load ca pacitance spec in crystal manufacturer's data sheet. Table 5-1. Example List of Supported Crystals Manufacturer 1 1.Contact your local Cirrus Logic representative for a list of supported manufacturers and part numbers. Part Number 1 Frequency (MHz) Bias Current Strength (µA) Crystal Setting Register (0x20052) River Electronics FCX-06-22.5792J51933 22.5792 12.5 0x04 FCX-06-24.5760J51930 24.576 7.5 0x06 NDK NX2016SA 22.5792M EXS00A-CS09116 22.5792 15 0x02 NX2016SA 24.576M EXS00A-CS09117 24.576 TXC 8Y22570001 22.5792 12.5 0x04 8Y24570001 24.576

56 DS1156F1

5.4 CS43198 Analog Output and Filtering

1. Power up and verify communication with CS 43198. If there is no communication, it is possible that the crystal did not start. Check power rails and load capacitance and try again. 3. Clear PDN_CLKOUT in the Power Down Control (0x20000) register. This sets the clock output at MCLK_INT/2 frequency from CLKOUT pin. 4. Measure the frequency and verify that it is within acceptable range of the desired frequency. If yes, continue normal operation. If not, power down the chip, change the load capacitor values and go back to step 2. Note: These steps need to be performed only once per PCB.

5.4 CS43198 Analog O utput and Filtering

The CS43198 requires an external opamp filter stage for driving headphone loads. One of the typical filter topologies used for this purpose is the multiple-feedback filter configuration. The CS43198 does not include phase or amplitude compensation for an external filter. Therefore, the DAC system and phase response is dependent on the external circuitry.

5.5 Audio Output Power Down Sequences

Examples of power down sequences for PCM and DSD are shown in Ex. 5-1 and Ex. 5-2, respectively. Follow the stated sequence every time to shut down the audio output. The sequence assumes that the PDN_DONE_INT interrupt bit is unmasked.

5.5.1 PCM Power Down Sequence

Example 5-1. PCM Power Down Sequence STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Enable PDN_DONE

Interrupt Mask 1. 0xF0010 data(0xF0010) AND (0xFE) DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK x x x x x x x

0 Enable PDN_DONE interrupt

2 Power down amplifier Power Down Control. 0x20000 data(0x20000) OR (0x10) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x x Turn off DAC output 3 Wait for interrupt. Check for PDN_DONE_INT = 1 in Interrupt Status 1 register (0xF0000). 4 Power down ASP Power Down Control. 0x20000 data(0x20000) OR (0x40) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x x Turn off ASP

5.6 Audio Output Power-Up Sequence

5.5.2 DSD Power Down Sequence

5.6 Audio Output Po wer-Up Sequence

An example of the power-up sequence for PCM and DSD are shown in Ex. 5-3 and Ex. 5-4, respectively. Follow the stated sequence every time to power up the audio output.

5.6.1 PCM Power-Up Sequence

Example 5-2. DSD Power Down Sequence STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION Interrupt Mask 1. 0xF0010 data(0xF0010) AND (0xFE) DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK x x x x x x x 2 Power down amplifier Power Down Control. 0x20000 data(0x20000) OR (0x10) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x x Turn off DAC output 3 Wait for interrupt. Check for PDN_DONE_INT = 1 in Interrupt Status 1 register (0xF0000).

4 Power down XSP/ASP/

Power Down Control. 0x20000 data(0x20000) OR (0xE0) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x Example 5-3. PCM Power-Up Sequence STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Pop-free power-up settings 0x10010 0x99

2 Power on appropriate interface.Power Down Control. 0x20000 data (0x20000) AND (0xBF) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x Power up ASP 3 Power on amplifier Power Down Control. 0x20000 data (0x20000) AND (0xEF) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x Power up DAC output

4 Wait for 12 ms

5 Restore default settings 0x80032 0x00

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5.7 Power-Down Sequence in External VCPFILT Mode

5.6.2 DSD Power-Up Sequence

These sequences allow the CS43198 to be powered down in external VCPFILT mode without any audible pops.

5.7.1 PCM Pop-Free Power-Down Sequence in External VCPFILT Mode

Example 5-4. DSD Power-Up Sequence STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 2 Power on appropriate interface.Power Down Control. 0x20000 data (0x20000) AND (0xHH) For DoP on XSP, HH = 7F. For DoP on ASP, HH = BF. For DSD interface, HH = DF. PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved B B B x x x x x Enable XSP, ASP, or DSDIF interface 3 Power on amplifier Power Down Control. 0x20000 data (0x20000) AND (0xEF) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x Power up DAC output STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Pop-free power-down settings 0x10010

2 Mute both channels PCM Path Signal Control 1. 0x90003 data(0x90003) OR (0x03) PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x xx x x Channel A is muted Channel B is muted

3 Wait 150 ms for mute to occur

4 Enable PDN_DONE interrupt Interrupt Mask 1. 0xF0010 data(0xF0010) AND (0xFE) DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK x x x x x x x 5 Power down amplifier Power Down Control. 0x20000 data(0x20000) OR (0x10) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x x Turn off HP 6 Wait for interrupt. Check for PDN_DONE_INT = 1 in Interrupt Status 1 register (0xF0000).

5.7.2 DSD Pop-Free Power-Down Se quence in External VCPFILT Mode

7 Power down ASP Power Down Control. 0x20000 data(0x20000) OR (0x40) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x x Turn off ASP 8 Unmute both channels PCM Path Signal Control 1. 0x90003 data(0x90003) AND (0xFC) PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x xx x x Channel A is unmuted Channel B is unmuted

9 Restore default settings 0x80046

STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 2 Mute both channels DSD Processor Path Signal Control 1. 0x70002 data(0x70002) OR (0x03) DSD_RAMP_UP DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B x x x x x x Channel A is muted Channel B is muted 4 Enable PDN_DONE interrupt Interrupt Mask 1. 0xF0010 data(0xF0010) AND (0xFE) DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK x x x x x x x 5 Power down amplifier Power Down Control. 0x20000 data(0x20000) OR (0x10) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x x Turn off HP 6 Wait for interrupt. Check for PDN_DONE_INT = 1 in Interrupt Status 1 register (0xF0000). 7 Power down XSP/ASP/DSDIF interfaces Power Down Control. 0x20000 data(0x20000) OR (0xE0) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x

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5.8 Enabling and Disabling NOS Filter

5.8 Enabling and Di sabling NOS Filter

5.8.1 Sequence for Enabling NOS Filter

8 Unmute both channels DSD Processor Path Signal Control 1. 0x70002 data(0x70002) AND (0xFC) DSD_RAMP_UP DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B x x x x x x Channel A is unmuted Channel B is unmuted STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Set mute to occur with soft ramp

PCM Path Signal Control 1. 0x90003 data (0x90003) AND (0xEF) OR (0x20) PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x x x x x Enable soft ramp 2 Mute both channels PCM Path Signal Control 1. 0x90003 data (0x90003) OR (0x03) PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x xx x x Channel A output is muted Channel B output is muted

3 Wait for 150 ms for mute to occur

4 Enable NOS filter PCM Filter Option. 0x90000 data (0x90000) OR (0x20) FILTER_SLOW_FASTB PHCOMP_LOWLATB NOS Reserved PCM_WBF_EN HIGH_PASS DEEMP_ON x x 0 0 x x x NOS emulation mode is on

5 Restore PCM_SZC mode if

PCM Path Signal Control 1. 0x90003 0xHH PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x BB x x x x Restore PCM_SZC to desired value 6 Unmute both channels PCM Path Signal Control 1. 0x90003 data (0x90003) AND (0xFC) PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x xx x x Function is disabled Function is disabled

5.9 Sequence for Using PCM Invert Bits

5.8.2 Sequence for Di sabling NOS Filter

5.9.1 Sequence for Enabling Channel A Invert

STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION PCM Path Signal Control 1. 0x90003 data (0x90003) AND (0xEF) OR (0x20) PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x x x x x Enable soft ramp 2 Mute both channels PCM Path Signal Control 1. 0x90003 data (0x90003) OR (0x03) PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x xx x x Channel A output is muted Channel B output is muted 4 Disable NOS filter PCM Filter Option. 0x90000 data (0x90000) AND (0xDF) FILTER_SLOW_FASTB PHCOMP_LOWLATB NOS Reserved PCM_WBF_EN HIGH_PASS DEEMP_ON x x 0 0 x x x NOS emulation mode is off PCM Path Signal Control 1. 0x90003 0xHH PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x BB x x x x Restore PCM_SZC to desired value 6 Unmute both channels PCM Path Signal Control 1. 0x90003 data (0x90003) AND (0xFC) PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B x x xx x x Function is disabled Function is disabled STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Invert channel A calibration 0x180005 0xD1

2 Enable channel A invert PCM Path Signal Control 2. 0x90004 data (0x90004) OR (0x08) Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 x x x Enable Channel A invert

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5.10 Sequences for Using the PCM Channel Swap Bit

5.9.2 Sequence for Disabling Channel A Invert

5.9.3 Sequence for Enabling Channel B Invert

5.9.4 Sequence for Disabling Channel B Invert

The following subsections describe sequences for enabling and disabling the PCM_SWAP_CHAN bit. STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Restore channel A calibration 0x180005 0x2F

2 Disable channel A invert PCM Path Signal Control 2. 0x90004 data (0x90004) AND (0xF7) Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 x x x Disable Channel A invert STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Invert channel B calibration 0x18000D 0x5F

2 Enable channel B invert PCM Path Signal Control 2. 0x90004 data (0x90004) OR (0x04) Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 x x x Enable Channel B invert STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Restore channel B calibration 0x18000D 0xA1

2 Disable channel B invert PCM Path Signal Control 2. 0x90004 data (0x90004) AND (0xFB) Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 x x x Disable Channel B invert

5.10.1 Sequence for Enabli ng the PCM_SWAP_CHAN Bit

5.10.2 Sequence for Disabling the PCM_SWAP_CHAN Bit

STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Swap channel A/B calibration 0x180005 0xA1

2 Enable PCM channel swap PCM Path Signal Control 2. 0x90004 data (0x90004) OR (0x02) Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 x x x Enable PCM channel swap STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION

1 Restore channel A/B calibration 0x180005 0x2F

2 Disable PCM channel swap PCM Path Signal Control 2. 0x90004 data (0x90004) AND (0xFD) Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 x x x Disable PCM channel swap

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5.11 Sequences for Enabling and Disabling Mono Mode for PCM Playback

The following subsections describe sequences for enabling and disabling mono mode for PCM playback.

5.11.1 Sequence for Enabling Mono Mode for PCM Playback

5.11.2 Sequence for Disabling Mono Mode for PCM Playback

STEP TASK REGISTER/BIT FIELDS VALUE

1 Enable mono mode 0x180009 0x2F

STEP TASK REGISTER/BIT FIELDS VALUE

1 Disable mono mode 0x180009 0xD1

5.12 Example Sequences

This section provides recommended instruction sequences for standard CS43198 operations.

5.12.1 Power-up Sequence to I 2S Playback

Example 5-5. Startup to I2S Playback STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms.

3 Configure XTAL driver

4 Configure XTAL bias

current strength (assuming River Crystal at

22.5792 MHz)

Crystal Setting. 0x20052 0x04 Reserved XTAL_IBIAS 0000 0 100 Bias current set to 12.5 µA 5 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts. 6 Enable XTAL interrupts Interrupt Mask 1. 0xF0010 0xE7 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Enable XTAL_READY interrupt Enable XTAL_ERROR interrupt 7 Start XTAL Power Down Control. 0x20000 0xF6 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Power up XTAL driver 8 Configure ASP interface. Sample rate set to 44.1 kHz. ASP is clock master. 9 Set ASP sample rate Serial Port Sample Rate. 0x1000B 0x01 Reserved ASP_SPRATE 0000 0001 Set sample rate to 44.1 kHz 10 Set ASP sample bit size. XSP is don't care Serial Port Sample Bit Size. 0x1000C 0x04 Reserved XSP_SPSIZE ASP_SPSIZE 0000 XSP sample bit size set to 24 bits ASP sample bit size set to 32 bits 11 Set ASP numerator ASP Numerator 1. 0x40010 0x01 ASP_N_LSB 0x01 LSB of ASP sample rate fractional divide numerator ASP Numerator 2. 0x40011 0x00 ASP_N_MSB 0x00 MSB of ASP sample rate fractional divide numerator 12 Set ASP denominator ASP Denominator 1. 0x40012 0x08 ASP_M_LSB 0x08 LSB of ASP sample rate fractional divide denominator ASP Denominator 2. 0x40013 0x00 ASP_M_MSB 0x00 MSB of ASP sample rate fractional divide denominator 13 Set ASP LRCK high time ASP LRCK High Time 1. 0x40014 0x1F ASP_LCHI_LSB 0x1F LSB of ASP LRCK high time duration ASP LRCK High Time 2. 0x40015 0x00 ASP_LCHI_MSB 0x00 MSB of ASP LRCK high time duration 14 Set ASP LRCK period ASP LRCK Period 1. 0x40016 0x3F ASP_LCPR_LSB 0x3F LSB of ASP LRCK period ASP LRCK Period 2. 0x40017 0x00 ASP_LCPR_MSB 0x00 MSB of ASP LRCK period 15 Configure ASP clock ASP Clock Configuration. 0x40018 0x1C Reserved ASP_M/SB ASP_SCPOL_OUT ASP_SCPOL_IN ASP_LCPOL_OUT ASP_LCPOL_IN 000 Set ASP port to be master Configure clock polarity for I 2S input

66 DS1156F1

16 Configure ASP frame ASP Frame Configuration. 0x40019 0x0A Reserved ASP_STP ASP_5050 ASP_FSD 000 010 Configure ASP port to accept I 2S input 17 Set ASP channel location ASP Channel 1 Location. 0x50000 0x00 ASP_RX_CH1 0x00 ASP Channel 1 starts on SCLK0 ASP Channel 2 Location. 0x50001 0x00 ASP_RX_CH2 0x00 ASP Channel 2 starts on SCLK0

18 Set ASP channel size and

ASP Channel 1 Size and Enable. 0x5000A 0x07 Reserved ASP_RX_CH1_AP ASP_RX_CH1_EN ASP_RX_CH1_RES 0000 ASP Channel 1 Active Phase ASP Channel 1 Enable ASP Channel 1 Size is 32 bits ASP Channel 2 Size and Enable. 0x5000B 0x0F Reserved ASP_RX_CH2_AP ASP_RX_CH2_EN ASP_RX_CH2_RES 0000 ASP Channel 2 Active Phase ASP Channel 2 Enable ASP Channel 2 Size is 32 bits 19 Configure PCM interface. HPF filter is used. Deemphasis off. 20 Configure PCM filter PCM Filter Option. 0x90000 0x02 FILTER_SLOW_FASTB PHCOMP_LOWLATB NOS Reserved PCM_WBF_EN HIGH_PASS DEEMP_ON 0 0 High pass filter is selected 21 Set volume for channel B PCM Volume B. 0x90001 0x00 PCM_VOLUME_B 0x00 Set volume to 0 dB 22 Set volume for channel A PCM Volume A. 0x90002 0x00 PCM_VOLUME_A 0x00 Set volume to 0 dB

23 Configure PCM path signal

PCM Path Signal Control 1. 0x90003 0xEC PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B Soft ramp down of volume on filter change Volume setting on both channels controlled by PCM_ VOLUME_A Enable soft ramp Mute after reception of 8192 samples of 0 or –1. Mute only when AMUTE condition is detected on both channels Function is disabled Function is disabled PCM Path Signal Control 2. 0x90004 0x00 Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 Disable all functions in this register

24 Configure DAC output

25 Configure Class H amplifierC lass H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 1 11 Output signal determines voltage level High voltage mode enabled Using internal VCPFILT source. 26 Set DAC output to full scaleAnalog Output Control 1. 0x80000 0x30 Reserved Reserved OUT_FS Reserved Reserved Reserved +1dB_EN Set DAC output to full scale (1.732 V rms)

27 Configure Headphone

HP Detect. 0xD0000 0x04 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 0 0 HP detect disabled HP detect input is not inverted Tip sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms Example 5-5. Startup to I2S Playback (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

5.12.2 Power-Up Sequence to DSD Playback

In Ex. 5-6, a 22.5792-MHz crystal is used, the PLL is used to create a 24.576-MHz MCLK, XSP is set as DSD slave at 2.8224 MHz, and full-scale output is 1.732 Vrms. 28 Headphone detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 0 0 HP detect enabled HP detect input is not inverted Tip sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms

29 Enable interrupts

30 Read Interrupt Status 1 register (0xF0000) and Interrupt Status 2 register (0xF0001) to clear sticky bits.

31 Enable headphone detect

Interrupt Mask 1. 0xF0010 0x87 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Enable HPDETECT_PLUG interrupt Enable HPDETECT_UNPLUG interrupt 32 Enable ASP interrupts Interrupt Mask 2. 0xF0011 0x07 ASP_OVFL_INT_MASK ASP_ERROR_INT_MASK ASP_LATE_INT_MASK ASP_EARLY_INT_MASK ASP_NOLRCK_INT_MASK Reserved 111 Enable ASP_OVFL interrupt Enable ASP_ERROR interrupt Enable ASP_LATE interrupt Enable ASP_EARLY interrupt Enable ASP_NOLRCK interrupt 33 Wait for interrupt. Check if XTAL_READY_INT = 1 in Interrupt Status 1 register (0xF0000).

34 Switch MCLK source to

System Clocking Control 1. 0x10006 0x04 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 MCLK Source set to XTAL. MCLK_INT frequency set to

22.5792 MHz

35 Wait at least 150 µs. 36 Enable ASP clocks Pad Interf ace Configuration. 0x1000D 0x02 Reserved XSP_3ST ASP_3ST 0000 00 XSP Interface status is don't care (set to default) Enable serial clocks in Master Mode 37 Power up DAC Refer to Ex. 5-3 for PCM power-up sequence Example 5-6. Startup to DSD Playback STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms.

4 Configure XTAL bias current

strength (assuming River Crystal at 22.5792 MHz) Crystal Setting. 0x20052 0x04 Reserved XTAL_IBIAS 0000 0 100 Bias current set to 12.5 µA 5 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts. 6 Enable XTAL interrupts Interrupt Mask 1. 0xF0010 0xE7 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Enable XTAL_READY interrupt Enable XTAL_ERROR interrupt 7 Start XTAL Power Down Control. 0x20000 0xF6 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Power up XTAL driver Example 5-5. Startup to I2S Playback (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

68 DS1156F1

9 Power up PLL Power Down Control. 0x20000 0xF2 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Power up PLL 10 Set PLL predivide PLL Setting 9. 0x40002 0x03 Reserved PLL_REF_PREDIV 0000 00

11 Divide PLL Reference by 8

11 Set PLL Output Divide PLL Setting 6. 0x30008 0x08 PLL_OUT_DIV 0x08 Divide PLL output by 8

12 Set Fractional portion of PLL

PLL Setting 2. 0x30002 0x00 PLL_DIV_FRAC_0 0x00 PLL Setting 3. 0x30003 0xF7 PLL_DIV_FRAC_1 0xF7 PLL Setting 4. 0x30004 0x06 PLL_DIV_FRAC_2 0x06

13 Set integer portion of PLL divide

PLL Setting 5. 0x30005 0x44 PLL_DIV_INT 0x44 14 Set PLL Mode PLL Setting 8. 0x3001B 0x01 Reserved PLL_MODE Reserved 0000 00 Use 500/512 factor 15 Set PLL Calibration Ratio P LL Setting 7. 0x3000A 0x8B PLL_CAL_RATIO 0x8B Set PLL Cal Ratio to 139 16 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts. 17 Enable PLL Interrupts Interrupt Mask 1. 0xF0010 0xE1 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Enable PLL Ready and Error Interrupts 18 Start PLL PLL Setting 1. 0x30001 0x01 Reserved PLL_START 0000 000

1 Start PLL

19 Configure DSDIF to playback 64•Fs DSD stream. DSDIF is configured as Slave 20 Configure DSD Volume DSD Volume A. 0x70001 0x00 DSD_VOLUME_A 0x00 Channel A volume set to 0dB

21 Configure DSD path Signal

DSD Processor Path Signal Control 1. 0x70002 0xCC DSD_RAMP_UP DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B DSD Volume B equals DSD volume A Immediate change Mute occurs after 256 repeated 8-bit DSD mute patterns Mute happens only when mute pattern is detected in both channels Function is disabled Function is disabled 22 Configure DSD Interface DSD In terface Configuration. 0x70003 0x00 Reserved DSD_M/SB DSD_PM_EN DSD_PM_SEL 0000 0 DSD is clock slave Function is disabled Function is disabled Example 5-6. Startup to DSD Playback (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

23 Configure DSD path Signal

DSD Processor Path Signal Control 2. 0x70004 0x13 Reserved DSD_PRC_SRC DSD_EN Reserved DSD_SPEED STA_DSD_DET INV_DSD_DET Set source of DSD processor to DSDIF Enable DSD playback Set DSD clock speed to 64•FS Static DSD detection enabled Invalid DSD detection enabled 25 Configure Class H Amplifier Class H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 111 Output signal determines voltage level High Voltage Mode Enabled Using Internal VCPFILT source. 26 Set DAC output to full scale Analog Output Control 1. 0x80000 0x30 Reserved Reserved OUT_FS Reserved Reserved Reserved +1dB_EN Set DAC output to Full Scale (1.732 V rms) 27 Configure Headphone Detect HP Detect. 0xD0000 0x04 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved HP detect disabled HP detect input is not inverted Tip Sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 28 Headphone Detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved HP detect enabled HP detect input is not inverted Tip sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 30 Read Interrupt Status 1 register (0xF0000) and Interru pt Status 5 register (0xF0004) to clear sticky bits Interrupt Mask 1. 0xF0010 0x81 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Unmask HPDETECT_PLUG interrupt and HPDETECT_UNPLUG interrupt 32 Enable DSD Interrupts Interrupt Mask 5. 0xF0014 0x03 DSD_STUCK_INT_MASK DSD_INVAL_A_INT_MASK DSD_INVAL_B_INT_MASK DSD_SILENCE_A_INT_MASK DSD_SILENCE_B_INT_MASK DSD_RATE_ERROR_INT_MASK DOP_MRK_DET_INT_MASK DOP_ON_INT_MASK Enable DSD_STUCK interrupt Enable DSD_INVAL_A interrupt Enable DSD_INVAL_B interrupt Enable DSD_SILENCE_A interrupt Enable DSD_SILENCE_B interrupt Enable DSD_RATE_ERROR interrupt Disable DOP_MRK_DET interrupt Disable DOP_ON interrupt 33 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000) 34 Switch MCLK source to PLL System Clocking Control 1. 0x10006 0x01 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 MCLK Source set to PLL. MCLK_INT frequency set to

24.576 MHz

35 Wait at least 150 µs. 36 Power up DAC Refer to Ex. 5-4 for DSD power-up sequence. Note that in Step 1 of Ex. 5-4, use HH = DF for the DSD interface. Example 5-6. Startup to DSD Playback (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

70 DS1156F1

5.12.3 Power-Up Sequence to DoP Playback with PLL

In Ex. 5-7, an external 19.2-MHz MCLK is used with a PLL to generate an internal MCLK or 22.5792 MHz, and the ASP is in clock master receiving DoP data with LRCLK at 176.4 kHz and SCLK at 8.4672 MHz. Example 5-7. DoP Playback with PLL STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms. settings for other frequency combinations 4 Power up PLL Power Down Control. 0x20000 0xFA PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x Power up PLL block 5 Set PLL Predivide value PLL Setting 9. 0x40002 0x03 Reserved PLL_REF_PREDIV 0000 00

11 Set PLL predivide value to 8

6 Set PLL output divide PLL Setting 6. 0x30008 0x08 PLL_OUT_DIV 0x08 Set PLL output divide value to 8 7 Set Fractional portion of PLL Divide Ratio PLL Setting 2. 0x30002 0x00 PLL_DIV_FRAC_0 0x00 Set LSB of PLL fractional divider value to 0 PLL Setting 3. 0x30003 0x00 PLL_DIV_FRAC_1 0x00 Set Middle Byte of PLL fractional divider value to 0 PLL Setting 4. 0x30004 0x80 PLL_DIV_FRAC_2 0x80 Set MSB of PLL fractional divider value to 0x80 8 Set Integer portion of PLL Divide Ratio PLL Setting 5. 0x30005 0x49 PLL_DIV_INT 0x49 Set PLL integer Divide value to 0x49 9 Set PLL mode PLL Setting 8. 0x3001B 0x01 Reserved PLL_MODE Reserved 0000 00 500/512 factor is used in PLL frequency calculation 10 Read Interrupt Status 1 register (0xF0000) to clear sticky bits. 11 Set PLL calibration ratio PLL Setting 7. 0x3000A 0x97 PLL_CAL_RATIO 0x97 PLL Calibration Ratio is set to 0x97 (151) 12 Enable PLL interrupts Interrupt Mask 1. 0xF0010 0xF9 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK DAC_OVFL_INT is don't care Unmask HPDETECT_PLUG interrupt Unmask HPDETECT_UNPLUG interrupt XTAL_READY_INT is Don't Care XTAL_ERROR_INT is Don't Care PLL_READY Interrupt is already unmasked PLL_ERROR Interrupt is already unmasked PDN_DONE_INT is Don't Care 13 Start PLL PLL Setting 1. 0x30001 0x01 Reserved PLL_START 0000 000

1 Enable PLL Output

14 Playback DoP audio. Assuming 64

• Fs DSD stream

15 Configure ASP interface for DoP input

16 Set ASP sample rate Serial Port Sample Rate. 0x1000B 0x05 Reserved ASP_SPRATE 0000 0101 Set sample rate to 176.4 kHz 17 Set ASP sample bit size. XSP is don't care Serial Port Sample Bit Size. 0x1000C 0x05 Reserved XSP_SPSIZE ASP_SPSIZE 0000 XSP sample bit size set to 24 bits ASP sample bit size set to 24 bits 18 Set ASP numerator ASP Numerator 1. 0x40010 0x03 ASP_N_LSB 0x03 LSB of ASP sample rate fractional divide numerator ASP Numerator 2. 0x40011 0x00 ASP_N_MSB 0x00 MSB of ASP sample rate fractional divide numerator

19 Set ASP denominator ASP Denominator 1. 0x40012 0x08 ASP_M_LSB 0x08 LSB of ASP sample rate fractional divide denominator ASP Denominator 2. 0x40013 0x00 ASP_M_MSB 0x00 MSB of ASP sample rate fractional divide denominator 20 Set ASP LRCK high time ASP LRCK High Time 1. 0x40014 0x17 ASP_LCHI_LSB 0x17 LSB of ASP LRCK high time duration ASP LRCK High Time 2. 0x40015 0x00 ASP_LCHI_MSB 0x00 MSB of ASP LRCK high time duration 21 Set ASP LRCK period ASP LRCK Period 1. 0x40016 0x2F ASP_LCPR_LSB 0x2F LSB of ASP LRCK period ASP LRCK Period 2. 0x40017 0x00 ASP_LCPR_MSB 0x00 MSB of ASP LRCK period 22 Configure ASP clock ASP Cloc k Configuration. 0x40018 0x1C Reserved ASP_M/SB ASP_SCPOL_OUT ASP_SCPOL_IN ASP_LCPOL_OUT ASP_LCPOL_IN 000 Set ASP port to be Master Set output SCLK polarity Input SCLK polarity is don't care Set Output LRCK polarity Input LRCK polarity is don't care 23 Configure ASP frame ASP Frame Configuration. 0x40019 0x0A Reserved ASP_STP ASP_5050 ASP_FSD 000 010 Configure ASP port to accept I 2S input 24 Set ASP channel location ASP Channel 1 Location. 0x50000 0x00 ASP_RX_CH1 0x00 ASP Channel 1 starts on SCLK0 ASP Channel 2 Location. 0x50001 0x00 ASP_RX_CH2 0x00 ASP Channel 2 starts on SCLK0 25 Set ASP channel size and enable ASP Channel 1 Size and Enable. 0x5000A 0x06 Reserved ASP_RX_CH1_AP ASP_RX_CH1_EN ASP_RX_CH1_RES 0000 ASP Channel 1 active phase ASP Channel 1 enable ASP Channel 1 size is 24 bits ASP Channel 2 Size and Enable. 0x5000B 0x0E Reserved ASP_RX_CH2_AP ASP_RX_CH2_EN ASP_RX_CH2_RES 0000 ASP Channel 2 active phase ASP Channel 2 enable ASP Channel 2 size is 24 bits 26 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000).

27 Configure DSD processor

28 Configure DSD volume DSD Volume A. 0x70001 0x00 DSD_VOLUME_A 0x00 Channel A volume set to 0 dB 29 Configure DSD Path Signal Control 1 DSD Processor Path Signal Control 1. 0x70002 0xCC DSD_RAMP_UP DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B DSD Volume B equals DSD volume A Immediate change Mute occurs after 256 repeated 8-bit DSD mute patterns Mute happens only when mute pattern is detected in both channels Function is disabled Function is disabled 30 Configure DSD interface DSD Interface Configuration. 0x70003 0x04 Reserved DSD_M/SB DSD_PM_EN DSD_PM_SEL 0000 0 DSD is clock master Function is disabled Function is disabled Example 5-7. DoP Playback with PLL (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

72 DS1156F1

31 Configure DSD Path Signal Control 2 DSD Processor Path Signal Control 2. 0x70004 0x50 Reserved DSD_PRC_SRC DSD_EN Reserved DSD_SPEED STA_DSD_DET INV_DSD_DET Set source of DSD processor to ASP Enable DSD playback Set DSD clock speed to 64•Fs Static DSD detection disabled Invalid DSD detection disabled 32 Configure DSD path Signal Control 3 DSD Processor Path Signal Control 3. 0x70006 0xC0 DSD_ZERODB DSD_HPF_EN Reserved SIGCTL_DSDEQPCM DSD_INV_A DSD_INV_B DSD_SWAP_CHAN DSD_COPY_CHAN The SACD 0–dB reference level (50%modulation index) matches PCM 0-dB full scale. Enable HPF in DSD processor Function is disabled Function is disabled Function is disabled Function is disabled Function is disabled 33 Configure DAC output for 1.732 V rms 34 Configure Class H amplifier Class H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 1 11 Output signal determines voltage level High voltage mode enabled Using internal VCPFILT source. 35 Set DAC output to full scale Analog Output Control 1. 0x80000 0x30 Reserved Reserved OUT_FS Reserved Reserved Reserved +1dB_EN Set DAC output to full scale (1.732 V rms) 36 Headphone detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 0 0 HP detect enabled HP detect input is not inverted Tip Sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms

37 Enable interrupts

38 Read Interrupt Status 1 register (0xF0000), Interrupt Status 2 register (0xF0001) and Interrupt Status 5 register (0xF0004) t o clear sticky bits. 39 Enable headphone detect interrupts Interrupt Mask 1. 0xF0010 0x99 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK DAC_OVFL_INT is don't care Enable HPDETECT_PLUG interrupt Enable HPDETECT_UNPLUG interrupt XTAL_READY_INT is don't care XTAL_ERROR_INT is don't care PLL_READY interrupt already enabled PLL_ERROR interrupt already enabled PDN_DONE_INT is don't care 40 Enable ASP interrupts Interrupt Mask 2. 0xF0011 0x07 ASP_OVFL_INT_MASK ASP_ERROR_INT_MASK ASP_LATE_INT_MASK ASP_EARLY_INT_MASK ASP_NOLRCK_INT_MASK Reserved 111 Enable ASP_OVFL interrupt Enable ASP_ERROR interrupt Enable ASP_LATE interrupt Enable ASP_EARLY interrupt Enable ASP_NOLRCK interrupt 41 Enable DSD and DoP interrupts Interrupt Mask 5. 0xF0014 0x01 DSD_STUCK_INT_MASK DSD_INVAL_A_INT_MASK DSD_INVAL_B_INT_MASK DSD_SILENCE_A_INT_MASK DSD_SILENCE_B_INT_MASK DSD_RATE_ERROR_INT_MASK DOP_MRK_DET_INT_MASK DOP_ON_INT_MASK Enable DSD_STUCK interrupt Enable DSD_INVAL_A interrupt Enable DSD_INVAL_B interrupt Enable DSD_SILENCE_A interrupt Enable DSD_SILENCE_B interrupt Enable DSD_RATE_ERROR interrupt Enable DOP_MRK_DET interrupt Disable DOP_ON interrupt 42 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000). 43 Set MCLK source and frequency System Clocking Control. 0x10006 0x05 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 MCLK Frequency is set to 22.5792 MHz MCLK Source is set to PLL 44 Wait for at least 150 µs. Example 5-7. DoP Playback with PLL (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

5.12.4 Power-up Sequence to I 2S Playback in Mono Mode

45 Enable ASP clocks Pad Interfac e Configuration. 0x1000D 0x02 Reserved XSP_3ST ASP_3ST 0000 00 XSP Interface status is don't care (set to default) Enable serial clocks in Master Mode 46 Power up DAC Refer to Ex. 5-4 for DSD power-up sequence. Note that in Step 1 of Ex. 5-4, use HH = BF for DoP over ASP interface. Example 5-8. Startup to I2S Playback in Mono Mode STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms. current strength (assuming River Crystal at Crystal Setting. 0x20052 0x04 Reserved XTAL_IBIAS 0000 0 100 Bias current set to 12.5 µA 5 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts. 6 Enable XTAL interrupts Interrupt Mask 1. 0xF0010 0xE7 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Enable XTAL_READY interrupt Enable XTAL_ERROR interrupt 7 Start XTAL Power Down Control. 0x20000 0xF6 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Power up XTAL driver 8 Configure ASP interface. Sample rate set to 44.1 kHz. ASP is clock master. 9 Set ASP sample rate Serial Port Sample Rate. 0x1000B 0x01 Reserved ASP_SPRATE 0000 0001 Set sample rate to 44.1 kHz 10 Set ASP sample bit size. XSP is don't care Serial Port Sample Bit Size. 0x1000C 0x04 Reserved XSP_SPSIZE ASP_SPSIZE 0000 XSP sample bit size set to 24 bits ASP sample bit size set to 32 bits 11 Set ASP numerator ASP Numerator 1. 0x40010 0x01 ASP_N_LSB 0x01 LSB of ASP sample rate fractional divide numerator ASP Numerator 2. 0x40011 0x00 ASP_N_MSB 0x00 MSB of ASP sample rate fractional divide numerator 12 Set ASP denominator ASP Denominator 1. 0x40012 0x08 ASP_M_LSB 0x08 LSB of ASP sample rate fractional divide denominator ASP Denominator 2. 0x40013 0x00 ASP_M_MSB 0x00 MSB of ASP sample rate fractional divide denominator 13 Set ASP LRCK high time ASP LRCK High Time 1. 0x40014 0x1F ASP_LCHI_LSB 0x1F LSB of ASP LRCK high time duration ASP LRCK High Time 2. 0x40015 0x00 ASP_LCHI_MSB 0x00 MSB of ASP LRCK high time duration 14 Set ASP LRCK period ASP LRCK Period 1. 0x40016 0x3F ASP_LCPR_LSB 0x3F LSB of ASP LRCK period ASP LRCK Period 2. 0x40017 0x00 ASP_LCPR_MSB 0x00 MSB of ASP LRCK period Example 5-7. DoP Playback with PLL (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

74 DS1156F1

15 Configure ASP clock ASP Clock Configuration. 0x40018 0x1C Reserved ASP_M/SB ASP_SCPOL_OUT ASP_SCPOL_IN ASP_LCPOL_OUT ASP_LCPOL_IN 000 Set ASP port to be master Configure clock polarity for I 2S input 16 Configure ASP frame ASP Frame Configuration. 0x40019 0x0A Reserved ASP_STP ASP_5050 ASP_FSD 000 010 Configure ASP port to accept I 2S input 17 Set ASP channel location ASP Channel 1 Location. 0x50000 0x00 ASP_RX_CH1 0x00 ASP Channel 1 starts on SCLK0 ASP Channel 2 Location. 0x50001 0x00 ASP_RX_CH2 0x00 ASP Channel 2 starts on SCLK0 enable. Set both Channel 1 and Channel 2 to the same active phase to get the same data for mono mode. ASP Channel 1 Size and Enable. 0x5000A 0x07/0x0F for Left/Right channel Reserved ASP_RX_CH1_AP ASP_RX_CH1_EN ASP_RX_CH1_RES 0000 ASP Channel 1 Active Phase ASP Channel 1 Enable ASP Channel 1 Size is 32 bits ASP Channel 2 Size and Enable. 0x5000B 0x07/0x0F for Left/Right channel Reserved ASP_RX_CH2_AP ASP_RX_CH2_EN ASP_RX_CH2_RES 0000 ASP Channel 2 Active Phase ASP Channel 2 Enable ASP Channel 2 Size is 32 bits 19 Configure PCM interface. HPF filter is used. Deemphasis off. 20 Configure PCM filter PCM Filter Option. 0x90000 0x02 FILTER_SLOW_FASTB PHCOMP_LOWLATB NOS Reserved PCM_WBF_EN HIGH_PASS DEEMP_ON 0 0 High pass filter is selected 21 Set volume for channel B PCM Volume B. 0x90001 0x00 PCM_VOLUME_B 0x00 Set volume to 0 dB 22 Set volume for channel A PCM Volume A. 0x90002 0x00 PCM_VOLUME_A 0x00 Set volume to 0 dB PCM Path Signal Control 1. 0x90003 0xEC PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B Soft ramp down of volume on filter change Volume setting on both channels controlled by PCM_ VOLUME_A Enable soft ramp Mute after reception of 8192 samples of 0 or –1. Mute only when AMUTE condition is detected on both channels Function is disabled Function is disabled PCM Path Signal Control 2. 0x90004 0x00 Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 Disable all functions in this register 25 Configure Class H amplifierC lass H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 1 11 Output signal determines voltage level High voltage mode enabled Using internal VCPFILT source. 26 Set DAC output to full scaleAnalog Output Control 1. 0x80000 0x30 Reserved Reserved OUT_FS Reserved Reserved Reserved +1dB_EN Set DAC output to full scale (1.732 V rms) Example 5-8. Startup to I2S Playback in Mono Mode (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

5.12.5 Power-Up Sequence to DSD Playback in Mono Mode

In Ex. 5-6, a 22.5792-MHz crystal is used, the PLL is used to create a 24.576-MHz MCLK, XSP is set as DSD slave at 2.8224 MHz, and full-scale output is 1.732 Vrms. HP Detect. 0xD0000 0x04 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 0 0 HP detect disabled HP detect input is not inverted Tip sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 28 Headphone detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 0 0 HP detect enabled HP detect input is not inverted Tip sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 30 Read Interrupt Status 1 register (0xF0000) and Interrupt Status 2 register (0xF0001) to clear sticky bits. Interrupt Mask 1. 0xF0010 0x87 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Enable HPDETECT_PLUG interrupt Enable HPDETECT_UNPLUG interrupt 32 Enable ASP interrupts Interrupt Mask 2. 0xF0011 0x07 ASP_OVFL_INT_MASK ASP_ERROR_INT_MASK ASP_LATE_INT_MASK ASP_EARLY_INT_MASK ASP_NOLRCK_INT_MASK Reserved 111 Enable ASP_OVFL interrupt Enable ASP_ERROR interrupt Enable ASP_LATE interrupt Enable ASP_EARLY interrupt Enable ASP_NOLRCK interrupt 33 Wait for interrupt. Check if XTAL_READY_INT = 1 in Interrupt Status 1 register (0xF0000). System Clocking Control 1. 0x10006 0x04 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 MCLK Source set to XTAL. MCLK_INT frequency set to 35 Wait at least 150 µs. 36 Enable ASP clocks Pad Interf ace Configuration. 0x1000D 0x02 Reserved XSP_3ST ASP_3ST 0000 00 XSP Interface status is don't care (set to default) Enable serial clocks in Master Mode 37 Enable mono mode Refer to Section 5.11.1 for the Sequence for Enabling Mono Mode 38 Power up DAC Refer to Ex. 5-3 for PCM power-up sequence Example 5-9. Startup to DSD Playback in Mono Mode STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms. strength (assuming River Crystal at 22.5792 MHz) Crystal Setting. 0x20052 0x04 Reserved XTAL_IBIAS 0000 0 100 Bias current set to 12.5 µA 5 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts. 6 Enable XTAL interrupts Interrupt Mask 1. 0xF0010 0xE7 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Enable XTAL_READY interrupt Enable XTAL_ERROR interrupt Example 5-8. Startup to I2S Playback in Mono Mode (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

76 DS1156F1

7 Start XTAL Power Down Control. 0x20000 0xF6 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Power up XTAL driver 9 Power up PLL Power Down Control. 0x20000 0xF2 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Power up PLL 10 Set PLL predivide PLL Setting 9. 0x40002 0x03 Reserved PLL_REF_PREDIV 0000 00 11 Set PLL Output Divide PLL Setting 6. 0x30008 0x08 PLL_OUT_DIV 0x08 Divide PLL output by 8 PLL Setting 2. 0x30002 0x00 PLL_DIV_FRAC_0 0x00 PLL Setting 3. 0x30003 0xF7 PLL_DIV_FRAC_1 0xF7 PLL Setting 4. 0x30004 0x06 PLL_DIV_FRAC_2 0x06 PLL Setting 5. 0x30005 0x44 PLL_DIV_INT 0x44 14 Set PLL Mode PLL Setting 8. 0x3001B 0x01 Reserved PLL_MODE Reserved 0000 00 Use 500/512 factor 15 Set PLL Calibration Ratio P LL Setting 7. 0x3000A 0x8B PLL_CAL_RATIO 0x8B Set PLL Cal Ratio to 139 16 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts. 17 Enable PLL Interrupts Interrupt Mask 1. 0xF0010 0xE1 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Enable PLL Ready and Error Interrupts 18 Start PLL PLL Setting 1. 0x30001 0x01 Reserved PLL_START 0000 000 19 Configure DSDIF to playback 64•Fs DSD stream. DSDIF is configured as Slave 20 Configure DSD Volume DSD Volume A. 0x70001 0x00 DSD_VOLUME_A 0x00 Channel A volume set to 0dB DSD Processor Path Signal Control 1. 0x70002 0xCC DSD_RAMP_UP DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B DSD Volume B equals DSD volume A Immediate change Mute occurs after 256 repeated 8-bit DSD mute patterns Mute happens only when mute pattern is detected in both channels Function is disabled Function is disabled Example 5-9. Startup to DSD Playback in Mono Mode (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

22 Configure DSD Interface DSD In terface Configuration. 0x70003 0x00 Reserved DSD_M/SB DSD_PM_EN DSD_PM_SEL 0000 0 DSD is clock slave Function is disabled Function is disabled DSD Processor Path Signal Control 2. 0x70004 0x13 Reserved DSD_PRC_SRC DSD_EN Reserved DSD_SPEED STA_DSD_DET INV_DSD_DET Set source of DSD processor to DSDIF Enable DSD playback Set DSD clock speed to 64•FS Static DSD detection enabled Invalid DSD detection enabled

24 Configure DSD path Signal

Control 3. Enable mono mode: a. Select Channel A/B (DSD_SWAP_CHAN) b. Copy Channel A to B (DSD_COPY_CHAN) c. Invert Channel B (DSD_INV_B) DSD Processor Path Signal Control 3. 0x70006 0xC5/0xC7 for Left/Right channel DSD_ZERODB DSD_HPF_EN Reserved SIGCTL_DSDEQPCM DSD_INV_A DSD_INV_B DSD_SWAP_CHAN DSD_COPY_CHAN The SACD 0–dB reference level (50%modulation index) matches PCM 0-dB full scale. Enable HPF in DSD processor Function is disabled Function is disabled Function is enabled Function is enabled/disabled Function is enabled

25 Configure DAC output

26 Configure Class H Amplifier Class H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 111 Output signal determines voltage level High Voltage Mode Enabled Using Internal VCPFILT source. 27 Set DAC output to full scale Analog Output Control 1. 0x80000 0x30 Reserved Reserved OUT_FS Reserved Reserved Reserved +1dB_EN Set DAC output to Full Scale (1.732 V rms) 28 Configure Headphone Detect HP Detect. 0xD0000 0x04 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved HP detect disabled HP detect input is not inverted Tip Sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 29 Headphone Detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved HP detect enabled HP detect input is not inverted Tip sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms

30 Enable Interrupts

31 Read Interrupt Status 1 register (0xF0000) and Interru pt Status 5 register (0xF0004) to clear sticky bits

32 Enable Headphone Detect

Interrupt Mask 1. 0xF0010 0x81 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Unmask HPDETECT_PLUG interrupt and HPDETECT_UNPLUG interrupt 33 Enable DSD Interrupts Interrupt Mask 5. 0xF0014 0x03 DSD_STUCK_INT_MASK DSD_INVAL_A_INT_MASK DSD_INVAL_B_INT_MASK DSD_SILENCE_A_INT_MASK DSD_SILENCE_B_INT_MASK DSD_RATE_ERROR_INT_MASK DOP_MRK_DET_INT_MASK DOP_ON_INT_MASK Enable DSD_STUCK interrupt Enable DSD_INVAL_A interrupt Enable DSD_INVAL_B interrupt Enable DSD_SILENCE_A interrupt Enable DSD_SILENCE_B interrupt Enable DSD_RATE_ERROR interrupt Disable DOP_MRK_DET interrupt Disable DOP_ON interrupt 34 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000) Example 5-9. Startup to DSD Playback in Mono Mode (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

78 DS1156F1

5.12.6 Power-Up Sequence to DoP Playback with PLL in Mono Mode

In Ex. 5-7, an external 19.2-MHz MCLK is used with a PLL to generate an internal MCLK or 22.5792 MHz, and the ASP is in clock master receiving DoP data with LRCLK at 176.4 kHz and SCLK at 8.4672 MHz. 35 Switch MCLK source to PLL System Clocking Control 1. 0x10006 0x01 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 MCLK Source set to PLL. MCLK_INT frequency set to 36 Wait at least 150 µs. 37 Power up DAC Refer to Ex. 5-4 for DSD power-up sequence. Note that in Step 1 of Ex. 5-4, use HH = DF for the DSD interface. Example 5-10. DoP Playback with PLL in Mono Mode STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms. settings for other frequency combinations 4 Power up PLL Power Down Control. 0x20000 0xFA PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x x Power up PLL block 5 Set PLL Predivide value PLL Setting 9. 0x40002 0x03 Reserved PLL_REF_PREDIV 0000 00 6 Set PLL output divide PLL Setting 6. 0x30008 0x08 PLL_OUT_DIV 0x08 Set PLL output divide value to 8 7 Set Fractional portion of PLL Divide Ratio PLL Setting 2. 0x30002 0x00 PLL_DIV_FRAC_0 0x00 Set LSB of PLL fractional divider value to 0 PLL Setting 3. 0x30003 0x00 PLL_DIV_FRAC_1 0x00 Set Middle Byte of PLL fractional divider value to 0 PLL Setting 4. 0x30004 0x80 PLL_DIV_FRAC_2 0x80 Set MSB of PLL fractional divider value to 0x80 8 Set Integer portion of PLL Divide Ratio PLL Setting 5. 0x30005 0x49 PLL_DIV_INT 0x49 Set PLL integer Divide value to 0x49 9 Set PLL mode PLL Setting 8. 0x3001B 0x01 Reserved PLL_MODE Reserved 0000 00 500/512 factor is used in PLL frequency calculation 10 Read Interrupt Status 1 register (0xF0000) to clear sticky bits. 11 Set PLL calibration ratio PLL Setting 7. 0x3000A 0x97 PLL_CAL_RATIO 0x97 PLL Calibration Ratio is set to 0x97 (151) 12 Enable PLL interrupts Interrupt Mask 1. 0xF0010 0xF9 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK DAC_OVFL_INT is don't care Unmask HPDETECT_PLUG interrupt Unmask HPDETECT_UNPLUG interrupt XTAL_READY_INT is Don't Care XTAL_ERROR_INT is Don't Care PLL_READY Interrupt is already unmasked PLL_ERROR Interrupt is already unmasked PDN_DONE_INT is Don't Care 13 Start PLL PLL Setting 1. 0x30001 0x01 Reserved PLL_START 0000 000 14 Playback DoP audio. Assuming 64

• Fs DSD stream

16 Set ASP sample rate Serial Port Sample Rate. 0x1000B 0x05 Reserved ASP_SPRATE 0000 0101 Set sample rate to 176.4 kHz Example 5-9. Startup to DSD Playback in Mono Mode (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

17 Set ASP sample bit size. XSP is don't care Serial Port Sample Bit Size. 0x1000C 0x05 Reserved XSP_SPSIZE ASP_SPSIZE 0000 XSP sample bit size set to 24 bits ASP sample bit size set to 24 bits 18 Set ASP numerator ASP Numerator 1. 0x40010 0x03 ASP_N_LSB 0x03 LSB of ASP sample rate fractional divide numerator ASP Numerator 2. 0x40011 0x00 ASP_N_MSB 0x00 MSB of ASP sample rate fractional divide numerator 19 Set ASP denominator ASP Denominator 1. 0x40012 0x08 ASP_M_LSB 0x08 LSB of ASP sample rate fractional divide denominator ASP Denominator 2. 0x40013 0x00 ASP_M_MSB 0x00 MSB of ASP sample rate fractional divide denominator 20 Set ASP LRCK high time ASP LRCK High Time 1. 0x40014 0x17 ASP_LCHI_LSB 0x17 LSB of ASP LRCK high time duration ASP LRCK High Time 2. 0x40015 0x00 ASP_LCHI_MSB 0x00 MSB of ASP LRCK high time duration 21 Set ASP LRCK period ASP LRCK Period 1. 0x40016 0x2F ASP_LCPR_LSB 0x2F LSB of ASP LRCK period ASP LRCK Period 2. 0x40017 0x00 ASP_LCPR_MSB 0x00 MSB of ASP LRCK period 22 Configure ASP clock ASP Cloc k Configuration. 0x40018 0x1C Reserved ASP_M/SB ASP_SCPOL_OUT ASP_SCPOL_IN ASP_LCPOL_OUT ASP_LCPOL_IN 000 Set ASP port to be Master Set output SCLK polarity Input SCLK polarity is don't care Set Output LRCK polarity Input LRCK polarity is don't care 23 Configure ASP frame ASP Frame Configuration. 0x40019 0x0A Reserved ASP_STP ASP_5050 ASP_FSD 000 010 Configure ASP port to accept I 2S input 24 Set ASP channel location ASP Channel 1 Location. 0x50000 0x00 ASP_RX_CH1 0x00 ASP Channel 1 starts on SCLK0 ASP Channel 2 Location. 0x50001 0x00 ASP_RX_CH2 0x00 ASP Channel 2 starts on SCLK0 25 Set ASP channel size and enable ASP Channel 1 Size and Enable. 0x5000A 0x06 Reserved ASP_RX_CH1_AP ASP_RX_CH1_EN ASP_RX_CH1_RES 0000 ASP Channel 1 active phase ASP Channel 1 enable ASP Channel 1 size is 24 bits ASP Channel 2 Size and Enable. 0x5000B 0x0E Reserved ASP_RX_CH2_AP ASP_RX_CH2_EN ASP_RX_CH2_RES 0000 ASP Channel 2 active phase ASP Channel 2 enable ASP Channel 2 size is 24 bits 26 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000). 28 Configure DSD volume DSD Volume A. 0x70001 0x00 DSD_VOLUME_A 0x00 Channel A volume set to 0 dB 29 Configure DSD Path Signal Control 1 DSD Processor Path Signal Control 1. 0x70002 0xCC DSD_RAMP_UP DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B DSD Volume B equals DSD volume A Immediate change Mute occurs after 256 repeated 8-bit DSD mute patterns Mute happens only when mute pattern is detected in both channels Function is disabled Function is disabled Example 5-10. DoP Playback with PLL in Mono Mode (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

80 DS1156F1

30 Configure DSD interface DSD Interface Configuration. 0x70003 0x04 Reserved DSD_M/SB DSD_PM_EN DSD_PM_SEL 0000 0 DSD is clock master Function is disabled Function is disabled 31 Configure DSD Path Signal Control 2 DSD Processor Path Signal Control 2. 0x70004 0x50 Reserved DSD_PRC_SRC DSD_EN Reserved DSD_SPEED STA_DSD_DET INV_DSD_DET Set source of DSD processor to ASP Enable DSD playback Set DSD clock speed to 64•Fs Static DSD detection disabled Invalid DSD detection disabled 32 Configure DSD path Signal Control 3. Enable mono mode: a. Select Channel A/B (DSD_SWAP_CHAN) b. Copy Channel A to B (DSD_COPY_CHAN) c. Invert Channel B (DSD_INV_B) DSD Processor Path Signal Control 3. 0x70006 0xC5/0xC7 for Left/Right channel DSD_ZERODB DSD_HPF_EN Reserved SIGCTL_DSDEQPCM DSD_INV_A DSD_INV_B DSD_SWAP_CHAN DSD_COPY_CHAN The SACD 0–dB reference level (50%modulation index) matches PCM 0-dB full scale. Enable HPF in DSD processor Function is disabled Function is disabled Function is enabled Function is enabled/disabled Function is enabled 33 Configure DAC output for 1.732 V rms 34 Configure Class H amplifier Class H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 1 11 Output signal determines voltage level High voltage mode enabled Using internal VCPFILT source. 35 Set DAC output to full scale Analog Output Control 1. 0x80000 0x30 Reserved Reserved OUT_FS Reserved Reserved Reserved +1dB_EN Set DAC output to full scale (1.732 V rms) 36 Headphone detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 0 0 HP detect enabled HP detect input is not inverted Tip Sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 38 Read Interrupt Status 1 register (0xF0000), Interrupt Status 2 register (0xF0001) and Interrupt Status 5 register (0xF0004) t o clear sticky bits. 39 Enable headphone detect interrupts Interrupt Mask 1. 0xF0010 0x99 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK DAC_OVFL_INT is don't care Enable HPDETECT_PLUG interrupt Enable HPDETECT_UNPLUG interrupt XTAL_READY_INT is don't care XTAL_ERROR_INT is don't care PLL_READY interrupt already enabled PLL_ERROR interrupt already enabled PDN_DONE_INT is don't care 40 Enable ASP interrupts Interrupt Mask 2. 0xF0011 0x07 ASP_OVFL_INT_MASK ASP_ERROR_INT_MASK ASP_LATE_INT_MASK ASP_EARLY_INT_MASK ASP_NOLRCK_INT_MASK Reserved 111 Enable ASP_OVFL interrupt Enable ASP_ERROR interrupt Enable ASP_LATE interrupt Enable ASP_EARLY interrupt Enable ASP_NOLRCK interrupt 41 Enable DSD and DoP interrupts Interrupt Mask 5. 0xF0014 0x01 DSD_STUCK_INT_MASK DSD_INVAL_A_INT_MASK DSD_INVAL_B_INT_MASK DSD_SILENCE_A_INT_MASK DSD_SILENCE_B_INT_MASK DSD_RATE_ERROR_INT_MASK DOP_MRK_DET_INT_MASK DOP_ON_INT_MASK Enable DSD_STUCK interrupt Enable DSD_INVAL_A interrupt Enable DSD_INVAL_B interrupt Enable DSD_SILENCE_A interrupt Enable DSD_SILENCE_B interrupt Enable DSD_RATE_ERROR interrupt Enable DOP_MRK_DET interrupt Disable DOP_ON interrupt Example 5-10. DoP Playback with PLL in Mono Mode (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

42 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000). 43 Set MCLK source and frequency System Clocking Control. 0x10006 0x05 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 MCLK Frequency is set to 22.5792 MHz MCLK Source is set to PLL 44 Wait for at least 150 µs. 45 Enable ASP clocks Pad Interfac e Configuration. 0x1000D 0x02 Reserved XSP_3ST ASP_3ST 0000 00 XSP Interface status is don't care (set to default) Enable serial clocks in Master Mode 46 Power up DAC Refer to Ex. 5-4 for DSD power-up sequence. Note that in Step 1 of Ex. 5-4, use HH = BF for DoP over ASP interface. Example 5-10. DoP Playback with PLL in Mono Mode (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

82 DS1156F1

5.12.7 Switching MCLK Frequency

Ex. 5-11 shows steps necessary to switch the MCLK frequency in order to play audio at a different sample rate that is no longer an integer divide of current MCLK. It makes the following assumptions:

• The CS43198 is already powered up and out of reset.
• MCLK_INT is 22.5792 MHz, an d the sample rate is an integer divide of MCLK.
• ASP is used for audio delivery and PDN_HP = 0.

5.12.8 Headphone Detection

Ex. 5-12 shows steps necessary to detect the presence of a headphone. It makes the following assumptions:

• The CS43198 is already powered up and out of reset.
• The HP Detect register is not configured. Example 5-11. Sequence for Switching MCLK Frequency STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION 1 Power down PCM Refer to Ex. 5-1 for PCM power-down sequence

2 Switch MCLK Source to RCO

3 Set MCLK Source to RCO System Clocking Control 1. 0x10006 0x06 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 Frequency of MCLK_INT is don't care MCLK source set to RCO 4 Wait for 150 µs. 5 Switch to a different MCLK Frequency. As suming new MCLK frequency is 24.576MHz.

6 Change MCLK_INT frequency to

System Clocking Control 1. 0x10006 0x02 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 MCLK_INT frequency set to 24.576 MHz 7 Configure ASP for appropriate sample rate, bit size and clock m ode. Unmute PCM CHA and CHB outputs. Enable appropriate interrupts 8 Switch MCLK source to direct MCLK m ode System Clocking Control 1. 0x10006 0x0 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 MCLK_INT frequency set to 24.576 MHz MCLK source set to direct MCLK mode 9 Wait at least 150 µs. 10 Power up ASP Power Down Control. 0x20000 data(0x20000) AND (0xBF) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x Enable ASP data pins XTAL is already enabled 11 Power up DAC Refer to Ex. 5-3 for PCM power-up sequence Example 5-12. Sequence for Headphone Detection STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION 1 Read Interrupt Status 1 register (0xF0000) to clear any sticky bits. 2 Read HP Status register (0xD000 1) to clear any sticky bits. 3 Enable HPDETECT interrupts Interrupt Mask 1. 0xF0010 data (0xF0010) AND 0x9F DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK x x x x x x Enable HPDETECT interrupts 4 Configure HP Detect parameters HP Detect. 0xD0000 0x04 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 0 0 Rising edge debounce time set to 0 ms Falling edge debounce time set to 500 ms

5 Enable HP Detect HP Detect. 0xD0000 data (0xD0000) OR (0xC0) HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved x x x xx Enable headphone detection 6 Wait for interrupt. Check if HPDETECT_PLUG_INT or HPDETECT_UNP LUG_INT is set in the Interrupt Status 1 register (0xF0000). Example 5-12. Sequence for Headphone Detection (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

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5.12.9 DoP and PCM Mixing

Ex. 5-13 shows steps necessary to mix DoP and PCM. The XSP is in clock master receiving DoP data with LRCLK at 176.4 kHz and SCLK at 8.4672 MHz. The ASP is clock master receiving PCM data with LRCLK at 44.1 kHz and SCLK at 2.8224 MHz. Example 5-13. DoP and PCM Mixing STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms strength (assuming River Crystal at 22.5792 MHz) Crystal Setting. 0x20052 0x04 Reserved XTAL_IBIAS 0000 0 100 Bias current set to 12.5 µA 5 Enable XTAL interrupts Interrupt Mask 1. 0xF0010 0xE7 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK Enable XTAL_READY interrupt Enable XTAL_ERROR interrupt 6 Start XTAL Power Down Control. 0x20000 0xF6 PDN_XSP PDN_XSP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Power up XTAL driver 7 Playback DoP audio. Assuming 64

• Fs DSD stream 8 Configure XSP interface for DoP input. 9 Set sample bit size. Serial Po rt Sample Bit Size. 0x1000C 0x05 Reserved XSP_SPSIZE ASP_SPSIZE 0000 XSP sample bit size is set to 24 bits ASP sample bit size is set to 24 bits 10 Set XSP Numerator XSP Numerator 1. 0x40020 0x03 XSP_N_LSB 0x03 LSB of XSP sample rate fractional divide numerator XSP Numerator 2. 0x40021 0x00 XSP_N_MSB 0x00 MSB of XSP sample rate fractional divide numerator 11 Set XSP Denominator XSP Denominator 1. 0x40022 0x08 XSP_M_LSB 0x08 LSB of XSP sample rate fractional divide denominator XSP Denominator 2. 0x40023 0x00 XSP_M_MSB 0x00 MSB of XSP sample rate fractional divide denominator 12 Set XSP LRCK high Time XSP LRCK High Time 1. 0x40024 0x17 XSP_LCHI_LSB 0x17 LSB of XSP LRCK high time duration XSP LRCK High Time 2. 0x40025 0x00 XSP_LCHI_MSB 0x00 MSB of XSP LRCK high time duration 13 Set XSP LRCK period XSP LRCK Period 1. 0x40026 0x2F XSP_LCPR_LSB 0x2F LSB of XSP LRCK period XSP LRCK Period 2. 0x40027 0x00 XSP_LCPR_MSB 0x00 MSB of XSP LRCK period 14 Configure XSP Clock XSP Clock Configuration. 0x40028 0x1C Reserved XSP_M/SB XSP_SCPOL_OUT XSP_SCPOL_IN XSP_LCPOL_OUT XSP_LCPOL_IN 000 Set XSP port to be Master Set output SCLK polarity Input SCLK polarity is don’t care Set Output LRCLK polarity Input LRCLK polarity is don’t care 15 Configure XSP Frame XSP Frame Configuration. 0x40029 0x0A Reserved XSP_STP XSP_5050 XSP_FSD 000 010 Configure XSP port to accept I 2S input

16 Set XSP Channel Location XSP Channel 1 Location. 0x60000 0x00 XSP_RX_CH1 0x00 XSP Channel 1 starts on SCLK0 XSP Channel 2 Location. 0x60001 0x00 XSP_RX_CH2 0x00 XSP Channel 2 starts on SCLK0

17 Set XSP Channel Size and

XSP Channel 1 Size and Enable. 0x6000A 0x06 Reserved XSP_RX_CH1_AP XSP_RX_CH1_EN XSP_RX_CH1_RES 0000 XSP Channel 1 Active Phase XSP Channel 1 Enable XSP Channel 1 Size is 24 bits XSP Channel 2 Size and Enable. 0x6000B 0x0E Reserved XSP_RX_CH2_AP XSP_RX_CH2_EN XSP_RX_CH2_RES 0000 XSP Channel 2 Active Phase XSP Channel 2 Enable XSP Channel 2 Size is 24 bits

18 Configure DSD Processor

19 Configure DSD Volume DSD Volume A. 0x70001 0x00 DSD_VOLUME_A 0x00 Channel A volume set to 0 dB

20 Configure DSD path Signal

DSD Processor Path Signal Control 1. 0x70002 0xCC DSD_RAMP_UP DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B DSD Volume B equals DSD volume A Immediate change Mute occurs after 256 repeated 8-bit DSD mute patterns Mute happens only when mute pattern is detected in both channels Function is disabled Function is disabled 21 Configure DSD Interface DSD Interface Configuration. 0x70003 0x00 Reserved DSD_M/SB DSD_PM_EN DSD_PM_SEL 0000 0 DSD_M/SB is don’t care Function is disabled Function is disabled

22 Configure DSD path Signal

DSD Processor Path Signal Control 2. 0x70004 0x70 Reserved DSD_PRC_SRC DSD_EN Reserved DSD_SPEED STA_DSD_DET INV_DSD_DET Set source of DSD processor to XSP Enable DSD playback Set DSD clock speed to 64

• FS Static DSD detection disabled Invalid DSD detection disabled

DSD Processor Path Signal Control 3. 0x70006 0xC0 DSD_ZERODB DSD_HPF_EN Reserved SIGCTL_DSDEQPCM DSD_INV_A DSD_INV_B DSD_SWAP_CHAN DSD_COPY_CHAN DSD stream volume setting Enable DSD HPF Function is disabled Function is disabled Function is disabled Function is disabled Function is disabled 24 Configure DAC Output for 1.732 Vrms 25 Configure Class H Amplifier Class H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 111 Output Signal determines voltage level High Voltage Mode enabled Using Internal VCPFILT source. 26 Set DAC output to full scale Analog Output Control 1. 0x80000 0x30 Reserved Reserved OUT_FS Reserved Reserved Reserved +1dB_EN Set DAC output to Full Scale (1.732 Vrms) Example 5-13. DoP and PCM Mixing (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

86 DS1156F1

27 Headphone Detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved HP detect enabled HP detect input is not inverted Tip Sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms

28 Enable Interrupts

29 Read Interrupt Status 1 register (0xF0000), Interrupt Status 2 register (0xF0001) and Interrupt Status 5 register (0xF0004) to clear sticky bits

30 Enable Headphone Detect

Interrupt Mask 1. 0xF0010 0x99 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK DAC_OVFL_INT is don’t care Unmask HPDETECT_PLUG interrupt Unmask HPDETECT_UNPLUG interrupt XTAL_READY_INT is don’t care XTAL_ERROR_INT is don’t care PLL_READY Interrupt is already unmasked PLL_ERROR Interrupt is already unmasked PDN_DONE_INT is don’t care 31 Enable XSP Interrupts Interrupt Mask 2. 0xF0011 0x07 XSP_OVFL_INT_MASK XSP_ERROR_INT_MASK XSP_LATE_INT_MASK XSP_EARLY_INT_MASK XSP_NOLRCK_INT_MASK Reserved 111 Enable XSP_OVFL interrupt Enable XSP_ERROR interrupt Enable XSP_LATE interrupt Enable XSP_EARLY interrupt Enable XSP_NOLRCK interrupt

32 Enable DSD and DoP

Interrupt Mask 5. 0xF0014 0x01 DSD_STUCK_INT_MASK DSD_INVAL_A_INT_MASK DSD_INVAL_B_INT_MASK DSD_SILENCE_A_INT_MASK DSD_SILENCE_B_INT_MASK DSD_RATE_ERROR_INT_MASK DOP_MRK_DET_INT_MASK DOP_ON_INT_MASK Enable DSD_STUCK interrupt Enable DSD_INVAL_A interrupt Enable DSD_INVAL_B interrupt Enable DSD_SILENCE_A interrupt Enable DSD_SILENCE_B interrupt Enable DSD_RATE_ERROR interrupt Enable DOP_MRK_DET interrupt Disable DOP_ON interrupt

33 Set MCLK Source and

System Clocking Control. 0x10006 0x04 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 MCLK Frequency is set to 22.5792 MHz MCLK Source is set to XTAL

34 Wait for at least 150 µs

35 Enable XSP Clocks Pad Interface Configuration. 0x1000D 0x01 Reserved XSP_3ST ASP_3ST 0000 00 ASP Interface status is don’t care (set to default) Enable XSP serial clocks in master mode 36 Enable XSP and CLKOUT Power Down Control. 0x20000 0x74 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Enable XSP Data pins and CLKOUT XTAL is already enabled 37 Apply the DSD Power-up Sequence in Ex. 5-4. Note that in Step 1 of Ex. 5-4, use HH = 7F for DoP over XSP interface.

38 Enable ASP

39 Set ASP sample rate Serial Port Sample Rate. 0x1000B 0x01 Reserved ASP_SPRATE 0000 0001 Set sample rate to 44.1 kHz 40 Set ASP sample bit size Serial Port Sample Bit Size. 0x1000C 0x04 Reserved XSP_SPSIZE ASP_SPSIZE 0000

00 ASP sample bit size set to 32 bits

41 Set ASP Numerator ASP Numerator 1. 0x40010 0x01 ASP_N_LSB 0x01 LSB of ASP sample rate fractional divide numerator ASP Numerator 2. 0x40011 0x00 ASP_N_MSB 0x00 MSB of ASP sample rate fractional divide numerator 42 Set ASP Denominator ASP Denominator 1. 0x40012 0x08 ASP_M_LSB 0x08 LSB of ASP sample rate fractional divide denominator ASP Denominator 2. 0x40013 0x00 ASP_M_MSB 0x00 MSB of ASP sample rate fractional divide denominator Example 5-13. DoP and PCM Mixing (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

43 Set ASP LRCK high Time ASP LRCK High Time 1. 0x40014 0x1F ASP_LCHI_LSB 0x1F LSB of ASP LRCK high time duration ASP LRCK High Time 2. 0x40015 0x00 ASP_LCHI_MSB 0x00 MSB of ASP LRCK high time duration 44 Set ASP LRCK period ASP LRCK Period 1. 0x40016 0x3F ASP_LCPR_LSB 0x3F LSB of ASP LRCK period ASP LRCK Period 2. 0x40017 0x00 ASP_LCPR_MSB 0x00 MSB of ASP LRCK period 45 Configure ASP Clock ASP Clock Configuration. 0x40018 0x1C Reserved ASP_M/SB ASP_SCPOL_OUT ASP_SCPOL_IN ASP_LCPOL_OUT ASP_LCPOL_IN 000 Set ASP port to be Master Set output SCLK polarity Input SCLK polarity is don’t care Set Output LRCLK polarity Input LRCLK polarity is don’t care 46 Configure ASP Frame ASP Frame Configuration. 0x40019 0x0A Reserved ASP_STP ASP_5050 ASP_FSD 000 010 Configure ASP port to accept I 2S input 47 Set ASP Channel Location ASP Channel 1 Location. 0x50000 0x00 ASP_RX_CH1 0x00 ASP Channel 1 starts on SCLK0 ASP Channel 2 Location. 0x50001 0x00 ASP_RX_CH2 0x00 ASP Channel 2 starts on SCLK0

48 Set ASP Channel Size and

ASP Channel 1 Size and Enable. 0x5000A 0x07 Reserved ASP_RX_CH1_AP ASP_RX_CH1_EN ASP_RX_CH1_RES 0000 ASP Channel 1 Active Phase ASP Channel 1 Enable ASP Channel 1 Size is 32 bits ASP Channel 2 Size and Enable. 0x5000B 0x0F Reserved ASP_RX_CH2_AP ASP_RX_CH2_EN ASP_RX_CH2_RES 0000 ASP Channel 2 Active Phase ASP Channel 2 Enable ASP Channel 2 Size is 32 bits

49 Setup PCM

50 Configure PCM Filter PCM Filter Option. 0x90000 0x02 FILTER_SLOW_FASTB PHCOMP_LOWLATB NOS Reserved PCM_WBF_EN HIGH_PASS DEEMP_ON High Pass Filter is selected 51 Set Volume for Channel B PCM Volume B. 0x90001 0x0C PCM_VOLUME_B 0x0C Set volume to –6 dB 52 Set Volume for Channel A PCM Volume A. 0x90002 0x0C PCM_VOLUME_A 0x0C Set volume to –6 dB

53 Configure PCM Path Signal

PCM Path Signal Control 1. 0x90003 0xEC PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B Soft ramp down of volume on filter change Volume setting on both channels controlled by PCM_VOLUME_A Enable soft ramp Mute after reception of 8192 samples of 0 or -1. Mute only when AMUTE condition is detected on both channels Function is disabled Function is disabled PCM Path Signal Control 2. 0x90004 0x00 Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 Disable all functions in this register

54 Read interrupt status 2

Interrupt Status 2. 0xF0001 Clear sticky bits Example 5-13. DoP and PCM Mixing (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

88 DS1156F1

55 Enable ASP Interrupts Interrupt Mask 2. 0xF0011 0x07 ASP_OVFL_INT_MASK ASP_ERROR_INT_MASK ASP_LATE_INT_MASK ASP_EARLY_INT_MASK ASP_NOLRCK_INT_MASK Reserved 111 Enable ASP_OVFL interrupt Enable ASP_ERROR interrupt Enable ASP_LATE interrupt Enable ASP_EARLY interrupt Enable ASP_NOLRCK interrupt 56 Enable ASP Clocks Pad Interface Configuration. 0x1000D 0x00 Reserved XSP_3ST ASP_3ST 0000 00 Enable ASP serial clocks 57 Enable ASP Power Down Control. 0x20000 0x24 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Enable ASP

58 Enable PCM/DoP mix

59 Configure DSD Volume DSD Volume A. 0x70001 0x0C DSD_VOLUME_A 0x0C Channel A volume set to 0 dB

60 Prepare for PCM/DoP Mix

DSD and PCM Mixing Control. 0x70005 0x02 Reserved MIX_PCM_PREP MIX_PCM_DSD 0000 00 Enable PCM playback path for DoP Mixing

61 Wait for 6 ms

62 Enable PCM/DoP mix DSD and PCM Mixing Control. 0x70005 0x03 Reserved MIX_PCM_PREP MIX_PCM_DSD 0000 00 Enable PCM/DoP Mixing Example 5-13. DoP and PCM Mixing (Cont.) STEP TASK R EGISTER/BIT FIELDS VALUE DESCRIPTION

6 Register Quick Reference

The registers for each CS43198 module are located at specific base addresses within the 24-bit register address space. The organization of this register space is summarized in Table 6-1. Notes: Default values are shown below the bit field names. The default values in all reserved bits must be preserved.

6.1 Global Registers

6.2 PLL Registers

Table 6-1. Register Base Addresses Base Address Module Reference 0x01 0000 Global Registers Section 6.1 0x03 0000 PLL Registers Section 6.2 0x04 0000 ASP and XSP Registers Section 6.3 0x06 0000 DSD Registers Section 6.4 0x08 0000 Analog Output and PCM Registers Section 6.5 0x0F 0000 Interrupt Status and Mask Registers Section 6.6 A d d r e s s F u n c t i o n 76543210 0x01 0000 Device ID A and B (Read Only) DEVIDA DEVIDB p. 96 01000011 0x01 0001 Device ID C and D (Read Only) DEVIDC DEVIDD p. 96 00011001 0x01 0002 Device ID E (Read Only) DEVIDE — p. 96 10000000 0x01 0004 Revision ID (Read Only) AREVID MTLREVID p. 96 xxxxxxxx 0x01 0005 Subrevision ID (Read Only) SUBREVID p. 96 0 x x x x x x x 0x01 0006 System Clocking Control — MCLK_INT MCLK_SRC_SEL p. 97 00000110 0x01 0007– 0x01 000A Reserved — 00000000 0x01 000B Serial Port Sample Rate —A S P _ S P R A T E p. 97 00000001 0x01 000C Serial Port Sample Bit Size — XSP_SPSIZE ASP_SPSIZE p. 97 00000101 0x01 000D Pad Interface Configuration — XSP_3ST ASP_3ST p. 97 00000011 0x01 000E– 0x01 FFFF Reserved — 00000000 0x02 0000 Power Down Control PDN_XSP PDN_ASP P DN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT — p. 98 11111110 0x02 0001– 0x02 0051 Reserved — 00000000 0x02 0052 Crystal Setting — XTAL_IBIAS p. 98 000 0 0 1 0 0 0x02 0053– 0x03 0000 Reserved — 00000000 A d d r e s s F u n c t i o n 76543210 0x03 0001 PLL Setting 1 — PLL_START p. 99 00000000 0x03 0002 PLL Setting 2 PLL_DIV_FRAC_0 p. 99 00000000 0x03 0003 PLL Setting 3 PLL_DIV_FRAC_1 p. 99 00000000 0x03 0004 PLL Setting 4 PLL_DIV_FRAC_2 p. 99 00000000

90 DS1156F1

6.3 ASP and XSP Registers

0x03 0005 PLL Setting 5 PLL_DIV_INT p. 99 01000000 0x03 0006– 0x03 0007 Reserved — 00000000 0x03 0008 PLL Setting 6 PLL_OUT_DIV p. 100 00010000 0x03 0009 Reserved — 00000000 0x03 000A PLL Setting 7 PLL_CAL_RATIO p. 100 10000000 0x03 000B– 0x03 001A Reserved — 00000000 0x03 001B PLL Setting 8 — — — PLL_MODE — p. 100 00000011 0x03 001C– 0x04 0001 Reserved — 00000000 A d d r e s s F u n c t i o n 76543210 0x04 0002 PLL Setting 9 — PLL_REF_PREDIV p. 100 00000010 0x04 0003 Reserved — 00000000 0x04 0004 CLKOUT Control — CLKOUT_DIV CLKOUT_SEL p. 101 00000000 0x04 0005– 0x04 000F Reserved — 00000000 0x04 0010 ASP Numerator 1 ASP_N_LSB p. 101 00000001 0x04 0011 ASP Numerator 2 ASP_N_MSB p. 101 00000000 0x04 0012 ASP Denominator 1 ASP_M_LSB p. 101 00001000 0x04 0013 ASP Denominator 2 ASP_M_MSB p. 102 00000000 0x04 0014 ASP LRCK High Time ASP_LCHI_LSB p. 102 00011111 0x04 0015 ASP LRCK High Time ASP_LCHI_MSB p. 102 00000000 0x04 0016 ASP LRCK Period 1 ASP_LCPR_LSB p. 102 00111111 0x04 0017 ASP LRCK Period 2 ASP_LCPR_MSB p. 102 00000000 0x04 0018 ASP Clock Configuration — ASP_M/SB ASP_SCPOL_ OUT ASP_SCPOL_ IN ASP_LCPOL_ OUT ASP_LCPOL_ IN p. 103 00001100 0x04 0019 ASP Frame Configuration — ASP_STP ASP_5050 ASP_FSD p. 103 00001010 0x04 001A– 0x04 001F Reserved — 00000000 0x04 0020 XSP Numerator 1 XSP_N_LSB p. 103 00000001 0x04 0021 XSP Numerator 2 XSP_N_MSB p. 104 00000000 0x04 0022 XSP Denominator 1 XSP_M_LSB p. 104 00000010 0x04 0023 XSP Denominator 2 XSP_M_MSB p. 104 00000000 0x04 0024 XSP LRCK High Time XSP_LCHI_LSB p. 104 00011111 0x04 0025 XSP LRCK High Time XSP_LCHI_MSB p. 104 00000000 A d d r e s s F u n c t i o n 76543210

6.4 DSD Registers

0x04 0026 XSP LRCK Period 1 XSP_LCPR_LSB p. 105 00111111 0x04 0027 XSP LRCK Period 2 XSP_LCPR_MSB p. 105 00000000 0x04 0028 XSP Clock Configuration — XSP_M/SB XSP_SCPOL_ OUT XSP_SCPOL_ IN XSP_LCPOL_ OUT XSP_LCPOL_ IN p. 105 00001100 0x04 0029 XSP Frame Configuration — XSP_STP XSP_5050 XSP_FSD p. 105 00001010 0x04 002A– 0x04 FFFF Reserved — 00000000 0x05 0000 ASP Channel 1 Location ASP_RX_CH1 p. 106 00000000 0x05 0001 ASP Channel 2 Location ASP_RX_CH2 p. 106 00000000 0x05 0002– 0x05 0009 Reserved — 00000000 0x05 000A ASP Channel 1 Size and Enable — ASP_RX_ CH1_AP ASP_RX_ CH1_EN ASP_RX_CH1_RES p. 106 00000110 0x05 000B ASP Channel 2 Size and Enable — ASP_RX_ CH2_AP ASP_RX_ CH2_EN ASP_RX_CH2_RES p. 106 00001110 0x05 000C– 0x05 FFFF Reserved — 00000000 A d d r e s s F u n c t i o n 76543210 0x06 0000 XSP Channel 1 Location XSP_RX_CH1 p. 107 00000000 0x06 0001 XSP Channel 2 Location XSP_RX_CH2 p. 107 00000000 0x06 0002– 0x06 0009 Reserved — 00000000 0x06 000A XSP Channel 1 Size and Enable — XSP_RX_ CH1_AP XSP_RX_ CH1_EN XSP_RX_CH1_RES p. 107 00000110 0x06 000B XSP Channel 2 Size and Enable — XSP_RX_ CH2_AP XSP_RX_ CH2_EN XSP_RX_CH2_RES p. 107 00001110 0x06 000C– 0x06 FFFF Reserved — 00000000 0x07 0000 DSD Volume B DSD_VOLUME_B p. 107 01111000 0x07 0001 DSD Volume A DSD_VOLUME_A p. 108 01111000 0x07 0002 DSD Processor Path Signal Control 1 DSD_RAMP_ UP DSD_VOL_ BEQA DSD_SZC — DSD_AMUTE DSD_AMUTE_ BEQA DSD_MUTE_A DSD_MUTE_B p. 108 10101000 0x07 0003 DSD Interface Configuration p. 108 00000000 0x07 0004 DSD Processor Path Signal Control 2 DIR_DSD DSD_PRC_SRC DSD_EN DSD_SPEED STA_DSD_ DET INV_DSD_ DET p. 109 00000010 0x07 0005 DSD and PCM Mixing Control —M I X _ P C M _ PREP MIX_PCM_ DSD p. 109 00000000 0x07 0006 DSD Processor Path Signal Control 3 DSD_ZERODB DSD_HPF_EN — SIGCTL_ DSDEQPCM CHAN DSD_COPY_ CHAN p. 110 01000000 0x07 0007 Direct DSD Path Signal Control — — — DSD_ DIRECT_MC DSD_ DIRECT_GAIN p. 110 00010100 0x07 0008– 0x07 FFFF Reserved — 00000000 A d d r e s s F u n c t i o n 76543210

92 DS1156F1

6.5 Analog Output and PCM Registers

A d d r e s s F u n c t i o n 76543210 0x08 0000 Analog Output Control p. 111 00110000 0x09 0000 PCM Filter Option FILTER_ SLOW_FASTB PHCOMP_ LOWLATB NOS — PCM_WBF_ EN HIGH_PASS DEEMP_ON p. 111 00000010 0x09 0001 PCM Volume B PCM_VOLUME_B p. 112 01111000 0x09 0002 PCM Volume A PCM_VOLUME_A p. 112 01111000 0x09 0003 PCM Path Signal Control 1 PCM_RAMP_ DOWN PCM_VOL_ BEQA PCM_SZC PCM_AMUTE PCM_ AMUTEBEQA PCM_MUTE_A PCM_MUTE_B p. 112 10101000 0x09 0004 PCM Path Signal Control 2 CHAN PCM_COPY_ CHAN p. 113 00000000 0x09 000A Programmable Filter Control 1 SOS1_CTRL SOS2_CTRL FOS_CTRL SOS3_ON — p. 113 00000000 0x09 000B Programmable Filter Control 2 —S O S 1 _ COEFF_CP SOS2_ COEFF_CP FOS_COEFF_ CP p. 113 00000000 0x09 000C p. 114 Programmable Filter Coefficients SOS1_COEFF_B0_LSBYTE 00000000 0x09 000D p. 114 Programmable Filter Coefficients SOS1_COEFF_B0_MSBYTE 10000000 0x09 000E Programmable Filter Coefficients — SOS1_ COEFF_B0_ SIGN p. 114 00000000 0x09 000F p. 114 Programmable Filter Coefficients SOS1_COEFF_B1_LSBYTE 00000000 0x09 0010 p. 114 Programmable Filter Coefficients SOS1_COEFF_B1_MSBYTE 00000000 0x09 0011 Programmable Filter Coefficients — SOS1_ COEFF_B1_ SIGN p. 114 00000000 0x09 0012 p. 114 Programmable Filter Coefficients SOS1_COEFF_B2_LSBYTE 00000000 0x09 0013 p. 114 Programmable Filter Coefficients SOS1_COEFF_B2_MSBYTE 00000000 0x09 0014 Programmable Filter Coefficients — SOS1_ COEFF_B2_ SIGN p. 114 00000000 0x09 0015 p. 114 Programmable Filter Coefficients SOS1_COEFF_A1_LSBYTE 00000000 0x09 0016 p. 114 Programmable Filter Coefficients SOS1_COEFF_A1_MSBYTE 00000000 0x09 0017 Programmable Filter Coefficients — SOS1_ COEFF_A1_ SIGN p. 114 00000000 0x09 0018 p. 114 Programmable Filter Coefficients SOS1_COEFF_A2_LSBYTE 00000000 0x09 0019 p. 114 Programmable Filter Coefficients SOS1_COEFF_A2_MSBYTE 00000000 0x09 001A Programmable Filter Coefficients — SOS1_ COEFF_A2_ SIGN p. 114 00000000 0x09 001B p. 114 Programmable Filter Coefficients SOS2_COEFF_B0_LSBYTE 00000000 0x09 001C p. 114 Programmable Filter Coefficients SOS2_COEFF_B0_MSBYTE 10000000

0x09 001D Programmable Filter Coefficients — SOS2_ COEFF_B0_ SIGN p. 114 00000000 0x09 001E p. 114 Programmable Filter Coefficients SOS2_COEFF_B1_LSBYTE 00000000 0x09 001F p. 114 Programmable Filter Coefficients SOS2_COEFF_B1_MSBYTE 00000000 0x09 0020 Programmable Filter Coefficients — SOS2_ COEFF_B1_ SIGN p. 114 00000000 0x09 0021 p. 114 Programmable Filter Coefficients SOS2_COEFF_B2_LSBYTE 00000000 0x09 0022 p. 114 Programmable Filter Coefficients SOS2_COEFF_B2_MSBYTE 00000000 0x09 0023 Programmable Filter Coefficients — SOS2_ COEFF_B2_ SIGN p. 114 00000000 0x09 0024 p. 114 Programmable Filter Coefficients SOS2_COEFF_A1_LSBYTE 00000000 0x09 0025 p. 114 Programmable Filter Coefficients SOS2_COEFF_A1_MSBYTE 00000000 0x09 0026 Programmable Filter Coefficients — SOS2_ COEFF_A1_ SIGN p. 114 00000000 0x09 0027 p. 114 Programmable Filter Coefficients SOS2_COEFF_A2_LSBYTE 00000000 0x09 0028 p. 114 Programmable Filter Coefficients SOS2_COEFF_A2_MSBYTE 00000000 0x09 0029 Programmable Filter Coefficients — SOS2_ COEFF_A2_ SIGN p. 114 00000000 0x09 002A p. 114 Programmable Filter Coefficients SOS3_COEFF_B0_LSBYTE 00000000 0x09 002B p. 114 Programmable Filter Coefficients SOS3_COEFF_B0_MSBYTE 10000000 0x09 002C Programmable Filter Coefficients — SOS3_ COEFF_B0_ SIGN p. 114 00000000 0x09 002D p. 114 Programmable Filter Coefficients SOS3_COEFF_B1_LSBYTE 00000000 0x09 002E p. 114 Programmable Filter Coefficients SOS3_COEFF_B1_MSBYTE 00000000 0x09 002F Programmable Filter Coefficients — SOS3_ COEFF_B1_ SIGN p. 114 00000000 0x09 0030 p. 114 Programmable Filter Coefficients SOS3_COEFF_B2_LSBYTE 00000000 0x09 0031 p. 114 Programmable Filter Coefficients SOS3_COEFF_B2_MSBYTE 00000000 0x09 0032 Programmable Filter Coefficients — SOS3_ COEFF_B2_ SIGN p. 114 00000000 0x09 0033 p. 114 Programmable Filter Coefficients SOS3_COEFF_A1_LSBYTE 00000000 0x09 0034 p. 114 Programmable Filter Coefficients SOS3_COEFF_A1_MSBYTE 00000000 0x09 0035 Programmable Filter Coefficients — SOS3_ COEFF_A1_ SIGN p. 114 00000000 A d d r e s s F u n c t i o n 76543210

94 DS1156F1

6.6 Interrupt Status and Mask Registers

p. 114 Programmable Filter Coefficients SOS3_COEFF_A2_LSBYTE 00000000 0x09 0037 p. 114 Programmable Filter Coefficients SOS3_COEFF_A2_MSBYTE 00000000 0x09 0038 Programmable Filter Coefficients — SOS3_ COEFF_A2_ SIGN p. 114 00000000 0x09 0039 p. 114 Programmable Filter Coefficients FOS_COEFF_B0_LSBYTE 00000000 0x09 003A p. 114 Programmable Filter Coefficients FOS_COEFF_B0_MSBYTE 10000000 0x09 003B Programmable Filter Coefficients — FOS_COEFF_ B0_SIGN p. 114 00000000 0x09 003C p. 114 Programmable Filter Coefficients FOS_COEFF_B1_LSBYTE 00000000 0x09 003D p. 114 Programmable Filter Coefficients FOS_COEFF_B1_MSBYTE 00000000 0x09 003E Programmable Filter Coefficients — FOS_COEFF_ B1_SIGN p. 114 00000000 0x09 003F p. 114 Programmable Filter Coefficients FOS_COEFF_A1_LSBYTE 00000000 0x09 0040 p. 114 Programmable Filter Coefficients FOS_COEFF_A1_MSBYTE 00000000 0x09 0041 Programmable Filter Coefficients — FOS_COEFF_ A1_SIGN p. 114 00000000 0x0B 0000 Class H Control — ADPT_PWR HV_EN EXT_VCPFILT p. 114 00011110 0x0D 0000 HP Detect HPDETECT_CTRL HPDETECT_ INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME — p. 114 00000100 0x0D 0001 HP Status (Read Only) — HPDETECT_ PLUG_DBC HPDETECT_ UNPLUG_DBC p. 115 00000000 0x0D 0002– 0x0E 001A Reserved — 00000000 0x0E 001B– 0x0E FFFF Reserved — 00000000 A d d r e s s F u n c t i o n 76543210 0x0F 0000 Interrupt Status 1 (Read Only) DAC_OVFL_ INT HP_DETECT_ PLUG_INT HP_DETECT_ UNPLUG_INT XTAL_ READY_INT XTAL_ ERROR_INT PLL_READY_ INT PLL_ERROR_ INT PDN_DONE_ INT p. 115 00000000 0x0F 0001 Interrupt Status 2 (Read Only) ASP_OVFL_ INT ASP_ERROR_ INT ASP_LATE_ INT ASP_EARLY_ INT ASP_ NOLRCK_INT p. 116 00000000 0x0F 0002 Interrupt Status 3 (Read Only) XSP_OVFL_ INT XSP_ERROR_ INT XSP_LATE_ INT XSP_EARLY_ INT XSP_ NOLRCK_INT p. 116 00000000 0x0F 0003 Reserved — 00000000 0x0F 0004 Interrupt Status 5 (Read Only) DSD_STUCK_ INT DSD_INVAL_ A_INT DSD_INVAL_ B_INT DSD_ SILENCE_A_ INT DSD_ SILENCE_B_ INT DSD_RATE_ ERROR_INT DOP_MRK_ DET_INT DOP_ON_INT p. 117 00000000 0x0F 0005– 0x0F 000F Reserved — 00000000 0x0F 0010 Interrupt Mask 1 DAC_OVFL_ INT_MASK HP_DETECT_ PLUG_INT_ MASK HP_DETECT_ UNPLUG_ INT_MASK XTAL_ READY_INT_ MASK XTAL_ ERROR_INT_ MASK PLL_READY_ INT_MASK PLL_ERROR_ INT_MASK PDN_DONE_ INT_MASK p. 117 11111111 A d d r e s s F u n c t i o n 76543210

0x0F 0011 Interrupt Mask 2 ASP_OVFL_ INT_MASK ASP_ERROR_ INT_MASK ASP_LATE_ INT_MASK ASP_EARLY_ INT_MASK ASP_ NOLRCK_ INT_MASK p. 118 11111111 0x0F 0012 Interrupt Mask 3 XSP_OVFL_ INT_MASK XSP_ERROR_ INT_MASK XSP_LATE_ INT_MASK XSP_EARLY_ INT_MASK XSP_ NOLRCK_ INT_MASK p. 118 11111111 0x0F 0003 Reserved — 00000000 0x0F 0014 Interrupt Mask 5 DSD_STUCK_ INT_MASK DSD_INVAL_ A_INT_MASK DSD_INVAL_ B_INT_MASK DSD_ SILENCE_A_ INT_MASK DSD_ SILENCE_B_ INT_MASK DSD_RATE_ ERROR_INT_ MASK DOP_MRK_ DET_INT_ MASK DOP_ON_ INT_MASK p. 119 11111111 0x0F 0015– 0x0F FFFF Reserved — 00000000 0x10 0000 ASP Master Mode Slew Rate Control p. 119 00101010 0x10 0001 XSP Master Mode Slew Rate Control p. 120 00101010 A d d r e s s F u n c t i o n 76543210

96 DS1156F1

7 Register Descriptions

All registers are read/write, except for the device’s ID, revision, and status registers, which are read only. The following tables describe bit assignments. The default state of each bit after a power-up sequence or reset is listed in each bit description. All reserved bits must maintain their default state.

7.1 Global Registers

7.1.1 Device ID A and B Address 0x10000

7:4 DEVIDA Part number first digit: 4 3:0 DEVIDB Part number second digit: 3

7.1.2 Device ID C and D Address 0x10001

7:4 DEVIDC Part number third digit: 1 3:0 DEVIDD Part number fourth digit: 9

7.1.3 Device ID E Address 0x10002

DEVIDE — D e f a u l t 10000000 Bits Name Description 7:4 DEVIDE Part number fifth digit: 8 3:0 — Reserved

7.1.4 Revision ID Address 0x10004

7:4 AREVID Alpha revision. CS43198 alpha revision level. AREVID and MTLREVID from the complete device revision ID (e.g., A0, B2). 3:0 MTLREVID Metal revision. CS43198 metal revision level. AREVID and MTLREVID from the complete device revision ID (e.g., A0, B2).

7.1.5 Subrevision ID Address 0x10005

7:0 SUBREVID CS43198 subrevision level.

7.1.6 System Clocking Control Address 0x10006

— MCLK_INT MCLK_SRC_SEL D e f a u l t 00000110 Bits Name Description 7:3 — Reserved 2 MCLK_INT The frequency of internal MCLK. 0 Internal MCLK is expected to be 24.576 MHz 1 (Default) Internal MCLK is expected to be 22.5792 MHz 1:0 MCLK_SRC_ SEL Select the source of internal MCLK.

00 Direct MCLK/XTAL Mode

01 PLL Mode

10 (Default) RCO Mode

11 Reserved

7.1.7 Serial Port Sample Rate Address 0x1000B

— ASP_SPRATE D e f a u l t 00000001 Bits Name Description 7:4 — Reserved 3:0 ASP_SPRATE ASP sample rate. This register must be programm ed for both Master Mode and Slave Mode operation. If ASP_SPRATE = 384 kHz and the CS43198 operates in Master Mode, MCLK_INT is required to be 24.576 MHz. For all other rates, MCLK_INT can be either 22.5792 MHz or 24.576 MHz. 0000 32 kHz 0001 (Default) 44.1 kHz 0010 48 kHz 0011 88.2 kHz 0100 96 kHz 0101 176.4 kHz 0110 192 kHz 0111 352.8 kHz 1000 384 kHz 1001–1111 Reserved

7.1.8 Serial Port Sample Bit Size Address 0x1000C

— XSP_SPSIZE ASP_SPSIZE D e f a u l t 00000101 Bits Name Description 7:4 — Reserved 3:2 XSP_SPSIZE XSP sample bit size. 00 32 bits 01 (Default) 24 bits 10–11 Reserved 1:0 ASP_SPSIZE ASP sample bit size. 00 32 bits 01 (Default) 24 bits 10 16 bits 11 8 bits

7.1.9 Pad Interface Configuration Address 0x1000D

— XSP_3ST ASP_3ST D e f a u l t 00000011 Bits Name Description 7:2 — Reserved

98 DS1156F1

1 XSP_3ST Determines the state of the XSP cl ock drivers when in Master Mode. When in Slave Mode, the serial port clocks are inputs, whose function is not affected by this bit. Before setting an xSP_3ST bit, the associated serial port must be powered down and not powered up until the xSP_3ST bit is cleared. 0 When in Master Mode, serial port clocks are active. 1 (Default) When in Master Mode, serial port clocks are Hi-Z. 0 ASP_3ST Determines the state of the ASP clock drivers when in Ma ster Mode. When in Slave Mode, the serial port clock pins are inputs, whose function is not affected by this bit. Before setting an xSP_3ST bit, the associated serial port must be powered down and not powered up until the xSP_3ST bit is cleared. 0 When in Master Mode, serial port clocks are active. 1 (Default) When in Master Mode, serial port clocks are Hi-Z.

7.1.10 Power Down Control Address 0x20000

PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT — D e f a u l t 11111110 Bits Name Description 7 PDN_XSP XSP input path power control. Configures XSP SDIN path power state. 0 Powered up. 1 (Default) Powered down. 6 PDN_ASP ASP input path power control. Configures ASP SDIN path power state. 0 Powered up. 1 (Default) Powered down. 5 PDN_DSDIF DSD interface power control. Sets the power state of the DSD interface block. 0 Powered up. 1 (Default) Powered down. 4 PDN_HP Power down AOUTx. 0 Powered up. The DACx are powered up. 1 (Default) Powered down. The DACx are powered down. When this bit is set, the audio outputs are soft ramped to mute. 3 PDN_XTAL Power down crystal oscillator. 0 Powered up. The XTAL driver is powered up to start generating MCLK. 1 (Default) Powered down. The XTAL driver is powered down. 2 PDN_PLL PLL output power control. Sets the power state of the PLL block. 0 Powered up. 1 (Default) Powered down. PLL block is powered down. 1P D N _ CLKOUT CLKOUT output power control. Sets the power state of the CLOCKOUT output.

0 Powered up

1 (Default) Powered down. CLKOUT are driven low. 0— R e s e r v e d

7.1.11 Crystal Setting Address 0x20052

— XTAL_IBIAS D e f a u l t 00000100 Bits Name Description 7:3 — Reserved 2:0 XTAL_IBIAS Crystal bias current strength. 010 15.0 µA 100 (Default) 12.5 µA 110 7.5 µA Others Reserved Bits Name Description

7.2 PLL Registers

7.2.1 PLL Setting 1 Address 0x30001

— PLL_START D e f a u l t 00000000 Bits Name Description 7:1 — Reserved 0 PLL_START PLL start bit. Enable PLL output after it has been properly configured. 0 (Default) PLL is not started

1 PLL is started

7.2.2 PLL Setting 2 Address 0x30002

PLL_DIV_FRAC_0 D e f a u l t 00000000 Bits Name Description 7:0 PLL_DIV_ FRAC_0 PLL fractional portion of divide ratio LSB. There are 3 bytes of PLL feedback divider fraction portion and this is LSB byte; 0000 0000 (Default)

7.2.3 PLL Setting 3 Address 0x30003

PLL_DIV_FRAC_1 D e f a u l t 00000000 Bits Name Description 7:0 PLL_DIV_ FRAC_1 PLL fractional portion of divide ratio middle byte; e.g., 0xFF means (2 -9 + 2-10 + …+2 -16). 0000 0000 (Default)

7.2.4 PLL Setting 4 Address 0x30004

PLL_DIV_FRAC_2 D e f a u l t 00000000 Bits Name Description 7:0 PLL_DIV_ FRAC_2 PLL fractional portion of divide ratio MSB; e.g., 0xFF means (2-1 + 2-2 + …+2 -8). 0000 0000 (Default)

7.2.5 PLL Setting 5 Address 0x30005

PLL_DIV_INT D e f a u l t 01000000 Bits Name Description 7:0 PLL_DIV_INT PLL integer portion of divide ra tio. Integer portion of PLL feedback divider. 0100 0000 (Default)

100 DS1156F1

7.2.6 PLL Setting 6 Address 0x30008

PLL_OUT_DIV D e f a u l t 00010000 Bits Name Description 7:0 PLL_OUT_ DIV Final PLL clock output divide value. 0001 0000 (Default)

7.2.7 PLL Setting 7 Address 0x3000A

PLL_CAL_RATIO D e f a u l t 10000000 Bits Name Description 7:0 PLL_CAL_ RATIO 1000 0000 (Default)

7.2.8 PLL Setting 8 Address 0x3001B

— PLL_MODE — D e f a u l t 00010011 Bits Name Description 7:2 — Reserved 1 PLL_MODE 500/512 factor used in PLL frequency calculation equation, Eq. 4-1.

0 No bypass

1 (Default) Bypass 0— R e s e r v e d

7.2.9 PLL Setting 9 Address 0x40002

— PLL_REF_PREDIV D e f a u l t 00000010 Bits Name Description 7:2 — Reserved 1:0 PLL_REF_ PREDIV PLL reference divide select.

00 Divide by 1

01 Divide by 2

10 (Default) Divide by 4

11 Divide by 8

7.3 ASP and XSP Registers

7.3.1 CLKOUT Control Address 0x40004

— CLKOUT_DIV CLKOUT_SEL D e f a u l t 00000000 Bits Name Description 7:5 — Reserved 4:2 CLKOUT_DIV Divider setting on internal MCLK path to CLKOUT. 000 (Default) Divide by 2

001 Divide by 3

010 Divide by 4

011 Divide by 8

100–111 Reserved 1:0 CLKOUT_SEL Select the source of CLKOUT. 00 (Default) XTAL/MCLK path

01 PLL output path

10–11 Reserved

7.3.2 ASP Numerator 1 Address 0x40010

ASP_N_LSB D e f a u l t 00000001 Bits Name Description 7:0 ASP_N_LSB The value in this register cannot be changed while the serial port is powered up. ASP sample rate fractional divide numerator LSB. Along with ASP_M_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) ASP_N = 1

7.3.3 ASP Numerator 2 Address 0x40011

ASP_N_MSB D e f a u l t 00000000 Bits Name Description 7:0 ASP_N_MSB The value in this register cannot be changed while the serial port is powered up. ASP sample rate fractional divide numerator MSB. Along with ASP_M_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) ASP_N = 1

7.3.4 ASP Denominator 1 Address 0x40012

ASP_M_LSB D e f a u l t 00001000 Bits Name Description 7:0 ASP_M_LSB The value in this register cannot be changed while the serial port is powered up. ASP sample rate fractional divide denominator LSB. Along with ASP_N_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) ASP_M = 8

102 DS1156F1

7.3.5 ASP Denominator 2 Address 0x40013

ASP_M_MSB D e f a u l t 00000000 Bits Name Description 7:0 ASP_M_MSB The value in this register cannot be changed while the serial port is powered up. ASP sample rate fractional divide denominator LSB. Along with ASP_N_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) ASP_M = 8

7.3.6 ASP LRCK High Time 1 Address 0x40014

ASP_LCHI_LSB D e f a u l t 00011111 Bits Name Description 7:0 ASP_LCHI_ LSB The value in this register cannot be changed while the serial port is powered up. ASP LRCK high duration, in units of ASP_SCLK periods stored in ASP_LCHI_MSB/LSB. This value must be less than ASP_LCPR. (Default) ASP_LCHI = 31

7.3.7 ASP LRCK High Time 2 Address 0x40015

ASP_LCHI_MSB D e f a u l t 00000000 Bits Name Description 7:0 ASP_LCHI_ MSB The value in this register cannot be changed while the serial port is powered up. ASP LRCK high duration, in units of ASP_SCLK periods stored in ASP_LCHI_MSB/LSB. This value must be less than ASP_LCPR. (Default) ASP_LCHI = 31

7.3.8 ASP LRCK Period 1 Address 0x40016

ASP_LCPR_LSB D e f a u l t 00111111 Bits Name Description 7:0 ASP_LCPR_ LSB The value in this register cannot be changed while the serial port is powered up. ASP LRCK period, in units of ASP_SCLK periods stored in ASP_LCPR_MSB/LSB. (Default) ASP_LCPR = 63

7.3.9 ASP LRCK Period 2 Address 0x40017

ASP_LCPR_MSB D e f a u l t 00000000 Bits Name Description 7:0 ASP_LCPR_ MSB The value in this register cannot be changed while the serial port is powered up. ASP LRCK period, in units of ASP_SCLK periods stored in ASP_LCPR_MSB/LSB. (Default) ASP_LCPR = 63

7.3.10 ASP Clock Configuration Address 0x40018

—A S P _ M / S B ASP_SCPOL_ OUT ASP_SCPOL_ IN ASP_LCPOL_ OUT ASP_LCPOL_ IN D e f a u l t 00001100 Bits Name Description 7:5 — Reserved 4 ASP_M/SB ASP port master or slave configuration. 0 (Default) Slave Mode (input)

1 Master Mode (output)

3A S P _ S C P O L _ OUT ASP SCLK output drive polarity. 0N o r m a l 1 (Default) Inverted 2A S P _ S C P O L _ IN ASP SCLK input polarity (pad to logic). 0N o r m a l 1 (Default) Inverted

1 ASP_LCPOL_

ASP LRCK output drive polarity. 0 (Default) Normal 1I n v e r t e d

0 ASP_LCPOL_

ASP LRCK input polarity (pad to logic). 0 (Default) Normal 1I n v e r t e d

7.3.11 ASP Frame Configuration Address 0x40019

— ASP_STP ASP_5050 ASP_FSD D e f a u l t 00001010 Bits Name Description 7:5 — Reserved 4 ASP_STP ASP start phase. Controls which LRCK/FSYNC phase starts a frame. 0 (Default) The frame begins when LRCK/FSYNC transitions from high to low

1 The frame begins when LRCK/FSYNC transitions from low to high

3 ASP_5050 ASP LRCK fixed 50/50 duty cycle. 0 Programmable duty cycle per ASP_LCHI and ASP_LCPR. 1 (Default) Fixed 50% duty cycle 2:0 ASP_FSD ASP frame start delay (units of ASP_SCLK periods). 000 0 delay 001 0.5 delay 010 (Default) 1.0 delay ... 101 2.5 delay 110–111 Reserved

7.3.12 XSP Numerator 1 Address 0x40020

XSP_N_LSB D e f a u l t 00000001 Bits Name Description 7:0 XSP_N_LSB The value in this register cannot be changed while the serial port is powered up. XSP sample rate fractional divide numerator LSB. Along with XSP_M_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) XSP_N = 1

104 DS1156F1

7.3.13 XSP Numerator 2 Address 0x40021

XSP_N_MSB D e f a u l t 00000000 Bits Name Description 7:0 XSP_N_MSB The value in this register cannot be changed while the serial port is powered up. XSP sample rate fractional divide numerator MSB. Along with XSP_M_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) XSP_N = 1

7.3.14 XSP Denominator 1 Address 0x40022

XSP_M_LSB D e f a u l t 00000010 Bits Name Description 7:0 XSP_M_LSB The value in this register cannot be changed while the serial port is powered up. XSP sample rate fractional divide denominator LSB. Along with XSP_N_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) XSP_M = 2

7.3.15 XSP Denominator 2 Address 0x40023

XSP_M_MSB D e f a u l t 00000000 Bits Name Description 7:0 XSP_M_MSB The value in this register cannot be changed while the serial port is powered up. XSP sample rate fractional divide denominator MSB. Along with XSP_N_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) XSP_M = 2

7.3.16 XSP LRCK High Time 1 Address 0x40024

XSP_LCHI_LSB D e f a u l t 00011111 Bits Name Description 7:0 XSP_LCHI_ LSB The value in this register cannot be changed while the serial port is powered up. XSP LRCK high duration, in units of XSP_SCLK periods stored in XSP_LCHI_LSB/MSB. This value must be less than XSP_LCPR. (Default) XSP_LCHI = 31

7.3.17 XSP LRCK High Time 2 Address 0x40025

XSP_LCHI_MSB D e f a u l t 00000000 Bits Name Description 7:0 XSP_LCHI_ MSB The value in this register cannot be changed while the serial port is powered up. XSP LRCK high duration, in units of XSP_SCLK periods stored in XSP_LCHI_LSB/MSB. This value must be less than XSP_LCPR. (Default) XSP_LCHI = 31

7.3.18 XSP LRCK Period 1 Address 0x40026

XSP_LCPR_LSB D e f a u l t 00111111 Bits Name Description 7:0 XSP_LCPR_ LSB The value in this register cannot be changed while the serial port is powered up. XSP LRCK period, in units of XSP_SCLK periods stored in XSP_LCPR_LSB/MSB. (Default) XSP_LCPR = 63

7.3.19 XSP LRCK Period 2 Address 0x40027

XSP_LCPR_MSB D e f a u l t 00000000 Bits Name Description 7:0 XSP_LCPR_ MSB The value in this register cannot be changed while the serial port is powered up. XSP LRCK period, in units of XSP_SCLK periods stored in XSP_LCPR_LSB/MSB. (Default) XSP_LCPR = 63

7.3.20 XSP Clock Configuration Address 0x40028

—X S P _ M / S B XSP_SCPOL_ OUT XSP_SCPOL_ IN XSP_LCPOL_ OUT XSP_LCPOL_ IN D e f a u l t 00001100 Bits Name Description 7:5 — Reserved 4 XSP_M/SB XSP port master or slave configuration. 0 (Default) Slave Mode (input) 3X S P _ S C P O L _ OUT XSP SCLK output drive polarity. 0N o r m a l 1 (Default) Inverted 2X S P _ S C P O L _ IN XSP SCLK input polarity (pad to logic). 0N o r m a l 1 (Default) Inverted

1 XSP_LCPOL_

XSP LRCK output drive polarity. 0 (Default) Normal 1I n v e r t e d

0 XSP_LCPOL_

XSP LRCK input polarity (pad to logic). 0 (Default) Normal 1I n v e r t e d

7.3.21 XSP Frame Configuration Address 0x40029

— XSP_STP XSP_5050 XSP_FSD D e f a u l t 00001010 Bits Name Description 7:5 — Reserved 4 XSP_STP XSP start phase. Controls which LRCK/FSYNC phase starts a frame. 0 (Default) The frame begins when LRCK/FSYNC transitions from high to low 3 XSP_5050 XSP LRCK fixed 50/50 duty cycle.

0 Programmable duty cycle per XSP_LCHI and XSP_LCPR

1 (Default) Fixed 50% duty cycle

106 DS1156F1

2:0 XSP_FSD XSP frame start delay (units of XSP_SCLK periods). 000 0 delay 001 0.5 delay 010 (Default) 1.0 delay ... 101 2.5 delay 110–111 Reserved

7.3.22 ASP Channel 1 and 2 Location Address 0x50000, 0x50001

ASP_RX_CH1 ASP_RX_CH2 D e f a u l t 00000000 Bits Name Description 7:0 ASP_RX_CHn ASP Rx channel n location. Sets the location in ASP_SCLK periods of the ASP Rx channel n from the start of the TDM frame. 0x00 Start on SCLK 0 ... 0xFF Start on SCLK 255 Defaults are 0x00.

7.3.23 ASP Channel 1 Size and Enable Address 0x5000A

— ASP_RX_CH1_ AP ASP_RX_CH1_ EN ASP_RX_CH1_RES D e f a u l t 00000110

7.3.24 ASP Channel 2 Size and Enable Address 0x5000B

— ASP_RX_CH2_ AP ASP_RX_CH2_ EN ASP_RX_CH2_RES D e f a u l t 00001110 Bits Name Description 7:4 — Reserved

3 ASP_RX_

CHn_AP ASP RX channel n active phase. Valid only in 50/50 mode (ASP_5050 = 1). 0 (Default when n = 1) In 50/50 mode, channel data is input when LRCK/FSYNC is low 1 (Default when n = 2) In 50/50 mode, channel data is input when LRCK/FSYNC is high

2 ASP_RX_

CHn_EN ASP RX channel n enable. Configures the state of the data for the ASP on channel n. The same rule applies to CHx_EN. 0 (Default) Input channel data is not propagated to the internal data path

1 Input channel data is propagated to the internal data path

1:0 ASP_RX_ CHn_RES ASP RX channel n size (in bits). Sets the output resolution of the ASP RX channel n samples. 00 8 bits per sample 01 16 bits per sample 10 (Default) 24 bits per sample 11 32 bits per sample Bits Name Description

7.4 DSD Registers

7.3.25 XSP Channel 1 and 2 Location Address 0x60000, 0x60001

XSP_RX_CH1 XSP_RX_CH2 D e f a u l t 00000000 Bits Name Description 7:0 XSP_RX_CH n XSP Rx channel n location. Sets the location in XSP_SCLK periods of the XSP Rx channel n from the start of the TDM frame. 0x00 Start on SCLK 0 ... 0xFF Start on SCLK 255 Defaults are 0x00.

7.3.26 XSP Channel 1 Size and Enable Address 0x6000A

— XSP_RX_CH1_ AP XSP_RX_CH1_ EN XSP_RX_CH1_RES D e f a u l t 00000110

7.3.27 XSP Channel 2 Size and Enable Address 0x6000B

— XSP_RX_CH2_ AP XSP_RX_CH2_ EN XSP_RX_CH2_RES D e f a u l t 00001110 Bits Name Description 7:4 — Reserved

3 XSP_RX_

CHn_AP XSP Rx channel n active phase. Valid only in 50/50 mode (XSP_5050 = 1). 0 (Default when n = 1) In 50/50 mode, channel data is input when LRCK/FSYNC is low 1 (Default when n = 2) In 50/50 mode, channel data is input when LRCK/FSYNC is high

2 XSP_RX_

CHn_EN XSP Rx channel n enable. Configures the state of the data for the XSP on channel n. The same rule applies to CHx_EN.

0 Input channel data is not propagated to the internal data path

1 (Default) Input channel data is propagated to the internal data path 1:0 XSP_RX_ CHn_RES XSP Rx channel n size (in bits). Sets the output resolution of the XSP Rx channel n samples. 00 8 bits per sample 01 16 bits per sample 10 (Default) 24 bits per sample 11 32 bits per sample

7.4.1 DSD Volume B Address 0x70000

DSD_VOLUME_B D e f a u l t 01111000 Bits Name Description 7:0 DSD_ VOLUME_B Digital volume control registers for DSD processor channel B. It allows independent control of the signal level in 1/2 dB increments from 0 dB. Volume settings are decoded as shown below. The volume changes are dictated by the DSD_ SZC bit. The same condition applies to DSD_VOLUME_A setting. 0000 0000 0 dB 0000 0001 –0.5 dB ... 01111000 –60 dB (Default) ... 1111 1110 –127 dB 1111 1111 Digital mute

108 DS1156F1

7.4.2 DSD Volume A Address 0x70001

DSD_VOLUME_A D e f a u l t 01111000 Bits Name Description 7:0 DSD_ VOLUME_A Digital volume control registers for channel A. See DSD_VOLUME_B for description.

7.4.3 DSD Processor Path Signal Control 1 Address 0x70002

DSD_RAMP_ UP DSD_VOL_ BEQA DSD_SZC — DSD_AMUTE DSD_AMUTE_ BEQA DSD_MUTE_A DSD_MUTE_B D e f a u l t 10101000 Bits Name Description

7 DSD_RAMP_

Soft volume ramp-up after error. An unmute is performed after any error is recovered.

0 Immediate unmute is performed

1 (Default) Unmute behavior is controlled by DSD_SZC settings 6D S D _ V O L _ BEQA DSD_VOLUME_B equals DSD_VOLUME_A. 0 (Default) Volume setting of both channels in DSD processor are controlled independently 1 Volume setting of both channels are controlled by DSD_VOLUME_A. DSD_VOLUME_B is ignored 5 DSD_SZC Soft ramp control.

0 Immediate change

1 (Default) Soft ramp 4— R e s e r v e d 3 DSD_AMUTE DSD auto mute.

0 Function disabled

1 (Default) Mute occurs after reception of 256 repeated 8-bit DSD mute patterns. A single bit not fitting the repeated pattern releases the mute. Detection and muting is done independently for each channel. 2D S D _ AMUTE_ BEQA DSD Processor Auto mute channel B equals channel A. 0 (Default) Function disabled

1 Only mute when both channels AMUTE conditions are detected

1D S D _ M U T E _ A DSD Processor Channel A mute. 0 (Default) Function is disabled 1 Channel output is muted. Muting function is affected by the DSD_SZC bit 0D S D _ M U T E _ B DSD Processor Channel B mute. 0 (Default) Function is disabled. 1 Channel output is muted. Muting function is affected by the DSD_SZC bit.

7.4.4 DSD Interface Configuration Address 0x70003

7:3 — Reserved 2 DSD_M/SB DSD clock master or Slave Mode. 0 (Default) Slave Mode

1 Master Mode

1 DSD_PM_EN DSD phase modulation mode. Can only be used when DSD_SPEED = 00 (64•Fs) or 01 (128•Fs). 0 (Default) this function is disabled (DSD normal mode) 1 DSD phase modulation input mode is enabled, and the DSD_PM_SEL bit must be set accordingly. 0 DSD_PM_SEL DSD phase modulation mode select. 0 (Default) The 2x data rate (BCKA) clock must be input to DSD_SCLK for phase modulation mode. 1 The 1x data rate (BCKD) clock must be input to DSD_SCLK for phase modulation mode.

7.4.5 DSD Processor Path Signal Control 2 Address 0x70004

DIR_DSD DSD_PRC_SRC DSD_EN DSD_SPEED STA_DSD_DET INV_DSD_DET D e f a u l t 00000010 Bits Name Description 7 DIR_DSD Enable Direct DSD playback. 0 (Default) Function disabled

1 Direct DSD playback is enabled

6:5 DSD_PRC_ SRC Select the source for DSD processor. 00 (Default) DSD interface

01 Reserved

10 ASP

11 XSP

4 DSD_EN Enable DSD playback. 0 (Default) Function disabled

1 DSD playback is enabled

3:2 DSD_SPEED Setup DSD clock speed. 00 (Default) 64•Fs 01 128•Fs 10 256•Fs. Note that this speed is only supported for DSD Processor Mode. This speed is not supported for Direct DSD mode. 1S T A _ D S D _ DET Static DSD detection. 1 (Default) Static DSD detection is enabled. The DSD processor checks for 28 consecutive zeros or ones and, if detected, sets the DSD_STUCK_INT interrupt status bit and mutes the output until the static condition is cleared. If DSD_AMUTE is enabled, AMUTE will be in effect in this scenario. 0I N V _ D S D _ DET Invalid DSD detection. 0 (Default) Function disabled 1 Invalid DSD detection is enabled. The DSD processor checks for 25 out of 28 bits of the same value and, if detected, sets the DSD_INVAL_A_INT and/or DSD_INVAL_B_INT interrupt status bits.

7.4.6 DSD and PCM Mixing Control Address 0x70005

— MIX_PCM_ PREP MIX_PCM_ DSD D e f a u l t 00000000 Bits Name Description 7:2 — Reserved 1M I X _ P C M _ PREP Enable PCM playback path for PCM and DSD mixing. This bit must be set prior to setting MIX_PCM_DSD. Disable this bit after disabling MIX_PCM_DSD. This mode requires DSD_EN to be enabled and DSD_PRC_SRC set to receive DSD through either the DSD interface or XSP. 0 (Default) Function disabled

1 Enable PCM playback path for PCM and DSD mixing

0M I X _ P C M _ DSD Enable PCM stream mixing into DSD stream. This bit must be set only after MIX_PCM_PREP is enabled. Disable this bit prior to disabling MIX_PCM_PREP bit. This mode requires DSD_EN to be enabled and DSD_PRC_SRC set to receive DSD through either the DSD interface or XSP . 0 (Default) Function disabled

1 Enable PCM stream mixing into the DSD stream

110 DS1156F1

7.4.7 DSD Processor Path Signal Control 3 Address 0x70006

DSD_ZERODB DSD_HPF_EN — SIGCTL_ DSDEQPCM DSD_INV_A DSD_INV_B DSD_SWAP_ CHAN DSD_COPY_ CHAN D e f a u l t 01000000 Bits Name Description 7D S D _ ZERODB Setting on DSD stream volume to match PCM stream volume. 0 (Default) The SACD +3.1-dB level (71% modulation index) matches PCM 0 dB full scale. 1 The SACD 0-dB reference level (50% modulation index) matches PCM 0 dB full scale. 6 DSD_HPF_EN Enable the high pass filter in the DSD processor.

0 HPF disabled

1 (Default) Enable HPF in the DSD processor 5— R e s e r v e d 4S I G C T L _ DSDEQPCM Enable DSD signal path control register bits to be controlled by PCM setting. DSD setting is ignored. Register bits affected are the following: DSD_RAMP_UP, DSD_VOL_BEQA, DSD_SZC, DSD_AMUTE, DSD_AMUTE_BEQA, DSD_MUTE_A, DSD_MUTE_B, DSD_INV_A, DSD_INV_B, DSD_SWAP_CHAN, DSD_COPY_CHAN After set, each DSD_x register bit is equal to setting of PCM_x register bit. 0 (Default) Function is disabled

1 Function is enabled

3 DSD_INV_A DSD Processor Channel A signal invert. 0 (Default) Function is disabled

1 Signal polarity of channel A is inverted

2 DSD_INV_B DSD Processor Channel B signal invert

0 (Default) the function is disabled

1 Signal polarity of channel B is inverted

1 DSD_SWAP_

Swap channels A and B at the input. This bit takes effect before DSD_COPY_CHAN and DSD_INV_x. 0 (Default) Function disabled

1 Enable channel A and B swapping

0D S D _ C O P Y _ CHAN Copy channel A to channel B. This bit takes effect after DSD_SWAP_CHAN, but before DSD_INV_x. 0 (Default) Function disabled

1 Enable copy A to B function

7.4.8 Direct DSD Pa th Signal Control Address 0x70007

—— DSD_DIRECT_ MC DSD_DIRECT_ GAIN —— D e f a u l t 00010100 Bits Name Description 7:4 — Reserved 3D S D _ DIRECT_MC Enables Direct DSD path magnitude compensation. When enabled, this filter has a low-gain output and is unaffected by the setting of DSD_DIRECT_GAIN. This bit is only effective if DIR_DSD = 1 and DSD_SPEED = 00. Otherwise, the bit setting will be ignored. 0 (Default) Disable 64•Fs magnitude compensation

1 Enable 64•Fs magnitude compensation

2D S D _ DIRECT_ GAIN Setup Direct DSD path gain settings. This bit is only effective if DIR_DSD = 1 and DSD_SPEED = 00 or 01. This bit is ignored when DSD_DIRECT_MC = 1.

0 Low gain

1 (Default) High gain 1:0 — Reserved

7.5 Analog Output and PCM Registers

7.5.1 Analog Output Control 1 Address 0x80000

7:6 — Reserved 5:4 OUT_FS Output full scale setting. This setting must only be updated when PDN_HP is set.

00 Reserved

10 1.41 V 11 (Default) 1.73 V 3:1 — Reserved 0 +1dB_EN If selected, output full scale voltage is at 2 V. This setting is only in effect when OUT_FS = 11 and HV_EN = 1. This setti ng is ignored if OUT_FS and HV_EN is set to any other settings. It should only be updated when PDN_HP is set. 0 (Default) Output full scale voltage is determined by OUT_FS setting. 1 Output full scale voltage is at 2 V.

7.5.2 PCM Filter Option Address 0x90000

FILTER_ SLOW_FASTB PHCOMP_ LOWLATB NOS — PCM_WBF_EN HIGH_PASS DEEMP_ON D e f a u l t 00000010 Bits Name Description 7F I L T E R _ SLOW_ FASTB Fast and slow filter selection. 0 (Default) Fast filter is selected. 1 Slow filter is selected.

6 PHCOMP_

Low-latency and phase-compensated filter selection 0 (Default) Low-latency is selected. 1 Phase-compensated filter is selected. 5 NOS Nonoversampling emulation mode on. When enabled, FILTER_SLOW_FASTB and PHCOMP_LOWLATB are ignored. 0 (Default) NOS emulation mode is off. 1 NOS emulation mode is on. 4:3 — Reserved 2P C M _ W B F _ EN Wideband flatness mode enable. This should only be used in PCM playback when xSP sample rate is at 192 kHz. This bit must be changed while PDN_HP is set. 0 (Default) Wideband flatness mode disabled

1 Wideband flatness mode enabled

1 HIGH_PASS High-pass filter enable. 0 High-pass filter is disabled. 1 (Default) High-pass filter is selected. 0 DEEMP_ON Deemphasis filter on. 0 (Default) Deemphasis for 44.1 kHz is disabled. 1 Deemphasis for 44.1 kHz is enabled.

112 DS1156F1

7.5.3 PCM Volume B Address 0x90001

PCM_VOLUME_B D e f a u l t 01111000 Bits Name Description 7:0 PCM_ VOLUME_B Digital volume control registers for PCM channel B. It allows independent control of the signal level in 1/2 dB increments from 0 to –127.5 dB. Volume settings are decoded as shown below. The volume changes are dictated by the PCM_SZC bits. The same rule applies to PCM_VOLUME_A setting. 0000 0000 0 dB 0000 0001 –0.5 dB ... 01111000 –60 dB (Default) ... 1111 1110 –127 dB 1111 1111 Digital mute

7.5.4 PCM Volume A Address 0x90002

PCM_VOLUME_A D e f a u l t 01111000 Bits Name Description 7:0 PCM_ VOLUME_A Digital volume control registers for channel A. See PCM_VOLUME_B for description.

7.5.5 PCM Path Signal Control 1 Address 0x90003

PCM_RAMP_ DOWN PCM_VOL_ BEQA PCM_SZC PCM_AMUTE PCM_ AMUTEBEQA PCM_MUTE_A PCM_MUTE_B D e f a u l t 10101000 Bits Name Description 7P C M _ R A M P _ DOWN Soft volume ramp-down before filter mode change. A mute is performed before filter mode change and an unmute is performed after executing the filter mode change.

0 Immediate mute is performed prior to executing a filter mode change

1 (Default) This mute and unmute is controlled by PCM_SZC. 6P C M _ V O L _ BEQA PCM_VOLUME_B equals PCM_VOLUME_A. 0 (Default) Volume setting of both channels are controlled independently. 1 Volume setting of both channels are controlled by PCM_VOLUME_A. PCM_VOLUME_B is ignored. 5:4 PCM_SZC Soft ramp and zero cross control.

00 Immediate change

01 In PCM mode, zero cross change

10 (Default) Soft ramp

11 In PCM mode, soft ramp and zero crossings

3 PCM_AMUTE PCM auto mute. 1 (Default) Mute occurs after reception of 8,192 consecutive audio samples of static +1, 0, or –1. A single sample of non-static data releases the mute. Detection and muting is done independently for each channel. 2P C M _ AMUTEBEQA Auto mute channel B equals channel A. 0 (Default) Function disabled. 1 Only mute when both channels AMUTE conditions are detected.

1 PCM_MUTE_

A Channel A mute. 0 (Default) Function is disabled. 1 Channel output is muted. Muting function is affected by the PCM_SZC bits.

0 PCM_MUTE_

B Channel A mute. 0 (Default) Function is disabled. 1 Channel output is muted. Muting function is affected by the PCM_SZC bits.

7.5.6 PCM Path Signal Control 2 Address 0x90004

PCM_COPY_ CHAN D e f a u l t 00000000 Bits Name Description 7:4 — Reserved 3 PCM_INV_A Channel A signal invert. 0 (Default) Function is disabled 2 PCM_INV_B Channel B signal invert. 0 (Default) the function is disabled 1P C M _ S W A P _ CHAN Swap channels A and B at the input. This bit takes effect before PCM_COPY_CHAN. 0 (Default) Function disabled 0P C M _ C O P Y _ CHAN Copy channel A to channel B. This bit takes effect after PCM_SWAP_CHAN. 0 (Default) Function disabled

7.5.7 Programmable Filter Control 1 Address 0x9 000A

SOS1_CTRL SOS2_CTRL FOS_CTRL SOS3_ON — D e f a u l t 00000000 Bits Name Description 7:6 SOS1_CTRL SOS1 filter control. 00 SOS1 filter disabled. 01 Reserved. 10 Reserved. 11 SOS1 filter enabled. 5:4 SOS2_CTRL SOS2 filter control. 00 SOS2 filter disabled. 01 Reserved. 10 Reserved. 11 SOS2 filter enabled. 3:2 FOS_CTRL FOS filter control. 00 FOS filter disabled. 01 Reserved. 10 Reserved. 11 FOS filter enabled. 1 SOS3_ON SOS3 filter enable. 0 (default) SOS3 filter is disabled. 1 SOS3 filter is enabled. 0— R e s e r v e d

7.5.8 Programmable Filter Control 2 Address 0x9 000B

— SOS1_ COEFF_CP SOS2_ COEFF_CP FOS_COEFF_ CP — D e f a u l t 00000000 Bits Name Description 7:4 — Reserved 3S O S 1 _ COEFF_CP Enable SOS1 coefficients from the control port. When the filter is not in use, this bit must be cleared to 0. 0 (default) SOS1 coefficients from the control port are not effective. 1 SOS1 coefficients from the control port are effective.

114 DS1156F1

2S O S 2 _ COEFF_CP Enable SOS2 coefficients from the control port. When the filter is not in use, this bit must be cleared to 0. 0 (default) SOS2 coefficients from the control port are not effective. 1 SOS2 coefficients from the control port are effective.

1 FOS_COEFF_

Enable FOS coefficients from the control port. When the filter is not in use, this bit must be cleared to 0. 0 (default) FOS coefficients from the control port are not effective. 1 FOS coefficients from the control port are effective. 0— R e s e r v e d

7.5.9 Programmable Fi lter Coefficients Address 0x9000C–0x90041

xOSx_COEFF_xx_LSBYTE xOSx_COEFF_xx_MSBYTE — xOSx_COEFF_ xx_SIGN Default See Quick Reference Bits Name Description 7:0 See Quick Reference Refer to Section 4.13 for details. Format is Q1.17.

7.5.10 Class H Control Address 0xB0000

— ADPT_PWR HV_EN EXT_VCPFILT D e f a u l t 00011110 Bits Name Description 7:5 — Reserved 4:2 ADPT_PWR Adaptive power adjustment. Config ures how power to line output amplifiers adapts to the output signal level.

000 Reserved

001 Fixed, Mode 0 (±VP_LDO)

010 Fixed, Mode 1 (±VCP)

011–110 Reserved 111 (Default) Adapt to signal. The output signal dynamically determines the voltage level. 1 HV_EN High voltage mode enable. 0 Function disabled (VP_LDO = 2.6V) 1 (Default) Function enabled (VP_LDO = 3.0 V). This requires VP min to be 3.3 V. Also, this mode only applies to load 600  and above. 0 EXT_VCPFILT External VCP_FILT± voltage mode. 0 (Default) Function disabled 1 When enabled, VCP_FILT± voltages can be provided externally at ±3.0 V. See power sequencing/timing requirement in related functional description.

7.5.11 HP Detect Address 0xD0000

HPDETECT_CTRL HPDETECT_ INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME — D e f a u l t 00000100 Bits Name Description 7:6 HPDETECT_ CTRL HP detect control. Configures operation of the HP detect circuit. The internal weak current source pull-up is enabled in all modes. 00 (Default) Disabled. The HP detect digital circuit is powered down and does not report to the status registers (HPDETECT_PLUG_INT and HPDETECT_UNPLUG_INT are also cleared). 01–10 Reserved

11 Enabled

5 HPDETECT_

HP detect invert. Can be used to invert the signal from the HP detect circuit. 0 (Default) Not inverted 1I n v e r t e d Bits Name Description

7.6 Interrupt Status and Mask Registers

4:3 HPDETECT_ RISE_DBC_ TIME Tip sense rising debounce time. 00 (Default) 0 ms 01 250 ms 10 500 ms 11 1.0 s 2:1 HPDETECT_ FALL_DBC_ TIME Tip sense falling debounce time. 00 0 ms 01 250 ms 10 (Default) 500 ms 11 1.0 s 0— R e s e r v e d

7.5.12 HP Status Address 0xD0001

— HPDETECT_ PLUG_DBC HPDETECT_ UNPLUG_DNC — D e f a u l t 00000000 Bits Name Description 7— R e s e r v e d

6 HPDETECT_

PLUG_DBC HPDETECT plug debounce status. Setting HPDETECT_INV reverses the meaning of this bit. 0 (Default) Condition is not present

1 Condition is present

UNPLUG_ DBC HPDETECT unplug debounce status. Setting HPDETECT_INV reverses the meaning of this bit. 0 (Default) Condition is not present 4:0 — Reserved

7.6.1 Interrupt Status 1 Address 0xF0000

DAC_OVFL_ INT HPDETECT_ PLUG_INT HPDETECT_ UNPLUG_INT XTAL_READY_ INT XTAL_ ERROR_INT PLL_READY_ INT PLL_ERROR_ INT PDN_DONE_ INT D e f a u l t 00000000 Bits Name Description

7 DAC_OVFL_

Status indicating DAC modulator overflow condition is detected.

0 Condition is not present

PLUG_INT Status indicating HP plug event is detected. UNPLUG_INT Status indicating HP unplug event is detected. 4X T A L _ READY_INT Status indicating XTAL is ready after PDN_XTAL is cleared. 3X T A L _ ERROR_INT Status indicating XTAL error condition is detected after PDN_XTAL is cleared.

2 PLL_READY_

Status indicating PLL ready condition is detected after PLL_START is set.

1 PLL_ERROR_

Status indicating PLL error condition is detected after PLL_START is set.

116 DS1156F1

0P D N _ D O N E _ INT Status indicating PDN_HP process is completed after a request.

7.6.2 Interrupt Status 2 Address 0xF0001

ASP_OVFL_ INT ASP_ERROR_ INT ASP_LATE_ INT ASP_EARLY_ INT ASP_ NOLRCK_INT — D e f a u l t 00000000 Bits Name Description

7 ASP_OVFL_

ASP RX request overload. 6A S P _ ERROR_INT ASP RX LRCK error. Logical OR of LRCK early and LRCK late errors.

5 ASP_LATE_

ASP RX LRCK late.

4 ASP_EARLY_

ASP RX LRCK early. 3A S P _ NOLRCK_INT ASP RX no LRCK. 2:0 — Reserved

7.6.3 Interrupt Status 3 Address 0xF0002

XSP_OVFL_ INT XSP_ERROR_ INT XSP_LATE_ INT XSP_EARLY_ INT XSP_ NOLRCK_INT — D e f a u l t 00000000 Bits Name Description

7 XSP_OVFL_

XSP RX request overload. 6X S P _ ERROR_INT XSP RX LRCK error. Logical OR of LRCK early and LRCK late errors.

5 XSP_LATE_

XSP RX LRCK late.

4 XSP_EARLY_

XSP RX LRCK early. 3X S P _ NOLRCK_INT XSP RX no LRCK. 2:0 — Reserved Bits Name Description

7.6.4 Interrupt Status 5 Address 0xF0004

DSD_STUCK_ INT DSD_INVAL_ A_INT DSD_INVAL_ B_INT DSD_ SILENCE_A_ INT DSD_ SILENCE_B_ INT DSD_RATE_ ERROR_INT DOP_MRK_ DET_INT DOP_ON_INT D e f a u l t 00000000 Bits Name Description 7D S D _ S T U C K _ INT At least one DSD input channel is stuck at 0 or 1.

6 DSD_INVAL_

A_INT Channel A input exceeds the max peak level of +3.1-dB SACD.

5 DSD_INVAL_

B_INT Channel B input exceeds the max peak level of +3.1-dB SACD. 4D S D _ SILENCE_A_ INT Channel A contains DSD silence pattern. 3D S D _ SILENCE_B_ INT Channel B contains DSD silence pattern. 2D S D _ R A T E _ ERROR_INT DSD data rate related error is detected. The rate of the input DSD stream is not as described in DSD_SPEED setting. If missed DoP header(s) is detected, the interrupt will also be triggered. 1D O P _ M R K _ DET_INT A valid sequence of DoP markers has been detected. 0D O P _ O N _ I N TThe DoP decoder is powered up.

7.6.5 Interrupt Mask 1 Address 0xF0010

DAC_OVFL_ INT_MASK HPDETECT_ PLUG_INT_ MASK HPDETECT_ UNPLUG_INT_ MASK XTAL_READY_ INT_MASK XTAL_ ERROR_INT_ MASK PLL_READY_ INT_MASK PLL_ERROR_ INT_MASK PDN_DONE_ INT_MASK D e f a u l t 11111111 Bits Name Description INT_MASK DAC_OVFL_INT mask.

0 Unmasked

1 (Default) Masked PLUG_INT_ MASK HP_DETECT_PLUG_INT mask. 1 (Default) Masked UNPLUG_ INT_MASK HP_DETECT_UNPLUG_INT mask. 1 (Default) Masked 4X T A L _ READY_INT_ MASK XTAL_READY_INT mask. 1 (Default) Masked 3X T A L _ ERROR_INT_ MASK XTAL_ERROR_INT mask. 1 (Default) Masked INT_MASK PLL_READY_INT mask. 1 (Default) Masked

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INT_MASK PLL_ERROR_INT mask. 1 (Default) Masked 0P D N _ D O N E _ INT_MASK PDN_DONE_INT mask. 1 (Default) Masked

7.6.6 Interrupt Mask 2 Address 0xF0011

ASP_OVFL_ INT_MASK ASP_ERROR_ INT_MASK ASP_LATE_ INT_MASK ASP_EARLY_ INT_MASK ASP_ NOLRCK_INT_ MASK D e f a u l t 11111111 Bits Name Description INT_MASK ASP_OVFL_INT mask. 1 (Default) Masked 6A S P _ ERROR_INT_ MASK ASP_ERROR_INT mask. 1 (Default) Masked INT_MASK ASP_LATE_INT mask. 1 (Default) Masked INT_MASK ASP_EARLY_INT mask. 1 (Default) Masked 3A S P _ NOLRCK_ INT_MASK ASP_NOLRCK_INT mask. 1 (Default) Masked 2:0 — Reserved

7.6.7 Interrupt Mask 3 Address 0xF0012

XSP_OVFL_ INT_MASK XSP_ERROR_ INT_MASK XSP_LATE_ INT_MASK XSP_EARLY_ INT_MASK XSP_ NOLRCK_INT_ MASK D e f a u l t 11111000 Bits Name Description INT_MASK XSP_OVFL_INT mask. 1 (Default) Masked 6X S P _ ERROR_INT_ MASK XSP_ERROR_INT mask. 1 (Default) Masked INT_MASK XSP_LATE_INT mask. 1 (Default) Masked INT_MASK XSP_EARLY_INT mask. 1 (Default) Masked 3X S P _ NOLRCK_ INT_MASK XSP_NOLRCK_INT mask. 1 (Default) Masked 2:0 — Reserved Bits Name Description

7.6.8 Interrupt Mask 5 Address 0xF0014

DSD_STUCK_ INT_MASK DSD_INVAL_ A_INT_MASK DSD_INVAL_ B_INT_MASK DSD_ SILENCE_A_ INT_MASK DSD_ SILENCE_B_ INT_MASK DSD_RATE_ ERROR_INT_ MASK DOP_MRK_ DET_INT_ MASK DOP_ON_INT_ MASK D e f a u l t 11111111 Bits Name Description 7D S D _ S T U C K _ INT_MASK DSD_STUCK_INT mask. 1 (Default) Masked A_INT_MASK DSD_INVAL_A_INT mask. 1 (Default) Masked B_INT_MASK DSD_INVAL_B_INT mask. 1 (Default) Masked 4D S D _ SILENCE_A_ INT_MASK DSD_SILENCE_A_INT mask. 1 (Default) Masked 3D S D _ SILENCE_B_ INT_MASK DSD_SILENCE_B_INT mask. 1 (Default) Masked 2D S D _ R A T E _ ERROR_INT_ MASK DSD_RATE_ERROR_INT mask. 1 (Default) Masked 1D O P _ M R K _ DET_INT_ MASK DOP_MRK_DET_INT mask. 1 (Default) Masked 0D O P _ O N _ INT_MASK DOP_ON_INT mask. 1 (Default) Masked

7.6.9 ASP Master Mode Slew Rate Control Address 0x10 0000

—S C L K 1 _ S L E W _ R A T E — D e f a u l t 00101010 Bits Name Description 7:4 — Reserved 3:2 SCLK1_ SLEW_RATE SCLK1 slew rate control. 01 Recommended drive strength for clock rate higher than 12.288 MHz 10 (Default) Recommended drive strength for clock rate 12.288 MHz or lower. 1:0 — Reserved

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7.6.10 XSP Master Mode Slew Rate Control Address 0x10 0001

— DSDCLK_SCLK2_SLEW_RATE — D e f a u l t 00101010 Bits Name Description 7:4 — Reserved 3:2 DSDCLK_ SCLK2_ SLEW_RATE DSDCLK/SCLK2 slew rate control. 01 Recommended drive strength for clock rate higher than 12.288 MHz 10 (Default) Recommended drive strength for clock rate 12.288 MHz or lower. 1:0 — Reserved

8 PCB Layout Considerations

The following sections provide general guidelines for PCB layout to ensure the best performance of the CS43198.

8.1 Power Supply

As with any high-resolution converter, the CS43198 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Fig. 2-1 shows the recommended power arrangements with VA and VCP connected to independent clean supplies. VL and VD, which power the digital circuitry, may be run from the shared system logic supply.

8.2 Grounding

Note the following:

• Extensive use of power and ground planes, ground-plane fill in unused areas, and surface-mount decoupling capacitors are recommended.
• Decoupling capacitors must be as clos e as possible to the CS43198 pins.
• To minimize inductance effects, the low-value ceramic ca pacitor must be closest to the pin and mounted on the same side of the board as the CS43198.
• To avoid unwanted coupling into the modulators, all signals, especially clocks, must be isolated from the FILT+ and FILT- pins.
• The FILT+ capacitors must be positioned to mi nimize the electrical path from the pin to VA.
• The FILT– capacitors must be positioned to mi nimize the electrical path from the pin to –VA.
• The VCP_FILT+ and VCP_FILT– capacitors must be positioned to minimize the electrical path from each respective pin to GNDCP.

8.3 REFA and REFB Routing

For best interchannel isolation performance, REFA and REFB must be routed independently to the headphone connector reference pin. The REFA and REFB are electrically connected to system’s ground plane through via at the headphone connector ground pin. Fig. 2-1 illustrates the recommended arrangements. For interfacing the REFA and REFB pins with an IC that performs alternate pinout headset detect functions, both signals must be routed independently to the CS43198’s ground pin connecting the detected headset ground pole. Follow the recommended grounding scheme of the CS43198.

8.4 QFN Thermal Pad

The CS43198 comes in a compact QFN package, the underside of which reveals a large metal pad that serves as a thermal relief to provide maximum heat dissipation. This pad must mate with a matching copper pad on the PCB and must be electrically connected to ground. A series of vias must be used to connect this copper pad to one or more larger ground planes on other PCB layers. For best performance in split-ground systems, connect this thermal pad to GNDA.

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9 Performance Plots

9.1 Digital Filter Response

9.1.1 Combined Filter R esponse—Single Speed (Fs = 32 kHz, Slow Roll-Off)

Figure 9-1. Passband Ripple Figure 9-2. Stopband Attenuation Figure 9-3. Impulse Response—Linear Phase F igure 9-4. Impulse Response—Minimum Phase Figure 9-5. Step Response—Linear Phase Fi gure 9-6. Step Response—Minimum Phase −0.02 −0.015 −0.01 −0.005 0.005 0.01 0.015 0.02 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 500 1000 1500 2000 2500 3000 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 3000 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 3000 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 3000 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V)

9.1.2 Combined Filter Res ponse—Single Speed (Fs = 32 kHz, Fast Roll-Off)

Figure 9-7. Passband Ripple Figure 9-8. Stopband Attenuation Figure 9-9. Impulse Response—Linear Phase F igure 9-10. Impulse Response—Minimum Phase Figure 9-11. Step Response—Linear Phase Figure 9-12. Step Response—Minimum Phase −0.02 −0.015 −0.01 −0.005 0.005 0.01 0.015 0.02 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 500 1000 1500 2000 2500 3000 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 3000 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 3000 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 3000 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V)

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9.1.3 Combined Filter Respons e—Single Speed (Fs = 44.1 a nd 48 kHz, Slow Roll-Off) Figure 9-13. Passband Ripple Figure 9-14. Stopband Attenuation Figure 9-15. Impulse Response—Linear Phase Figure 9-16. Impulse Response—Minimum Phase Figure 9-17. Step Response—Linear Phase Figure 9-18. Step Response—Minimum Phase −0.02 −0.015 −0.01 −0.005 0.005 0.01 0.015 0.02 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 500 1000 1500 2000 2500 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V)

9.1.4 Combined Filter Respons e—Single Speed (Fs = 44.1 a nd 48 kHz, Fast Roll-Off) Figure 9-19. Passband Ripple Figure 9-20. Stopband Attenuation Figure 9-21. Impulse Response—Linear Phase Figure 9-22. Impulse Response—Minimum Phase Figure 9-23. Step Response—Linear Phase Figure 9-24. Step Response—Minimum Phase −0.02 −0.015 −0.01 −0.005 0.005 0.01 0.015 0.02 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 500 1000 1500 2000 2500 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 500 1000 1500 2000 2500 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V)

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9.1.5 Combined Filter Response— Double Speed (Slow Roll-Off)

Figure 9-25. Passband Ripple Figure 9-26. Stopband Attenuation Figure 9-27. Impulse Response—Linear Phase Figure 9-28. Impulse Response—Minimum Phase Figure 9-29. Step Response—Linear Phase Figure 9-30. Step Response—Minimum Phase −0.04 −0.03 −0.02 −0.01 0.01 0.02 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 100 200 300 400 500 600 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 100 200 300 400 500 600 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 100 200 300 400 500 600 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 100 200 300 400 500 600 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V)

9.1.6 Combined Filter Response— Double Speed (Fast Roll-Off)

Figure 9-31. Passband Ripple Figure 9-32. Stopband Attenuation Figure 9-33. Impulse Response—Linear Phase Figure 9-34. Impulse Response—Minimum Phase Figure 9-35. Step Response—Linear Phase Figure 9-36. Step Response—Minimum Phase −0.04 −0.02 0.02 0.04 0.06 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 100 200 300 400 500 600 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 100 200 300 400 500 600 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 100 200 300 400 500 600 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 100 200 300 400 500 600 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V)

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9.1.7 Combined Filter Response— Quad Speed (Slow Roll-Off)

Figure 9-37. Passband Ripple Figure 9-38. Stopband Attenuation Figure 9-39. Impulse Response—Linear Phase Figure 9-40. Impulse Response—Minimum Phase Figure 9-41. Step Response—Linear Phase Figure 9-42. Step Response—Minimum Phase −0.05 −0.04 −0.03 −0.02 −0.01 0.01 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 50 100 150 200 250 300 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 50 100 150 200 250 300 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 50 100 150 200 250 300 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 50 100 150 200 250 300 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V)

9.1.8 Combined Filter Response— Quad Speed (Fast Roll-Off)

Figure 9-43. Passband Ripple Figure 9-44. Stopband Attenuation Figure 9-45. Impulse Response—Linear Phase Figure 9-46. Impulse Response—Minimum Phase Figure 9-47. Step Response—Linear Phase Figure 9-48. Step Response—Minimum Phase −0.05 −0.04 −0.03 −0.02 −0.01 0.01 0.02 0.03 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 50 100 150 200 250 300 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 50 100 150 200 250 300 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 50 100 150 200 250 300 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 50 100 150 200 250 300 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V)

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9.1.9 Combined Filter Response—Octuple Speed

9.1.10 Combined Filter Res ponse—Single Speed (NOS = 1)

Note: 44.1 kHz and 48 kHz only. Figure 9-49. Passband Ripple Figure 9-50. Stopband Attenuation Figure 9-51. Impulse Response Figure 9-52. Step Response Figure 9-53. Passband Ripple Figure 9-54. Stopband Attenuation −0.1 −0.09 −0.08 −0.07 −0.06 −0.05 −0.04 −0.03 −0.02 −0.01 0.01 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 10 20 30 40 50 60 70 80 90 100 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 10 20 30 40 50 60 70 80 90 100 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) −3.5 −2.5 −1.5 −0.5 Frequency (Normalized to Fs) Magnitude (dB) 0 0.5 1 1.5 2 2.5 −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB)

9.1.11 Combined Filter Res ponse—Double Speed (NOS = 1)

Figure 9-55. Impulse Response Figure 9-56. Step Response Figure 9-57. Passband Ripple Figure 9-58. Stopband Attenuation Figure 9-59. Impulse Response Figure 9-60. Step Response 0 50 100 150 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 50 100 150 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) −3.5 −2.5 −1.5 −0.5 Frequency (Normalized to Fs) Magnitude (dB) 0 0.5 1 1.5 2 2.5 −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 10 20 30 40 50 60 70 80 90 100 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 10 20 30 40 50 60 70 80 90 100 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V)

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9.1.12 Combined Filter Res ponse—Quad Speed (NOS = 1)

9.1.13 Combined Filter Res ponse—Wideband Flatness Mode

Figure 9-61. Passband Ripple Figure 9-62. Stopband Attenuation Figure 9-63. Impulse Response Figure 9-64. Step Response Figure 9-65. Magnitude Response −3.5 −2.5 −1.5 −0.5 Frequency (Normalized to Fs) Magnitude (dB) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB) 0 10 20 30 40 50 60 70 80 90 100 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 10 20 30 40 50 60 70 80 90 100 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (Normalized to Fs) Magnitude (dB)

9.1.14 Combined Filter Response—DSD

9.1.15 Highpass Filter and Deemphasis

Figure 9-66. Passband Ripple Figure 9-67. Stopband Attenuation Figure 9-68. Impulse Response Figure 9-69. Step Response Figure 9-70. Highpass Filter for PCM and DSD Paths Figure 9-71. Deemphasis 0 5 10 15 20 25 30 −0.1 −0.09 −0.08 −0.07 −0.06 −0.05 −0.04 −0.03 −0.02 −0.01 0.01 Frequency (NHz) Magnitude (dB) 200 400 600 800 1000 1200 1400 −180 −160 −140 −120 −100 −80 −60 −40 −20 Frequency (NHz) Magnitude (dB) 0 10 20 30 40 50 60 70 80 90 100 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) 0 10 20 30 40 50 60 70 80 90 100 −0.2 0.2 0.4 0.6 0.8 1.2 Time (µs) Normalized Amplitude (V) −30 −25 −20 −15 −10 Frequency (Normalized to Fs) Magnitude (dB) −10 Frequency (Normalized to Fs) Magnitude (dB)

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10.1 40-Pin QFN Package Dimensions Figure 10-1. 40-Pin QFN Package Drawing Table 10-1. 40-Pin QFN Package Dimensions Description Dim Millimeters Minimum Nominal Maximum T o t a l t h i c k n e s s A 0 . 70 . 7 50 . 8 Stand off A1 0 0.035 0.05 Mold thickness A2 — 0.55 — L/F thickness A3 0.203 REF Lead width b 0.15 0.2 0.25 Body size X D 5 BSC YE 5 B S C Lead pitch e 0.4 BSC EP size X J 3.4 3.5 3.6 Y K 3.4 3.5 3.6 Lead length L 0.35 0.4 0.45 Package edge tolerance aaa 0.1 Mold flatness bbb 0.1 Coplanarity ccc 0.08 Lead offset ddd 0.1 Exposed pad offset eee 0.1 Notes:

• Dimensioning and tolerances per ASME Y 14.5M–1995.
• X/Y Dimensions are estimates.
• The Ball 1 location indicator shown above is for illustration purposes only and may not be to scale.
• Dimensioning and tolerances per ASME Y 14.5M–1994.
• Dimension “b” applies to the solder sphere diameter and is measured at the midpoint between the package body and the seating plane.

10.2 42-Ball WLCSP Package Dimensions 10.2 42-Ball WLCSP Package Dimensions

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11 Thermal Characteristics

Notes:

• Natural convection at the maximum recommended operating temperature T A (see Table 3-2)
• Four-layer, 2s2p PCB as specified by JESD51-9 and JESD51-11; dimensions: 101.5 x 114.5 x 1.6 mm
• Thermal parameters as defined by JESD51-12

13 References

• NXP Semiconductors, The I2C-Bus Specification and User Manual (UM10204). http://www.nxp.com/ Table 11-1. Typical JEDEC Four-Layer, 2s2p Board Thermal Characteristics Parameter Symbol WLCSP QFN Units Junction-to-ambient thermal resistance JA 42.3 32.7 °C/W Junction-to-board thermal resistance JB 11.1 8.8 °C/W Junction-to-case thermal resistance JC 0.22 0.92 °C/W Junction-to-board thermal-characterization parameter JB 11.0 8.8 °C/W Junction-to-package-top thermal-characterization parameter JT 0.09 0.23 °C/W Table 12-1. Ordering Information 1 1.The Revision ID fields in Section 7.1.4, “Revision ID,” list the alpha (AREVID) and metal (MTLREVID) revisions. Product Description Package RoHS Compliant Grade Temperature Range Container Order Number CS43198 130-dB, 32-Bit High-Performance DAC with Pseudodifferential Outputs 42-ball WLCSP Yes Commercial –10°C to +70°C Tape and Reel CS43198-CWZR 40-pin QFN Yes Commercial –10°C to +70°C Tray CS43198-CNZ Tape and Reel CS43198-CNZR Table 14-1. Revision History Revision Changes OCT ‘17 Initial release Important: Please check with your Cirrus Logic sales representative to confirm that you are using the latest revision of this document a nd to determine whether there are errata associated with this device.

Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners. DSD and DSD Direct Stream Digital are registered trademarks of Sony Kabushiki TA Sony Corporation. Copyright © 2015–2017 Cirrus Logic, Inc. All rights reserved.