CS4231A

CS4231A ETC | Alldatasheet

Document overview

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Technical content

Features

• Windows Sound SystemTM Compatible Codec
• ADPCM Compression/Decompression
• Extensive Software Support
• MPC Level 2 Compatible Mixer
• Dual DMA Registers support Full Duplex Operation
• On-Chip FIFOs for higher performance
• Selectable Serial Audio Data Port
• Pin Compatible with CS4231/CS4248 General Description The CS4231A includes stereo 16-bit audio converters and complete on-chip filtering for record and playback of 16-bit audio data. In addition, analog mixing and programmable gain and attenuation are included to provide a complete audio subsystem. A selectable se- rial port can pass audio data to and from DSPs or ASICs. Crystal-developed high-performance software drivers for various operating systems are available that support all the CS4231A features including full duplex transfers. The CS4231A is a pin compatible upgrade to the CS4231 and CS4248. ORDERING INFORMATION: CS4231A-KL 0 to 70 °C 68-pin PLCC CS4231A-KQ 0 to 70 °C 100-pin TQFP SEPT ’94 DS139PP2 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 Fax: (512) 445-7581 Parallel Interface, Multimedia Audio Codec Semiconductor Corporation CS4231A This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice.Preliminary Product Information Mute Gain Gain Mux LMIC RMIC LLINE RLINE LAUX1 RAUX1 LOUT ROUT RAUX2 LAUX2 Mute AGND1 AGND2 DAC Attenuate 20dB Gain VREF VREFI VREF XTAL2I XTAL2O Oscillators LFILT RFILT D<7:0> A<1:0> CS WR PDRQ CDRQ PDAK CDAK IRQ DBDIR DBEN XCTL1 XCTL0 Parallel Bus Interface PDWN Mute MIN MOUT Linear µ-law A-law ADPCM Linear µ-law A-law ADPCM DGND3/4/7/8DGND1 DGND2 XTAL1I XTAL1O VD1 VD2 FIFO Samples VD3 VD4

16 Bit Timer

I20,I21 I 16 TEST Audio Data Serial Port I16 Copyright  Crystal Semiconductor Corporation 1994 (All Rights Reserved)

TABLE OF CONTENTS: Power Down - CS4231A

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ANALOG CHARACTERISTICS (TA = 25 °C; VA1, VA2, VD1-VD4 = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD4; 1 kHz Input Sine wave; Conversion Rate = 48 kHz; Measurement Bandwidth is 10 Hz to 20 kHz, 16-bit linear coding.) Parameter* Symbol Min Typ Max Units Analog Input Characteristics - Minimum Gain Setting (0dB); unless otherwise specified. ADC Resolution (Note 1) 16 Bits ADC Differential Nonlinearity (Note 1) ±0.5 LSB Instantaneous Dynamic Range Line Inputs (Note 2) Mic Inputs IDR 80 dB dB Total Harmonic Distortion Line Inputs Mic Inputs THD 0.006 0.01 0.02 0.025 Signal-to-Intermodulation Distortion 90 dB Interchannel Isolation Line to Line Inputs Line to Mic Inputs Line-to-AUX1 Line-to-AUX2 dB dB dB dB Interchannel Gain Mismatch Line Inputs Mic Inputs 0.5 0.5 dB dB Programmable Input Gain Span Line Inputs 21.5 22.5 dB Gain Step Size 1.3 1.5 1.7 dB ADC Offset Error 0 dB gain 10 100 LSB Full Scale Input Voltage: (MGE=1) MIC Inputs (MGE=0) MIC Inputs LINE, AUX1, AUX2, MIN Inputs 0.266 2.66 2.66 0.29 2.9 2.9 0.31 3.1 3.1 V pp Vpp Vpp Gain Drift 100 ppm/°C Input Resistance (Note 1) 20 kΩ Input Capacitance (Note 1) 15 pF Notes: 1. This specification is guaranteed by characterization, no production testing. 2. MGE = 1 and a 10 µF capacitor on the VREF pin. *Parameter definitions are given at the end of this data sheet. Windows and Windows Sound System are registered trademarks of Microsoft Corporation. Specifications are subject to change without notice. CS4231A DS139PP2 3

ANALOG CHARACTERISTICS (Continued) Parameter* Symbol Min Typ Max Units Analog Output Characteristics - Minimum Attenuation (0dB); unless otherwise specified. DAC Resolution 16 Bits DAC Differential Nonlinearity (Note 1) ±0.5 LSB Dynamic Range -Total All Outputs -Instantaneous TDR IDR 80 dB dB Total Harmonic Distortion (Note 3) THD 0.01 0.02 % Signal-to-Intermodulation Distortion 85 dB Interchannel Isolation Line Out (Note 3) 95 dB Interchannel Gain Mismatch Line Out 0.1 0.5 dB Voltage Reference Output 2.0 2.2 2.35 V Voltage Reference Output Current (Note 4) 100 µA DAC Programmable Attenuation Span 93 94.5 dB DAC Attenuation Step Size 0 dB to -81 dB -82.5 dB to -94.5 dB 1.3 1.0 1.5 1.5 1.7 dB dB DAC Offset Voltage 1 10 mV Full Scale Output Voltage: OLB = 0 (Notes 3, 5) OLB = 1 OUT, MOUT 1.8 2.6 2.0 2.8 2.25 3.2 V pp Vpp Gain Drift 100 ppm/°C Deviation from Linear Phase (Note 1) 1 Degree External Load Impedance 10 kΩ Mute Attenuation (0 dB) 80 dB Total Out-of-Band Energy 0.6xFs to 100 kHz (Note 1) -45 dB Audible Out-of-Band Energy 0.6xFs to 22 kHz (Fs=8kHz) -60 dB Power Supply Power Supply Current Digital, Operating Analog, Operating Total Digital, Power Down Analog, Power Down 0.1 0.8 120 mA mA mA mA mA Power Supply Rejection 1 kHz (Note 1) 40 dB Notes: 3. 10 kΩ , 100 pF load. 4. DC current only. If dynamic loading exists, then the voltage reference output must be buffered or the performance of ADCs and DACs will be degraded. 5. All mixer and output gain tables assume the output level bit, OLB, in indirect register 16 (I16) is set, wherein the input and output full scale values are equal. When OLB=0, the output value is 3 dB below the input value, given no gain or attenuation. CS4231A

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ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.) Parameter Symbol Min Max Units Power Supplies: Digital Analog VD1-VD4 VA1,VA2 -0.3 -0.3 6.0 6.0 V V Input Current per Pin (Except Supply Pins) -10.0 +10.0 mA Output Current per Pin (Except Supply Pins) -50 +50 mA Analog Input Voltage -0.3 VA+0.3 V Digital Input voltage -0.3 VD+0.3 V Ambient Temperature (Power Applied) -55 +125 °C Storage Temperature -65 +150 °C Warning: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with repect to 0V.) Parameter Symbol Min Typ Max Units Power Supplies: Digital Analog VD1-VD4 VA1,VA2 4.75 4.75 5.0 5.0 5.25 5.25 V V Operating Ambient Temperature T A 02 5 7 0 ° C AUXILIARY INPUT MIXERS (TA = 25 °C; VA1, VA2, VD1-VD4 = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD4; 1 kHz Input Sine wave) Parameter Symbol Min Typ Max Units Mixer Gain Range Span LINE, AUX1, AUX2 (Note 6) MIN 46.5 dB dB Step Size LINE, AUX1, AUX2 MIN 1.3 2.3 1.5 3.0 1.7 3.4 dB dB Notes: 6. All mixer gain values assume OLB=1. If OLB=0, the analog output will be 3 dB below listed settings. CS4231A DS139PP2 5

DIGITAL CHARACTERISTICS (TA = 25°C; VA1, VA2, VD1-VD4 = 5V; AGND1, AGND2, DGND1-DGND4, DGND7, DGND8 = 0V.) Parameter Symbol Min Max Units High-level Input Voltage Digital Inputs XTAL1I, XTAL2I, PDWN VIH 2.0 VD-1.0 VD+0.3 VD+0.3 V V Low-level Input Voltage V IL -0.3 0.8 V High-level Output Voltage: D<7:0> I 0 = -16.0 mA All Others I 0 = -1.0 mA VOH 2.4 2.4 VD VD V V Low-level Output Voltage: D<7:0> I 0 = 16.0 mA All Others I 0 = 4.0 mA VOL 0.4 0.4 V V Input Leakage Current (Digital Inputs) -10 10 µA Output Leakage Current (High-Z Digital Outputs) -10 10 µA DIGITAL FILTER CHARACTERISTICS Parameter Symbol Min Typ Max Units Passband 0 0.40xFs Hz Frequency Response -0.5 +0.2 dB Passband Ripple (0-0.4xFs) ±0.1 dB Transition Band 0.40xFs 0.60xFs Hz Stop Band 0.60xFs Hz Stop Band Rejection 74 dB Group Delay 16- and 8-bit formats ADPCM stereo format ADPCM mono format 10/Fs 14/Fs 18/Fs s s s Group Delay Variation vs. Frequency ADCs DACs 0.0 0.1/Fs µs µs CS4231A

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TIMING PARAMETERS (TA = 25 °C; VA1, VA2, VD1-VD4 = +5V, outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD4) Parameter Symbol Min Max Units WR or RD strobe width t STW 90 ns Data valid to WR rising edge (write cycle) t WDSU 22 ns RD falling edge to data valid (read cycle) t RDDV 60 ns CS setup to WR of RD falling edge t CSSU 10 ns CS hold from WR or RD rising edge t CSHD 0n s ADDR <> setup to RD or WR falling edge t ADSU 22 ns ADDR <> hold from WR or RD rising edge t ADHD 10 ns DAK inactive to WR or RD falling edge (DMA cycle completion immediately followed by a non-DMA cycle) tSUDK1 60 ns DAK active from WR or RD rising edge (non-DMA cycle completion immediately followed by DMA cycle) tSUDK2 0n s DAK setup to RD falling edge (DMA cycles) DAK setup to WR falling edge tDKSUa tDKSUb ns ns Data hold from WR rising edge t DHD2 15 ns DRQ hold from WR or RD falling edge (assumes no more DMA cycles needed) tDRHD 02 5 n s Time between rising edge of WR or RD to next falling edge of WR or RD tBWND 80 ns Data hold from RD rising edge t DHD1 02 0 n s DAK hold from WR rising edge DAK hold from RD rising edge tDKHDa tDKHDb ns ns DBEN or DBDIR active from WR or RD falling edge t DBDL 40 ns PDWN pulse width low t PDWN 200 ns Crystals, XTAL1I, XTAL2I frequency (Notes 1,7,8) 25.6 MHz XTAL1I, XTAL2I high time (Notes 1,8) 18 ns XTAL1I, XTAL2I low time (Notes 1,8) 18 ns Sample frequency (Note 1) Fs 5.5 50 kHz Serial Port Timing SCLK frequency (Note 9) t SCLKW Fsx64 Hz SCLK rising to SDOUT valid t PD1 30 ns SCLK rising to FSYNC transition t PD2 -20 20 ns SDIN valid to SCLK falling t S1 30 ns SDIN hold after SCLK falling t H1 30 ns Notes: 7. When only one crystal is used, it must be XTAL1. When using two crystals, the high frequency crystal should be on XTAL1 which is designed for higher loop gains. 8. Sample frequency specifications must not be exceeded. 9. When SF1, 0 = 10, 32-bit mode, SCLK is active for the first 32 bit periods of the frame, and remains low during the last 32 bit periods of the frame. CS4231A DS139PP2 7

D<7:0> RD DBDIR t DBDL 8-Bit Mono DMA Read/Capture Cycle SDIN SDOUT tpd1 ts1 th1 MSB, Left SCLK tpd2 tpd2FSYNC tsckw MSB, Left tpd2FSYNC SF1,0=01,10 SF1,0=00 Serial Port Timing CS4231A

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(high) t DRHD t DBDL t DHD2t WDSU t DKSUb tSTW PDRQ PDAK D<7:0> WR DBDIR t DKHDa DBEN 8-Bit Mono DMA Write/Playback Cycle RIGHT/HIGH BYTE LEFT/LOW BYTE tBWDN D<7:0> RD/ WR CDRQ/PDRQ CDAK/PDAK 8-Bit Stereo or 16-Bit Mono DMA Cycle D<7:0> LOW BYTE tBWDN HIGH BYTE RD/ WR CDRQ/ PDRQ LEFT SAMPLE RIGHT SAMPLE HIGH BYTE LOW BYTE CDAK/ PDAK 16-Bit Stereo or ADPCM DMA Cycle CS4231A DS139PP2 9

D<7:0> A<1:0> tCSSU tCSHD tDHD1tRDDV tADSU tADHD tSUDK1 tSUDK2 tDBDL tDBDL I/O Read Cycle CDRQ/PDRQ CDAK/PDAK CS DBEN DBDIR WR D<7:0> A<1:0> tCSSU tCSHD tDHD2 tSUDK2 tADSU tADHD tWDSU tSUDK1 tSTW (high) tDBDL I/O Write Cycle CS4231A

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21 XTAL2I

22 XTAL2O

17 XTAL1I

18 XTAL1O

Figure 1. Recommended Connection Diagram

The CS4231A is a monolithic integrated circuit that provides audio in personal computers or other parallel interface environments. The func- tions include stereo Analog-to-Digital and Digital-to-Analog converters (ADCs and DACs), analog mixing, anti-aliasing and reconstruction filters, line and microphone level inputs, optional A-Law / µ-Law coding, simultaneous capture and playback and a parallel bus interface. Five analog inputs are provided and three can be mul- tiplexed to the ADC. The line input, two auxiliary inputs and a mono input can be mixed with the output of the DAC with full volume control. Several data modes are supported in- cluding 8- and 16-bit linear as well as 8-bit companded, 4-bit ADPCM compressed, and 16- bit Big Endian. The CS4231A is packaged in a 68-pin PLCC or a 100-pin TQFP. Enhanced Functions (MODE 2) The CS4231A’s initial state is labeled MODE 1 and forces the CS4231A to appear as a CS4248. Enhanced functionality is provided by a second mode on the CS4231A. To switch from MODE 1 to MODE 2, the MODE2 bit should be set to one in the MODE and ID register (I12). When MODE 2 is selected, the bit IA4 in the Index Address register (R0) will be decoded as a valid index pointer, providing 16 additional reg- isters and increased functionality over the CS4248. To reverse the procedure, clear the MODE2 bit and the CS4231A will resume operation in MODE 1. Since previous code writes a zero to bit IA4 of the Index Address register (R0), the CS4231A is backwards compatible with the CS4248 and the AD1848. Mixer Attenuation Control on Line Input The CS4231A adds mixer attenuation control for the LINE inputs which are then summed into the output mixer. This fourth input to the mixer completes the recommended mixer configuration for MPC Level-2 compliance. The LINE mix register provides 32 volume adjustments in 1.5 dB steps. In addition, there is a one bit mute control. The additional MODE 2 functions are: 1. Full-Duplex DMA support 2. A programmable timer 3. Mono output with mute control 4. Mono input with mixer volume control 5. ADPCM and Big Endian audio data formats 6. Independent selection of capture and playback audio data formats 7. Selectable serial audio data port. ANALOG HARDWARE DESCRIPTION The analog hardware consists of an MPC Level 2-compatible mixer (four stereo mix sources), three line-level stereo inputs, a stereo microphone input, a mono input, a mono output, and a stereo line output. This section describes the analog hardware needed to interface with these pins. Analog Inputs The analog inputs consist of four stereo analog inputs, and one mono input. As shown on this data sheet cover, the input to the ADCs comes from a multiplexer that selects between two ana- log line-level inputs (LINE, AUX1), a microphone level input (MIC), and the output from the MPC-compatible mixer. The LINE and AUX1 lines also feed the MPC mixer and in- clude individual volume controls. Unused analog inputs should be connected together and then connected through a capacitor to analog ground. CS4231A

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modate four stereo inputs and one mono input. capacitively coupled to the CS4231A. line-level inputs on the CS4231A. possible to minimize noise coupling. steps. In addition, a mute control is provided. illustrates a typical input circuit for the Mono In. Figure 2. Line Inputs Figure 3. Left or Mono Microphone Input

46 MIN

Figure 4. Mono Input

mono speaker using an appropriate drive circuit. ing the capacitance on VREF to 10 µF. (PIO) access, and DMA access. to or from the ADC and DAC sections. Figure 5. Mono Output

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transparent and have no programming associated with them. When playback is enabled, the playback FIFO continually requests data until the FIFO is full, and then makes requests as positions inside the FIFO are emptied, thereby keeping the playback FIFO as full as possible. Thus when the system cannot respond within a sample period, the FIFO is emptied, avoiding a momentary loss of audio data. If the FIFO runs out of data, the last valid sample can be continuously output to the DACs (if DACZ in I16 is set) which will eliminate pops from occurring. When capture is enabled, the capture FIFO tries to continually stay empty by making requests every sample period. Thus when the system can- not respond within a sample period, the capture FIFO starts filling thereby avoiding a loss of data in the audio data stream. High Current Data Bus Drivers The CS4231A provides 16 mA drivers eliminat- ing the need for off chip drivers in many cases. If a full 24 mA drive is required, the appropriate direction and driver select lines are provided. The current drivers are provided for the data bus, DMA request line, and the interrupt request line. PIO Registers Interface The first type of parallel bus access is pro- grammed I/O (PIO) to the four control registers. The control registers allow access to status, audio data, and all indirect registers via the in- dex registers. The RD and WR signals are used to define the read and write cycles respectively. The PIO register cycle is defined by the asser- tion of the CS4231A CS signal while the DMA acknowledge signals, CDAK and PDAK, are in- active. For read cycles, the CS4231A will drive data on the DATA lines while the host asserts the RD strobe. Write cycles require the host to assert data on the DATA lines and strobe the WR sig- nal. The CS4231A will latch data into the PIO register on the rising edge of the WR strobe. The CS4231A CS signal should remain active until after completion of the read or write cycle. I/O cycles are the only type of cycle which can ac- cess the internal control and status registers. When reading or writing audio data via PIO, the Status register (R2) indicates which byte of the audio sample is ready. The Status register does not have to be read after every byte; however, once all bytes of a sample are transferred, the Status register must be read before the next sam- ple can be transferred. The audio data interface typically uses DMA re- quest/grant pins to transfer the digital audio data between the CS4231A and the bus. The CS4231A is responsible for asserting a request signal whenever the CS4231A’s internal buffers need updating. The logic interfaced with the CS4231A responds with an acknowledge signal and strobes data to and from the CS4231A, 8 bits at a time. The CS4231A keeps the request pin active until the appropriate number of 8-bit cycles have occurred to transfer one audio sam- ple. Notice that different audio data types will require a different number of 8-bit transfers. DMA Interface The second type of parallel bus cycle on the CS4231A is a DMA transfer. DMA cycles are distinguished from PIO register cycles by the as- sertion by the CS4231A of a CDRQ (or PDRQ) followed by an acknowledgment by the host by the assertion of CDAK (or PDAK). While the acknowledgment is received from the host, the CS4231A assumes that any cycles occurring are DMA cycles and ignores the addresses on the address lines and the CS line. The CS4231A may assert the DMA request sig- nal at any time. Once asserted, the DMA request will remain asserted until a DMA cycle occurs to the CS4231A. Once the falling edge of the final CS4231A DS139PP2 15

supports up to two DMA channels. are independently using playback and capture. multaneous DMA capture and playback. and acknowledges are handled. ture are enabled, the default will be playback. Figure 9. When the mono audio format is se-

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through a sample frequency change.

16 Bits

32 Bits

Figure 6. 64-bit enhanced mode (SF1,0 = 00)

16 Clocks 16 Clocks 16 Clocks 16 Clocks

Figure 7. 64-bit mode (SF1,0 = 01)

16 Clocks

32 No-Clock bit periods

Figure 8. 32-bit mode (SF1,0 = 10)

contains status information.

64 SCLKs per frame, but has FSYNC transition-

interrupt overhead of the 32 unused bit periods. should be optimally quieter than VD1 and VD2. Figure 9. Serial Audio Data Justification

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higher frequencies, but any crystal with the above specifications should suffice. The standard crystals for audio are: XTAL1: 24.576 MHz Fundamental Mode Parallel Resonant, CL = 20 pF XTAL2: 16.9344 MHz Fundamental Mode Parallel Resonant, C L = 20 pF These crystal frequencies support the standard sample frequencies listed in Table 7. External CMOS clocks may be connected the crystal inputs (XTAL1I, XTAL2I) in lieu of the crystals. When using external CMOS clocks, the XTAL out pins should be left floating. Extreme care should be used when laying out a board us- ing external clocks since coupling between clocks can degrade analog performance. Power Down - PDWN The PDWN signal places the CS4231A into maximum power conservation mode. When PDWN goes low, any reads of the codec’s paral- lel interface return 80 hex, all analog outputs are muted, and the voltage reference then slowly de- cays to ground. When PDWN is brought high, a full calibration cycle automatically occurs. While the codec is initializing, any reads from the par- allel interface will return 80 hex and writes will be ignored. When initialization is completed, the registers will contain their reset value as stated in the register section of the data sheet. The CS4231A contains an internal "Power On Reset" signal that causes a proper initialization at power up time. Therefore, if no power down mode is needed, PDWN can be tied permanently to VD3/4. DBEN/DBDIR If needed, the DBEN and DBDIR pins can con- trol an external data buffer to the CS4231A. The CS4231A contains 16 mA bus drivers so the ex- ternal data buffer is only needed when driving a full 24 mA bus. DBEN enables the external driv- ers and DBDIR controls the direction of the data flow. Both signals are normally high, where DBDIR high points the transceiver towards the codec and low points the transceiver towards the data bus. See Figure 1 for a typical connection diagram. SOFTWARE DESCRIPTION The CS4231A must be in Mode Change Enable Mode (MCE=1) before any changes to the Inter- face Configuration register (I9), the Sample Frequency (lower four bits) in the Fs & Playback Data Format register (I8), or the serial port bits (SF1, SF0, SPE) in the Alternate Feature Enable I register (I16) are allowed. The actual audio data formats, which are the upper four bits of I8 for playback and I28 for capture, can be changed by setting MCE (R0) or PMCE/CMCE (I16) high. The exceptions are CEN and PEN which can be changed "on-the-fly" via programmed I/O writes to these bits. All outstanding DMA trans- fers must be completed before new values of CEN or PEN are recognized. Power-Down and Initialization To put the CS4231A into a power-down mode, the PDWN pin is pulled low. In this state the host interface reads 80h indicating that it is un- able to respond and all analog circuits are turned off. To let the CS4231A go through its reset initiali- zation the PDWN pin should be set high. This CS4231A DS139PP2 19

rising edge starts the initialization process in which a full calibration occurs. While the CS4231A is initializing, 80 hex is returned from all reads by the host computer. All writes during initialization of the CS4231A will be ignored. At the end of the initialization, all registers are set to known reset values as documented in the register definition section. Calibration Modes The CS4231A has four different calibration modes. The selected calibration occurs whenever the Mode Change Enable (MCE, R0) bit goes from 1 to 0. The completion of calibration can be determined by polling the Auto-Calibrate In-Progress bit in the Error Status and Initialization register (ACI, I11). This bit will be high while the calibration is in progress and low once completed. The cali- bration time varies with calibration mode. The Calibration procedure is as follows: 1) Place the CS4231A in Mode Change En- able using the MCE bit of the Index Address register (R0). 2) Set the CAL1,0 bits in the Interface Con- figuration register (I9). 3) Return from Mode Change Enable by reset- ting the MCE bit of the Index Address register (R0). 4) Wait until ACI (I11) cleared to proceed No Calibration (CAL1,0 = 00) This is the fastest mode since no calibration is performed. This mode is useful for games which need to change the sample frequency quickly. This mode is also useful when the codec is oper- ating in full-duplex and an ADC data format change is desired. This is the only calibration mode that does not affect the DACs (i.e. mute the DACs at some point). Changing from any other calibration mode to No Calibration mode will take 40 sample periods to complete; how- ever, subsequent MCE cycles will take 0 sample periods. Converter Calibration (CAL1,0 = 01) This calibration mode calibrates the ADCs and DACs but does not calibrate any of the analog mixing channels. This is the second longest cali- bration mode, taking 136 sample periods, and is software and hardware similar to the CS4231 or CS4248. Since the mixer is not calibrated, any analog signals mixing into the output will be un- affected. The calibration sequence done by the CS4231A is as follows: The DACs are muted The ADCs are calibrated The DACs are calibrated The DACs are unmuted DAC Calibration (CAL1,0 = 10) This calibration mode only calibrates the DACs’ (playback) interpolation filters leaving the ADCs unaffected. This is the second fastest calibration mode (no cal. is the fastest) taking 40 sample pe- riods to complete. The calibration sequence done by the CS4231A is as follows: The DACs are muted The DAC filters are calibrated The DACs are unmuted Full Calibration (CAL1,0 = 11) This calibration mode calibrates all offsets, ADCs, DACs, and analog mixers. Full calibra- tion is automatically initiated on power up or anytime the CS4231A exits from a power down state. This is the longest calibration mode and takes 168 sample periods to complete. The cali- bration sequence done by the CS4231A is as follows: CS4231A

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All outputs are muted (DACs and mixer) The mixer is calibrated The ADCs are calibrated The DACs are calibrated All outputs are unmuted Changing Sampling Rate The internal states of the CS4231A are synchro- nized by the selected sampling frequency defined in the Fs and Playback Data Format register (I8). The changing of either the clock source or the clock frequency divide requires a special se- quence for proper CS4231A operation: 1) Place the CS4231A in Mode Change En- able using the MCE bit of the Index Address register (R0). 2) During a single write cycle, change the Clock Frequency Divide Select (CFS) and/or Clock 2 Source Select (C2SL) bits of the Fs & Playback Data Format register (I8) to the desired value. (The data format may also be changed.) 3) The CS4231A resynchronizes its internal states to the new clock. During this time the CS4231A will be unable to respond at its parallel interface. Writes to the CS4231A will not be recognized and reads will always return the value 80 hex. 4) The host now polls the CS4231A’s Index Address register (R0) until the value 80 hex is no longer returned. 5) Once the CS4231A is no longer responding to reads with a value of 80 hex, normal op- eration can resume and the CS4231A can be removed from MCE. The CSL and CFS bits cannot be changed unless the MCE bit has been set. Attempts to change the Data Format registers (I8, I28) or Interface Configuration register (I9, except CEN and PEN) without MCE set, will not be recognized. When fast changing of sample frequency is de- sired, the XTALE bit (I17) should be set. When set, both crystals are kept running thereby pro- viding the fastest switching time (80h never appears) between sample frequencies. When XTALE is cleared, the unused crystal is powered down to minimize noise coupling. This causes 80h to appear after leaving an MCE cycle until the newly selected crystal is operational. XTALE (and the No Calibration mode, I9) provide the fastest switching time for applications such as games that constantly change the sample fre- quency. Changing Audio Data Formats I n M O D E 1 , M C E m u s t b e u s e d t o s e l e c t t h e audio data format in I8. Since MCE causes a calibration cycle, it is not ideal for full-duplex operation. In MODE 2, individual Mode Change Enable bits for capture and playback are pro- vided in register I16. MCE (R0) must still be used to select the sample frequency, but PMCE (for playback) and CMCE (for capture) allow changing their respective data formats without causing a calibration to occur. Setting PMCE (I16) clears the playback FIFO and allows the upper four bits of I8 to be changed. Setting CMCE (I16) clears the capture FIFO and allows the upper four bits of I28 to be changed. Audio Data Formats In MODE 1 operation, all data formats of the CS4231A are in "little endian" format. This for- mat defines the byte ordering of a multibyte word as having the least significant byte occupy- ing the lowest memory address. Likewise, the most significant byte of a little endian word oc- cupies the highest memory address. The sample frequency is always selected in the Fs and Playback Data Format register (I8). In MODE 1 the same register, I8, determines the audio data format for both playback and capture; however, in MODE 2, I8 only selects the play- CS4231A DS139PP2 21

ple is 16- or 8-bit in size. panded µ-Law, and 8-bit companded A-Law. signed big endian. See Figures 16 through 19. represents maximum positive analog amplitude. functions are shown in Figure 10. Figure 10. Linear Transfer Functions Figure 11. Companded Transfer Functions

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Figure 16. 4-bit Mono, ADPCM Audio Data Figure 17. 4-bit Stereo, ADPCM Audio Data Figure 18. 16-bit Mono, Signed Big Endian Audio Data Figure 19. 16-bit Stereo, Signed Big Endian Audio Data

24 DS139PP2

using only 8-bits per sample. This is accom- plished using a non-linear companding transfer function which assigns more digitalization codes to lower amplitude analog signals with the sacri- fice of precision on higher amplitude signals. The µ-Law and A-Law formats of the CS4231A conform to the CCITT G.711 specifications. Fig- ure 11 illustrates the transfer function for both A- and µ-Law. Please refer to the standards men- tioned above for an exact definition. ADPCM Compression/Decompression In MODE 2, the CS4231A also contains Adap- tive Differential Pulse Code Modulation (ADPCM) for improved performance and com- pression ratios over µ-Law or A-Law. The ADPCM format is compliant with the IMA standard and provides a 4-to-1 compression ratio (i.e. 4 bits are saved for each 16-bit sample cap- tured). For more detailed information on the IMA ADPCM format contact the IMA at (410) 626-1380. Figures 16 and 17 illustrate the ADPCM data flow. The ADPCM format is unique with respect to the FIFO depth and the DMA Base register value. The ADPCM format fills the FIFOs com- pletely (64 bytes); therefore, the FIFOs hold 64 stereo samples and 128 mono samples. When samples are transferred using DMA, the DMA request stays active for four bytes, similar to the 16-bit stereo mode. The Status register indicates which of the four bytes is being transferred in PIO mode. When CEN is 0 (capture disabled), the ADPCM block’s accumulator and step size are cleared. When CEN is enabled, the ADPCM block will start converting. The "overrun" condition should never occur, otherwise the data may not be con- structed properly upon playback. If pausing the capture sequence is desired, the ADPCM Cap- ture Freeze bit (ACF, I23) should be set. When set, the ADPCM algorithm will continue to oper- ate until a complete word (4 bytes) is written to the FIFO. Then the ADPCM’s block accumulator and step size will be frozen. The user is required to read the FIFO until empty, at which time the requests will stop. When ACF is cleared, the ADPCM adaptation will continue. When PEN is 0 (playback disabled), the ADPCM block’s accumulator and step size are cleared. When PEN is set, the ADPCM block will start converting. When pausing the playback stream is desired, audio data should not be sent to the codec causing an underrun. This can be accomplished by disabling the DMA controller or not sending data in PIO mode. The underrun will be detected by the CS4231A and the adapta- tion will freeze. As data is sent to the codec, adaptation is resumed. It is critical that all play- back ADPCM samples are sent to the codec, since dropped samples will cause errors in the adaptation. Whereas toggling PEN resets the ac- cumulator and step size, the APAR bit (I17) only resets the accumulator without affecting the step size. DMA Registers The DMA registers allow easier integration of the CS4231A in ISA systems. Peculiarities of the ISA DMA controller require an external count mechanism to notify the host CPU of a full DMA buffer via interrupt. The programmable DMA Base registers provide this service. The act of writing a value to the Upper Base register causes both Base registers to load the Current Count register. DMA transfers are en- abled by setting the PEN/CEN bit while PPIO/CPIO is clear. (PPIO/CPIO can only be changed while the MCE bit is set.) Once trans- fers are enabled, each sample that is transferred by a DMA cycle will decrement the appropriate Current Count register (with the exception of the ADPCM format) until zero is reached. The next sample after zero generates an interrupt and re- CS4231A DS139PP2 25

loads the Current Count register with the values in the Base registers. For all data formats except ADPCM, the DMA Base registers must be loaded with the number of samples, minus one, to be transferred between "DMA Interrupts". Stereo data contains twice as many bytes as mono data but the same number of samples. Likewise, 16-bit data contains twice the number of bytes as 8-bit data but the same number of samples. The equation for loading the DMA Base registers is: DMA Base register 16 = NS - 1 Where N S is the number of samples transferred between interrupts and the "DMA Base regis- ter16" consists of the concatenation of the upper and lower DMA Base registers. For the ADPCM data format, the contents of the DMA Base registers are calculated differently from any other data format. In the ADPCM for- mat the data is transferred 4 bytes at a time. Each four byte word transferred, decrements the DMA Current Count register. The Base registers must be loaded with the number of BYTES to be transferred between "DMA interrupts", divided by four, minus one. The same calculation is used whether the data format is stereo or mono ADPCM. The 4-byte word contains 8 mono ADPCM samples or 4 stereo ADPCM samples. The equation for loading the DMA Base regis- ters is: DMA Base register 16 = Nb/4 - 1 Where N b is the number of BYTES transferred between interrupts and the "DMA Base regis- ter16" consists of the concatenation of the upper and lower DMA Base registers. Playback DMA Registers The playback DMA registers (I14/15) are used for sending playback data to the DACs in MODE 2. In MODE 1 or when SDC = 1, these registers (I14/15) are used for both playback and capture. When the playback Current Count register rolls under, the Playback Interrupt bit, PI, (I24) is set causing the INT bit (R2) to be set. The interrupt is cleared by a write of any value to the Status register (R2), or writing a "0" to the Playback Interrupt bit, PI (I24). When SDC = 1, PI re- flects the status of I14/I15 for both playback and capture. Capture DMA Registers The Capture DMA Base registers (I30/31) pro- vide a second pair of Base registers that allow full-duplex DMA operation. With full-duplex op- eration, capture and playback can occur simultaneously utilizing different DMA channels. These registers are only used in MODE 2 with SDC = 0. If SDC in I9 is set, I14/I15 are used for Capture DMA Base registers. When the capture Current Count register rolls under, the Capture Interrupt bit, CI, (I24) is set causing the INT bit (R2) to be set. The interrupt is cleared by a write of any value to the Status register (R2), or by writing a "0" to the Capture Interrupt bit, CI (I24). The CI bit is tied to the Capture DMA base registers; therefore, when SDC = 1, the CI bit is non-functional. Digital Loopback Digital Loopback is enabled via the LBE bit in the Loopback Control register (I13). This loop- back routes the digital data from the ADCs to the DACs. This loopback can be digitally attenu- ated via additional bits in the Loopback Control register (I13). Loopback is then summed with DAC data supplied at the digital bus interface. When loopback is enabled, it will "freerun" syn- chronous with the sample rate. The digital loopback is shown in the CS4231A Block Dia- gram on the front cover. This loopback can be CS4231A

26 DS139PP2

used to mix the incoming microphone data with data from the DACs. Since the CS4231A allows selection of different data formats between cap- ture and playback, if the capture channel is set to mono and the playback channel set to stereo, the mono input (mic) data will be mixed into both channels of the output mixer. If the sum of the loopback and bus data are greater than full scale, CS4231A will send the appropriate full scale value to the DACs (clip- ping). Timer Registers The Timer Base registers are provided for syn- chronization, watch dog, and other functions where a high resolution time reference is re- quired. This counter is 16 bits and the exact time base, listed in the register description, is deter- mined by the crystal selected. When the Timer Enable bit TE, in the Alternate Feature Enable register (I16) is clear, the timer does not count. The Timer is set by loading the Upper and then the Lower Base register to the appropriate values and setting TE. When the Timer Lower Base register (I20) is loaded, the entire 16-bit value is loaded into an internal Cur- rent Count register which is decremented at approximately a 10 µsec rate. When the value of the Current Count register reaches zero, the Timer Interrupt bit, TI, in I24 is set, and and in- terrupt is generated if the INT bit (R2) is set. On the next timer clock, the value of the Timer Base registers are automatically loaded into the inter- nal Current Count register which begin counting to zero again. The interrupt is cleared by any write to the Status register (R2) or by writing a "0" to the Timer Interrupt bit, TI, in the Alternate Feature Status register (I24). Since the timer will continue counting down while an interrupt is pending, interrupts will be generated at fixed time intervals regardless of the time required to service the interrupt (assuming the interrupt is serviced before the next timer interrupt is gener- ated). Interrupts The INT bit of the Status register (R2) always reflects the status of the CS4231A internal inter- rupt state. A roll-over from any Current Count register (DMA playback, DMA capture, or Timer) sets the INT bit. This bit remains set until cleared by a write of ANY value to Status regis- ter (R2), or by clearing the appropriate bit or bits (PI, CI, TI) in the Alternate Feature Status regis- ter (I24). The Interrupt Enable (IEN) bit in the Pin Control register (I10) determines whether the interrupt pin responds to the interrupt event in the CS4231A. When the IEN bit is 0, the interrupt is masked and the IRQ pin of the CS4231A is forced low. However, the INT bit in the Status register (R2) always responds to the counter. Error Conditions Data overrun or underrun could occur if data is not supplied to or read from the CS4231A in the appropriate amount of time. The amount of time for such data transfers depends on the frequency selected within the CS4231A. Should an overrun condition occur during data capture, the last whole sample (before the over- run condition) will be read by the DMA interface. A sample will not be overwritten while the DMA interface is in the process of transfer- ring the sample. Should an underrun condition occur in a play- back case, the last valid sample will be output (assuming DACZ = 0) to the DACs which will mask short duration error conditions. When the next complete sample arrives from the host com- puter the data stream will resume on the next sample clock. CS4231A DS139PP2 27

out using DMA cycles or indexing. Table 1. Direct Registers Table 2. Indirect Registers

28 DS139PP2

IA3-IA0 Index Address: These bits define the address of the CS4231A register ac- cessed by the Indexed Data register (R1). These bits are read/write. IA4 Allows access to indirect registers 16 - 31. Only available in MODE 2. In MODE 1,this bit is reserved. TRD Transfer Request Disable: This bit, when set, causes DMA transfers to cease when the INT bit of the status register is set. Independent for play- back and capture interrupts. 0 - Transfers Enabled (PDRQ and CDRQ occur uninhibited) 1 - Transfers Disabled (PDRQ and CDRQ only occur if INT bit is 0) MCE Mode Change Enable: This bit must be set whenever the sample fre- quency,D3-D0 of I8, or the Interface Configuration (I9) register is changed. The exceptions are CEN and PEN which can be changed "on- the-fly". The DAC output is muted when MCE is set. MCE or PMCE (I16) may be used to changed the playback data format, D7-D3 of I8. MCE or CMCE (I16) may be used to change the capture data format, D7- D3 of I28. INIT CS4231A Initialization: This bit is read as 1 when the CS4231A is in a state in which it cannot respond to parallel interface cycles. This bit is read-only. Immediately after RESET (and once the CS4231A has left the INIT state), the state of this register is: 010x0000 During initialization and power down, this regis- ter CANNOT be written and always reads 10000000 (80h) ID7-ID0 Indexed Data register: These bits are the indirect register referenced by the Indexed Address register (R0). During initialization and power down, this regis- ter can NOT be written and is always read 10000000 (80h) INT Interrupt Status: This indicates the status of the internal interrupt logic of the CS4231A. This bit is cleared by any write of any value to this reg- ister. The IEN bit of the Pin Control register (I10) determines whether the state of this bit is reflected on the IRQ pin of the CS4231A. Read States 0 - Interrupt inactive 1 - Interrupt active PRDY Playback Data Ready. The Playback Data register (R3) is ready for more data. This bit would be used when di- rect programmed I/O data transfers are desired. 0 - Data still valid. Do not overwrite. 1 - Data stale. Ready for next host data write value. PL/ R Playback Left/Right Sample: This bit indicates whether data needed is for the Left channel or Right channel in all audio data formats except ADPCM. In ADPCM it indicates whether the first two or last two bytes of a 4-byte set (8 ADPCM samples) is needed. 0 - Right or 3/4 ADPCM byte needed 1 - Left, Mono, or 1/2 ADPCM byte needed Index Address Register (R0) D7 D6 D5 D4 D3 D2 D1 D0 INIT MCE TRD IA4 IA3 IA2 IA1 IA0 Indexed Data Register (R1) D7 D6 D5 D4 D3 D2 D1 D0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Status Register (R2, Read Only) D7 D6 D5 D4 D3 D2 D1 D0 CU/L CL/R CRDY SER PU/L PL/R PRDY INT CS4231A DS139PP2 29

PU/L Playback Upper/Lower Byte: This bit indicates whether the playback data needed is for the upper or lower byte of the channel. In ADPCM it in- dicates, along with PL/ R, which one of four ADPCM bytes is needed. 0 - Lower or 1/3 ADPCM byte needed 1 - Upper, any 8-bit mode, or 2/4 ADPCM byte needed SER Sample Error: This bit indicates that a sample was not serviced in time and an error has occurred. The bit indi- cates an overrun for capture and underrun for playback. If both the capture and playback are enabled, the source which set this bit can not be determined. However, the Alter- nate Feature Status register (I24) can indicate the exact source of the error. CRDY Capture Data Ready. The Capture Data register (R3) contains data ready for reading by the host. This bit would be used for direct pro- grammed I/O data transfers. 0 - Data is stale. Do not reread the information. 1 - Data is fresh. Ready for next host data read. CL/ R Capture Left/Right Sample: This bit indicates whether the capture data waiting is for the Left channel or Right channel in all audio data for- mats except ADPCM. In ADPCM it indicates whether the first two or last two bytes of a 4-byte set (8 ADPCM samples) is waiting. 0 - Right or 3/4 ADPCM byte waiting 1 - Left, Mono, or 1/2 ADPCM byte waiting CU/ L Capture Upper/Lower Byte: This bit indicates whether the capture data ready is for the upper or lower byte of the channel. In ADPCM it indi- cates, along with CL/ R, which one of four ADPCM bytes is waiting. 0 - Lower or 1/3 ADPCM byte waiting 1 - Upper, any 8-bit mode, or 2/4 ADPCM byte waiting Note on PRDY/CRDY: These two bits are de- signed to be read as one when action is required by the host. For example, when PRDY is set to one, the device is ready for more data; or when the CRDY is set to one, data is available to the host. The definition of the CRDY and PRDY bits are therefore consistent in this regard. I/O Data Registers The PIO Data register is two registers mapped to the same address. Writes to this register send data to the Playback Data register. Reads from this register will receive data from the Capture Data register. During initialization and power down, this regis- ter CANNOT be written and is always read 10000000 (80h) CD7-CD0 Capture Data Port. This is the control register where capture data is read during programmed I/O data trans- fers. The reading of this register will increment the state machine so that the following read will be from the next appropriate byte in the sample. The exact byte which is next to be read can be determined by reading the Status register (R2). Once all relevant bytes have been read, the state machine will point to the last byte of the sample. Once the Status register (R2) is read and a new sample is received from the FIFO, the state ma- chine and Status register (R2) will point to the first byte of the new sample. Capture I/O Data Register (R3, Read Only) D7 D6 D5 D4 D3 D2 D1 D0 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 CS4231A

30 DS139PP2

During initialization and power down, this regis- ter can NOT be written and is always read 10000000 (80h) PD7-PD0 Playback Data Port. This is the control register where playback data is written during programmed IO data transfers. Writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ignored. The state machine is reset after the Status register (R2) is read and the current sam- ple is sent to the DACs via the FIFOs. Indirect Mapped Registers These registers are accessed by placing the ap- propriate index in the Index Address register (R0) and then accessing the Indexed Data regis- ter (R1). All reserved bits should be written zero and may be 0 or 1 when read. Indirect registers 16-31 are only available when the MODE2 bit in MODE and ID register (I12) is set. LAG3-LAG0 Left ADC Gain. The least significant bit represents +1.5 dB, with 0000 = 0 dB. See Table 4. LMGE Left Mic Gain Enable: This bit enables the 20 dB gain stage of the left mic input signal, LMIC. LSS1-LSS0 Left ADC Input Source Select. These bits select the input source for the left ADC channel. 0 - Left Line: LLINE 1 - Left Auxiliary 1: LAUX1 2 - Left Microphone: LMIC 3 - Left Line Output Loopback This register’s initial state after reset is: 000x0000 RAG3-RAG0 Right ADC Gain. The least significant bit represents +1.5 dB, with 0000 = 0 dB. See Table 4. RMGE Right Mic Gain Enable: This bit enables the 20 dB gain stage of the right mic input signal, RMIC. RSS1-RSS0 Right ADC Input Select. These bits select the input source for the right ADC channel. 0 - Right Line: RLINE 1 - Right Auxiliary 1: RAUX1 2 - Right Microphone: RMIC 3 - Right Line Out Loopback This register’s initial state after reset is: 000x0000 LX1G4-LX1G0 Left Auxiliary #1, LAUX1, Mix Gain. The least significant bit represents 1.5 dB, with 01000 = 0 dB. See Ta- ble 5. LX1M Left Auxiliary #1 Mute. When set to 1, the left Auxiliary #1 input, LAUX1, to the mixer, is muted. This register’s initial state after reset is: 1xx01000. Playback I/O Data Register (R3, Write Only) D7 D6 D5 D4 D3 D2 D1 D0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Left ADC Input Control (I0) D7 D6 D5 D4 D3 D2 D1 D0 LSS1 LSS0 LMGE res LAG3 LAG2 LAG1LAG0 Right ADC Input Control (I1) D7 D6 D5 D4 D3 D2 D1 D0 RSS1 RSS0 RMGE res RAG3 RAG2 RAG1RAG0 Left Auxiliary #1 Input Control (I2) D7 D6 D5 D4 D3 D2 D1 D0 LX1M res res LX1G4 LX1G3 LX1G2 LX1G1 LX1G0 CS4231A DS139PP2 31

RX1G4-RX1G0 Right Auxiliary #1, RAUX1, Mix Gain. The least significant bit represents 1.5 dB, with 01000 = 0 dB. See Ta- ble 5. RX1M Right Auxiliary #1 Mute. When set to 1, the right Auxiliary #1 input, RAUX1, to the mixer, is muted. This register’s initial state after reset is: 1xx01000. LX2G4-LX2G0 Left Auxiliary #2, LAUX2, Mix Gain. The least significant bit represents 1.5 dB, with 01000 = 0 dB. See Ta- ble 5. LX2M Left Auxiliary #2 Mute. When set to 1, the left Auxiliary #2 input, LAUX2, to the mixer, is muted. This register’s initial state after reset is: 1xx01000. RX2G4-RX2G0 Right Auxiliary #2, RAUX2, Mix Gain. The least significant bit represents 1.5 dB, with 01000 = 0 dB. See Ta- ble 5. RX2M Right Auxiliary #2 Mute. When set to 1, the right Auxiliary #2 input, RAUX2, to the mixer, is muted. This register’s initial state after reset is: 1xx01000. LDA5-LDA0 Left DAC Attenuator. The least signifi- cant bit represents -1.5 dB, with 000000 = 0 dB. See T able 6. LDM Left DAC Mute. When set to 1, the left DAC output to the mixer will be muted. This register’s initial state after reset is: 1x000000. RDA5-RDA0 Right DAC Attenuator. The least signifi- cant bit represents -1.5 dB, with 000000 = 0 dB. See T able 6. RDM Right DAC Mute. When set to 1, the right DAC output to the mixer will be muted. This register’s initial state after reset is: 1x000000. Right Auxiliary #1 Input Control (I3) D7 D6 D5 D4 D3 D2 D1 D0 RX1M res res RX1G4 RX1G3 RX1G2 RX1G1 RX1G0 Left Auxiliary #2 Input Control (I4) D7 D6 D5 D4 D3 D2 D1 D0 LX2M res res LX2G4 LX2G3 LX2G2 LX2G1 LX2G0 Right Auxiliary #2 Input Control (I5) D7 D6 D5 D4 D3 D2 D1 D0 RX2M res res RX2G4RX2G3 RX2G2 RX2G1 RX2G0 Left DAC Output Control (I6) D7 D6 D5 D4 D3 D2 D1 D0 LDM res LDA5 LDA4 LDA3 LDA2 LDA1 LDA0 Right DAC Output Control (I7) D7 D6 D5 D4 D3 D2 D1 D0 RDM res RDA5 RDA4 RDA3 RDA2 RDA1 RDA0 CS4231A

32 DS139PP2

C2SL Clock 2 Source Select: This bit selects the clock source used for the audio sample rates for both capture and playback. If only one crystal is sup- plied in hardware, it must be XTAL1. CAUTION: C2SL can only be changed while MCE (R0) is set. 0 - XTAL1 Typically 24.576 MHz 1 - XTAL2 Typically 16.9344 MHz CFS2-CFS0 Clock Frequency Divide Select: These bits select the audio sample fre- quency for both capture and playback. The actual audio sample frequency depends on which clock source (C2SL) is selected and its fre- quency. Frequencies listed as N/A are not available because their sam- ple frequency violates the maximum specifications; however, the decodes are available and may be used with crystals that do not violate the sam- ple frequency specifications. CAUTION: CFS2-CFS0 can only be changed while MCE (R0) is set. M Stereo/Mono Select: This bit deter- mines how the audio data streams are formatted. Selecting stereo will result in alternating samples repre- senting left and right audio channels. Mono playback plays the same audio sample on both channels. Mono capture only captures data from the left channel. In MODE 1, this bit is used for both playback and capture. In MODE 2, this bit is only used for playback, and the capture format is independently selected via I28. MCE (R0) or PMCE (I16) must be set to modify S/ M. See Changing Audio Data Formats section for more details. 0 - Mono 1 - Stereo The C/L, FMT1, and FMT0 bits set the audio data format as shown below. In MODE 1, FMT1, which is forced low, FMT0, and C/ L are used for both play- back and capture. In MODE 2, these bits are only used for playback, and the capture format is inde- pendently selected via register I28. MCE (R0) or PMCE (I16) must be set to modify the lower four bits of this register. See Changing Audio Data Formats section for more details. This register’s initial state after reset is: 0000000. Fs and Playback Data Format (I8) D7 D6 D5 D4 D3 D2 D1 D0 FMT1 FMT0 C/ LS /M C S F 2C F S 1C F S 0C 2 S L XTAL1 XTAL2 Divide 24.576 MHz 16.9344 MHz 0 - 3072 8.0 kHz 5.51 kHz 1 - 1536 16.0 kHz 11.025 kHz 2 - 896 27.42 kHz 18.9 kHz 3 - 768 32.0 kHz 22.05 kHz 4 - 448 N/A 37.8 kHz 5 - 384 N/A 44.1 kHz 6 - 512 48.0 kHz 33.075 kHz 7 - 2560 9.6 kHz 6.62 kHz FMT1 † FMT0 C/L D7 D6 D5 0 0 0 Linear, 8-bit unsigned 00 1 µ-Law, 8-bit companded 01 0 Linear, 16-bit two’s complement, Little Endian 0 1 1 A-Law, 8-bit companded 1 0 0 RESERVED 1 0 1 ADPCM, 4-bit, IMA compatible 1 1 0 Linear, 16-bit two’s complement, Big Endian 1 1 1 RESERVED † FMT1 is not available in MODE 1 (forced to 0). CS4231A DS139PP2 33

PEN Playback Enable. This bit enables playback. The CS4231A will generate PDRQ and respond to PDAK signals when this bit is en- abled and PPIO=0. If PPIO=1, PEN enables PIO playback mode. PEN may be set and reset without setting the MCE bit. 0 - Playback Disabled (PDRQ and PIO inactive) 1 - Playback Enabled CEN Capture Enabled. This bit enables the capture of data. The CS4231A will generate CDRQ and respond to CDAK signals when CEN is enabled and CPIO=0. If CPIO=1, CEN en- ables PIO capture mode. CEN may be set and reset without setting the MCE bit. 0 - Capture disabled (CDRQ and PIO inactive) 1 - Capture enabled SDC Single DMA Channel: This bit will force BOTH capture and playback DMA re- quests to occur on the Playback DMA channel. The Capture DMA CDRQ pin will be zero. This bit forces the CS4231A to use one DMA channel. Should both capture and playback be enabled in this mode, only the playback will occur. See the DMA section for further ex- planation. 0 - Dual DMA channel mode 1 - Single DMA channel mode CAL1,0 Calibration: These bits determine which type of calibration the CS4231A performs whenever the Mode Change Enable (MCE) bit, R0, changes from 1 to 0. The number of sample periods required for calibra- tion is listed in parenthesis. 0 - No calibration (0, 40 the first time) 1 - Converter calibration (136) 2 - DAC calibration (40) 3 - Full Calibration (168) PPIO Playback PIO Enable: This bit deter- mines whether the playback data is transferred via DMA or PIO. 0 - DMA transfers 1 - PIO transfers CPIO Capture PIO Enable: This bit deter- mines whether the capture data is transferred via DMA or PIO. 0 - DMA transfers 1 - PIO transfers CAUTION: This register, except bits CEN and PEN, can only be written while in Mode Change Enable (either MCE or PMCE). See Changing Sampling Rate section for more details. This register’s initial state after reset is: 00x01000 Interface Configuration (I9) D7 D6 D5 D4 D3 D2 D1 D0 CPIO PPIO res CAL1 CAL0 SDC CEN PEN CS4231A

34 DS139PP2

IEN Interrupt Enable: This bit enables the interrupt pin. The Interrupt pin will re- flect the value of the INT bit of the Status register (R2). The interrupt pin is active high. 0 - Interrupt disabled 1 - Interrupt enabled DEN Dither Enable: When set, triangular pdf dither is added before truncating the ADC 16-bit value to 8-bit, un- signed data. Dither is only active in the 8-bit unsigned mode. 0 - Dither disabled 1 - Dither enabled XCTL1-XCTL0 XCTL Control: These bits are reflected on the XCTL1,0 pins of the CS4231A. 0 - TTL logic low on XCTL1,0 pins 1 - TTL logic high on XCTL1,0 pins This registers initial state after reset is: 00xx0x0x ORL1-ORL0 Overrange Left Detect: These bits determine the overrange on the left ADC channel. These bits are up- dated on a sample by sample basis. 0 - Less than -1.5 dB from full scale 1 - Between -1.5 dB and 0 dB 2 - Between 0 dB and 1.5 dB overrange 3 - Greater than 1.5 dB overrange ORR1-ORR0 Overrange Right Detect: These bits determine the overrange on the Right ADC channel. 0 - Less than -1.5 dB from full scale 1 - Between -1.5 dB and 0 dB 2 - Between 0 dB and 1.5 dB overrange 3 - Greater than 1.5 dB overrange DRS DRQ Status: This bit indicates the current status of the PDRQ and CDRQ pins of the CS4231A. 0 - CDRQ AND PDRQ are presently inactive 1 - CDRQ OR PDRQ are presently active ACI Auto-calibrate In-Progress: This bit indicates the state of calibration. The length of time high is dependent on the calibration mode selected. 0 - Calibration not in progress 1 - Calibration is in progress PUR Playback underrun: This bit is set when playback data has not arrived from the host in time to be played. As a result, if DACZ = 0, the last valid sample will be sent to the DACs. This bit is set when an error occurs and is cleared when the Status register (R2) is read. COR Capture overrun: This bit is set when the capture data has not been read by the host before the next sample arrives. The old sample will not be overwritten and the new sample will be ignored. This bit is set when an error condition occurs and is cleared when the Status register (R2) is read. The SER bit in the Status register (R2) is simply a logical OR of the COR and PUR bits. This enables a polling host CPU to detect an error condition while checking other status bits. This register’s initial state after reset is: 00000000 Pin Control (I10) D7 D6 D5 D4 D3 D2 D1 D0 XCTL1 XCTL0 res res DEN res IEN res Error Status and Initialization (I11, Read Only) D7 D6 D5 D4 D3 D2 D1 D0 COR PUR ACI DRS ORR1 ORR0 ORL1 ORL0 CS4231A DS139PP2 35

ID3-ID0 Codec ID: These four bits indicate the ID of the codec. Revisions are con- tained in indirect register 25. These bits are read only. 1010 MODE2 MODE 2: Enables the expanded mode of the CS4231A. Must be set to en- able access to indirect registers 16-31 and their associated features. 0 - MODE 1: CS4248 "look-alike". 1 - MODE 2: Expanded features. This register’s initial state after reset is: 10xx1010 LBE Loopback Enable: When set to 1, the ADC data is digitally mixed with data sent to the DACs. 0 - Loopback disabled 1 - Loopback enabled LBA5-LBA0 Loopback Attenuation: These bits determine the attenuation of the loop- back from ADC to DAC. The least significant bit represents -1.5 dB, with 000000 = 0 dB. See T able 6. This register’s initial state after reset is: 000000x0 PUB7-PUB0 Playback Upper Base: This register is the upper byte which represents the 8 most significant bits of the 16-bit Playback Base register. Reads from this register return the same value which was written. The Current Count registers cannot be read. When set for MODE 1 or SDC, this register is used for both the Play- back and Capture Base registers. This register’s initial state after reset is: 0000000 PLB7-PLB0 Lower Base Bits: This register is the lower byte which represents the 8 least significant bits of the 16-bit Playback Base register. Reads from this register return the same value which was written. When set for MODE 1 or SDC, this register is used for both the Playback and Cap- ture Base registers. This register’s initial state after reset is: 00000000 MODE and ID (I12) D7 D6 D5 D4 D3 D2 D1 D0

1 MODE2 res res ID3 ID2 ID1 ID0

Loopback Control (I13) D7 D6 D5 D4 D3 D2 D1 D0 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 res LBE Playback Upper Base (I14) D7 D6 D5 D4 D3 D2 D1 D0 PUB7 PUB6 PUB5 PUB4 PUB3 PUB2 PUB1 PUB0 Playback Lower Base (I15) D7 D6 D5 D4 D3 D2 D1 D0 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB0 CS4231A

36 DS139PP2

DACZ DAC Zero: This bit will force the out- put of the playback channel to AC zero when an underrun error occurs 1 - Go to center scale 0 - Hold previous valid sample SPE Serial Port Enable. When enabled, audio data from the ADCs is sent out SDOUT and audio data from SDIN is sent to the DACs. MCE must be set before this bit can be changed. 1 - Enable serial port 0 - Disable serial port. Parallel port used for audio data. SF1,SF0 Serial Format. Selects the format of the serial port when enabled by SPE. MCE must be set before these bits can be changed. 0 - 64-bit enhanced 1 - 64-bit 2 - 32-bit 3 - Reserved. PMCE Playback Mode Change Enable. When set, it allows modification of the ste- reo/mono and audio data format bits (D7-D4) for the playback channel, I8. MCE in R0 must be used to change the sample frequency. CMCE Capture Mode Change Enable. When set, it allows modification of the ste- reo/mono and audio data format bits (D7-D4) for the capture channel, I28. MCE in R0 must be used to change the sample frequency. TE Timer Enable: This bit, when set, will enable the timer to run and interrupt the host at the specified frequency in the timer registers. 0 - Timer Disabled - Does not count 1 - Timer Enabled - Counts down OLB Output Level Bit: Sets the analog out- put level. When clear, analog line outputs are attenuated 3 dB. 0 - Full scale of 2 Vpp (-3 dB) 1 - Full scale of 2.8 Vpp (0 dB) This register’s initial state after reset is: 00000000 HPF High Pass Filter: This bit enables a DC-blocking high-pass filter in the digital filter of the ADC. This filter forces the ADC offset of 0. 0 - disabled 1 - enabled XTALE Crystal Enable. When set, both crystals are always active. When clear, only the crystal selected by C2SL, I8, is active with the other crystal powered down. This bit is normally set when working with games software that switch sample frequencies often. APAR ADPCM Playback Accumulator Reset. While set, the Playback ADPCM accumulator is held at zero. Used when pausing a playback stream. TEST Factory T est. These bits are used for factory testing and must remain at 0 for normal operation. This register’s initial state after reset is: 0000x000. LLG4-LLG0 Left Line, LLINE, Mix Gain. The least significant bit represents 1.5 dB, with 01000 = 0 dB. See Table 5. LLM Left Line Mute. When set to 1, the left Line input, LLINE, to the mixer, is muted. This register’s initial state after reset is: 1xx01000. Alternate Feature Enable I (I16) D7 D6 D5 D4 D3 D2 D1 D0 OLB TE CMCEPMCE SF1 SF0 SPE DACZ Alternate Feature Enable II (I17) D7 D6 D5 D4 D3 D2 D1 D0 TEST TEST TEST TEST res APAR XTALE HPF Left Line Input Control (I18) D7 D6 D5 D4 D3 D2 D1 D0 LLM res res LLG4 LLG3 LLG2 LLG1 LLG0 CS4231A DS139PP2 37

0 LSS1 LSS0 LMGE - LAG3 LAG2 LAG1 LAG0

1 RSS1 RSS0 RMGE - RAG3 RAG2 RAG1 RAG0

2 LX1M - - LX1G4 LX1G3 LX1G2 LX1G1 LX1G0

3 RX1M - - RX1G4 RX1G3 RX1G2 RX1G1 RX1G0

4 LX2M - - LX2G4 LX2G3 LX2G2 LX2G1 LX2G0

5 RX2M - - RX2G4 RX2G3 RX2G2 RX2G1 RX2G0

6 LDM - LDA5 LDA4 LDA3 LDA2 LDA1 LDA0

7 RDM - RDA5 RDA4 RDA3 RDA2 RDA1 RDA0

10 XCTL1 XCTL0 - - DEN - IEN -

11 COR PUR ACI DRS ORR1 ORR0 ORL1 ORL0

13 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 - LBE

17 TEST TEST TEST TEST - APAR XTALE HPF

18 LLM - - LLG4 LLG3 LLG2 LLG1 LLG0

19 RLM - - RLG4 RLG3 RLG2 RLG1 RLG0

21 TU7 TU6 TU5 TU4 TU3 TU2 TU1 TU0

25 V2 V1 V0 - - CID2 CID1 CID0

26 MIM MOM MBY - MIA3 MIA2 MIA1 MIA0

30 CUB7 CUB6 CUB5 CUB4 CUB3 CUB2 CUB1 CUB0

31 CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1 CLB0

† IA4 and FMT2 bits are only available in MODE 2 (I12, bit 6 = 1). In MODE1, IA4 is forced to 0.

• When in MODE 1, the playback base registers ( upper and lower) are used for both playback and capture.

§ In I8, MCE must be set to modify the lower 4 bits. MCE or PMCE must be set to modify the upper 4 bits. In I9, MCE must be set to modify the upper 6 bits. PEN and CEN can be changed anytime. In I16, MCE must be set to modify the serial port bits: SF1, SF0, and SPE. In I28, MCE or CMCE must be set to modify the upper 4 bits. Table 3. Register Bit Summary

38 DS139PP2

NOTE: Output level relative to input level assuming OLB=1. Table 5. AUX1 & AUX2 & LINE Mixer Gain Table 6. DAC & Loopback Attenuation Table 7. Mono Mixer Attenuation Table 9. ADC Input Selector

24.576 MHz

Table 8. Sample Frequency Select Linear, 16-bit, 2’s C, LEnd. Table 10. Audio Data Format Table 4. ADC Input Gain

RLG4-RLG0 Right Line, RLINE, Mix Gain. The least significant bit represents 1.5 dB, with 01000 = 0 dB. See T able 5. RLM Right Line Mute. When set to 1, the Right Line input, RLINE, to the mixer, is muted. This register’s initial state after reset is: 1xx01000. TL7-TL0 Lower Timer Bits: This is the low order byte of the 16-bit timer base register. Writes to this register cause both timer base registers to be loaded into the internal timer; therefore, the upper timer register should be loaded before the lower. Once the count reaches zero, an interrupt is generated, if enabled, and the timer is automatically reloaded with these base registers. This register’s initial state after reset is: 00000000. TU7-TU0 Upper Timer Bits: This is the high order byte of the 16-bit timer. The time base is determined by the clock source selected from C2SL in I8: C2SL = 0 - divide XTAL1 by 245 (24.576 MHz - 9.969 µs) C2SL = 1 - divide XTAL2 by 168 (16.9344 MHz - 9.92 µs) This register’s initial state after reset is: 00000000 This register’s initial state after reset is: xxxxxxxx ACF ADPCM Capture Freeze. When set, the capture ADPCM accumulator and step size are frozen. This bit must be clear for adaptation to con- tinue. Used when pausing a capture stream. This register’s initial state after reset is: xxxxxxx0 Right Line Input Control (I19) D7 D6 D5 D4 D3 D2 D1 D0 RLM res res RLG4 RLG3 RLG2 RLG1 RLG0 Timer Lower Base (I20) D7 D6 D5 D4 D3 D2 D1 D0 T L 7T L 6T L 5T L 4T L 3T L 2T L 1T L 0 Timer Upper Base (I21) D7 D6 D5 D4 D3 D2 D1 D0 TU7 TU6 TU5 TU4 TU3 TU2 TU1 TU0 RESERVED (I22) D7 D6 D5 D4 D3 D2 D1 D0 res res res res res res res res Alternate Feature Enable III (I23) D7 D6 D5 D4 D3 D2 D1 D0 res res res res res res res ACF CS4231A

40 DS139PP2

PU Playback Underrun: This bit, when set, indicates that the DAC has run out of data and a sample has been missed. PO Playback Overrun: This bit, when set, indicates that the host attempted to write data into a full FIFO and the data was discarded. CO Capture Overrun: This bit, when set, indicates that the ADC had a sample to load into the FIFO but the FIFO was full. In this case the bit is set and the new sample is discarded. CU Capture Underrun: This bit indicates that the host has read more data out of the FIFO than it contained. In this condition, the bit is set and the last valid byte is read by the host. PI Playback Interrupt: This bit indicates that an interrupt is pending from the playback DMA count registers. When SDC = 1, this bit responds for both capture and playback. CI Capture Interrupt: This bit indicates that an interrupt is pending from the record DMA count registers. When SDC=1, this bit is non-functional. TI Timer Interrupt: This bit indicates that an interrupt is pending from the timer count registers The PI, CI, and TI bits are reset by writing a "0" to the particular interrupt bit or by writing any value to the Status register (R2). This register’s initial state after reset is: x0000000 V2-V0 Version number. As enhancements are made to the CS4231A, the version number is changed so software can distinguish between the different ver- sions. 100 - All CS4231 revisions. See Appendix A. 101 - CS4231A. This Data Sheet. CID2-CID0 Chip Identification. Distinguishes between this chip and future chips that support this register set. 000 - CS4231 or CS4231A This register’s initial state after reset is: 101xx000 MIA3-MIA0 Mono Input Attenuation. When MIM is 0, these bits set the level of MIN summed into the mixer. MIA0 is the least significant bit and represents 3 dB attenuation, with 0000 = 0 dB. See T able 7. MBY Mono Bypass. MBY connects MIN directly to MOUT with an attenuation of 9 dB. When MBY = 1, MIM should be 1. 0 - MIM not connected directly to MOUT . Use MIM and MIA bits. 1 - MIN connected to MOUT directly. MOM Mono Output Mute. The MOM bit will mute the mono mix output, MOUT . This mute is independent of the line output mute. 0 - no mute 1 - mute Alternate Feature Status (I24) D7 D6 D5 D4 D3 D2 D1 D0 res TI CI PI CU CO PO PU Version / ID (I25) D7 D6 D5 D4 D3 D2 D1 D0 V2 V1 V0 res res CID2 CID1 CID0 Mono Input & Output Control (I26) D7 D6 D5 D4 D3 D2 D1 D0 MIM MOM MBY res MIA3 MIA2 MIA1 MIA0 CS4231A DS139PP2 41

MIM Mono Input Mute. This bit controls the mute function on the mono input, MIN to the mixer. The mono input provides mix for the "beeper" func- tion in most personal computers. When MIM = 0, MBY should be 0. 0 - no mute 1 - muted This register’s initial state after reset is: 101x0000. This register’s initial state after reset is: xxxxxxxx M Stereo/Mono Select: This bit deter- mines how the capture audio data stream is formatted. Selecting stereo will result with alternating samples representing left and right audio channels. Selecting mono only cap- tures data from the left audio channel. 0 - Mono 1 - Stereo The C/ L, FMT1, and FMT0 bits set the capture data format in MODE 2. See Table 10 or register I8 for the bit settings and data formats. The capture data format can be different that the playback data for- mat; however, the sample frequency must be the same and is set in I8. MCE (R0) or CMCE (I16) must be set to modify this register. See Changing Audio Data Formats section for more details. This register’s initial state after reset is: 0000xxxx This register’s initial state after reset is: xxxxxxxx CUB7-CUB0 Capture Upper Base: This register is the upper byte which represents the 8 most significant bits of the 16-bit Capture Base register. Reads from this this register returns the same value that was written. This register’s initial state after reset is: 0000000 CLB7-CLB0 Lower Base Bits: This register is the lower byte which represents the 8 least significant bits of the 16-bit Capture Base register. Reads from this register returns the same value which was written. This register’s initial state after reset is: 00000000 RESERVED (I27) D7 D6 D5 D4 D3 D2 D1 D0 res res res res res res res res Capture Data Format (I28) D7 D6 D5 D4 D3 D2 D1 D0 FMT1 FMT0 C/ LS /M res res res res RESERVED (I29) D7 D6 D5 D4 D3 D2 D1 D0 res res res res res res res res Capture Upper Base (I30) D7 D6 D5 D4 D3 D2 D1 D0 CUB7 CUB6 CUB5 CUB4 CUB3 CUB2 CUB1 CUB0 Capture Lower Base (I31) D7 D6 D5 D4 D3 D2 D1 D0 CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1 CLB0 CS4231A

42 DS139PP2

Figure 16 is a suggested layout for the CS4231A. Similar to other Crystal codecs, it is recommended that the device be located on a separate analog ground plane. With the CS4231A’s parallel data interface, however, opti- mum performance is achieved by extending the digital ground plane across pins 65 through 68 and pins 1 through 8. Pins 2 and 8 are grounds for the data bus and should be electrically con- nected to the digital ground plane which will minimize the effects of the bus interface due to transient currents during bus switching. Figure 17 shows the recommended positioning of the decoupling capacitors. The capacitors must be on the same layer as, and close to, the CS4231A. The vias shown go through to the ground plane layer. Vias, power supply traces, and VREF traces should be as large as possible to minimize the impedance. COMPATIBILITY WITH AD1848 The CS4231A is compatible with the AD1848 rev. J silicon, the CS4231, and the CS4248 in terms of the applications circuit. The AD1848 rev K requires 0.1 µF capacitors (not 1000 pF) on pins 26 and 31. The CS4231A requires 1000 pF NPO-type capacitors on filter pins 26 and 31 (not 0.1 µF). To achieve compatibility with the CS4231A: 1. Correct spacing of pads will ensure that either 0.1 µF capacitors (for the AD1848 rev K) or 1000 pF NPO capacitors (for the CS4231A) may be installed. 2. The CS4231A does not require the input anti-aliasing filters included as an input R/C for the AD1848 (5.1kΩ and 560 pF). The additional R/C’s can be used with the CS4231A if desired, with no degrada- tion in performance. 3. Although optimum performance is achieved using the ground plane shown in Figure 16, any ground plane scheme that achieves acceptable performance with the AD1848 should work with the CS4231A. 4. The AD1848 needs extra power and ground pins. The power pins (V DD ) are pins 24, 45, and 54. The ground pins (GNDD) are pins 25 and 44. The CS4231A PLCC package does not use these pins and the appropriate power/ground connections can be made. 5. The Mono In/Mono Out pins do not exist on the AD1848. 6. The AD1848 does not contain 16 mA bus drivers. Therefore, buffers must be used. 7. MODE 2 and all associated features do not exist on the AD1848. 8. The AD1848 does not contain the select- able dither (DEN, I10) 9. The AD1848 is not available in a 100-pin TQFP package. Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. Call: (512) 445-7222 CS4231A DS139PP2 43

Figure 17. Recommended Decoupling Capacitor Positions Figure 16. Suggested Layout Guideline

44 DS139PP2

Figure 24. DAC Phase Response. Figure 23. DAC Transition Band. Figure 22. DAC Passband Ripple. Figure 21. DAC Filter Response.

46 DS139PP2

(Q) Top View CS4231A DS139PP2 47

Parallel Bus Interface Pins CDRQ - Capture Data Request, Output, Pin 12 (L), Pin 7 (Q). The assertion of this signal indicates that the codec has a captured audio sample ready for transfer. This signal will remain asserted until all the bytes from the capture buffer have been transferred. CDAK - Capture Data Acknowledge, Input, Pin 11 (L), Pin 6 (Q). The assertion of this active low signal indicates that the RD cycle occurring is a DMA read from the capture from the buffer. PDRQ - Playback Data Request, Output, Pin 14 (L), Pin 9 (Q). The assertion of this signal indicates that the codec is ready for more playback data. The signal will remain asserted until the bytes needed for a playback sample have been transferred. 13579 6 76 56 36 1 3533312927 37 39 41 43 VD1 DGND1 D4 D3 D5 D2 D6 D1 D7 D0 DGND8 VD2 DBEN DGND2 DBDIR A1 WR A0 RD CDAK CS CDRQ XCTL1 PDAK IRQ PDRQ XCTL0 VD3 TEST DGND3 * NC (V DD ) XTAL1I DGND7 XTAL1O SDOUT VD4 SCLK DGND4 FSYNC XTAL2I SDIN XTAL2O NC PDWN MOUT * NC (VDD )M I N * NC (GNDD) * NC (V DD ) RFILT * NC (GNDD) RLINE RAUX2 RMIC RAUX1 LMIC ROUT LLINE LOUT LFILT LAUX1 VREF LAUX2 VREFI AGND2 AGND1 VA2 * see Power Supply section VA1 CS4231A 68-pin PLCC (L) Top View CS4231A

48 DS139PP2

PDAK - Playback Data Acknowledge, Input, Pin 13 (L), Pin 8 (Q). The assertion of this active low signal indicates that the WR cycle occurring is a DMA write to the playback buffer. A<1:0> - Address Bus, Input, Pin 9, 10 (L), Pin 100, 1 (Q). These address pins are read by the codec interface logic during an I/O cycle access. The state of these address lines determines which register (R0-R3) is accessed. RD - Read Strobe, Input, Pin 60 (L), Pin 75 (Q). This signal defines a read cycle to the codec. The cycle may be an I/O cycle read, or the cycle could be a read from the codec’s DMA sample registers. WR - Write Strobe, Input, Pin 61 (L), Pin 76 (Q). This signal indicates a write cycle to the codec. The cycle may be an I/O cycle write, or the cycle could be a write to the codec’s DMA sample registers. CS - Chip Select, Input, Pin 59 (L), Pin 74 (Q). The codec will not respond to any I/O cycle accesses until this signal goes low. This signal is ignored during the DMA transfers. D<7:0> - Data Bus, Input/Output, Pin 65-68, 3-6 (L), Pin 84-87, 90-93 (Q). These signals are used to transfer data to and from the CS4231A. DBEN - Data Bus Enable, Output, Pin 63 (L), Pin 78 (Q). This pin indicates that the bus drivers attached to the CS4231A should be enabled. This signal is active low. DBDIR - Data Bus Direction, Output Pin 62, (L), Pin 77 (Q). This pin indicates the direction of the data bus transceiver. High points to the CS4231A, low points to the host bus. This signal is normally high. IRQ - Host Interrupt Pin, Output, Pin 57 (L), Pin 72 (Q). This active high signal is used to notify the host of events which need servicing. Serial Audio Port Pins SDOUT - Serial Data Output, Pin 52 (L), Pin 62 (Q). Enabled via SPE in I16, the serial data out pin outputs audio data bits, on the rising edge of SCLK, from the ADCs in the audio data format selected. The serial audio data is always 16 bits wherein the MSB of the different audio formats (16, 8 , 4 bit) is aligned with zero padding after the LSB. When SPE is zero (disabled), this pin is held low. SCLK - Serial Clock, Output, Pin 51 (L), Pin 61 (Q). Enabled via SPE in I16, the serial clock outputs audio data bits on the rising edge of SCLK and receives audio data on the falling edge of SCLK. Two different formats are supported: 64 SCLKs per frame, and 32 SCLKs per frame. When SPE is zero (disabled), this pin is held low. CS4231A DS139PP2 49

FSYNC - Frame Sync, Output, Pin 50 (L), Pin 60 (Q). Enabled via SPE in I16, the frame sync output indicates the start of the data frame. Two different formats are supported: FSYNC high for one bit period before the start of a frame, and FSYNC high during the left word (either 16 or 32 bit periods). When the serial port is disabled, this output is held low. SDIN - Serial Data In, Input, Pin 49 (L), Pin 59 (Q). Enabled via SPE in I16, the serial data input accepts data, on the falling edge of SCLK, from an external source and sends the data to the DACs for conversion to analog. The serial port supports three serial formats and supports all audio data formats of the CS4231A. The serial audio data is always 16 bits wherein the MSB of the different audio (16, 8, 4 bit) is aligned with zero padding after the LSB. Analog Inputs LLINE- Left Line Input, Pin 30 (L), Pin 31 (Q). Nominally 1 V RMS max analog input for the Left LINE channel, centered around VREF. The LINE inputs may be selected for an A/D conversion via the input multiplexer (I0). A programmable gain block (I18) also allows routing to the mixer. RLINE - Right Line Input , Pin 27 (L), Pin 28 (Q). Nominally 1 VRMS max analog input for the Right LINE channel, centered around VREF. The LINE inputs may be selected for A/D conversion via the input multiplexer (I1). A programmable gain block (I19) also allows routing to the mixer. LMIC - Left Mic Input, Pin 29 (L), Pin 30 (Q). Microphone input for the Left MIC channel, centered around VREF. This signal can be either 1 V RMS (LMGE = 0) or 0.1 V RMS (LMGE = 1). The MIC inputs may be selected for A/D conversion via the input multiplexer (I0). RMIC - Right Mic Input, Pin 28 (L), Pin 29 (Q). Microphone input for the Right MIC channel, centered around VREF. This signal can be either 1 VRMS (RMGE = 0) or 0.1 VRMS (RMGE = 1). The MIC inputs may be selected for A/D conversion via the input multiplexer (I1). LAUX1 - Left Auxiliary #1 Input, Pin 39 (L), Pin 45 (Q). Nominally 1 VRMS max analog input for the Left AUX1 channel, centered around VREF. The AUX1 inputs may be selected for A/D conversion via the input multiplexer (I0). A programmable gain block (I2) also allows routing to the output mixer. RAUX1 - Right Auxiliary #1 Input, Pin 42 (L), Pin 48 (Q). Nominally 1 V RMS max analog input for the Right AUX1 channel, centered around VREF. The AUX1 inputs may be selected for A/D conversion via the input multiplexer (I1). A programmable gain block (I3) also allows routing to the output mixer. CS4231A

50 DS139PP2

LAUX2 - Left Auxiliary #2 Input, Pin 38 (L), Pin 44 (Q). Nominally 1 VRMS max analog input for the Left AUX2 channel, centered around VREF. A programmable gain block (I4) allows routing of the AUX2 channels into the output mixer. RAUX2 - Right Auxiliary #2 Input, Pin 43 (L), Pin 49 (Q). Nominally 1 VRMS max analog input for the Right AUX2 channel, centered around VREF. A programmable gain block (I5) allows routing of the AUX2 channels into the output mixer. MIN - Mono Input, Pin 46 (L), Pin 56 (Q). Nominally 1 V RMS max analog input, centered around VREF, that goes through a programmable gain stage (I26) into both channels of the mixer. This is a general purpose mono analog input that is normally used to mix the typical "beeper" signal on most computers into the audio system. On power-up, MIN is connected directly to MOUT, but not to L/ROUT. The default condition can be changed in I26. Analog Outputs LOUT - Left Line Level Output, Pin 40 (L), Pin 46 (Q). Analog output from the mixer for the left channel. Nominally 1 V RMS max centered around VREF when OLB = 1 (I16). When OLB = 0, the output is attenuated 3 dB and is a maximum of 0.707 V RMS ROUT - Right Line Level Output, Pin 41 (L), Pin 47 (Q). Analog output from the mixer for the right channel. Nominally 1 VRMS max centered around VREF when OLB = 1 (I16). When OLB = 0, the output is attenuated 3 dB and is a maximum of 0.707 VRMS MOUT - Mono Output, Pin 47 (L), Pin 57 (Q). When OLB=1 (I16), MOUT is nominally 1 VRMS max analog output, centered around VREF. When OLB=0, the maximum output voltage is 3 dB lower, 0.707 VRMS . This output is a summed analog output from both the left and right output channels of the mixer. MOUT typically is connected to a speaker driver that drives the internal speaker in most computers. Independently mutable via MOM in I26. Miscellaneous XTAL1I - Crystal #1 Input, Pin 17 (L), Pin 12 (Q). This pin will accept either a crystal with the other pin attached to XTAL1O or an external CMOS clock. XTAL1 must have a crystal or clock source attached for proper operation. The standard crystal frequency is 24.576 MHz although other frequencies can be used. The crystal should be designed for fundamental mode, parallel resonance operation. XTAL1O - Crystal #1 Output, Pin 18 (L), Pin 13 (Q). This pin is used for a crystal placed between this pin and XTAL1I. CS4231A DS139PP2 51

XTAL2I - Crystal #2 Input, Pin 21 (L), Pin 16 (Q). If a second crystal is used, it should be placed between this pin and XTAL2O. The standard crystal frequency is 16.9344 MHz although other frequencies can be used. The crystal should be designed for fundamental mode, parallel resonance operation. XTAL2O - Crystal #2 Output, Pin 22 (L), Pin 17 (Q). This pin is used for a crystal placed between this pin and XTAL2I. PDWN - Power Down, Input, Pin 23 (L), Pin 18 (Q). Places CS4231A in lowest power consumption mode. All sections of the CS4231A, except the digital bus interface which reads 80h, are shut down and consuming minimal power. The CS4231A is in power down mode when this pin is logic low. XCTL0, XCTL1 - External Control, Output, Pin 56, 58 (L), Pin 71, 73 (Q). These signals are controlled by the register bits XCTL0 and XCTL1 in register I10. They can be used to control external logic via TTL levels. VREF - Voltage Reference, Output, Pin 32 (L), Pin 35 (Q). All analog inputs and outputs are centered around VREF which is nominally 2.1 V olts. This pin may be used to level shift external circuitry, although any AC loads should be buffered. High internal-gain microphone inputs S/N ratio can be slightly improved by placing a 10µF capacitor on VREF. VREFI - V oltage Reference Internal, Input, Pin 33 (L), Pin 38 (Q). V oltage reference used internal to the CS4231A must have a 0.1 µF + 10 µF capacitor with short fat traces to attach to this pin. No other connections should be made to this pin. LFILT - Left Channel Antialias Filter Input, Pin 31 (L), Pin 33 (Q). A 1000 pF NPO capacitor must be attached between this pin and analog ground. RFILT - Right Channel Antialias Filter Input, Pin 26 (L), Pin 25 (Q). A 1000 pF NPO capacitor must be attached between this pin and analog ground. TEST - Test, Pin 55 (L), Pin 70 (Q). This pin must be tied to ground for proper operation. Power Supplies V A1, V A2 - Analog Supply Voltage, Pin 35, 36 (L), Pin 41, 42 (Q). Supply to the analog section of the codec. AGND1, AGND2 - Analog Ground, Pin 34, 37 (L), Pin 40, 43 (Q). Ground reference to the analog section of the codec. Internally, these pins are connected to the substrate as are DGND3/4/7/8; therefore optimum layout is achieved with the AGND pins on the same ground plane as DGND3/4/7/8 (see Figure 17). However, other ground arrangements should yield adequate results. CS4231A

52 DS139PP2

VD1, VD2 - Digital Supply Voltage, Pin 1, 7 (L), Pin 88, 98 (Q). Digital supply for the parallel data bus section of the codec. VD3, VD4 - Digital Supply V oltage, Pin 15, 19 (L), Pin 10, 14 (Q). Digital supply for the internal digital section of the codec (except for the parallel data bus). DGND1, DGND2 - Digital Ground, Pin 2, 8 (L), Pin 89, 99 (Q). Digital ground reference for the parallel data bus section of the codec. These pins are isolated from the other digital grounds and should be connected to the digital ground section of the board (see Figure 17). DGND3, DGND4, DGND7, DGND8 - Digital Ground, Pin 16, 20, 53, 64(L), Pin 11, 15, 69, 79 (Q). Digital ground reference for the internal digital section of the codec (except the parallel data bus). These pins are connected to the substrate of the die as are the AGND pins. Optimum layout is achieved by placing DGND3/4/7/8 on the analog ground plane with the AGND pins as shown in Figure 17. However, other ground arrangements should yield adequate results. *NC (V DD ) - No Connect, Pins 24, 45, 54 (L) These pins are no connects for the CS4231A. When compatibility with the AD1848 is desired, these pins should be connected to the digital power supply. For other compatibility issues, see the Compatibility with AD1848 section of the data sheet. *NC (GNDD) - No Connect, Pins 25, 44 (L) These pins are no connects for the CS4231A. When compatibility with the AD1848 is desired, these pins should be connected to digital ground. For other compatibility issues, see the Compatibility with AD1848 section of the data sheet. CS4231A DS139PP2 53

The number of bits in the input words to the DACs, and in the output words in the ADCs. Differential Nonlinearity The worst case deviation from the ideal code width. Units in LSB. Total Dynamic Range TDR is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor. It is measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e. attenuation bits for the DACs at full attenuation). Units in dB. Instantaneous Dynamic Range IDR is the ratio of a full-scale rms signal to the rms noise available at any instant in time, without changing the input gain or output attenuation settings. It is measured using S/(N+D) with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal. Use of a small input signal reduces the harmonic distortion components to insignificance when compared to the noise. Units in dB. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. Interchannel Isolation The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz 0 dB signal present on the other channel. Units in dB. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units in dB. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation in volts of the output from VREF with mid-scale input code. CS4231A

54 DS139PP2

This data sheet describes the CS4231A which is backwards compatible with the CS4231 - both hard- ware and software. The CS4231A uses four pins that were "No Connects", on the CS4231 (for the audio serial port). Since the CS4231 defines these pins as "No Connects", the CS4231A will drop into a CS4231 socket and function properly, although the serial port will not be connected. There are also software additions to the CS4231A. New bits have been defined to enhance the opera- tion of the CS4231A. These added bits were reserved in the CS4231. The data sheet states that reserved bits should be written as 0 and may read back as 0 or 1; therefore, properly written software is forwards compatible with the CS4231A. The version bits V2-V0 (upper three bits of I25) distinguish between the CS4231 and the CS4231A. The additions to the CS4231A are as follows: 1. Interface Configuration register (I9): The CAL1 bit does not exist in the CS4231. The CAL0 bit was labeled ACAL in the CS4231 but the function was the same. The extra calibration modes in the CS4231A better support full duplex and games software. 2. Alternate Feature Enable I register (I16): The PMCE and CMCE bits do not exist in the CS4231. These bits were added to enhance full-duplex operation. The serial audio data port and associated bits - SF1, SF0, SPE - do not exist on the CS4231. The serial audio data port was added to the CS4231A to allow DSP’s and ASIC’s to act as an audio coprocessor to the CS4231A. 3. Alternate Feature Enable II register (I17): The APAR and XTALE bits do not exist in the CS4231. The APAR bit was added better support the ADPCM playback mechanism. The XTALE bit was added to better support software that switches sample frequencies often, e.g. games. 4. Alternate Feature Enable III register (I23): The ACF bit does not exist on the CS4231. This bit better supports the ADPCM capture mechanism. 5. Version / ID register (I25): The V ersion number bits - V2, V1, V0 - were modified (changed to 101) to allow software to uniquely identify the CS4231A. 6. Mono Input & Output Control register (I26): The MBY bit does not exist in the CS4231. The power up default value of this register was also changed. The extra bit and the changes will approxi- mate the CS4231 at power-up. The difference is that the MIN pin (normally the PC beeper) is directed to the MOUT pin - but not to the L/ROUT pins. CS4231A DS139PP2 55

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES. 0.25 (0.010) R Max 1.27 (0.050) MIN MAX MIN MAX MIN MAX AB C 25.02 (0.985) 25.27 (0.995) 24.13 24.33 (0.950)(0.958) 22.61 23.62 (0.890)(0.930)68

3 NOM

C 0.51 (0.020) 2.29 (0.090) Min 3.30 (0.130) Max 4.20 (0.165) Min 5.08 (0.200) Max 1.07 (0.042) Min 1.42 (0.056) Max x45deg.NOM 0.33 ( 0.013 )Min 0.53 (0.021)Max x 45deg. Nom 1.067 (0.042) Min 1.219 (0.048) Max D EE 1 e1 b 100 N A b c D E 100-pin TQFP T Symbol Description Lead Count Overall Height Stand Off Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Angle MIN NOM MAX 0.077 100 0.00 0.14 15.70 15.70 0.40 0.30 0.0° 12.0° 0.20 0.127 16.00 14.0 16.00 14.0 0.50 0.50 1.66 0.26 0.177 16.30 16.30 0.60 0.70 A1 A c T Notes: 1) Dimensions in millimeters. 2) Package body dimensions do not include mold protrusion, which is 0.25 mm. 3) Coplanarity is 0.004 in. 4) Lead frame material is AL-42 or copper, and lead finish is solder plate. 5) Pin 1 identification may be either ink dot or dimple. 6) Package top dimensions can be smaller than bottom dimensions by 0.20 mm. 7) The "lead width with plating" dimension does not include a total allowable dambar protrusion of 0.08 mm (at maximum material condition). 8) Ejector pin marks in molding are present on every package. CS4231A

56 DS139PP2

• PC ISA Plug-In Card
• Serial Audio Data Port Header for CS4231A Support
• Mono In / Mono Out Support
• Microphone Pre-Amplifier
• Line Out / Headphone Circuit
• Microsoft Windows 3.1 Software Support General Description The CDB4231/4248 evaluation board supports all the features of the CS4231A, CS4231, and CS4248. The DMA, IRQ, and base address are all selectable via on- board jumpers. Four stereo jacks provide MIC in, AUX1 in, LINE in, and Line/Headphone out. In addi- tion, on-board headers provide an internal analog CD-ROM interface via the AUX2 inputs, and support for the mono in and mono out capabilities of the CS4231. The CDB4231 also includes a serial port header to support the expanded features of the CS4231A. Software that runs under Microsoft Windows 3.1 is also provided along with an extensive diagnostics pro- gram. ORDERING INFORMATION: CDB4231, CDB4248 SEP ’95 DS111DB7 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 Fax: (512) 445 7581 CS4231/4248 Evaluation Board Semiconductor Corporation CDB4231/4248 CS4231A/ Digital Patch Area CDROM IN (Aux2) Line In Line/Head- Aux1 In Mic In A = 2 A = 1/2 A = 8 Speaker In Speaker Out CS4231/ DMA INT Address Decode PC Bus J18 Base Address phone Out A = 1/2 CAPTURE DMA PLAY A = 1/2 CS4248

The CDB4231/4248 is designed to provide an easy platform for evaluating the performance of the CS4231A, CS4231, or CS4248 Parallel Inter- face, Multimedia Audio Codecs in a PC environment. This board is not a reference de- sign, although many aspects of the design should be incorporated in reference designs. The board is optimized for performance and ease of modifi- cation for testing purposes. For those interested in a reference design, the CRD4231 provides most of the capabilities of the CDB4231, plus games support. Software that operates under the Microsoft Win- dows  environment is also included with applets that control all the CS4231 or CS4248 features. This software also provides full Win- dows  3.1 compatibility with extensions to utilize the more powerful CS4231 features in custom code. Four stereo jacks, externally accessible, allow connection to Microphone inputs, Auxiliary 1 in- puts, Line inputs, and Line/Headphone outputs. Headers allow internal connections to a CD- ROM analog output (using the codec’s Auxiliary 2 inputs), and speaker pass-through and control via the SPEAKER IN (Mono In) and SPEAKER OUT (Mono Out) headers. Additional headers on the board allow the setting of the Base Address, DMA channel, and IRQ for the CS4231. The factory default for the CDB4231 is base address 530h, DMA playback channel 3, DMA capture channel 0 and IRQ 7. The CDB4248 is the same with the exception of the DMA capture header which is not used and has both shorting jumpers removed. The software must be configured to match the settings on the evaluation board headers for proper operation. STEREO ANALOG INPUTS Three of the four external 1/8" stereo jacks are for analog inputs. The stereo Mic I, Microphone Input, (Figure 2) contains an op-amp buffer with a gain of 18 dB providing a maximum full scale input to the evaluation board of 12 mV (with the 20 dB boost inside the codec enabled). For mi- crophones that output signals larger than 12 mV , the 20 dB gain block inside the codec can be disabled in software (the "Boost" button in the input applet). With the 20 dB gain block dis- abled, the maximum full-scale value is 120 mV . The microphone circuit is designed for single- ended microphones which are the most common type available. The J35 header, close to the mic input jack allows selection of a stereo micro- phone when the jumper is in the ’S’ position, or mono input where the jumper is in the ’M’ posi- tion. In the mono position, a mono mic input would go to both the left and right mic input pins on the codec. The second input jack is Ax1 I, Auxiliary 1 In, (Figure 1) which has an input impedance of ap- proximately 10 kΩ with a maximum full scale into the Ax1 I jack of 2 VRMS . The third stereo input jack is Line I, Line In, (Figure 4) which also has a maximum full scale of 2 V RMS and provides a typical audio input impedance of 47 kΩ . An internal header, labeled CDROM IN (AUX2), (Figure 4) may be used by any internal device for analog mixing into the codec’s output mixer via the Auxiliary 2 inputs, AUX2. Since the AUX2 inputs don’t have a path to the ADCs, when nothing is plugged into the Line I jack, the analog contained on the CDROM IN header is summed into the Line inputs of the codec as well as the AUX2 inputs. When a plug is in- serted into the Line I jack, the CDROM IN header is disconnected from the Line inputs (but is still connected to the AUX2 inputs). CDB4231/4248

58 DS111DB7

The CDB4231/4248 contains one stereo analog output labeled Ln/Hp O , Line/Headphone Out, (Figure 5) with a maximum full-scale output of 2 VRMS . This output provides a high-quality line out for use with external power amps or other equipment containing line-level inputs. It is also designed to drive headphones directly with ex- ceptional quality. MONO INPUT AND OUTPUT The CS4231 contains a MIN (mono in) pin and a MOUT (mono out) pin that are typically placed in between the internal PC speaker and the beeper chip. The CDB4231 comes with a ca- ble that should be connected between the PC beeper chip and the SPEAKER IN header (Fig- ure 1) on the CDB4231 board. The cable wire, pin 1, should be placed on pin 1 of the SPEAKER IN header and pin 1 of the beeper header. If the PC beeps do not mix into the codec, try reversing the beeper header connector. This connects the beeper to the MIN pin on the CS4231 and allows traditional PC beeps to be mixed into the audio path. The SPEAKER OUT header (Figure 3) should be connected to the PC speaker. The MOUT pin on the CS4231 is a mix of both left and right chan- nels and has an independent software mute. The quality of this circuit is limited to the quality of the speaker used. Much higher fidelity can be achieved by using a higher quality speaker. Since the CS4248 does not have MIN and MOUT pins, the CDB4248 board does not pro- vide a cable, and the SPEAKER IN and SPEAKER OUT headers are non-functional. SERIAL AUDIO DATA PORT The CS4231A contains a serial audio data port that can pass audio data from the ADCs and to the DACs across the serial port. All control data must still be transferred via the ISA bus. The CDB4231 supports the CS4231A by providing a header, labeled J34, that is connected to the se- rial audio data port on the CS4231A. The even pins are connected to ground and the rest of the header pins are defined as follows: 1 - not used 3 - SDOUT 5 - SDIN 7 - SCLK 9 - FSYNC Twisted pair ribbon cable should be used when connecting to this header. Since the CS4231 and CS4248 do not support the serial audio data port, these pins are non-functional on the CDB4248 and when using a CS4231. BASE ADDRESS The base address is set using header J18 (Fig- ure 6) and must match the software selected base address. The CDB4231/4248 evaluation board uses 8 I/O addresses. The first four are used to read the board ID of 04. Writes to the first four addresses are ignored. The board ID is output from the ID31 PLD and indicates that the board is Windows Sound System, WSS, compatible (see limitations listed in the SOFTWARE COM- P ATIBILITY section). CDB4231/4248 DS111DB7 59

The second four addresses are used by the codec. The default for the evaluation board and the software is 530h - no jumpers. The following table lists the available base addresses (along with the associated codec address), with a "1" defined as no shorting jumper and a "0" defined as a shorting jumper installed: Base Codec X1 X0 Address Address 1 1 530h 534h (default) 1 0 604h 608h 0 1 E80h E84h 0 0 F40h F44h INTERRUPT Although the hardware supports a wide selection of interrupts, software may have limitations in the available options. See the SOFTWARE COM- P ATIBILITY section for more information. The interrupt is set using header J2, also labeled INT, (Figure 7) and must also match the software selected interrupt. The default for the evaluation board and the software is 7. DMA SELECTION Although the hardware supports a wide selection of DMA channels for playback and capture, soft- ware may have limitations in the available options. See the SOFTWARE COMP ATIBILITY section for more information. The CDB4231 contains two headers for DMA selection: one determines the playback channel and the other, if used, determines the capture channel for full duplex operation. Two shorting jumpers are needed for the selected DMA chan- nel, one for the DRQ and one for the DACK. Header J20, labeled DMA PLAY , (Figure 7) is the primary DMA channel used for both playback and capture on the CS4248 or CS4231 in SDC mode, as well as playback on the CS4231 in full-duplex operation. Half Duplex - Single DMA Channel The default configuration for the CDB4231 is full duplex. When the evaluation board is config- ured for half duplex, both jumpers on the DMA CAPTURE header J1, (Figure 7) SHOULD BE REMOVED. Otherwise, contention with other system resources may occur. The CS4248 does not contain the second set of DMA base registers; therefore, it must be oper- ated in half duplex mode. Since only one DMA channel is needed at any particular time, the CS4248 is usually operated in Single DMA Channel, SDC, mode. If only one DMA channel is available, the CS4231 can be programmed for SDC mode wherein the playback channel, selected on the DMA PLAY header is used for both playback and capture. The default setting for the evaluation board for the DMA PLAY header DRQ3/DACK3. Full Duplex - Two DMA Channels Full duplex is only supported on the CS4231 (MODE 2 operation) which contains independent capture and playback DMA Base registers. The J1 header, labeled DMA CAPTURE , (Fig- ure 7) is used to support simultaneous capture in the CS4231 full-duplex mode. The default for the CDB4231 evaluation board DMA CAPTURE header, J1, is DRQ0/DACK0. To support full-duplex operation, a unique DMA channel from each header must be selected. CDB4231/4248

60 DS111DB7

The CDB4231/4248 comes with two sets of soft- ware: diagnostics and Windows 3.1 drivers. The diagnostics will support all hardware jumper set- tings. The Windows software will support all hardware settings when configured for generic hardware. When the included Windows software (or any software) is configured or designed for 100% Windows Sound System compatibility, limitations in the hardware selections exist. The CDB4231/4248 evaluation board includes a board ID PLD, ID31, that indicates to software that the board is Windows Sound System, WSS, compatible. This read-only register is located at the first four addresses (the second four are for the codec). This ID will read back 0x04 from the lower six bits. Although the evaluation board is WSS compatible from the codec register per- spective, the auto-select hardware of the WSS board is not included. The DMA and IRQ set- tings must be configured via on-board jumpers. The four base addresses supported by the evalu- ation board are the same as specified for WSS hardware. Windows software, such as the included drivers and applets, that check for a WSS board will read the board ID and assume that the auto-se- lect register needs to be loaded. The auto-select register only allows certain combinations which must be adhered to when using the evaluation board with this software. Therefore, to run 100% compatible Windows Sound System, WSS, software, the IRQ and DMA selection must be made from the follow- ing: INT: 7 (default) Half Duplex:DMA PLAY: 3 (CDB4248 default) DMA CAPTURE: No jumpers (CDB4248 default) Full Duplex: PLAY CAPTURE 0 1 1 0 (CDB4231 default) 3 0 Note in full duplex, only the three combinations listed are allowed with the last combination be- ing the default for the CDB4231. If the software does not support full duplex, remove the jumpers on the DMA CAPTURE header, J1 (Figure 7). The Crystal Windows software provided with the evaluation board can be configured for 100% WSS compatible hardware and will load the Auto-Select register with the proper DMA and IRQ settings. In 100% WSS mode, the Crystal software will not allow improper settings for the DMA and IRQ. Some hardware, including the CDB4231/4248, allow selection of DMA and IRQ via on-board jumpers. These jumpers allow a wider selection of configuration options since it is not limited by the Auto-Select register options listed above. CDB4231/4248 DS111DB7 61

The Crystal Windows 3.1 software (version 1.04) supports a "generic hardware" switch that forces the software to use the DMA and IRQ set- tings in the SYSTEM.INI file and assume no Auto-Select register exists. With this switch on, all combinations of DMA and IRQ, supported by the hardware, are allowed. To use this option, the SYSTEM.INI file must contain: [CSBusAud] GenericHardware=On ; either On or Off ; Off is default This switch is added to the SYSTEM.INI file by the installation software when the "Generic Hardware" option is selected from the Windows Sound System screen. WSS SOFTWARE COMPATIBILITY The CS4231/4248 is compatible with Microsoft Windows Sound System software (version 2.0) with respect to wave audio data support. Since the evaluation board does not contain a synthe- sizer, the MIDI portion of WSS will not function. When installing the Microsoft software, select Custom Installation and set the base ad- dress, IRQ, and DMA channel consistent with the evaluation board jumper settings. Since the board does not contain the extra hardware needed for software configuration of the IRQ and DMA channel, the Auto Installation mode of the Microsoft WSS software is not supported. The Microsoft WSS hardware and software driv- ers do not use all the analog inputs. The only hardware supported by the Microsoft WSS hard- ware and software are a mono microphone input (set jumper on J35 to M), and the stereo Line input jack, Line I. CRYSTAL ENHANCED WSS 2.0 DRIVERS Crystal also provides enhanced Windows Sound System drivers that support software written to the Windows Sound System standard. These drivers, currently version 1.0, were designed to support the CRD4231 reference design, but will also support the CDB4231. When using the En- hanced WSS 2.0 drivers, the following settings in the SYSTEM.INI file must be set to: OldMSDosGameCompatibility=0 BlasterSupport=SWEmulation Msft Hardware=0 Auto Select=0 Midi Play=0 SCHEMATICS The following pages contain the full schematics for the CDB4231/4248, the PLD equations, and layout plots of each PCB layer. Windows and Windows Sound System are registered trademarks of Microsoft Corporation CDB4231/4248

62 DS111DB7

Figure 1. C S4231 & A ux1 In

Figure 2. Microphone In Figure 3. Mono Speaker Out

64 DS111DB7

Figure 4. Line In & CDROM In (Aux2)

Figure 5. Line/Headphone Out

66 DS111DB7

Figure 6. A ddress D ecode and B oard ID

Figure 7. A nalog Pow er & B uffer

68 DS111DB7

;PALASM Design Description ; CDB4231 Rev. D TITLE Address Decode for CS4231 and Read ID PATTERN AD31.PDS REVISION 2.0 AUTHOR Clif Sanchez COMPANY Crystal Semiconductor DATE 10/15/93 CHIP _AD31 PAL20V8 PIN 1 AEN ; Eight addresses in all. PIN 2 A2 ; The first four addresses are used by the PIN 3 A3 ; board PLD ID31 - address select RDID. PIN 4 A4 ; The second four addresses are used by the PIN 5 A5 ; CS4231/4248. PIN 6 A6 PIN 7 A7 ; Base Address: X1,X0 (header J18) PIN 8 A8 ; 1 1 530-537, codec 534 PIN 9 A9 ; 1 0 604-60B, codec 608 PIN 10 A10 ; 0 1 E80-E87, codec E84 PIN 11 A11 ; 0 0 F40-F47, codec F44 PIN 13 X0 ; I - Address selector X1,X0: PIN 14 X1 ; I - PIN 15 /DBENP ; O - Data Bus Enable Prime for 245 chip PIN 16 /IOR ; I - Qualifies Read ID enable PIN 17 A0 ; I - from bus PIN 18 BA0 ; O - Buffered A0 (PLD just used for buffer) PIN 19 /RDID ; O - Read ID register enable PIN 20 RESDRV ; I - Global Reset PIN 21 /CCS ; O - Chip Select for Codec PIN 22 /CRES ; O - Inverted RESDRV - to codec PWDN pin PIN 23 /DBEN ; I - Data Bus Enable from codec EQUATIONS /BA0 = /A0 RDID = /A11*A10*/A9* A8*/A7*/A6* A5* A4*/A3*/A2*/AEN*IOR* X1* X0 ; 530-533 + /A11*A10* A9*/A8*/A7*/A6*/A5*/A4*/A3* A2*/AEN*IOR* X1*/X0 ; 604-607 + A11*A10* A9*/A8* A7*/A6*/A5*/A4*/A3*/A2*/AEN*IOR*/X1* X0 ; E80-E83 + A11*A10* A9* A8*/A7* A6*/A5*/A4*/A3*/A2*/AEN*IOR*/X1*/X0 ; F40-F43 CCS = /A11*A10*/A9* A8*/A7*/A6* A5* A4*/A3* A2*/AEN* X1* X0 ; 534-537 + A11*A10* A9*/A8* A7*/A6*/A5*/A4*/A3* A2*/AEN*/X1* X0 ; E84-E87 + A11*A10* A9* A8*/A7* A6*/A5*/A4*/A3* A2*/AEN*/X1*/X0 ; F44-F47 DBENP = DBEN + A11*A10* A9*/A8* A7*/A6*/A5*/A4*/A3* /AEN*/X1* X0 ; E80-E87 + A11*A10* A9* A8*/A7* A6*/A5*/A4*/A3* /AEN*/X1*/X0 ; F40-F47 CRES = RESDRV Address PLD - AD31 CDB4231/4248 DS111DB7 69

;PALASM Design Description TITLE Read ID + relay enable PATTERN ID31.PDS REVISION 2.0 AUTHOR Clif Sanchez COMPANY Crystal Semiconductor DATE 10/28/93 CHIP _ID31 PAL22V10 PIN 1 MUTE ; I - from Codec XCTL1 pin, Software Mute PIN 2 /BIOR ; I - buffered /IOR from 244 PIN 3 /CRES ; I - inverted RESDRV from the AD31 PLD PIN 4 /CCS ; I - codec chip select, used for ACCESS PIN 5 /RDID ; I - Read ID chip select, from the AD31 PLD PIN 6 INT PIN 7 NC PIN 8 NC PIN 9 NC PIN 10 NC PIN 11 NC PIN 13 SBHE ; I PIN 14 D0 ; O - Data Bus, Enabled for /RDID PIN 15 D1 ; O Places Read on the data bus PIN 16 D2 ; O PIN 17 D3 ; O PIN 18 D4 ; O PIN 19 D5 ; O PIN 20 D6 ; O PIN 21 D7 ; O PIN 22 ACCESS ; O - True after first read of the codec PIN 23 /RLYEN ; O - Relay Enable EQUATIONS D0 = GND D0.TRST = RDID D1 = GND D1.TRST = RDID D2 = VCC D2.TRST = RDID D3 = GND D3.TRST = RDID D4 = GND D4.TRST = RDID D5 = GND D5.TRST = RDID D6 = /INT D6.TRST = RDID D7 = SBHE D7.TRST = RDID Board ID PLD - ID31 CDB4231/4248

70 DS111DB7

ACCESS = ACCESS * /CRES + CCS * BIOR * /CRES RLYEN = ACCESS * /MUTE Board ID PLD - ID31 (continued) CDB4231/4248 DS111DB7 71

Figure 8. Silk Screen

72 DS111DB7

Figure 9. Component Side (Top , 1st Layer)

Figure 10. Solder Side (Bottom, 4th Layer)

74 DS111DB7

Figure 11. Ground (2nd Layer - Inverse)

Figure 12. Power (3rd Layer - Inverse)

76 DS111DB7