CS4228A_03 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
!Six 24-bit D/A converters - 100 dB dynamic range - -90 dB THD+N !Two 24-bit A/D converters - 97 dB dynamic range - -88 dB THD+N !S a m p l er a t e su pt o1 0 0k H z !Pop-free digital output volume controls - 90.5 dB range, 0.5 dB resolution (182 levels) - Variable smooth ramp rate, 0.125 dB steps !Mute control pin for off-chip muting circuits !On-chip anti-alias and output filters !De-emphasis filters for 32, 44.1 and 48 kHz
Description
The CS4228A codec provides two analog-to-digital and six digital-to-analog Delta-Sigma converters, along with volume controls, in a compact 28-pin SSOP device. Combined with an IEC958 (SPDIF) receiver (like the CS8414) and surround sound decoder (such as one of the CS492x or CS493xx families), it is ideal for use in DVD player, A/V receiver and car audio systems sup- porting multiple standards such as Dolby Digital AC-3 AAC,D T S, Dolby ProLogic ,T H X, and other multi-channel formats. A flexible serial audio interface allows operation in Left Justified, Right Justified, I2S, or One Line Data modes.
ORDERING INFORMATION
CS4228A-KS -10° to +70°C 28-pin SSOP CDB4228A Evaluation Board I SCL/CCLK SDA/CDIN VD FLLRCK SCLK SDIN1 SDOUT SERIAL AUDIO CONTROL PORT DIGITAL FILTERS ANALOG LOW PASS AND OUTPUT STAGE VA FR AINL+ AINL- SDIN2 MCLK DGND SL SR AINR+ AINR- LEFT ADC SDIN3 MUTECAD0/CS RST FILT CENTER SUB DIGITAL FILTERS DATA INTERFACE VL RIGHT ADC AGND WITH DE-EMPHASIS ∆Σ DAC #1 CLOCK MANAGER MUTE CONTROL ∆Σ DAC #2 ∆Σ DAC #3 ∆Σ DAC #4 ∆Σ DAC #5 ∆Σ DAC #6DIGITAL VOLUME DIGITAL VOLUME DIGITAL VOLUME DIGITAL VOLUME DIGITAL VOLUME DIGITAL VOLUME MAR ‘03 DS511F1
Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go towww.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms andconditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is as- sumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringementof patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creatingany work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC ForeignT r a d e Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTH- ER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANT- ABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOM- ER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I 2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system. DTS is a registered trademark of the Digital Theater Systems, Inc. Dolby, Dolby Digital, AC-3, AAC, and Pro Logic are registered trademarks of Dolby Laboratories, Inc. THX is a registered trademark of Lucasfilms Ltd.
- CHARACTERISTICS AND SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA =2 5°C, VA = 5.0V, VD = 5.0V) SPECIFIED OPERATING CONDITIONS ((AGND, DGND = 0V; all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to ground.) Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 2. The maximum over or under voltage is limited by the input current. 3. Bidirectional pins configured as inputs. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Min Typ Max Units DC Power Supply Digital Analog Interface VD - VL (Note 12) VD VA VL 4.75 4.75 3.0* 5.0 5.0 5.25 5.25 5.25 2.00 V V V V Specified Temperature Range (-KS) T A -10 - 70 °C Parameter Symbol Min Max Units DC Power Supply Digital Analog Interface VD - VL VD VA VL -0.3 -0.3 -0.3 6.0 6.0 6.0 2.0 V V V V Input Current (Note 1) - ±10 mA Analog Input Voltage (Note 2) -0.7 VA + 0.7 V Digital Input Voltage Input Pins Bidirectional Pins (Notes 2 and 3) -0.7 -0.7 VL + 2.5 VL + 0.7 V V Ambient Temperature (Power Applied) -55 +125 °C Storage Temperature -65 +150 °C
ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): Input test signal is a
997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL =1 0k Ω,C L =1 5p F )
Notes: 4. Referenced to typical full-scale differential input voltage (2 Vrms). Tested at -1 dBFS 5. Filter characteristics scale with output sample rate. 6. The analog modulator samples the input at 128 times Fs. For example, to obtain an output sample rate of 48 kHz the input must be sampled at 6.144 MHz. There is no rejection of input signals which are 7. High Pass Filter characteristics are specified for Fs=44.1 kHz. Base Rate Mode High Rate Mode Parameter Symbol Min Typ Max Min Typ Max Units Analog Input Characteristics - Minimum gain setting (0 dB) Differential Input; unless otherwise specified. Dynamic Range, -60 dBFS input (A weighted) (unweighted) 91 97 91 97 dB dB Total Harmonic Distortion + Noise (Note 4) THD+N - -88 -83 - -88 -83 dB Interchannel Isolation - 100 - - 100 - dB Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Offset Error (with high pass filter) - - 0 - - 0 LSB Gain Drift - 100 - - 100 - ppm/°C Input Resistance 10 - - 10 - - k Ω Input Capacitance - - 15 - - 15 pF A/D Decimation Filter Characteristics Passband (Note 5) 0.022 - 21.77 0.022 - 43.54 kHz Passband Ripple - - 0.01 - - 0.05 dB Stopband (Note 5) 30.0 - 6114 72.41 - 6071 kHz Stopband Attenuation (Note 6) 80 - - 45 - - dB Group Delay t gd - 17/Fs - - 17/Fs - s Group Delay Variation vs. Frequency ∆ tgd --0--0 µs High Pass Filter Characteristics Frequency Response: -3 dB (Note 7) -0.13 dB 3.4 3.4 Hz Hz Phase Deviation @ 20 Hz (Note 7) - 10 - - 10 - Degree Passband Ripple - - 0 - - 0 dB
ANALOG CHARACTERISTICS (Continued) 8. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz, the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs. 9. Digital filter characteristics. 10. Measurement bandwidth is 10 Hz to 3 Fs. Base Rate Mode High Rate Mode Parameter Symbol Min Typ Max Min Typ Max Units Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 10 pF load; unless otherwise specified. Dynamic Range, -60 dBFS input (A weighted) (unweighted) 100 100 dB dB Total Harmonic Distortion + Noise (unweighted) THD+N - -90 -83 - -90 -83 dB Interchannel Isolation - 95 - - 95 - dB Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Offset Voltage - 10 - - 10 - mV Gain Drift - 100 - - 100 - ppm/°C Analog Output Load Minimum Load Resistance: Maximum Load Capacitance: 100 100 kΩ pF Combined Digital and Analog Filter Characteristics Frequency Response 10 Hz to 20 kHz ±0.1 ±0.1 dB Deviation from Linear Phase - ±0.5 - - ±0.5 - Degrees Passband: to 0.01 dB corner (Notes 8, 9) 0 - 21.77 0 - 43.54 kHz Passband Ripple (Note 9) - - ±0.01 - - ±0.01 dB Stopband (Notes 8, 9) 26.2 - - 62.5 - - kHz Stopband Attenuation (Notes 8, 10) 70 - - 65 - - dB Group Delay (Fs = Input Word Rate) tgd - 29/Fs - - 17/Fs - s Analog Loopback Performance Signal-to-noise Ratio (CCIR-2K weighted, -20 dB FS input) CCIR-2K - 90 - - 90 - dB
POWER AND THERMAL CHARACTERISTICS Notes: 11. Current consumption increases with increasing FS and increasing MCLK. Variance between speed m o d e si ss m a l l . 12. VD current consumption increases (ID normal and ID_pdn) when VD - VL > 1.5V. When VD - VL = 1.7V, ID typically increases by 2 mA and when VD - VL = 2V, ID typically increases by 12 mA. 13. Power down mode is defined as RST pin = Low with clocks running. DIGITAL CHARACTERISTICS (AGND, DGND = 0V, all voltages with respect to ground.) Parameters Symbol Min Typ Max Units Power Supplies Power Supply Current normal operation, V A=V D =VL =5V (Note 11, Note 12) BRM power-down state (all supplies) (Note 13) BRM IA ID IL IA ID IL 0.3 0.2 0.4 0.2 105 0.5 mA mA mA mA mA mA Power Dissipation (Note 11) V A=V D =V L = 5V normal operation power-down (Note 13) 567 715 12.5 mW mW Package Thermal Resistance TSSOP (-KS) θJA θJC °C/Watt °C/Watt Power Supply Rejection Ratio (1 kHz, 10 mV rms)P S R R - 5 0 - d B Parameter Symbol Min Max Units High-level Input Voltage VL=5V Low-level Input Voltage VIH VIL 0.7 x VL 0.3 x VL V V High-level Input Voltage VL=3.3V Low-level Input Voltage VIH VIL 2.2 1.0 V V High-level Output Voltage at VL = 5V I 0 =- 2 . 0m A I0 = -100 µA VL = 3.3V I 0 =- 2 . 0m A VOH VOH VOH VL - 1.0 VL - 0.7 2.3 V V V Low-level Output Voltage at VL = 5V I 0 =2 . 0m A I0 = 100 µA VL = 3.3V I 0 =- 2 . 0m A VOL VOL VOL 0.4 0.2 0.4 V V V Input Leakage Current (Digital Inputs) - 10 µA Output Leakage Current (High-Impedance Digital Outputs) - 10 µA
SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0V, Logic 1 = VL) Notes: 14. See Cl1:0 register on page 22 for settings. 15. After powering up the CS4228A, RST should be held low for 1 ms after the power supplies and clocks are settled. 16. Scales with sample rate Fs. 50 ns valid at 48 kHz, more time at slower Fs and less time at faster Fs. 17. See DCK1:0 register on page 25 for settings. Parameter Symbol Min Typ Max Units Audio ADC's and DAC's Sample Rate BRM HRM Fs 30 100 kHz kHz MCLK Frequency (Note 14) 3.84 - 25.6 MHz MCLK Duty Cycle BRM MCLK =128, 384 Fs MCLK = 256, 512 Fs HRM MCLK = 64, 192 Fs MCLK = 128, 256 Fs RST Low Time (Note 15) 1- - m s SCLK Falling Edge to SDOUT Output Valid (Note 16) t dpd -5 0 n s LRCK Edge to MSB Valid t lrpd -2 0 n s SDIN Setup Time Before SCLK Rising Edge t ds -1 0 n s SDIN Hold Time After SCLK Rising Edge t dh -3 0 n s SCLK Period BRM (Note 17) t sck -- n s SCLK Period HRM (Note 17) t sck -- n s Master Mode SCLK Falling to LRCK Edge t mslr +10 - ns SCLK Duty Cycle 50 - % Slave Mode SCLK High Time t sckh 50 - - ns SCLK Low Time t sckl 50 - - ns SCLK rising to LRCK Edge t lrckd 25 - - ns LRCK Edge to SCLK Rising t lrcks 25 - - ns
Notes: 18. Data must be held for sufficient time to bridge the transition time of CCLK. Figure 3. SPI Control Port Timing
- TYPICAL CONNECTION DIAGRAM
both be tied to a common ground plane. Figure 6. Recommended Connection Diagram
3.1 Overview
3.2 Analog Inputs
3.2.1 Line Level Inputs
serves this bias and minimizes signal distortion. 7FFFFFH or 800000H, respectively.
3.2.2 High Pass Filter
Figure 7. Optional Line Input Buffer
ing full frequency response down to DC.
3.3 Analog Outputs
3.3.1 Line Level Outputs
of which is removed by the on-chip analog filters. filtering for sample rates from 44.1 kHz to 96 kHz.
3.3.2 Digital Volume Control
RMP1:0 bits in the Digital Volume Control register. sponding DAC to its maximum value (90.5 dB). Figure 8. Passive Output Filter with Mute Figure 9. Butterworth Output Filter with Mute
returns to the attenuation level set in the Digital Volume Control register. The attenuation is ramped up and down at the rate specified by the RMP1:0 bits. To achieve complete digital attenuation of an in- coming signal, Hard Mute controls are provided. When asserted, Hard Mute will send zero data to a corresponding pair of DACs. Hard Mute is not ramped, so it should only be asserted after setting the two corresponding MUT bits to prevent high frequency transients from appearing on the DAC outputs. Hard Mute is controlled by the HMUTE56/34/12 bits in the DAC Mute2 Control register.
3.4 Mute Control
The Mute Control pin is typically connected to an external mute control circuit as shown in Figure 8 and Figure 9. The Mute Control pin is asserted dur- ing power up, power down, and when serial port clock errors are present. The pin can also be con- trolled by the user via the control port, or automat- ically asserted when zero data is present on all six DAC inputs. To prevent large transients on the out- put, it is desirable to mute the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin in the Pin Descriptions section for more information.
3.5 Clock Generation
The master clock, MCLK, is supplied to the CS4228A from an external clock source. If MCLK stops for 10 µs, the CS4228A will enter Power Down Mode in which the supply current is reduced as specified under “Power Supply”. In all modes it is required that the number of MCLK periods per SCLK and LRCK period be constant.
3.5.1 Clock Source
The CS4228A internal logic requires an external master clock, MCLK, that operates at multiples of the sample rate frequency, Fs. The MCLK/Fs ratio is determined by the CI1:0 bits in the CODEC Clock Mode register.
3.5.2 Synchronization
The serial port is internally synchronized with MCLK. If from one LRCK cycle to the next, the number of MCLK cycles per LRCK cycle changes by more than 32, the CS4228A will undergo an in- ternal reset of its data paths in an attempt to resyn- chronize. Consequently, it is advisable to mute the DACs and clear the DIGPDN bit when changing from one clock source to another to avoid the out- put of undesirable audio signals as the device re- synchronizes. It is adviseable to ensure that MCLK complies with the Switching Characteristics at all times when switching clock sources without reset- ting the part.
3.6 Digital Interfaces
3.6.1 Serial Audio Interface Signals
The serial audio data is presented in 2's comple- ment binary form with the MSB first in all formats. The serial interface clock, SCLK, is used for both transmitting and receiving audio data. SCLK can be generated by the CS4228A (master mode) or it can be input from an external source (slave mode). Mode selection is made with the DMS1:0 bits in the Serial Port Mode register. The number of SCLK cycles in one sample period can be set using the DCK1:0 bits as detailed in the Serial Port Mode register. The Left/Right clock (LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS4228A (master mode), or it may be generated by an exter- nal source (slave mode). The frequency of LRCK is the same as the system sample rate, Fs. SDIN1, SDIN2, and SDIN3 are the data input pins. SDOUT, the data output pin, carries data from the two 24-bit ADC's. The serial audio port may also be operated in One Line Data Mode in which all 6
3.6.2 Serial Audio Interface Formats
Table 1. Serial Audio Port Input Channel Allocations Figure 10. I 2S Serial Audio Formats Figure 11. Left Justified Serial Audio Formats
3.7 Control Port Signals
2C mode. SDOUT is internally pulled high to VL. will enable I2C mode after a hardware reset.
3.7.1 SPI Mode
therefore all registers are write-only in SPI mode. Data is clocked in on the rising edge of CCLK. registers designated by the MAP. reads, or writes, of successive registers.
3.7.2 I 2C Mode
is clocked into and out of the port by the SCL clock. transitions of SDA occur while the clock is low. pin determines the LSB of the chip address field. Figure 14. Control Port Timing, SPI Slave Mode Write
Send 001000x0 chip address & write operation. Send MAP byte, auto increment off. Send stop condition, aborting write. Send 001000x1 chip address & read operation. Receive byte, contents of selected register. successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
3.8 Control Port Bit Definitions
formation, see the bit definition tables.
3.9 Power-up/Reset/Power Down Mode
Figure 15. Control Port Timing, I 2C Slave Mode Write Figure 16. Control Port Timing, I 2C Slave Mode Read
The CS4228A will enter a stand-by mode if the master clock source stops for approximately 10 µs or if the number of MCLK cycles per LRCK period varies by more than 32. Should this occur, the con- trol registers retain their settings. The CS4228A will mute the analog outputs, assert the MUTEC pin and enter the Power Down Mode if the supply drops below approximately 4V.
3.10 Power Supply, Layout, and
The CS4228A requires careful attention to power supply and grounding details. VA is normally sup- plied from the system 5 VDC analog supply. VD is from a 5 VDC digital supply. VL should be from the supply used for the devices digitally interfacing with the CS4228A. Attention should be placed on the VL and VD power up sequence such that the VD supply is applied at the same time or after VL supply is applied (see “Specified Operating Condi- tions” on page 4). AGND and DGND pins should both be tied to a solid ground plane surrounding the CS4228A. The system analog and digital ground planes should not be separated under normal circumstances. A solid ground plane underneath the part is recommended. Decoupling capacitors should be mounted and routed in such a way as to minimize the circuit path length from the CS4228A supply pin or FILT pin, through the capacitor, and back to the applicable CS4228A AGND or DGND pin. The small value ceramic capacitors should be closest to the part. In some cases, ferrite beads in the VL, VD and VA supply lines, and low-value resistances (~ 50 Ω) in series with the LRCK, SCLK, SDIN and SDOUT lines can help reduce coupling of digital signals into the analog portions of the CS4228A. Both capacitors on the FILT pin should be as close to the CS4228A as possible. Any noise that couples onto the FILT pin will couple directly onto all of the analog outputs. Please see the CDB4228 evalu- ation board data sheet for recommended layout of the decoupling components.
Table 2. User Registers
- REGISTER DESCRIPTIONS All registers are read/write except for Chip Status, which is read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in the tables underneath each bit’s label. Default values are also marked in the text with an asterisk.
5.1 Memory Address Pointer (MAP)
INCR memory address pointer auto increment control 0 - MAP is not incremented automatically. *1 - internal MAP is automatically incremented after each read or write. MAP4:0 Memory address pointer (MAP). Sets the register address that will be read or written by the con- trol port.
5.2 CODEC Clock Mode
HRM Sets the sample rate mode for the ADCs and DACs * 0- B a s eR a t eM o d e( B R M )s u p p o r t ss a m p l er a t e su pt o5 0k H z 1 - High Rate Mode (HRM) supports sample rates up to 100 kHz. Typically used for 96 kHz sample rate. CI1:0 Specifies the ratio of MCLK to the sample rate of the ADCs and DACs (Fs)5.3 Chip Control Address 0x02 DIGPDN Power down the digital portions of the CODEC 0 - Digital power down. *1 - Normal operation ADCPDN Power down the analog section of the ADC *0 - Normal 1 - ADC power down. 76543210 INCR RESERVED MAP4 MAP3 MAP2 MAP1 MAP0 10000001 76543210 HRM RESERVED CI1 CI0 RESERVED 00000100 CI1:0 BRM (Fs) HRM (Fs) 0 128 64 *1 256 128 23 8 4 1 9 2 35 1 2 2 5 6 7 6543210 DIGPDN RESERVED ADCPDN DACPDN56 DACPDN34 DACPDN12 RESERVED 1 0000000
DACPDN12 Power down the analog section of DAC 1 and 2 *0 - Normal 1 - Power down DAC 1 and 2. DACPDN34 Power down the analog section of DAC 3 and 4 *0 - Normal 1 - Power down DAC 3 and 4. DACPDN56 Power down the analog section of DAC 5 and 6 *0 - Normal 1 - Power down DAC 5 and 6.
5.4 ADC Control
MUTL, MUTR ADC left and right channel mute control *0 - Normal 1 - Selected ADC output muted HPF ADC DC offset removal. See “High Pass Filter”for more information *0 - Enabled 1 - Disabled HPFZ ADC DC offset averaging freeze. See “High Pass Filter”for more information *0 - Normal. The DC offset average is dynamically calculated and subtracted from in- coming ADC data. 1 - Freeze. The DC offset average is frozen at the current value and subtracted from incoming ADC data. Allows passthru of DC information.
5.5 DAC Mute1 Control
MUT6 - MUT1 Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC attenu- ation value returns to the value stored in the corresponding Digital Volume Control register. The attenuation value is ramped up and down at the rate specified by RMP1:0. 0 - Normal output level *1 - Selected DAC output fully attenuated. RMP1:0 Attenuation ramp rate. *0 - 0.5 dB change per 4 LRCKs 1- 0 . 5d Bc h a n g ep e r8L R C K s 2 - 0.5 dB change per 16 LRCKs 3 - 0.5 dB change per 32 LRCKs 76543210 MUTL MUTR HPF HPFZ RESERVED 00000000 76543210 MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 RMP1 RMP0 11111100
5.6 DAC Mute2 Control
MUTEC Controls the MUTEC pin 0 - Normal operation *1 - MUTEC pin asserted low MUTCZ Automatically asserts the MUTEC pin on consecutive zeros. When enabled, 512 consecutive z e r o so na l ls i xD A Ci n p u t sw i l lc a u s et h eM U T E Cpin to be asserted low. A single non-zero value on any DAC input will cause the MUTEC pin to deassert. *0 - Disabled 1 - Enabled HMUTE56/34/12 Hard mute the corresponding DAC pair. When asserted, zero data is sent to the corresponding DAC pair causing an instantaneous mute. To prevent high frequency transients on the outputs, a DAC pair should be fully attenuated by asserting the corresponding MUT6-MUT1 bits in the DAC Mute Control register or by writing 0xFF to the corresponding Digital Volume Control reg- isters before asserting HMUTE. *0 - Normal operation 1 - DAC pair is muted
5.7 DAC De-emphasis Control
DEMS1:0 Selects the DAC de-emphasis response curve. 0- R e s e r v e d 1 - De-emphasis for 48 kHz *2 - De-emphasis for 44.1 kHz 3 - De-emphasis for 32 kHz DEM6 - DEM1 De-emphasis control for DAC6 - DAC1 respectively *0 - De-emphasis off 1 - De-emphasis on
5.8 Digital Volume Control
Addresses 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C VOL6 - VOL1 Address 0x0C - 0x07 sets the attenuation level for DAC 6 - DAC1 respectively. The attenutation level is ramped up and down at the rate specified by RMP1:0 in the DAC Volume Control Setup register. 0 - 181 represents 0 to 90.5 dB of attenuation in 0.5 dB steps. 76543210 MUTEC MUTCZ RESERVED HMUTE56 HMUTE34 HMUTE12 RESERVED 10000000 76543210 DEMS1 DEMS0 DEM6 DEM5 DEM4 DEM3 DEM2 DEM1 10000000 76543210 VOLn 00000000
5.9 Serial Port Mode
DCK1:0 Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK) DMS1:0 Sets the master/slave mode of the serial audio port *0 - Slave (External LRCLK, SCLK) 1- R e s e r v e d 2- R e s e r v e d 3- M a s t e r( N o4 8F sS C L Ki nB R M ) DDF2:0 Serial Port Data Format 0 - Right Justified, 24-bit 1 - Right Justified, 20-bit 2 - Right Justified, 16-bit 3 - Left Justified, maximum 24-bit *4 - I 2S compatible, maximum 24-bit 5 - One-line Data Mode, available in BRM only 6- R e s e r v e d 7- R e s e r v e d
5.10 Chip Status
CLKERR Clocking system status, read only 0- N oE r r o r 1 - No MCLK is present, or a request for clock change is in progress ADCOVL ADC overflow bit, read only 0 - No overflow 1- A D Co v e r f l o wh a so c c u r r e d 76543210 DCK1 DCK0 DMS1 DMS0 RESERVED DDF2 DDF1 DFF0 10000100 DCK1:0 BRM (Fs) HRM (Fs) 03 2 ( 1 ) ( 3 ) 14 8 ( 2 ) ( 3 ) 2 *64 32 (1) 3 128 64 Notes: 1. All formats will default to 16 bits 2. Slave mode only 3. Invalid mode 7 6543210 CLKERR ADCOVL RESERVED XX000000
- PIN DESCRIPTION SDIN1, SDIN2, SDIN3 1, 2, 3 Serial Audio Data In(Input) - Two's complement MSB-first serial audio data is input on this pin. The data is clocked into SDIN1, SDIN2, SDIN3 via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The options are detailed in Figures 10, 11, 12, and 13. SDOUT 4 Serial Audio Data Out (Output) - Two's complement MSB-first serial data is output on this pin. The data is clocked out of SDOUT via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The options are detailed in Figures 10, 11, 12 and 13. The state of the SDOUT pin during reset is used to set the Control Port Mode (I 2C or SPI). When RST is low, SDOUT is configured as an input, and the rising edge of RSTlatches the state of the pin. A weak internal pull up is present such that a resistive load less than 47 kΩ will pull the pin low, and the control port mode is I2C. When the resistive load on SDOUT is greater than 47 kΩ during reset, the control port mode is SPI. SCLK 5 Serial Clock (Bidirectional) - Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins, and out of the SDOUT pin. The pin is an output in master mode, and an input in slave mode. In master mode, SCLK is configured as an output. MCLK is divided internally to generate SCLK at the desired multiple of the sample rate. In slave mode, SCLK is configured as an input. The serial clock can be provided externally, or the pin can be grounded and the serial clock derived internally from MCLK. The required relationship between the Left/Right clock, serial clock and serial audio data is defined by the Serial Port Mode register. The options are detailed in Figures 10, 11, 12 and 13. Serial Audio Data In 3 SDIN3 SUB Analog Out #6,Subwoofer Serial Audio Data In 2 SDIN2 CENTER Analog Out #5, Center Serial Audio Data In 1 SDIN1 SR Analog Out #4, Surround Right Serial Audio Data Out SDOUT SL Analog Out #3, Surround Left Serial Clock SCLK FR Analog Out #2, Front Right Left/Right Clock LRCK FL Analog Out #1, Front Left Digital Ground DGND AGND Analog Ground Digital Power VD VA Analog Power Digital Interface Power VL AINL+ Left Channel Analog Input+ Master Clock MCLK AINL- Left Channel Analog Input- SCL/CCLK SCL/CCLK FILT Internal Voltage Filter SDA/CDIN SDA/CDIN AINR - Right Channel Analog Input- AD0/CS AD0/CS AINR+ Right Channel Analog Input+ Reset RST MUTEC Mute Control 1514
synchronous to the Master clock. DGND 7 Digital Ground (Input) - Digital Ground Reference. VD 8 Digital Power (Input) - Digital Power Supply. and input threshholds scale with VL. CI1:0 bits in the CODEC Clock Mode register. is used to set the control port mode. SPI mode, CS is used as a enable for the control port interface. When high, the control port and the CODEC become operational. Table 3. Common Master Clock Frequencies
AINR+, AINR-, AINL+, AINL- 16, 17, 19, 20 Differential Analog Inputs (Input) - The analog signal inputs are presented differentially to the modulators via the AINR+/- and AINL+/- pins. The + and - input signals are 180° out of phase resulting in a nominal differential input voltage of twice the input pin voltage. These pins are biased to the internal reference voltage. A passive anti-aliasing filter is required for best performance, as shown in Figure 6. The inputs can be driven at -1 dB FS single-ended if the unused input is connected to ground through a large value capacitor. A single ended to differential converter circuit can also be used for slightly better performance. FILT 18 Internal Voltage Filter(Output) - Filter for internal circuits. An external capacitor is required from FILT to analog ground, as shown in Figure 6. FILT is not intended to supply external current. FILT+ has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance. Care should be taken during board layout to keep dynamic signal traces away from this pin. VA 21 Analog Power (Input) - Power for the analog and reference circuits. AGND 22 Analog Ground (Input) - Analog ground reference. F R ,F L ,S R ,S L SUB, CENTER 23, 24, 25, 26, 27, 28 Analog Outputs(Output) - Analog outputs from the DACs. The full scale analog output level is specified in the Analog Characteristics specifications table. The amplitude of the outputs is controlled by the Digital Volume Control registers 0x07 - 0x0C.
- PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1 dBFs as suggested in AES 17-1991 Annex A. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the RMS analog output level with 1 kHz full scale digital input to the RMS analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels.
The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with mid- scale input code. Units are in V olts.
- PACKAGE DIMENSIONS Notes: 1. “D”and “E1”are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.Dimension “b”does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b”dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b”by more than 0.07 mm at least material condition. 3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-150 Controlling Dimension is Millimeters 28L SSOP PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW