CS4172 CHERRY | Alldatasheet
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Technical content
Features
COSÐ COS+ SINÐ SIN+ VBBVCC POR Serial to Parallel Shift Register POR OC
7 Bit
D0 Ð D6 VTOP VVAR MUX OE CS VBAT FAULT Latch LOGIC ST RS S D7 Ð D9 n Serial Input Bus n 2 MHz Operating Frequency n Tangential Drive Algorithm n 80mA Drive Circuits n 0.5¡ Accuracy (Typ.) n Power-On-Reset n Protection Features Output Short Circuit Overtemperature Package Options Single Air-Core Gauge Driver CS4172
Description
The CS4172 is a monolithic BiCMOS integrated circuit used to translate a digital 10-bit word from a micropro- cessor/microcontroller to complemen- tary DC outputs. The DC outputs drive an air-core meter commonly used in vehicle instrument panels. The 10 bits of data are used to linearly con- trol the quadrature coils of the meter directly with a 0.35¡ resolution and ±1.0¡ accuracy over the full 360¡ range of the gauge. The interface from the microcontroller is by a Serial Periph- eral Interface (SPI) compatible serial connection using up to a 2MHz shift clock rate. The digital code, which is directly pro- portional to the desired gauge pointer deflection, is shifted into a DAC and multiplexer. These two blocks provide a tangential conversion function to change the digital data into the appro- priate DC coil voltage for the angle demanded. The tangential algorithm creates approximately 40% more torque in the meter movement than does a sin-cos algorithm at 45¡, 135¡, 225¡, and 315¡ angles. This increased torque reduces the error due to pointer droop at these critical angles. Each output buffer is capable of sup- plying up to 80mA per coil and are controlled by a common enable pin. When OE is low the output buffers are turned off but the logic portion of the chip remains powered and continues to operate normally. The Serial Gauge Driver is self-protect- ed against output short circuit condi- tions. The output drivers are disabled anytime the on-chip protection circuit- ry detects a short circuit condition. The outputs remain off until a falling edge is presented on CS. If the short circuit is still present the output drivers auto- matically disable themselves again. A thermal protection circuit limits the junction temperature to approximately 160¡C for conditions of high supply voltage and high ambient temperature. The status pin (ST) reflects the state of the outputs and is low whenever the outputs are disabled. Block Diagram
16 Lead PDIP
16 Lead SO Wide
(internally fused leads) Rev. 4/19/99 CS4172 Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ¨
Lead Temperature Soldering CS4172 Electrical Characteristics: -40¡C ² TA ² 105¡C; 7.5V ² VBB ² 14V; 4.5V ² VCC ² 5.5V (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT n Supply Voltages and Currents VBB Quiescent Current Output disabled (OE = 0V) 1 5 mA [RCOS, RSIN = RL(MIN)] @45¡ 175 mA (code = XÕ080) VBB = 14V VCC Quiescent Current OE = high, V BB = 0V SCLK = 2.0MHz 1 mA n Digital Inputs and Outputs Output High Voltage SO, I OH = 0.8mA V CC - 0.8 V Output Low Voltage SO, I OL =0.8mA 0.4 V ST, IOL = 2.5mA 0.8 V Output High Current ST, V CC = 5.0V 25 µA Input High Voltage CS, SCLK, SI, OE 0.7 ´ VCC V Input Low Voltage CS, SCLK, SI, OE 0.3 ´ VCC V Input High Current CS, SCLK, SI, OE; V IN = 0.7 ´ VCC 1µ A Input Low Current CS, SCLK, SI, OE; V IN = 0.3 ´ VCC 1µ A n Analog Outputs Output Function Accuracy -1.2 +1.2 deg Output Shutdown Current, V BB = 14.0V 70 250 mA Source Output Shutdown Current, V BB = 14.0V 70 250 mA Sink Output Shutdown Current, V BB = 7.5V 43 250 mA Source Output Shutdown Current, V BB = 7.5V 43 250 mA Sink Coil Drive Output Voltage 0.748 ´ VBB V Minimum Load Resistance T A = 105¡C 229 ½ TA = 25¡C 171 ½ TA = -40¡C 150 ½
PACKAGE PIN# PIN SYMBOL FUNCTION PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Shift Clock Frequency 2.0 MHz SCLK High Time 175 ns SCLK Low Time 175 ns SO Rise Time 0.75V to V CC - 1.2V; CL = 90pF 150 ns SO Fall Time 0.75V to V CC - 1.2V; CL = 90pF 150 ns SO Delay Time C L = 90pF 150 ns SI Setup Time 75 ns SI Hold Time 75 ns CS Setup Time 0 ns CS Hold Time 75 ns
16 Lead SO Wide 16 Lead PDIP
1 1 SIN - Negative output for SINE coil. 2 2 SIN + Positive output for SINE coil. 34 V BB Analog supply. Nominally 13.5V. 4,5,12,13 3,13,14 Gnd Ground. 6 6 SI Serial data input. Data present at the rising edge of the clock signal is shifted into the internal shift register. 77 V CC 5V logic supply. The internal registers and latches are reset by a POR generated by the rising edge of the voltage on this pin. 8 8 OE Controls the state of the output buffers. A logic low on this pin turns them off. 9 9 SCLK Serial clock for shifting in/out of data. Rising edge shifts data on SI into the shift register and the falling edge changes the data on SO. 10 10 CS When high allows data at SI to be shifted into part with the rising edges of SCLK. The falling edge transfers the shift register contents into the DAC and multiplexer to update the output buffers. The falling edge also re-enables the output drivers if they have been disabled by a fault. 11 11 ST STATUS reflects the state of the outputs and is low any- time the outputs are disabled, either by OE or the internal protection circuitry. Requires external pull-up resistor. 14 5 SO Serial data output. Existing 10-bit data is shifted out when new data is shifted in. Allows cascading of multiple devices on common serial port. 15 15 COS - Negative output for COSINE coil. 16 16 COS + Positive output for COSINE coil. 12 NC No connection. Electrical Characteristics: -40¡C ² TA ² 105¡C; 7.5V ² VBB ² 14V; 4.5V ² VCC ² 5.5V (unless otherwise specified) CS4172
Figure 1. Major gauge outputs. Graph 1. Major gauge response.
port. These 10 bits are divided as shown in Figure 2. 360¡ circle is divided into 1024 equal parts of .35¡ each. Figure 2. Definition of serial word. Table 1. Nominal output for major gauge (VBB = 14V). DAC is updated and the outputs change accordingly. Figure 3. Serial data timing diagram. Figure 4. Power-up sequence.
10 Bits
Data PDIP SO Wide* RQJC typ 42 18 ûC/W RQJA typ 80 75 ûC/W CS4172 Part Number Description CS4172XN16 16 Lead PDIP CS4172XDWF16 16 Lead SO Wide* CS4172XDWFR16 16 Lead SO Wide* (tape & reel) D Lead Count Metric English Max Min Max Min 16 Lead PDIP 19.69 18.67 .775 .735 16 Lead SO Wide* 10.50 10.10 .413 .398 © 1999 Cherry Semiconductor CorporationRev. 4/19/99
Ordering Information
PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. *Internally Fused Leads Surface Mount Wide Body (DW); 300 mil wide Plastic DIP (N); 300 mil wide 0.39 (.015) MIN. 1.14 (.045) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. .203 (.008) .356 (.014) REF: JEDEC MS-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022) 1.27 (.050) BSC 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) D 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) REF: JEDEC MS-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 2.35 (.093) 0.30 (.012) 0.10 (.004)