CS4124 ONSEMI | Alldatasheet

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Technical content

Features

  • 150 mA Peak PWM Gate Drive Output
  • Patented V oltage Compensation Circuit
  • 100% Duty Cycle Capability
  • 5.0 V , ± 3.0% Linear Regulator
  • Low Current Sleep Mode
  • Overvoltage Protection
  • Boost Mode Power Supply
  • Output Inhibit http://onsemi.com A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week PIN CONNECTION AND MARKING DIAGRAM 161 CS4124 AWLYYWW VREGVCC SNIPGND PMPCTL ISENSE–C OSC ISENSE+R OSC IADJFLT INHBOOST GNDOUTPUT Device Package Shipping ORDERING INFORMATION* CS4124YN16 DIP–16 25 Units/Rail DIP–16 N SUFFIX CASE 648 * Contact your local sales representative for 16-lead SOIC wide package.

Figure 1. Applications Diagram *The maximum package power dissipation must be observed.

http://onsemi.com ELECTRICAL CHARACTERISTICS (4.0 V ≤ VCC ≤ 26 V; –40°C < TJ < 125°C; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit VCC Supply Operating Current Supply 7.0 V ≤ VCC ≤ 18 v 4.0 V ≤ VCC < 7.0 V, 18 V < VCC ≤ 26 V 5.0 mA mA Quiescent Current VCC = 12 V – 170 275 µA Overvoltage Shutdown – 26.5 – 29 V Control (CTL) Control Input Current CTL = 0 V to 5.0 V –2.0 0.1 2.0 µA Sleep Mode Threshold – 8.0% 10% 12% VREG Sleep Mode Hysteresis 7.0 V ≤ VCC ≤ 26 V 4.0 V ≤ VCC < 7.0 V 100 150 150 mV mV Control Sense Differential Voltage Sense 7.0 V ≤ VCC ≤ 18 V: IADJ = 1.0 V and RCS1 = 51 Ω IADJ = 4.0 V and RCS1 = 51 Ω 4.0 V ≤ VCC < 7.0 V: IADJ = 1.0 V and RCS1 = 51 Ω

18 V < VCC ≤ 26 V:

IADJ = 1.0 V and RCS1 = 51 Ω IADJ = 4.0 V and RCS1 = 51 Ω 104 102 125 130 mV mV mV mV mV Linear Regulator Output Voltage, VREG VCC = 4.0 V VCC = 13.2 V VCC = 26 V 2.0 4.85 4.85 5.15 5.20 V V V Inhibit Inhibit Threshold – 40% 50% 60% VREG Inhibit Hysteresis 4.0 V ≤ VCC ≤ 7.0 V

7.0 V ≤ VCC ≤ 26 V

External Drive (OUTPUT) Output Frequency 4.0 V ≤ VCC < 7.0 V: R OSC = 93.1 kΩ , COSC = 470 pF

7.0 V ≤ VCC ≤ 18 V:

R OSC = 93.1 kΩ , COSC = 470 pF R OSC = 93.1 kΩ , COSC = 470 pF kHz kHz kHz Voltage to Duty Cycle Conversion 4.0 V ≤ VCC < 7.0 V: VCC = 13 V, CTL = 1.0 V VCC = 13 V, CTL = 2.0 V VCC = 13 V, CTL = 30% VREG VCC = 13 V, CTL = 55.8% VREG VCC = 13 V, CTL = 1.5 V VCC = 13 V, CTL = 3.5 V 100 28.3 56.0 11.8 34.2 36.3 64.0 21.8 44.2 Output Rise Time 4.0 V ≤ VCC ≤ 26 V: R GATE = 6.0 Ω , CGATE = 5.0 nF – .25 1.0 µs Output Fall Time 4.0 V ≤ VCC ≤ 26 V: R GATE = 6.0 Ω , CGATE = 5.0 nF – .30 1.0 µs

http://onsemi.com ELECTRICAL CHARACTERISTICS (continued) (4.0 V ≤ VCC ≤ 26 V; –40°C < TJ < 125°C; unless otherwise specified.) Characteristic UnitMaxTypMinTest Conditions External Drive (OUTPUT) (continued) Output Sink Current 4.0 V ≤ VCC < 7.0 V: R GATE = 6.0 Ω , CGATE = 5.0 nF

7.0 V ≤ VCC ≤ 26 V:

R GATE = 6.0 Ω , CGATE = 5.0 nF 150 300 mA mA Output Source Current 4.0 V ≤ VCC < 7.0 V: R GATE = 6.0 Ω , CGATE = 5.0 nF R GATE = 6.0 Ω , CGATE = 5.0 nF 150 300 mA mA Output High Voltage IOUT = 1.0 mA VBOOST = 1.7 – – V Output Low Voltage IOUT = –1.0 mA – – 1.3 V Charge Pump (DRV) Boost Voltage – VCC + 6.4 – – V PIN FUNCTION DESCRIPTION PACKAGE PIN #

16 Lead PDIP PIN SYMBOL FUNCTION

1 OUTPUT MOSFET gate drive. 2 BOOST Boost voltage. 3 FLT Fault time out capacitor. 4 R OSC Oscillator resistor. 5 C OSC Oscillator capacitor. 6 CTL Pulse width control input. 7 PGND Power ground for on chip clamp. 8 VCC Positive power supply input. 9 VREG 5.0 V linear regulator. 10 SNI Sense inductor current. 11 PMP Collector of boost power transistor. 12 ISENSE– Current sense minus. 13 ISENSE+ Current sense plus. 14 IADj Current limit adjust. 15 INH Output Inhibit. 16 GND Ground.

5.0 V Regulator

Figure 2. Block Diagram

Figure 5. OUTPUT Voltage (Sinking Figure 6. OUTPUT Saturation Voltage

0.8 VREG

2.1 VREG

the nominal frequency will be approximately 20 kHz. be changed to adjust the oscillator frequency. CC = 14 V the duty cycle will equal VCTL divided by VREG . hence keep the average load voltage at 7.0 V . Figure 7. Voltage Compensation

5.0 V Linear Regulator

approximately 1.5 V at room temperature.

1000 R CS

terminals and the voltage at the IADJ lead.

37000 VI(ADJ)

http://onsemi.com reset and the IC reverts back to run mode until another fault occurs. If a number of faults occur in a given period of time, the IC “times out” and disables the MOSFET for a long period of time to let it cool off. This is accomplished by charging the C FLT capacitor each time an over current condition occurs. If a cycle goes by with no overcurrent fault occurring, an even smaller amount of charge will be removed from C FLT. If enough faults occur together, eventually CFLT will charge up to 2.4 V and the fault latch will be set. The fault latch will not be reset until CFLT discharges to 0.6 V . This action will continue indefinitely if the fault persists. The off time and on time are set by the following: Off Time C FLT 2.4V0.6V 4.5A On Time C FLT 2.4V0.6V IAVG where: IAVG (295.5A DC) [4.5A (1DC)] DC PWM Duty Cycle IAVG (300A DC) 4.5A Boost Switch Mode Power Supply The CS4124 has an integrated boost mode power supply which charges the gate of the external high–side MOSFET to greater than 5.0 V above V CC . Three leads are used for voltage boost. They are Boost, PMP and SNI. The PMP lead is the collector of a darlington tied NPN power transistor. This device charges the inductor during its on time. The boost lead is the input to chip from the external reservoir capacitor. The SNI lead is the emitter of the power NPN and is connected externally to the R SNI resistor. The power supply is controlled by the oscillator. At the start of a cycle an R–S flip flop is set the internal power NPN transistor is turned on and energy begins to build up in the inductor. The RSNI resistor sets the peak current of the inductor by tripping a comparator when the voltage across the resistor is 450 mV . The flip flop is reset and the inductor delivers its stored energy to the load. The ripple voltage RIPPLE ) at the Boost lead is controlled by CBOOST . A snubber circuit, made up of a series resistor and capacitor, is required to dampen the ringing of the inductor. A value of 4.0 Ω is recommended for R SNI. A zener diode is needed between the boost output voltage and the battery. This will clamp the boost lead to a specified value above the battery to prevent damage to the IC. A 9.0 volt zener diode is recommended. Sleep State This device will enter into a low current mode (< 275 µA) when CTL lead is brought to less than 0.5 V . All functions are disabled in this mode, except for the regulator. Inhibit When the inhibit is greater than 2.5 V the internal latch is set and the external MOSFET will be turned off for the remainder of the oscillator cycle. The latch is then reset at the start of the next cycle. Overvoltage Shutdown The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the internal latch and therefore is independent of the oscillator timing (i.e. asynchronous). There is 325 mV (typical) of hysteresis on the overvoltage function. There is no undervoltage lockout. The device will shutdown gracefully once it runs out of headroom. Reverse Battery The CS4124 will not survive a reverse battery condition. A series diode is required between the battery and the VCC lead for reverse battery. Load Dump A 10 Ω resistor, (RS) is placed in series with VCC to limit the current into the IC during 40 V peak transient conditions.

http://onsemi.com PACKAGE DIMENSIONS DIP–16 N SUFFIX CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– B F C S H G D J L M 16 PL SEATING 916 K PLANE–T– MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01 PACKAGE THERMAL DATA Parameter DIP–16 Unit R Θ JC Typical 42 °C/W R Θ JA Typical 80 °C/W

http://onsemi.com Notes

http://onsemi.com Notes

http://onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone : 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit–asia@hibbertco.com JAPAN : ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone : 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. CS4124/D NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support German Phone : (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET) Email: ONlit–german@hibbertco.com French Phone : (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET) Email: ONlit–french@hibbertco.com English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT) Email: ONlit@hibbertco.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, UK, Ireland