CS4124 CHERRY | Alldatasheet
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Technical content
Features
I 100% Duty Cycle Capability I 5V , ± 3% Linear Regulator I Low Current Sleep Mode I Overvoltage Protection I Boost Mode Power Supply I Output Inhibit Package Option CS4124 High Side PWM FET Controller CS4124
Description
16 Lead PDIP
Consult Factory for 16 Lead SOIC Wide package. Rev. 4/26/99 Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ® The CS4124 is a monolithic integrat- ed circuit designed primarily to control the rotor speed of perma- nent magnet, direct current (DC) brush motors. It drives the gate of an N channel power MOSFET or IGBT with a user-adjustable, fixed frequency, variable duty cycle, pulse width modulated (PWM) sig- nal. The CS4124 can also be used to control other loads such as incan- descent bulbs and solenoids. Inductive current from the motor or solenoid is recirculated through an external diode. The CS4124 accepts a DC level input signal of 0 to 5V to control the pulse width of the output signal. This signal can be generated by a potentiometer referenced to the on- chip 5V linear regulator, or a fil- tered 0% to 100% PWM signal also referenced to the 5V regulator. The IC is placed in a sleep state by pulling the CTL lead below 0.5V. In this mode everything on the chip is shutdown except for the on-chip regulator and the overall current draw is less than 275µA. There are a number of on-chip diagnostics that look for potential failure modes and can disable the external power MOSFET. VBAT 42.5µH 1000µF 1000µF 10K 10nF 100µF .01µF CFLT .25µF ROSC COSC 470pF 93.1K OUTPUT Gnd INHBOOST FLT ROSC IADJ PMP SNI VREG COSC CTL PGnd VCC N1 10µF10K 100K 10K 10K 10K RCS1 RCS2 CCS .022µF 10K 10K Input 470µH MOT+ RGATE 6 RSENSE 4mRSNI 1.5µF 1µF ISENSE+ ISENSE- MOT- RS
Electrical Characteristics: 4V ≤ VCC ≤ 26V, -40˚C < TA < 125°C, (unless otherwise specified) CS4124 1196 Absolute Maximum Ratings Lead Temperature Soldering PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I VCC Supply Operating Current Supply 7V ≤ VCC ≤ 18V 5 10 mA 4V ≤ VCC < 7V, 18V < VCC ≤ 26V 15 mA Quiescent Current V CC = 12V 170 275 µA Overvoltage Shutdown 26.5 29 V I Control (CTL) Control Input Current CTL = 0V to 5V -2 0.1 2 µA Sleep Mode Threshold 8% 10% 12% V REG Sleep Mode Hysteresis 7V ≤ VCC ≤ 26V 50 100 150 mV 4V ≤ VCC < 7V 10 150 mV I Current Sense Differential Voltage Sense 7V ≤ VCC ≤ 18V IADJ = 1V and RCS1 = 51Ω 18 34 mV IADJ = 4V and RCS1 = 51Ω 104 125 mV 4V ≤ VCC < 7V IADJ =1V and RCS1 = 51Ω 15 39 mV 18V < VCC ≤ 26V IADJ = 1V and RCS1 = 51Ω 15 39 mV IADJ = 4V and RCS1 = 51Ω 102 130 mV IADJ Input Current 4V ≤ VCC ≤ 26V -2 0.3 2 µA IADJ = 0V to 5V I Linear Regulator Output Voltage, VREG VCC = 4V 2.0 V VCC = 13.2V 4.85 5.15 V VCC = 26V 4.85 5.20 V I Inhibit Inhibit Threshold 40% 50% 60% V REG Inhibit Hysteresis 4V ≤ VCC ≤ 7V 100 500 mV 7V ≤ VCC ≤ 26V 150 325 500 mV I External Drive (OUTPUT) Output Frequency 4V ≤ VCC < 7V ROSC = 93.1kΩ, COSC = 470pF 10 25 kHz 7V ≤ VCC ≤ 18V, ROSC = 93.1kΩ, COSC = 470pF 17 20 23 kHz 18V < VCC ≤ 26V ROSC = 93.1kΩ, COSC = 470pF 17 20 25 kHz
Electrical Characteristics: 4V ≤ VCC ≤ 26V, -40˚C < TA = 125°C, (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION I External Drive (OUTPUT): continued Voltage to Duty Cycle 4V ≤ VCC < 7V Conversion V CC = 13V, CTL = 1V 65 75 % VCC = 13V, CTL = 2V 100 % 7V ≤ VCC ≤ 18V VCC = 13V, CTL = 30% VREG 28.3 36.3 % VCC = 13V, CTL = 55.8% VREG 56.0 64.0 % 18V < VCC ≤ 26V VCC = 13V, CTL = 1. 5V 11.8 21.8 % VCC = 13V, CTL = 3. 5V 34.2 44.2 % Output Rise Time 4V ≤ VCC ≤ 26V .25 1 µs RGATE = 6Ω, CGATE = 5nF Output Fall Time 4V ≤ VCC ≤ 26V .30 1 µs RGATE = 6Ω, CGATE = 5nF Output Sink Current 4V ≤ VCC < 7V 150 mA RGATE = 6Ω, CGATE = 5nF 7V ≤ VCC ≤ 26V 300 mA RGATE = 6Ω, CGATE = 5nF Output Source Current 4V ≤ VCC < 7V 150 mA RGATE = 6Ω, CGATE = 5nF 7V ≤ VCC ≤ 26V 300 mA RGATE = 6Ω, CGATE = 5nF Output High Voltage I OUT = 1mA V BOOST - 1.7 V Output Low Voltage I OUT = -1mA 1.3 V I Charge Pump (DRV) Boost Voltage V CC + 6.4 V
1 OUTPUT MOSFET gate drive
2 BOOST Boost voltage
3 FLT Fault time out capacitor
5C OSC Oscillator capacitor
6 CTL Pulse width control input
7 PGnd Power ground for on chip clamp
CC Positive power supply input 9V REG 5V linear regulator
10 SNI Sense inductor current
11 PMP Collector of boost power transistor
SENSE- Current sense minus
13 I SENSE+ Current sense plus
14 I ADJ Current limit adjust
15 INH Output Inhibit
16 Gnd Ground
Application Information
The IC sets up a constant frequency triangle wave at the COSC lead whose frequency is related to the external com- ponents ROSC and COSC, by the following equation: Frequency = The peak and valley of the triangle wave are proportional to VCC by the following: VVALLEY = 0.1 × VCC VPEAK = 0.7 × VCC This is required to make the voltage compensation function properly. In order to keep the frequency of the oscillator constant the current that charges C OSC must also vary with supply. ROSC sets up the current which charges COSC. The voltage across ROSC is 50% of VCC and therefore: IROSC = 0.5 × IROSC is multiplied by (2) internally and transferred to the COSC lead. Therefore: ICOSC = ± The period of the oscillator is: T = 2COSC × The ROSC and COSC components can be varied to create fre- quencies over the range of 15Hz to 25kHz. With the sug- gested values of 93.1kΩ and 470pF for R OSC and COSC , the nominal frequency will be approximately 20 kHz. IROSC, at VCC = 14V, will be 66.7 µA. IROSC should not change over a more than 2:1 ratio and therefore COSC should be changed to adjust the oscillator frequency. Voltage Duty Cycle Conversion The IC translates an input voltage at the CTL lead into a duty cycle at the OUTPUT lead. The transfer function incorporates Cherry Semiconductor’s patented Voltage Compensation method to keep the average voltage and current across the load constant regardless of fluctuations in the supply voltage. The duty cycle is varied based upon the input voltage and supply voltage by the following equation: Duty Cycle = 100% × An internal DC voltage equal to: V DC = (1.683 × VCTL) + VVALLEY is compared to the oscillator voltage to produce the com- pensated duty cycle. The transfer is set up so that when VCC = 14V the duty cycle will equal VCTL divided by VREG. For example at VCC = 14V, VREG = 5V and VCTL = 2.5V, the duty cycle would be 50% at the output. This would place a 7V average voltage across the load. If V CC then drops to 10V, the IC would change the duty cycle to 70% and hence keep the average load voltage at 7V. Figure 1: Voltage Compensation 5V Linear Regulator There is a 5V, 5mA linear regulator available at the VREG lead for external use. This voltage acts as a reference for many internal and external functions. It has a drop out of approximately 1.5V at room temperature. Current Sense and Timer The IC differentially monitors the load current on a cycle by cycle basis at the I SENSE+ and ISENSE- leads. The differen- tial voltage across these two leads is amplified internally and compared to the voltage at the I ADJ lead. The gain, AV is set internally and externally by the following equation: AV == The current limit (ILIM) is set by the external current sense resistor (RSENSE) placed across the ISENSE+ and ISENSE- ter- minals and the voltage at the IADJ lead. ILIM = × The RCS resistors and CCS components form a differential low pass filter which filters out high frequency noise gen- erated by the switching of the external MOSFET and the associated lead noise. R CS also forms and error term in the gain of the ILIM equation because the ISENSE+ and ISENSE- leads are low impedance inputs thereby creating a good current sensing amplifier. Both leads source 50µA while the chip is in run mode. I ADJ should be biased between 1V and 4V. When the current through the external MOSFET VI(ADJ) RSENSE 1000 + RCS 37000 37000 1000 + RCS VI(ADJ) ISENSE+ - ISENSE- 120% 100% 80% 60% 40% 20% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% CTL Voltage (% of VREG) Duty Cycle( %) VCC = 8V VCC = 14V VCC = 16V 2.8 × VCTL VCC VPEAK - VVALLEY ICOSC VCC ROSC VCC ROSC 0.83 ROSC × COSC Theory Of Operation
Application Information: continued exceeds ILIM, an internal latch is set and the output pulls the gate of the MOSFET low for the remainder of the oscil- lator cycle (fault mode). At the start of the next cycle, the latch is reset and the IC reverts back to run mode until another fault occurs. If a number of faults occur in a given period of time, the IC “times out” and disables the MOS- FET for a long period of time to let it cool off. This is accomplished by charging the C FLT capacitor each time an over current condition occurs. If a cycle goes by with no overcurrent fault occurring, an even smaller amount of charge will be removed from C FLT. If enough faults occur together, eventually CFLT will charge up to 2.4V and the fault latch will be set. The fault latch will not be reset until C FLT discharges to 0.6V. This action will continue indefi- nitely if the fault persists. The off time and on time are set by the following: Off Time = CFLT × On Time = CFLT × where: IAVG = (295.5µA × DC) - [4.5µA × (1 - DC)] IAVG = (300µA × DC) - 4.5µA DC = PWM Duty Cycle Boost Switch Mode Power Supply The CS4124 has an integrated boost mode power supply which charges the gate of the external high-side MOSFET to greater than 5V above V CC. Three leads are used for voltage boost. They are Boost, PMP and SNI. The PMP lead is the collector of a darlington tied NPN power tran- sistor. This device charges the inductor during its on time. The boost lead is the input to chip from the external reser- voir capacitor. The SNI lead is the emitter of the power NPN and is connected externally to the R SNI resistor. The power supply is controlled by the oscillator. At the start of a cycle an R-S flip flop is set the internal power NPN transistor is turned on and energy begins to build up in the inductor. The R SNI resistor sets the peak current of the inductor by tripping a comparator when the voltage across the resistor is 450mV. The flip flop is reset and the inductor delivers its stored energy to the load. The ripple voltage (V RIPPLE) at the Boost lead is controlled by CBOOST. A snubber circuit, made up of a series resistor and capaci- tor, is required to dampen the ringing of the inductor. A value of 4Ω is recommended for R SNI. A zener diode is needed between the boost output voltage and the battery. This will clamp the boost lead to a speci- fied value above the battery to prevent damage to the IC. A 9 volt zener diode is recommended. Sleep State This device will enter into a low current mode (< 275µA) when CTL lead is brought to less than 0.5V. All functions are disabled in this mode, except for the regulator. Inhibit When the inhibit is greater than 2.5V the internal latch is set and the external MOSFET will be turned off for the remainder of the oscillator cycle. The latch is then reset at the start of the next cycle. Overvoltage Shutdown The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the internal latch and therefore is independent of the oscillator timing (i.e. asynchronous). There is 325mV (typical) of hysteresis on the overvoltage function. There is no under- voltage lockout. The device will shutdown gracefully once it runs out of headroom. Reverse Battery The CS4124 will not survive a reverse battery condition. A series diode is required between the battery and the V CC lead for reverse battery. Load Dump A 10Ω resistor, (RS) is placed in series with VCC to limit the current into the IC during 40V peak transient conditions. 2.4V - 0.6V IAVG 2.4V - 0.6V 4.5µA
D Lead Count Metric English Max Min Max Min 16L PDIP 19.69 18.67 .775 .735 © 1999 Cherry Semiconductor Corporation Thermal Data 16 Lead PDIP RΘJC typ 42 ˚C/W RΘJA typ 80 ˚C/W Rev. 4/26/99
Ordering Information
PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA Part Number Description CS4124YN16 16L PDIP CS4124 Plastic DIP (N); 300 mil wide 0.39 (.015) MIN. 1.14 (.045) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. .203 (.008) .356 (.014) REF: JEDEC MS-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.