CS403 CHERRY | Alldatasheet
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Technical content
Features
n 5V ±5% Output Voltage n Low Drift n High Efficiency n Short Circuit Protection n Active Delayed Reset n Noise Immunity on Reset n 750mA Output Current Package Options
5 Lead TO-220
Tab (Gnd) CS403 5V , 750mA Linear Regulator with RESET CS403 Gnd Delay VIN + - TO VOUT REF VOUT Output Current LimitStart VCMP Delay Comparator Low Voltage INHIBIT Comparator Error Amp ICHARGE SCR Latch RESET Block Diagram Absolute Maximum Ratings Lead Temperature Soldering
Description
- VIN 2. RESET 3. Gnd 4. Delay 5. V OUT Rev. 2/18/98 Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ¨
CS403 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics : Refer to the test circuit, -40¡C ² TC ² 125¡C, -40 ² TJ ² 150¡C, 7V ² VIN ² 10V unless otherwise specified td = Cd x VDTC/Ich = CDelay x 2.105 (typical) where: td = Time delay Cd = Value of external charging capacitor (see test circuit). VDTC = Delay threshold charge Ich = Reset delay capacitor charging current. Output Voltage, VOUT VIN = 8.5V, IOUT = 250mA TJ = 25¡C 4.95 5.00 5.05 V 100mA ² IOUT ² 750mA 4.85 5.00 5.15 Operating Input Voltage 100 to 750mA -0.75 18.0 V Load Regulation 100mA ² I OUT ² 750mA, VIN = 8.5V 30 100 mV Dropout Voltage I OUT = 750mA 1.4 1.8 V Quiescent Current I OUT = 0mA 3 4 mA IOUT = 750mA 5 25 mA PSRR I OUT-250mA f = 120Hz 70 dB COUT = 10µF, VIN = 8.5V±Vpp Output Short Circuit Current 1 A Reset Output Leakage Current VOUT in regulation 0 50 µA Delay Time for Reset Output C d = 100nF 10 20 30 ms Reset Threshold: VRTH VOUT Increasing V OUT-0.04 V VRTL VOUT Decreasing 4.75 V Threshold Hysteresis 10 50 mV Delay, V DTC Charge 3.7 4.0 4.4 V Delay, VDTD Discharge 3.1 3.5 3.9 V Delay Hysteresis, VDH 200 500 1000 mV Reset Delay Capacitor 10 20 40 µA Charging Current, ICH Reset Delay Capacitor 0.6 1.2 V Discharge Voltage, VDIS Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION 1V IN Input voltage. 2 CMOS compatible output lead. goes low whenever V OUT falls out of regulation. 3 Gnd Ground connection. 4 Delay Timing capacitor for function. 5V OUT Regulated output voltage, 5V (typ). RESET RESETRESET
Output Current (mA), IOUT Dropout Voltage (V) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 100 200 300 400 500 TA = -40ûC TA = 25ûC -40 Junction Temperature (ûC), TJ VOUT (V) 5.02 4.95 5.01 5.00 4.99 4.98 4.97 4.96 0 40 80 120 150 IOUT = 250mA CS403 Typical Performance Characteristics 10.00.0 0.0 VIN Supply Current (mA) VOUT VO IQ 1.5 2.5 3.5 4.5 5.5 2.0 4.0 6.0 8.0 0.0 6.0 10.0 14.0 18.0 22.0 Output Voltage vs. Junction Temperature Dropout Voltage vs. Output Current Over TemperatureOutput Voltage vs. VIN, IQ RESET (1) - No Delay Capacitor. (2) - With Delay Capacitor. (3) - Max. Reset Voltage (<1.0V) (1) (2) (2) V RT(ON) VOUT (3) VRT(OFF) VDH VDTD VDTC Delay VRL VRH VDIS TDelay Reset Circuit Waveform
The CS403 function is very precise, has hysteresis on both the and Delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1V. The circuit output is an open collector type with ON and OFF parameters as specified. The output NPN transistor is controlled by the two circuits described (see Block Diagram). This circuit monitors output voltage, and when output voltage is below the specified minimum, causes the output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the output transistor to go into the OFF state if allowed by the reset Delay circuit. This circuit provides a programmable (external capacitor) delay on the output lead. The Delay lead provides source current to the external delay capacitor only when the Low Voltage Inhibit circuit indicates that output volt- age is above V RT(ON). Otherwise, the Delay lead sinks cur- rent to ground (used to discharge the Delay capacitor). The discharge current is latched ON when the output volt- age is below V RT(OFF), or when the voltage on the Delay capacitor is above VDIS. In other words, the Delay capaci- tor is fully discharged any time the output voltage falls out of regulation, even for a short period of time. This fea- ture ensures a controlled pulse is generated follow- ing detection of an error condition. The circuit allows the output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than V DIS. RESET RESET RESET Reset Delay Circuit RESET RESET Low Voltage Inhibit Circuit RESET RESET RESET RESET CS403 Application Notes The output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause insta- bility. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low tem- peratures (-25¡C to -40¡C), both the value and ESR of the capacitor will vary considerably. The capacitor manufac- turers data sheet usually provides this information. The value for the output capacitor C OUT shown in the test and applications circuit should work for most applica- tions, however it is not necessarily the optimized solution. To determine an acceptable value for C OUT for a particular application, start with a tantalum capacitor of the recom- mended value and work towards a less expensive alterna- tive part. Step 1: Place the completed circuit with a tantalum capac- itor of the recommended value in an environmental cham- ber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by Stability Considerations Test Circuit C1* 100nF VIN Gnd Delay VOUT CS403 C2** COUT =10mF to 100mF 100nF Cd RESET C1* is required if the regulator is far from the power source filter. C2** is required for stability Circuit Description
the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscil- lations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage condi- tions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capaci- tor will usually cost less and occupy less board space. If the output oscillates within the range of expected operat- ing conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Remove the unit from the environmental chamber and heat the IC with a heat gun. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regula- tor performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. The maximum power dissipation for a single output regu- lator (Figure 1) is: PD(max) = {VIN(max) - VOUT(min)}IOUT(max) + VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the applica- tion, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permis- sible value of RQJA can be calculated: RQJA = (2) The value of RQJA can then be compared with those in the package section of the data sheet. Those packages with R QJA's less than the calculated value in equation 2 will keep the die temperature below 150¡C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. Figure 1: Single output regulator with key performance parameters labeled. A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R QJA. RQJA = RQJC + RQCS + RQSA (3) where RQJC = the junctionÐtoÐcase thermal resistance, RQCS = the caseÐtoÐheatsink thermal resistance, and RQSA = the heatsinkÐtoÐambient thermal resistance. RQJC appears in the package section of the data sheet. Like RQJA, it is a function of package type. RQCS and RQSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. Heat Sinks VIN Smart Regulator VOUT IOUT IIN IQ Control 150¡C - TA PD Calculating Power Dissipation in a Single Output Linear Regulator Application Notes CS403
CS403GTVA5 TO-220 Vertical CS403GTHA5 TO-220 Horizontal 6Rev. 2/18/98 CS403
Ordering Information
RQJC typ 4.1 ûC/W RQJA typ 50 ûC/W Package Specification PACKAGE THERMAL DATAPACKAGE DIMENSIONS IN mm(INCHES) © 1999 Cherry Semiconductor Corporation Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.
5 Lead TO-220 (T) Straight
2.87 (.113) 2.62 (.103) 6.93(.273) 6.68(.263) 9.78 (.385) 10.54 (.415) 1.02(.040) 0.63(.025) 1.83(.072) 1.57(.062) 0.56 (.022) 0.36 (.014) 2.92 (.115) 2.29 (.090) 1.40 (.055) 4.06 (.160) 6.55 (.258) 5.94 (.234) 14.22 (.560) 0.76 (.030) 3.71 (.146) 3.96 (.156) 14.99 (.590) 14.22 (.560)
5 Lead TO-220 (TVA) Vertical
1.68 7.51 (.296) 1.78 (.070) 4.34 (.171) 0.56 (.022) 0.36 (.014) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 14.99 (.590) 14.22 (.560) 2.92 (.115) 2.29 (.090) .94 (.037) .69 (.027) 8.64 (.340) 7.87 (.310) 6.80 (.268) 10.54 (.415) 9.78 (.385) 2.87 (.113) 2.62 (.103) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146)
5 Lead TO-220 (THA) Horizontal
0.81(.032) 1.70 (.067) 6.81(.268) 1.40 (.055) 1.14 (.045) 5.84 (.230) 6.60 (.260) 6.83 (.269) 0.56 (.022) 0.36 (.014) 10.54 (.415) 9.78 (.385) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146) 1.68 (.066) TYP 14.99 (.590) 14.22 (.560) 2.77 (.109) 2.29 (.090) 2.92 (.115) 4.83 (.190) 4.06 (.160) 2.87 (.113) 2.62 (.103)