CS3524A

CS3524A CHERRY | Alldatasheet

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Technical content

Features

T RS CLOCK S RAMP VIN VIN200mV 1kΩ 10k Ω I Precision Reference Internally Trimmed to ±1% I Current Limit I Undervoltage Lockout I Start-up Supply Current < 4mA I Output to 200mA I 60V Output Capability I Wide Common-mode Input Range for Error and Current Limit Amplifiers I PWM Latch Insures Single Pulse per Period I Double Pulse Suppression I 200ns Shutdown I Guaranteed Frequency I Thermal Shutdown Package Options

16 Lead PDIP & SO Wide

Voltage Mode PWM Control Circuit with 200mA Output Drivers 1111 EA- EA+ SYNC ISENSE+ ISENSE- RT CT Gnd VREF VIN EB VOUTB VOUTA EA SHUTDOWN COMP CS3524A

Description

The CS3524A PWM control circuit retains the same versatile architecture of the industry standard CS3524 (SG3524) while adding substantial improvements. The CS3524 is pin-compatible with “non-A” versions, and in most applica- tions can be directly interchanged. The CS3524A, however, eliminates many of the design restrictions which had pre- viously required additional external circuitry. The CS3524A includes a precision 5V reference trimmed to ±1% accuracy (eliminating the need for potentiometer adjustments), an error amplifier with an output voltage swing extending to 5V, and a current sense amplifier use- ful in either the ground or power sup- ply output lines. The uncommitted 60V, 200mA NPN output pair greatly enhances the output drive capability. The CS3524A features an undervoltage lockout circuit which disables all inter- nal circuitry (except the reference) until the input voltage has risen to 8V. This holds standby current low until turn- on, and greatly simplifies the design of low power, off-line supplies. The turn- on circuit has approximately 600mV of hysteresis for jitter free activation. Other improvements include a PWM latch that insures freedom from multi- ple pulsing within a period, even in noisy environments; logic to eliminate double pulsing on a single output, a 200ns external shutdown capability, and automatic thermal protection from excessive chip temperature. The oscil- lator circuit is usable to 500kHz and is easier to synchronize with an external clock pulse. A Company ® Rev. 10/28/96 Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Absolute Maximum Ratings CS3524A I Turn-on Characteristics Input Voltage Operating range after Turn-on 8 40 V Turn-on Threshold 5.5 7.5 8.5 V Turn-on Current V IN Turn-on - 100mV 2.5 4.0 mA Operating Current V IN = 8 to 40V 5 10 mA Turn-on Hysteresis* 0.6 V I Reference Section Output Voltage T A = 25˚C 4.90 5.00 5.20 V Line Regulation V IN = 10 to 40V 10 30 mV Load Regulation I L = 0 to 20mA 20 50 mA Temperature Stability* Over Operating Range 20 50 mV Short Circuit Current V REF = 0, TA = 25˚C 80 100 mA Output Noise Voltage* 10Hz ≤ f ≤ 10kHz, TA = 25˚C 40 µVrms Long Term Stability* T A = 125˚C; 1000 Hrs. 20 50 mV I Oscillator Section (Unless otherwise specified, RT = 2700Ω, CT = 0.01µF) Initial Accuracy T A = 25˚C3 9 4 3 4 7 k H z Temperature Stability* Over Operating Temperature Range 1 2 % Minimum Frequency R T = 150kΩ, CT = 0.1µF 120 Hz Maximum Frequency R T = 2.0kΩ, CT = 470pF 500 kHz Output Amplitude* T A = 25˚C 3.5 V Output Pulse Width* T A = 25˚C 0.5 µs Ramp Peak 3.3 3.5 3.7 V Ramp Valley 0.7 0.9 1.0 V I Error Amplifier Section (Unless otherwise specified, V CM = 2.5V) Input Offset Voltage 2 10 mV Input Bias Current 1 10 µA Input Offset Current 0.5 1.0 µA Common Mode Rejection Ratio V CM = 1.5 to 5.5V 60 75 dB Power Supply Rejection Ratio V IN = 10 to 40V 50 60 dB Output Swing Minimum Total Range 0.5 5.0 V * These parameters are guaranteed by design but not 100% tested in production.

Electrical Characteristics: continued PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Typical Performance Characteristics 100 1k 10k 100k 1M FREQUENCY (Hz) RF = ∞ OPEN VOLTAGE GAIN (dB) RF = 1MΩ RF = 300kΩ RF = 100kΩ RF = 30kΩ VIN = 20V TA = 25˚C RF is impedance to ground. Values below 30kΩ will begin to limit the maximum duty-cycle. 12345 INPUT VOLTAGE VIN DUTY-CYCLE (ONE OUTPUT) - % VIN = 20V RT = 2700Ω TA = 25˚C CT = 10 µF CT = 1 µF Note: Duty-Cycle is percent of two clock periods that one output conducts Duty Cycle vs. Input VoltageError Amplifier Voltage Gain vs. Frequency Over RF I Error Amplifier Section (Unless otherwise specified, VCM = 2.5V): continued Open Loop Voltage Gain ∆VOUT = 1 to 4V, RL ≥ 10 MΩ 60 80 dB Gain-Bandwidth* T A = 25˚C, AV = 0dB 3 MHz I Current Limit Amplifier (Unless otherwise specified, VSENSE = VO) Input Offset Voltage T A = 25˚C, EA Set for Max. Output 180 200 220 mV Input Offset Voltage Over Operating Temperature Range 170 230 mV Input Bias Current -1 -10 µA Common Mode Rejection Ratio V SENSE = 0 to 15V 50 60 dB Power Supply Rejection Ratio V IN = 10 to 40V 50 60 dB Output Swing Minimum Total Range 0.5 5.0 V Open Loop Voltage Gain ∆ VOUT = 1 to 4V, RL ≥ 10MΩ 70 80 dB Delay Time* ∆VIN = 300mV 300 ns I Output Section (Each Output) Collector Emitter Voltage I C = 100µA 60 80 V Collector Leakage Current V CE = 50V 0.1 20.0 µA Saturation I C = 20mA 0.2 0.4 V IC = 200mA 1.0 2.2 V Emitter Output Voltage I E = 50mA 17 18 V Rise Time* T A = 25˚C, R = 2kΩ 200 ns Fall Time* T A = 25˚C, R = 2kΩ 100 ns Comparator Delay* T A = 25˚C, VCOMP to VOUT 300 ns Shutdown Delay* T A = 25˚C, VSHUT to VOUT 200 ns Shutdown Threshold T A = 25˚C, RC = 2kΩ 0.5 0.7 1.0 V Thermal Shutdown* 165 ˚C * These parameters are guaranteed by design but not 100% tested in production.

Typical Performance Characteristics continued 2 5 10 20 100 TIMING RESISTOR - RT (kΩ) OSCILLATOR FREQUENCY (Hz) 1 50 100k 10k 100 VIN = 20V TA = 25˚C CT = 1.0nf CT = 3.0nf CT = 10nf CT = 30nf CT = 100nf 1.15 RTCT 2 5 10 20 100 TIMING CAPACITOR - CT (nf) OUTPUT DEAD TIME (µs) 1 50 5.0 2.0 1.0 0.5 0.2 0.1 VIN = 20V RT = 2700Ω TA = 25˚C Note: Dead time = osc output pulse width plus output delay Output Dead Time vs. Timing Capacitor ValueOscillator Frequency vs. Timing Components Resistor Over Timing Capacitance 1234 DELAY TIME (µs) OUTPUT (V) INPUT at ISENSE+ 0.2 0.1 0.0INTPUT (V) VIN 20V TA 25˚C EA+ = VREF ISENSE– = Gnd OUTPUT at COMP Overdrive 10% 20% 50% 1.0 0.5 0.0 0123 DELAY TIME (µs) OUTPUT (V) VIN = 20V RL = 2kΩ TA = 25˚C INTPUT (V) OUTPUT at VOA OR VOB INPUT at SHUTDOWN Note: Minimum input pulse width to latch is 200ns 0123 DELAY TIME (µs) OUTPUT (V)INTPUT (V) VIN = 20V RL = 2kΩ TA = 25˚C OUTPUT at VOA or VOB INPUT at VOB Note: Minimum input pulse width to latch is 200ns Shutdown Delay From PWM Comparator Turn-Off Delay From ShutdownCurrent Limit Amplifier Delay 01 02 0 3 0 4 05 0 Note: Outputs off. RT = ∞ SUPPLY VOLTAGE VIN (V) TA = -55°C TA = 25°C TA = 125°C QUIESCENT CURRENT (mA) Quiescent Supply Current vs. Supply Voltage Over Temperature

Typical Performance Characteristics continued 50 100 150 200 250 OUTPUT COLLECTOR CURRENT (mA) VCE SAT (V) TA = 125˚C TA = 25˚C TA = –55˚C Output Saturation Voltage vs. Output Current Over Temperature IS CS3524A 0.1 RT CT 0.1 10k Ω 2kΩ 10k Ω 1kΩ 2kΩ 100k Ω 100k Ω SHUTDOWN 2kΩ 2kΩ VCC VIN SYNC VREF VOUTA VOUTB EA EB R T C T EA+ EA– COMP ISENSE ISENSE SHUTDOWNGnd Open Loop Test Circuit Note: The CS3524A should be able to be tested in any 3524 test circuit with two possible exceptions: 1. The higher gain-bandwidth of the current limit amplifier in the CS 3524A may cause oscillations in an uncom- pensated 3524 test circuit. 2. The effect of the shutdown, cannot be seen at the compensation terminal, but must be observed at the outputs. CS3524A

CS3524AGDW16 16 Lead SO Wide CS3524AGDWR16 16 Lead SO Wide (tape & reel) Thermal Data 16 Lead 16L PDIP SO Wide RΘJC typ 42 23 ˚C/W RΘJA typ 80 105 ˚C/W D Lead Count Metric English Max Min Max Min 16 Lead PDIP 19.69 18.67 .775 .735 16L SO Wide 10.50 10.10 .413 .398 Package Specification PACKAGE DIMENSIONS IN mm (INCHES)

Ordering Information

Rev. 10/28/96 CS3524A © 1999 Cherry Semiconductor Corporation Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Plastic DIP (N); 300 mil wide 0.39 (.015) MIN. 1.14 (.045) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. .203 (.008) .356 (.014) REF: JEDEC MS-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022) Surface Mount Wide Body (DW); 300 mil wide 1.27 (.050) BSC 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) D 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) REF: JEDEC MS-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 2.35 (.093) 0.30 (.012) 0.10 (.004)