CS2841B

CS2841B CHERRY | Alldatasheet

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Rev. 6/23/99 Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ®

Electrical Characteristics: d -40≤TA≤85˚C RT=680kΩ, CT=0.022µF for triangular mode, VCC=15V (Note 1), RT=10kΩ, CT=3.3nF for sawtooth mode (See Fig. 3), unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS2841B Notes: 1. Adjust Vcc above the start threshold before setting at 15V. 3. Parameter measured at trip point of latch with V FB=0. 2.These parameters, although guaranteed, are not 100% tested in production. 4. Gain defined as: A = ; 0 ≤ VSense ≤ 0.8V. ∆VCOMP ∆VSense I Reference Section Output Voltage T J=25˚C, IOUT=1mA 4.90 5.00 5.10 V Line Regulation 8.4 ≤VCC≤16V 6 20 mV Load Regulation 1 ≤IOUT≤20mA 6 25 mV Temperature Stability (Note 2) 0.2 0.4 mV/ ˚C Total Output Variation Line, Load, Temp. (Note 2) 4.82 5.18 V Output Noise Voltage 10Hz ≤f≤10kHz, T J=25˚C (Note 2) 50 µV Long Term Stability T A=125˚C, 1000 Hrs. (Note 2) 5 25 mV Output Short Circuit T A=25˚C -30 -100 -180 mA I Oscillator Section Initial Accuracy Sawtooth Mode: (See Fig. 3)T J=25˚C 47 52 57 kHz Sawtooth Mode: -40˚C≤TA≤+85˚ 44 52 60 kHz Triangular Mode (See Fig. 3) TJ=25˚C 44 52 60 kHz Voltage Stability 8.4V ≤Vcc≤16V 0.2 1.0 % Temperature Stability Sawtooth Mode T MIN≤TA≤TMAX 5% Triangular Mode TMIN≤TA ≤TMAX 8% (Note 2) Amplitude V OSC (peak to peak) 1.7 V Discharge current T J=25˚C 7.4 8.3 9.2 mA TMIN≤TA≤TMAX 7.2 9.4 mA I Error Amp Section Input Voltage V COMP=2.5V 2.42 2.50 2.58 V Input Bias Current V FB=0V -0.3 -2.0 µA AVOL 2≤VOUT≤4V 65 90 dB Unity Gain Bandwidth (Note 2) 0.7 1.0 MHz PSRR 8.4V ≤V CC≤16V 60 70 dB Output Sink Current V FB=2.7V, VCOMP=1.1V 2 6 mA Output Source Current V FB=2.3V, VCOMP=5V -0.5 -0.8 mA VOUT High V FB=2.3V, RL=15kΩ to ground 5 6 V VOUT Low V FB=2.7V, RL=15kΩ to VREF 0.7 1.1 V I Current Sense Section Gain (Notes 3 & 4) 2.85 3.00 3.15 V/V Maximum Input Signal V COMP=5V (Note 3) 0.9 1.0 1.1 V PSRR 12V ≤VCC≤25V (Note 3) 70 dB Input Bias Current V Sense=0V -2 -10 µA Delay to Output T J=25˚C (Note 2) 150 300 ns

Electrical Characteristics: continued PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I Output Section Output Low Level I SINK=20mA 0.1 0.4 V ISINK=200mA 1.5 2.2 V Output High Level I SOURCE=20mA 13.0 13.5 V ISOURCE=200mA 12.0 13.5 V Rise Time T J=25˚C, CL=1nF (Note 2) 50 150 ns Fall Time T J=25˚C, CL=1nF (Note 2) 50 150 ns Output Leakage Undervoltage Active, V OUT=0 -0.01 -10.00 µA I Total Standby Current Start-Up Current 0.5 1.0 mA Operating Supply Current I CC VFB=VSense=0V, RT=10kΩ, CT=3.3nF 11 17 mA I Under-Voltage Lockout Section Start Threshold 7.6 8.0 8.4 V Min. Operating Voltage After Turn On 7.0 7.4 7.8 V Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION 8L PDIP 14L SO Narrow 1 1 COMP Error amp output, used to compensate error amplifier 23 V FB Error amp inverting input 3 5 Sense Noninverting input to Current Sense Comparator 4 7 OSC Oscillator timing network with Capacitor to Ground, resistor to V REF 5 8 Gnd Ground

9 Pwr Gnd Output driver Ground

61 0 V OUT Output drive pin

11 V CCPwr Output driver positive supply

71 2V CC Positive power supply 81 4V REF Output of 5V internal reference 2,4,6,13 NC No Connection

1k Ω 0.1 µF 0.1 µF VREF VCC VOUT Gnd VFB Sense OSC COMP 5k Ω 100k Ω 4.7k Ω 1k Ω Error Amp Adjust 4.7k Ω Sense Adjust RT 2N2222 CT Gnd A Test Circuit Undervoltage Lockout During Undervoltage Lockout (Figure 1), the output driv- er is biased to a high impedance state. The output should be shunted to ground with a resistor to prevent output leakage current from activating the power switch. PWM Waveform To generate the PWM waveform, the control voltage from the error amplifier is compared to a current sense signal which represents the peak output inductor current (Figure 2). An increase in V CC causes the inductor current slope to increase, thus reducing the duty cycle. This is an inherent feed-forward characteristic of current mode control, since the control voltage does not have to change during changes of input supply voltage. When the power supply sees a sudden large output cur- rent increase, the control voltage will increase allowing the duty cycle to momentarily increase. Since the duty cycle tends to exceed the maximum allowed to prevent trans- VCC VON = 8.0V VOFF = 7.4V ON/OFF Command to reset of IC <15mA <1mA 7.4V 8.0V ICC VCC Circuit Description Typical Performance Characteristics: 800 900 FREQ. (kHz) CT (µF) 700 600 500 400 300 200 100 .05 RT =1.5kΩ RT =680Ω RT =10kΩ 100 200 700 1k 2k 5k 7k 10k DUTY CYCLE (%) RT (Ω) 4k3k500400300 100 Oscillator Duty Cycle vs RTOscillator Frequency vs CT Figure 1: Typical Undervoltage Characteristics

D Lead Count Metric English Max Min Max Min 8 Lead PDIP 10.16 9.02 .400 .355 14 Lead SO Narrow 8.75 8.55 .344 .337 6Rev. 6/23/99 CS2841B Part Number Description CS2841BEN8 8L PDIP CS2841BED14 14L SO Narrow CS2841BEDR14 14L SO Narrow (tape & reel)

Ordering Information

RΘJC typ 52 30 ˚C/W RΘJA typ 100 125 ˚C/W Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA © 1999 Cherry Semiconductor Corporation Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) D 0.25 (0.10) 0.10 (.004) 1.75 (.069) MAX 1.27 (.050) 0.40 (.016) REF: JEDEC MS-012 0.25 (.010) 0.19 (.008) Surface Mount Narrow Body (D); 150 mil wide Plastic DIP (N); 300 mil wide 0.39 (.015) MIN. 1.14 (.045) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. .203 (.008) .356 (.014) REF: JEDEC MS-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022)