CS201

CS201 FUJITSU | Alldatasheet

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DS06-20211-1EFUJITSU SEMICONDUCTOR DATA SHEET Copyright©2007 FUJITSU LIMITED All rights reserved Semicustom CMOS Standard Cell CS201 Series ■ DESCRIPTION The CS201 series of 65 nm standard cells is a line of CMOS ASICs that satisfy demands for lower power consumption and higher integration. These cells offer the minimum level of leakage current in the semiconductor industry, and are able to implement a mixture of core transistors with three different threshold voltages, as appropriate for the applications ranging from handheld terminals to digital audiovisual equipment. The integration level in this series is twice the previous series with lower power consumption. ■ FEATURES

• Technology : 65 nm Si gate CMOS : 6 to 12 layers of metal wiring. Ultra Low-K (low permittivity) material is used for dielectric inter-layers. Three different types of core transistors (low leak, standard and high speed) can be used on the same chip.  Power supply voltage : Supports a wide range from + 0.9 V to + 1.3 V  Operation junction temperature : − 40 °C to + 125 °C (standard)  Gate delay time : 11 ps (1.2 V, Inverter, F/O = 1)  Gate power consumption : 1.77 nW/gate (operating condition: 1.2 V, operating rate 0.5, 1 MHz)  Reduced chip size achieved by creating the wi re bonding pads within the I/O macro regions.  Support various cell sets (from low po wer versions to high speed versions)  Compiled cell (RAM, ROM, others)  Support large capacity memory “1T -SRAM-Q ®”*1 “1T -SRAM-Q ®” is the embedded memory which enable maximum 128Mbit.  Support low-consumption technology “ CoolAdjustTM ”*2  Support ultra high speed (up to 10 Gbps) interface macros  Special interfaces (LVDS, SSTL, others)  Short-term development using a physical prototyping tool  One pass design using a physical synthesis tool  Hierarchical design environment for supporting large-scale circuits  Support Signal Integrity, EMI noise reduction  Support static timing sign-off (Continued)

(Continued)  Improve timing convergence by using Statistical Static Timing Analysis (SSTA)  Design For Manufacturing (DFM) enables stable product-supply and reduced variation  Optimum package range : FBGA, PBGA, TEBGA, FC-BGA *1: To realize this memory, the “1T -SRAM-Q ®” technology by MoSys Inc. was used *2: “CoolAdjust TM” is low power solution presented by Fujitsu. Note : Some of the features are not available yet. ■ MACRO LIBRARIES (including macros currently being prepared) 1. Logic cells (about 400 types) Library sets having three different threshold voltages of core transistors. 2. IP macros The following macros will be made available for the CS201 series. * : ARM is the trademark of ARM Limited. 3. Special I/O interface macro

• Adder • AND • AND-OR
• AND-OR Inverter • Buffer • Clock Buffer
• Decoder • Delay Buffer • ENOR
• EOR • Inverter • Latch
• NAND • NOR • OR
• OR-AND • OR-AND Inverter • SCAN Flip flop
• Non-SCAN Flip Flop • Multiplexer
• Others CPU/DSP ARM ™* cores(ARM7/ARM9/ARM11),Peripherals IP Mixed signal macro ADC, DAC, OPAMP, others Compiled macro SRAM (1 Port, 2 Port), 1 ROM, product sum calculators Large capacity memory 1T-SRAM-Q PLL Analog PLL Interface macro (PHY) LVDS, SSTL2, SSTL18, PCI, I 2C, others Interface macro (controller) USB2.0 Device/host, Serial ATA, PCI-Express, DDR2, HDMI, others

■ COMPILED CELL Compiled cells are macro cells that can be automatically generated by specifying the bit/word configuration. The following compiled cells are available for the CS201 series (Note that the bit/word ranges for each macro vary depending on the column type). 1. Clock synchronous single-port RAM (1 address : 1 read/write) 2. Clock synchronous dual port RAM (2 address: 2 read/write) 3. Clock synchronous ROM 4. Clock synchronous register file (2 address : 1 read, 1 write) Column type Memory capacity (bit) Word range (word) Bit range (bit) 2 16 to 160 K 16 to 1 K 1 to 160 4 32 to 640 K 32 to 8 K 1 to 80 8 64 to 640 K 64 to 16 K 1 to 40 Column type Memory capacity (bit) Word range (word) Bit range (bit) 4 64 to 72 K 32 to 1K 2 to 72 Column type Memory capacity (bit) Word range (word) Bit range (bit) 16 256 to 1M 128 to 8 K 2 to 128 64 1K to 1M 512 to 32 K 2 to 32 Column type Memory capacity (bit) Word range (word) Bit range (bit) 1 16 to 1152 8 2 to 144 1 32 to 18 K 16 to 128 2 to 144

■ ABSOLUTE MAXIMUM RATINGS *1 : VSS = 0 V *2 : Internal gates *3 : 1.8 V interface on dual-power supply system *4 : 2.5 V interface on dual-power supply system *5 : 3.3 V interface on dual-power supply system *6 : The output current varies depending on the number of wiring layers in the chip and the wiring configuration of the I/O cells. Contact your Fujitsu representative for details. WARNING: Semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*

1 VDD

− 0.5 + 1.8 V − 0.5 + 4.6 *5 Input voltage*1 VI V Output voltage*1 VO V Storage temperature T ST − 55 + 125 °C Operation junction temperature Tj − 40 + 125 °C Output current*6 IO ⎯ 15 mA Power supply pin current I D ⎯ 40 mA

■ RECOMMENDED OPERATING CONDITIONS

• Dual power supply (under planning) (VSS = 0 V)
• Dual power supply (under planning) (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Power supply voltage VDDE 1.65 1.8 1.95 V VDDI 0.9 1.0 1.1 V 1.1 1.2 1.3 V H level input voltage

1.8 V CMOS Normal

VDDE × 0.65 ⎯ VDDE + 0.3 V 1.8 V CMOS Schmitt V DDE × 0.70 ⎯ VDDE + 0.3 V L level input voltage − 0.3 ⎯ VDDE × 0.35 V 1.8 V CMOS Schmitt − 0.3 ⎯ VDDE × 0.30 V Schmitt hysteresis voltage V H VDDE × 0.10 ⎯ VDDE × 0.40 V Operation junction temperature Tj − 40 ⎯ + 125 °C Parameter Symbol Value Unit Min Typ Max Power supply voltage VDDE 2.3 2.5 2.7 V VDDI 0.9 1.0 1.1 V 1.1 1.2 1.3 V H level input voltage

2.5 V CMOS Normal

1.7 ⎯ VDDE + 0.3 V 2.5 V CMOS Schmitt 1.7 ⎯ VDDE + 0.3 V L level input voltage − 0.3 ⎯ + 0.7 V 2.5 V CMOS Schmitt − 0.3 ⎯ + 0.7 V Schmitt hysteresis voltage V H 0.2 ⎯ 1.0 V Operation junction temperature Tj − 40 ⎯ + 125 °C

• Dual power supply (VSS = 0 V) WARNING: The recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Min Typ Max Power supply voltage V DDE 3.0 3.3 3.6 V VDDI 0.9 1.0 1.1 V 1.1 1.2 1.3 V H level input voltage

3.3 V CMOS Normal

2.0 ⎯ VDDE + 0.3 V 3.3 V CMOS Schmitt 2.1 ⎯ VDDE + 0.3 V L level input voltage − 0.3 ⎯ + 0.8 V 3.3 V CMOS Schmitt − 0.3 ⎯ + 0.7 V Schmitt hysteresis voltage V H 0.2 ⎯ 1.4 V Operation junction temperature Tj − 40 ⎯ + 125 °C

■ ELECTRICAL CHARACTERISTICS

• Dual power supply (under planning)
• Dual power supply (under planning)
• Dual power supply Parameter Symbol Conditions Value Unit Min Typ Max H level output voltage V OH 1.8 V output IOH = − 100 µAV DDE − 0.2 ⎯ VDDE V L level output voltage V OL 1.8 V output IOL = 100 µA0 ⎯ 0.2 V Input leakage current I L ⎯⎯ ⎯ ⎯ µ A Pull-up/Pull-down resistor Rp Pull-up VIL = 0 V Pull-down VIH = VDDE ⎯ 18 ⎯ kΩ Parameter Symbol Conditions Value Unit Min Typ Max H level output voltage V OH 2.5 V output IOH = − 100 µAV DDE − 0.2 ⎯ VDDE V L level output voltage V OL 2.5 V output IOL = 100 µA0 ⎯ 0.2 V Input leakage current I L ⎯⎯ ⎯ ⎯ µ A Pull-up/Pull-down resistor Rp Pull-up V IL = 0 V/ Pull-down VIH = VDDE ⎯ 25 ⎯ kΩ Parameter Symbol Conditions Value Unit Min Typ Max H level output voltage V OH 3.3 V output IOH = − 100 µAV DDE − 0.2 ⎯ VDDE V L level output voltage V OL 3.3 V output IOL = 100 µA0 ⎯ 0.2 V Input leakage current I L ⎯ − 10 ⎯ + 10 µA Pull-up/Pull-down resistor Rp Pull-up V IL = 0 V/ Pull-down VIH = VDDE 15 33 70 k Ω

■ DESIGN METHODS Fujitsu’s Reference Design Flow provides the following functions that help reduce the development time of large scale, high quality LSIs.  Statistical Static Timing Analysis (SSTA) improves timing convergence.  Physical Prototyping enables more accurate estimation of highly reliable designs.  Layout synthesis with optimized timing is realized by Physical Synthesis Tool.  High accuracy design environment considers drop in power supply voltage, signal noise, delay penalty and crosstalk.  I/O design environment (power line design, assignment and selection of I/Os, package selection) considers noise. ■ PACKAGES The CS201 series can use the same pa ckages that were available for the previous series, allowing a smooth transition from previously developed models. For details of delivery time, contact Fujitsu.  FBGA packages  PBGA packages  TEBGA packages  FC-BGA packages

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.