CS1301

CS1301 NSC | Alldatasheet

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© 2002 National Semiconductor Corporation 1 www.national.com Geode™ CS1301/CS1311 Multimedia Companion: Media Data Processor General Description The National Semiconductor® Geode™ CS1301 and CS1311 multimedia companions act as coprocessors to decode multimedia in National’s Geode single chip proces- sor-based systems (i.e., SC1200/SC1201, SC2200, and SC3200, hereafter referred to as SCx200). They provide a multimedia experience for an Information Appliance (IA) user that cannot typically be achieved on a PC. By implementing a dedicated coprocessor to perform multi- media tasks, a high quality video viewing experience can be achieved. This high quality is achieved by having a coprocessor architecture that is ideally suited for decoding digital media. In addition, since the decoding is not occur- ring on the SCx200, system events cannot interrupt the coprocessor’s task of decoding media and thereby causing stuttering of sound or interruptions in the video. Lower power consumption can also be achieved using the SCx200/CS1301 or SCx200/CS1311 solution. The CS1301/CS1311 has an architecture specifically designed for decoding media. The architecture is such that while decoding media, power is not consumed by portions of the system that are not used to decode media. Since the SCx200 is not decoding the media locally, it is able to go into a lower power state. When the CS1301/CS1311 is not decoding media, it uses almost no power. Additionally, since the architecture is designed for decoding media, fewer CS1301/CS1311 cycles are required. Internal Block Diagram 2/4/6/8 Ch. Digital Audio 16/32-Bit Data I2SD C , up to 22 MHz AO_SCK IEC958 up to 40 Mbit/sec Huffman Decoder Slice-At-A-Time MPEG-1 & 2 CCIR-656 Digital Video 32-Bit Data (up to 664 MB/sec) Down and Up Scaling YUV --> RGB (50 Mpix/sec) PCI V2.1 (32 bits, 33 MHz) External Bus ACCESS.bus Interface to EEPROM Video In SDRAM PCI Interface Video Out Audio In Audio Out S/PDIF Out ACCESS.bus Interface VLD Coprocessor Timers VLIW CPU 32K I$ 16K D$ Image Coprocessor Main Memory Interface Stereo Digital Audio 8/16-bit data I2SD C , up to 22 MHz AI_SCK CCIR-656 Digital Video YUV 4:2:2 up to 81 MHz (40 Mpix/sec) Preliminary August 2002 Revision 2.2 Geode™ CS1301/CS1311 Multimedia Companion: Media Coprocessor National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode, MacPHYTER, WebPAD, and VSA are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.

www.national.com 2 Revision 2.2 Geode™ CS1301/CS1311

Features

I Process 0.25-micron CMOS I Packaged in a 292-terminal TEPBGA (Thermally Enhanced Plastic Ball Grid Array) I Power supply: — CS1301: 2.5V Core; 3.3V I/O (5V tolerant) — CS1311: 2.2V Core; 3.3V I/O (5V tolerant) I Consumption 1300 mA; 3.5W I Power-down 300 mA I Case Temperature 0° to 85°C Central Processing Unit I Clock speed: — CS1301: 180 MHz — CS1311: 166 MHz I I n s t r u c t i o nl e n g t hv a r i a b l e( 2t o2 3b y t e s ) I Instruction set arithmetic and logical operations, load/store operations, special multimedia and DSP operations, IEEE compliant floating point operations I Functional units 27, pipelined Caches I Data 16 KB, instructions 32 KB Memory System I Speed 166 MHz SDRAM I CPU/Memory programmable; 1:1, 5:4, 4:3, 3:2, and 2:1 speed ratios I Memory size 512 KB to 64 MB (up to four banks) I Recommended configurations: — 16 MB: Two 4M x 16 or two 2M x 32 — 32 MB: Four 2M x 32 or four 4M x 16 I Width 32-bit bus I Max. bandwidth 664 MB/sec (at 166 MHz) Image Coprocessor I Scaling programmable scale factor (0.2X to 10X) using 5-tap filters: — Horizontal or vertical scaling and filtering of individual Y, U o r V — Horizontal scaling and filtering with color conversion and overlay — HYUV to RGB, RGB overlay and alpha blending, bit mask blanking VLD Coprocessor I Parses MPEG-1 and MPEG-2 elementary bit streams generating run-level pairs and filling macroblock headers Timers I Four 32-bit wide timers Input/Output Support I PCI Interface: — PCI 2.1 compliant — Speed 33 MHz —B u sw i d t h3 2b i t s — Voltage drive and receive at 3.3V I Audio In (AI): —T w oI2S compliant channels — Sample size 8 or 16-bit samples per channel I Audio Out (AO): — Eight I2S compliant channels — Sample size 16 or 32-bit samples per channel I Video In (VI): — Supported signals CCIR-601/656: – 8-bit video (up to 40 Mpix/sec) — Image sizes all sizes, subject to sample rate — Provides programmable on-the-fly 2X horizontal resolution subsampling I Video Out (VO): — Image sizes flexible, including CCIR-601; max. 4K x 4K pixels (subject to 80 MB/sec data rate) — Outputs CCIR-601/656 8-bit video, PAL or NTSC — Clock rates programmable (4-80 MHz), typical 27 MB/sec (13.5 Mpix/sec for NTSC, PAL;

40 Mpix/sec in YUV 4:2:2 mode)

— Features full 129-level alpha blending, GenLock mode, frame synchronization chroma key, programmable YUV color clipping I S/PDIF Out: — Number of channels up to 6 — Sample size 16 or 24 bits per channel — IEC-958, output up to 40 Mbits/sec I ACCESS.bus Interface: — Supported modes single master only — Addressing 7-bit — Rates up to 400 Kbps

Revision 2.2 3 www.national.com Geode™ CS1301/CS1311

1.0 System Architecture

The CS1301/CS1311 multimedia companion acts as a coprocessor to decode multimedia in National’s Geode SC1200/SC1201, SC2200, and SC3200 (SCx200 unless otherwise specified). Figure 1-1 provides a typical system block diagram. Media decoding is one of the most demanding system applications. If media is decoded on the main processor, a much higher performance processor is required to achieve even comparable levels of media decoding quality. Such a system would be significantly over-designed for other tasks, such as browsing the Internet. Using a low-cost pro- cessor that is ideally suited for all tasks, and adding the coprocessor for the high performance media decoding requirement, results in a cost-effective solution. Another advantage of an processor/coprocessor solution is that an OEM (Original Equipment Manufacturer) can pro- vide a scalable solution. A single board can be designed that supports the coprocessor. If it is desired to support a low-end product that does not support the high quality media decoding capabilities, the coprocessor and its sup- porting components can be excluded from the system, which results in additional savings in an already cost-effec- tive design.

1.1 IMPORTANT DESIGN NOTE

The CS1301/CS1311 was designed to be a general pur- pose media data processor. As such, the CS1301/CS1311 is capable of far more than the current National CS1301/CS1311 solution. The solution that National is pro- viding is only one possible implementation of the CS1301/CS1311 and only this implementation is fully sup- ported by National Semiconductor. In order to maintain software compatibility with National’s provided software, any deviation of the CS1301/CS1311 section of the sche- matic is strongly discouraged. For those wishing to deviate from the schematic, or wishing to take advantage of other features of the CS1301/CS1311, documentation is available on the Philips Semiconductors SDE CD-ROM to support design varia- tions. However, additional support to implement these vari- ations must be obtained from one of the T riMedia Alliance Partners who support the CS1301/CS1311, its software, and the peripheral functions. For a list of TriMedia Alliance Partners, visit: http://www.trimedia.com/TAPP/ Figure 1-1. System Block Diagram Data Control Sub-ISA U S B1 ,2 ,3 Flash or M-Systems’ DiskOnChip Display: TV, CRT, or TFT SDRAM PCI Bus AMP LM4880 Codec LM4549 XpressROM BIOS IRDA IDE CompactFlash CCIR 656 VIP WM8725 DAC Geode TM CS1301/ CS1311 Geode TM SCx200 SDRAM EEPROM

www.national.com 4 Revision 2.2 Geode™ CS1301/CS1311 System Architecture(Continued)

1.2 SOFTWARE

The CS1301/CS1311 software and reference schematic is provided for a system that decodes media quickly with no original software development needed. As part of the CS1301/CS1311 purchase (see Section A.1 "Ordering Information" on page 24 for purchase details), National will license for the use of the operating system drivers and media decoder codecs in object form, which include:  Communications manager driver.  Video filter: Takes the video from the VIP (Video Input Port) of the Geode SCx200 and plays it back through the operating system media player.  Various multimedia codecs.

1.2.1 Software Support

National provides a reference schematic and the associ- ated software for a processor/coprocessor solution using the Geode SCx200 and the CS1301/CS1311. This imple- mentation is currently supplied as a multimedia decoder for CE player under Microsoft Windows CE.net or Linux. Future support for Microsoft Windows XP is planned. Since this is a software-based DSP (Digital Signal Processor) coprocessor rather than strictly a silicon-based coproces- sor, the software can be upgraded to support evolving media standards without a redesign of the hardware.

1.2.2 Software Features Support

The CS1301/CS1311 multimedia solution supports the fol- lowing software components: General Support  Reverse 3:2 pull down  Progressive display output  Capture Video Input MPEG-1 Decoding System stream (ISO 11172-1): —U pt o1 . 5M b p s  Video stream (ISO 11172-2): — CIF (up to 360x288) resolution — 29.97 fps (NTSC) —2 5f p s( P A L ) —U pt o1 . 1 2M b p s  Audio stream (ISO 11172-3): MPEG-1 layers 1 and 2: — Up to 384 Kbps, 32 KHz, 44.1 KHz or 48 KHz sample rate MPEG-2 Decoding  Program stream (ISO 13818-1): DVD style MPEG-2 program stream  Video stream (ISO 13818-2) - Main level at main profile: — Full screen NTSC (720x480) at 29.97 fps — Full screen PAL (720x576) at 25 fps  Audio stream - MPEG-2 audio: — Layers 1 and 2 (ISO 13818-3) at 32 KHz, 44.1 KHz or

48 KHz sample rate

— AC3 audio at 32 KHz, 44.1 KHz or 48 KHz sample rate MPEG-1, MPEG-2 Layer 3 Audio Decoding (MP3)  Up to 384 Kbps  Up to 48 KHz sample rate  Fixed bit rate decoding MPEG-4 Decoding Video stream - “Simple profile”: — CIF resolution at 30 fps, up to 384 Kbps  Audio stream - “High quality profile”: — MPEG-4 AAC low complexity and MPEG-4 CELP WMT (Windows Media Technology) Decoding  Video stream - Windows Media Video v8, also supports v7 decode: — CIF resolution at 30 fps, up to 1 Mbps  Audio stream - Windows Media Audio v8, also supports v7 decode: — Up to 128 Kbps and 48 KHz sample rate Windows Media Player Integration An implementation has been developed to seamlessly inte- grate Windows Media Player with WindowsCE.net or Linux. National has taken advantage of the native playback features supported by Microsoft DirectShow and has extended that functionality to the CS1301/CS1311. Win- dowsCE.net ships with an ActiveX control that wraps the filter graph manager and provides a very high level API (Application Programming Interface). It also supports a browser plug-in. An application writer can use the ActiveX control interface to playback MPEG-1/MPEG-2 media types. The user can also open the MPEG-1/MPEG-2/WMT files in Windows Media Player by double clicking on the file or by launching WMP , then opening the selected media. New codecs are continually being developed and added (see National’s IA Developer’s web site for a list of sup- ported codecs).

Revision 2.2 5 www.national.com Geode™ CS1301/CS1311 System Architecture(Continued)

1.2.3 Software Architecture Overview

Figure 1-2 demonstrates the interaction between the vari- ous software layers. Note: The shaded boxes indicate components provided by Microsoft Corporation. Figure 1-2. Software Architecture Diagram Windows Media Player ActiveX Control Filter Graph Manager File Source Video RendererDirectShow Filter TMComm TMMan32/HostComm/LibLoad/TMCRT TMMan32/HostComm/LibLoad/TMCRT CommTM ExolTMpeg Application TSSA* TRead Video Decoder Demux Audio Decoder VT ransCrystal Video Renderer Audio Renderer DAC To SCx200 Video Input Port TMMan Driver Geode Part TMMan Driver TM PartGeode™CS1301/CS1311 Geode™ SCx200 * TriMedia Streaming Software Architecture

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1.2.4 Software Component Pricing and Licensing

National delivers and supports a complete software solu- tion when paired up with the WindowsCE.net or Linux operating system. The delivered software is a compilation of software created by National Semiconductor, Philips Semiconductors and Microsoft. Customers may need sep- arate pricing and support agreements for Windows Media Technology (Microsoft), BIOS, Operating System, and mid- dleware. National’s pricing excludes fundamental patents: MPEG-1, -2, -4 (MPEG-LA) and MP3 (Thomson Multime- dia/Fraunhofer ILS). The following tables list the associ- ated software, their respective owners and the licensing requirements for each.

1.2.4.1 Codec Software

The codec software includes video and audio decoders and operates on the CS1301/CS1311 (see Table 1-1). This software performs the task of decoding the encoded media content, which are the workhorses of the solution.

1.2.4.2 Host Filter Software

The DirectShow filter is the core piece of software that inte- grates the CS1301/CS1311 media companion with Microsoft DirectShow (see T able 1-2). Table 1-1. Codec Software Components IP Owner(s) Available as Source/Binary Licensing Requirements TM MP3 Decoder Philips Semiconductors Binary Licensee is responsible for licensing of all fundamental patents.TM MP3 Basic Application TM MPEG-1 Video Decoder TM MPEG-1 Audio Decoder TM MPEG-2 Video Decoder TM MPEG-2 Audio Decoder TM AC-3 Audio Decoder TM MPEG-2 Program Stream Demux TM MPEG-2 Basic Application TM MPEG-4 Video Decoder TM MPEG-4 AAC Audio Decoder TM MPEG-4 CELP Audio Decoder TM MPEG-1 File Parser and Demultiplexer TM MPEG-4 Basic Application TM WMT v8 Video Decoder National Semiconductor Microsoft Binary Microsoft WMT license required.TM WMT v8 Audio Decoder Table 1-2. Host Filter Software Components IP Owner Available as Source/Binary Licensing Requirements DirectShow Filter National Semiconductor Binary Not licensed as source code.

Revision 2.2 7 www.national.com Geode™ CS1301/CS1311 System Architecture(Continued)

1.2.4.3 Communications Driver Software

The communications driver software includes most of the components that perform the communication and control tasks between the Geode SCx200 and the CS1301/CS1311 (see Table 1-3).

1.2.4.4 Software Development Kit

The Software Development Kit (SDK) includes the core software components that run on the TM32A core of the CS1301/CS1311. These are the supporting software com- ponents that enable the execution of the codec software on the CS1301/CS1311 (see Table 1-4).

1.2.4.5 System Software

To expand system functionality beyond media decoding, Geode software components are included. These are stan- dard components to be used in a non-media enabled appli- cation to support the required functions of an Information Appliance. In some cases, these drivers have been opti- mized to work with the CS1301/CS1311 (see Table 1-5). Table 1-3. Communications Driver Software Components IP Owner(s) Available as Source/Binary Licensing Requirements Host TMMan Driver National Semiconductor Philips Semiconductors Open Source Per Philips Semiconductors public source license provi- sions.TM TMMan Library TMComm Library HostComm Library TMCRT Library TMMan 32 LibLoad TriMedia Technologies, Inc. Binary NA Table 1-4. SDK Software Components IP Owner(s) Available as Source/Binary Licensing Requirements COMMTM National Semiconductor Philips Semiconductors Binary NA Video Renderer Audio Renderer TRead VTrans Crystal PSOS VxWorks Binary OS run-time licenses. Table 1-5. System Software Components IP Owner(s) Available as Source/Binary Licensing Requirements Graphics Driver (Linux, WinCE.net) National Semiconductor Source National source code license. Audio Driver (Linux, WinCE.net) WinCE.net Power Management OAL Touchscreen Driver (Linux, WinCE.net) National’s DP83815 MacPHYTER™ Network Driver (Linux, WinCE.net)

www.national.com 8 Revision 2.2 Geode™ CS1301/CS1311

2.0 Signal Definitions

This section defines the signals and describes the external interface of the CS1301/CS1311 media companion. Figure 2-1 shows the signals organized by their functional groups. The remaining subsections of this chapter describe:  Section 2.1 "Ball Assignments": Provides a ball assign- ment diagram and tables listing the signals sorted according to ball number and alphabetically by signal name.  Section 2.2 "Signal Descriptions": Detailed descriptions of each signal according to functional group.  Section 2.3 "Reference Voltages": Discussion on ball reference voltages.

2.1 BALL ASSIGNMENTS

The CS1301/CS1311 has a total of 169 functional pins, excluding VDDQ ,V SSQ , VREF_PCI, VREF_PERIPH, and digital power/ground. For pins with 5.0V input capability, the VREF_PCI or VREF_PERIPH determines 3.3V or 5.0V input tolerance. Unused pins can remain floating/uncon- nected; all pins that drive a clock should drive a series resistor. Table 2-1 shows the types of I/O circuits used by the CS1301/CS1311 series. Note that the # symbol in a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. Otherwise, the signal is asserted when at a high voltage level. Figure 2-1. Functional Block Diagram Table 2-1. Ball Type Descriptions Modes Description I Input only, except during boundary scan. O Output only, except during boundary scan. OD Open Drain output, active pull low, no active drive high, requires external pull-up. I/O Input or Output. I/OD Input with Open Drain output, active pull low, no active drive high, requires external pull-up. MM_DQ[31:00] MM_CLK[1:0] MM_RAS # MM_CAS# MM_WE# MM_DQM[3:0] MM_CS[3:0]# VREF_PCI VREF_PERIPH Video Out*VO_CLK Memory Interface Interface TRI_TIMER_CLK TRI_USERIRQSystem Interface Geode™ CS1301/CS1311 TRI_CLKIN MM_A[13:00] JTAG_TCK JTAG_TMS JTAG_TDI JTAG VO_IO[2:1] VO_DATA[07:00] AO_OSCLK AO_SCK AO_WS AO_SD[4:1] SPDO IIC-SDA Audio Out Interface MM_CKE[1:0] JTAG_TDO IIC-SCL TRI_RESET# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_AD[31:00] PCI_SERR# PCI_CLK PCI_GNT# PCI_REQ# PCI_IDSEL PCI_FRAME# PCI_IRDY# PCI_INTD# PCI_INTA# PCI_INTB# PCI_INTC# PCI Bus Interface PCI_PAR PCI_C/BE[3:0]# PCI_PERR# VI_CLK VI_DVALID VI_DATA[09:00] Video In *Video In and Audio In are supported by third party software solutions, not by the National Semiconductor solution. Interface AI_OSCLK AI_SCK AI_SD AI_WS Audio In* Interface S/PDIF ACCESS.bus BOOT_CLK TESTMODE SCANCPU Test and Measurement Interface Interface Interface VDDQ VSSQ (Total of 24) VDD (Total of 40) VCC (Total of 55) VSS (T otal of 8) NC Power, Ground and No Connections Interface

Revision 2.2 9 www.national.com Geode™ CS1301/CS1311 Signal Definitions(Continued) Figure 2-2. 292-TEPBGA Ball Assignment Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y A B C D E F G H J K L M N P R T U V W Y PA D 2 3PIDSEL P AD24 P AD27 P AD28 P AD31 PCIID# PCIIB# NC NC NC SPDO AOSD2 AOSC AOWS AISCK VILD VIDT8 VIDT5 VIDT4 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 PA D 2 0P AD19 PCBE3# P AD26 PGT# P AD30 PRQ# PCIIC# NC NC NC AOSD4 OSD1 AOOCK AIOCK AIWS VIDT9 VIDT7 VIDT3 VIDT2 PA D 1 8 PA D 2 1 PA D 2 2 PA D 2 5 VSS PA D 2 9 VCC VDD PCIIA# V CC VCC AOSD3 V DD VCC AISD V SS VIDT6 VRPER VIDT1 VICK P AD16 PCBE#2 P AD17 V SS VSS VCC VCC VDD VDD VCC VCC VDD VDD VCC VCC VSS VSS VIDT0 NC SCNCPU PIRD# PFM# V SS VSS PDVSL# VRPC PTRD# V CC PPR# PSTP# V CC VCC PP AR PSR# V DD VDD P AD14 P AD15 PCBE1# V DD PA D 1 2 PA D 1 3 VCC VCC PA D 1 1 PA D 1 0 VCC VCC P AD9 P AD8 PCBE0# V DD PA D 7 PA D 6 V DD VDD P AD5 P AD4 V CC VCC PA D 3 PA D 2 PA D 1 V CC PA D 0 P C I C K VSS VSS MCE1 MCS0# MCS2# V SS MDQM2 MDQ24 MDQ25 MDQM3 MDQ26 MDQ27 MDQ30 MDQ23 VSS VSS NC JTTMS VSS MDQ7 MDQM0 BTCK VSS VCC VCC VDD VDD VCC VCC VDD VDD VCC VCC VSS VSS MDQ4 MCS3# MCS1# VSS MDQ19 V CC VDD MMA6 V CC VCC MMA10 V DD VCC MDQ15 V SS MDQ9 MDQ1 MDQ5 MDQ6 VSS VSS VSS VSS VSS VSS VDD VDD TRTRCK VOIO2 VSS VSS VSS VSS VSS VSS VDD VOIO1 VOCLK VODT7 VSS VSS VSS VSS VSS VSS VCC VCC VODT6 V DDQ VSS VSS VSS VSS VSS VSS VCC VCC VSSQ TRCKIN VSS VSS VSS VSS VSS VSS VDD VODT3 VODT4 VODT5 VSS VSS VSS VSS VSS VSS VDD VDD VODT1 VODT2 VCC JTTDO JTTCK JTTDI VCC VCC TRRST# TRUSIQ VCC VCC TEST VODT0 VCC MDQM1 ICSDA ICSCL MDQ21 MDQ18 MDQ16 MMA8 MMA5 MMCK1 MMA2 MMA0 MMA12 MRS# MWE# MDQ13 MDQ11 MDQ8 MDQ2 MDQ3 Note: Signal names have been abbreviated in this figure due to space constraints. = GND Connection = CS1301 2.5V Core Power Connection; CS1311 2.2V Core Power Connection = 3.3V I/O Power Connection Geode™ CS1301/CS1311 Multimedia Companion MDQ28 MDQ29 MDQ31 MDQ22 MDQ20 MDQ17 MMA9 MMA7 MMA4 MMCK0 MMA3 MMA1 MMA11 MMA13 MCS# MDQ14 MDQ12 MDQ10 MCE0 MDQ0

www.national.com 10 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions(Continued) Table 2-2. Ball Assignment Sorted by Ball Number Ball No. Signal Name Type A1 PCI_AD23 I/O A2 PCI_IDSEL I A3 PCI_AD24 I/O A4 PCI_AD27 I/O A5 PCI_AD28 I/O A6 PCI_AD31 I/O A7 PCI_INTD# I/OD A8 PCI_INTB# I/O/OD A9 NC --- A10 NC --- A11 NC --- A12 SPDO O A13 AO_SD2 O A14 AO_SCK I/O A15 AO_WS I/O A16 AI_SCK I/O A17 VI_DVALID I A18 VI_DATA8 I A19 VI_DATA5 I A20 VI_DATA4 I B1 PCI_AD20 I/O B2 PCI_AD19 I/O B3 PCI_C/BE3# I/O B4 PCI_AD26 I/O B5 PCI_GNT# I B6 PCI_AD30 I/O B7 PCI_REQ# O B8 PCI_INTC# I/OD B9 NC --- B10 NC --- B11 NC --- B12 AO_SD4 O B13 AO_SD1 O B14 AO_OSCLK O B15 AI_OSCLK O B16 AI_WS I/O B17 VI_DATA9 I B18 VI_DATA7 I B19 VI_DATA3 I B20 VI_DATA2 I C1 PCI_AD18 I/O C2 PCI_AD21 I/O C3 PCI_AD22 I/O C4 PCI_AD25 I/O C5 V SS GND C6 PCI_AD29 I/O C7 V CC PWR C8 V DD PWR C9 PCI_INTA# I/OD C10 V CC PWR C11 V CC PWR C12 AO_SD3 O C13 V DD PWR C14 V CC PWR C15 AI_SD I C16 V SS GND C17 VI_DATA6 I C18 VREF_PERIPH PWR C19 VI_DATA1 I C20 VI_CLK I/O D1 PCI_AD16 I/O D2 PCI_C/BE#2 I/O D3 PCI_AD17 I/O D4 V SS GND D5 V SS GND D6 V CC PWR D7 V CC PWR D8 V DD PWR D9 V DD PWR D10 V CC PWR D11 V CC PWR D12 V DD PWR D13 V DD PWR D14 V CC PWR D15 V CC PWR D16 V SS GND D17 V SS GND D18 VI_DATA0 I D19 NC --- D20 SCANCPU I E1 PCI_IRDY# I/O E2 PCI_FRAME# I/O E3 V SS GND E4 V SS GND E17 V SS GND E18 V SS GND E19 NC --- E20 JTAG_TMS I F1 PCI_DEVSEL# I/O F2 VREF_PCI PWR F3 PCI_TRDY# I/O F4 V CC PWR F17 V CC PWR F18 JTAG_TDO I/O F19 JTAG_TCK I F20 JTAG_TDI I G1 PCI_PERR# I/O G2 PCI_STOP# I/O G3 V CC PWR G4 V CC PWR G17 V CC PWR G18 V CC PWR Ball No. Signal Name Type G19 TRI_RESET# I G20 TRI_USERIRQ I H1 PCI_PAR I/O H2 PCI_SERR# OD H3 V DD PWR H4 V DD PWR H8 V SS GND H9 V SS GND H10 V SS GND H11 V SS GND H12 V SS GND H13 V SS GND H17 V DD PWR H18 V DD PWR H19 TRI_TIMER_CLK I H20 VO_IO2 I/O J1 PCI_AD14 I/O J2 PCI_AD15 I/O J3 PCI_C/BE1# I/O J4 V DD PWR J8 V SS GND J9 V SS GND J10 V SS GND J11 V SS GND J12 V SS GND J13 V SS GND J17 V DD PWR J18 VO_IO1 I/O J19 VO_CLK I/O J20 VO_DATA7 O K1 PCI_AD12 I/O K2 PCI_AD13 I/O K3 V CC PWR K4 V CC PWR K8 V SS GND K9 V SS GND K10 V SS GND K11 V SS GND K12 V SS GND K13 V SS GND K17 V CC PWR K18 V CC PWR K19 VO_DATA6 O K20 V DDQ PWR L1 PCI_AD11 I/O L2 PCI_AD10 I/O L3 V CC PWR L4 V CC PWR L8 V SS GND Ball No. Signal Name Type

Revision 2.2 11 www.national.com Geode™ CS1301/CS1311 Signal Definitions(Continued) L9 V SS GND L10 V SS GND L11 V SS GND L12 V SS GND L13 V SS GND L17 V CC PWR L18 V CC PWR L19 V SSQ GND L20 TRI_CLKIN I M1 PCI_AD09 I/O M2 PCI_AD08 I/O M3 PCI_C/BE0# I/O M4 V DD PWR M8 V SS GND M9 V SS GND M10 V SS GND M11 V SS GND M12 V SS GND M13 V SS GND M17 V DD PWR M18 VO_DATA3 O M19 VO_DATA4 O M20 VO_DATA5 O N1 PCI_AD07 I/O N2 PCI_AD06 I/O N3 V DD PWR N4 V DD PWR N8 V SS GND N9 V SS GND N10 V SS GND N11 V SS GND N12 V SS GND N13 V SS GND N17 V DD PWR N18 V DD PWR N19 VO_DATA1 O N20 VO_DATA2 O P1 PCI_AD05 I/O P2 PCI_AD04 I/O P3 V CC PWR P4 V CC PWR P17 V CC PWR P18 V CC PWR P19 TESTMODE I P20 VO_DATA0 O R1 PCI_AD03 I/O R2 PCI_AD02 I/O R3 PCI_AD01 I/O R4 V CC PWR Ball No. Signal Name Type R17 V CC PWR R18 MM_DQM1 O R19 IIC_SDA I/OD R20 IIC_SCL I/OD T1 PCI_AD00 I/O T2 PCI_CLK I T3 V SS GND T4 V SS GND T17 V SS GND T18 MM_DQ07 I/O T19 MM_DQM0 O T20 BOOT_CLK I U1 MM_CKE1 O U2 MM_CS0# O U3 MM_CS2# O U4 V SS GND U5 V SS GND U6 V CC PWR U7 V CC PWR U8 V DD PWR U9 V DD PWR U10 V CC PWR U11 V CC PWR U12 V DD PWR U13 V DD PWR U14 V CC PWR U15 V CC PWR U16 V SS GND U17 V SS GND U18 MM_DQ04 I/O U19 MM_CS3# O U20 MM_CS1# O V1 MM_DQM2 O V2 MM_DQ24 I/O V3 MM_DQ25 I/O V4 MM_DQM3 O V5 V SS GND V6 MM_DQ19 I/O V7 V CC PWR V8 V DD PWR V9 MM_A06 O V10 V CC PWR V11 V CC PWR V12 MM_A10 O V13 V DD PWR V14 V CC PWR V15 MM_DQ15 I/O V16 V SS GND V17 MM_DQ09 I/O Ball No. Signal Name Type V18 MM_DQ01 I/O V19 MM_DQ05 I/O V20 MM_DQ06 I/O W1 MM_DQ26 I/O W2 MM_DQ27 I/O W3 MM_DQ30 I/O W4 MM_DQ23 I/O W5 MM_DQ21 I/O W6 MM_DQ18 I/O W7 MM_DQ16 I/O W8 MM_A08 O W9 MM_A05 O W10 MM_CLK1 O W11 MM_A02 O W12 MM_A00 O W13 MM_A12 O W14 MM_RAS# O W15 MM_WE# O W16 MM_DQ13 I/O W17 MM_DQ11 I/O W18 MM_DQ08 I/O W19 MM_DQ02 I/O W20 MM_DQ03 I/O Y1 MM_DQ28 I/O Y2 MM_DQ29 I/O Y3 MM_DQ31 I/O Y4 MM_DQ22 I/O Y5 MM_DQ20 I/O Y6 MM_DQ17 I/O Y7 MM_A09 O Y8 MM_A07 O Y9 MM_A04 O Y10 MM_CLK0 O Y11 MM_A03 O Y12 MM_A01 O Y13 MM_A11 O Y14 MM_A13 O Y15 MM_CAS# O Y16 MM_DQ14 I/O Y17 MM_DQ12 I/O Y18 MM_DQ10 I/O Y19 MM_CKE0 O Y20 MM_DQ00 I/O Ball No. Signal Name Type Table 2-2. Ball Assignment Sorted by Ball Number (Continued)

www.national.com 12 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions(Continued) Table 2-3. Ball Assignment Sorted Alphabetically by Signal Name Signal Name Ball No. AI_OSCLK B15 AI_SCK A16 AI_SD C15 AI_WS B16 AO_OSCLK B14 AO_SCK A14 AO_SD1 B13 AO_SD2 A13 AO_SD3 C12 AO_SD4 B12 AO_WS A15 BOOT_CLK T20 IIC_SCL R20 IIC_SDA R19 JTAG_TCK F19 JTAG_TDI F20 JTAG_TDO F18 JTAG_TMS E20 MM_A00 W12 MM_A01 Y12 MM_A02 W11 MM_A03 Y11 MM_A04 Y9 MM_A05 W9 MM_A06 V9 MM_A07 Y8 MM_A08 W8 MM_A09 Y7 MM_A10 V12 MM_A11 Y13 MM_A12 W13 MM_A13 Y14 MM_CAS# Y15 MM_CKE0 Y19 MM_CKE1 U1 MM_CLK0 Y10 MM_CLK1 W10 MM_CS0# U2 MM_CS1# U20 MM_CS2# U3 MM_CS3# U19 MM_DQ00 Y20 MM_DQ01 V18 MM_DQ02 W19 MM_DQ03 W20 MM_DQ04 U18 MM_DQ05 V19 MM_DQ06 V20 MM_DQ07 T18 MM_DQ08 W18 MM_DQ09 V17 MM_DQ10 Y18 MM_DQ11 W17 MM_DQ12 Y17 MM_DQ13 W16 MM_DQ14 Y16 MM_DQ15 V15 MM_DQ16 W7 MM_DQ17 Y6 MM_DQ18 W6 MM_DQ19 V6 MM_DQ20 Y5 MM_DQ21 W5 MM_DQ22 Y4 MM_DQ23 W4 MM_DQ24 V2 MM_DQ25 V3 MM_DQ26 W1 MM_DQ27 W2 MM_DQ28 Y1 MM_DQ29 Y2 MM_DQ30 W3 MM_DQ31 Y3 MM_DQM0 T19 MM_DQM1 R18 MM_DQM2 V1 MM_DQM3 V4 MM_RAS# W14 MM_WE# W15 NC (Total of 8) A9, A10, A11, B9, B10, B11, E19, D19 PCI_AD00 T1 PCI_AD01 R3 PCI_AD02 R2 PCI_AD03 R1 PCI_AD04 P2 PCI_AD05 P1 PCI_AD06 N2 PCI_AD07 N1 PCI_AD08 M2 PCI_AD09 M1 PCI_AD10 L2 PCI_AD11 L1 PCI_AD12 K1 PCI_AD13 K2 PCI_AD14 J1 PCI_AD15 J2 PCI_AD16 D1 PCI_AD17 D3 PCI_AD18 C1 PCI_AD19 B2 PCI_AD20 B1 PCI_AD21 C2 Signal Name Ball No. PCI_AD22 C3 PCI_AD23 A1 PCI_AD24 A3 PCI_AD25 C4 PCI_AD26 B4 PCI_AD27 A4 PCI_AD28 A5 PCI_AD29 C6 PCI_AD30 B6 PCI_AD31 A6 PCI_C/BE0# M3 PCI_C/BE1# J3 PCI_C/BE2# D2 PCI_C/BE3# B3 PCI_CLK T2 PCI_DEVSEL# F1 PCI_FRAME# E2 PCI_GNT# B5 PCI_IDSEL A2 PCI_INTA# C9 PCI_INTB# A8 PCI_INTC# B8 PCI_INTD# A7 PCI_IRDY# E1 PCI_PAR H1 PCI_PERR# G1 PCI_REQ# B7 PCI_SERR# H2 PCI_STOP# G2 PCI_TRDY# F3 SCANCPU D20 SPDO A12 TESTMODE P19 TRI_CLKIN L20 TRI_RESET# G19 TRI_TIMER_CLK H19 TRI_USERIRQ G20 V CC (3.3V I/O Power Supply, Total of 40) C7, C10, C11, C14, D6, D7, D10, D11, D14, D15, F4, F17, G3, G4, G17, G18, K3, K4, K17, K18, L3, L4, L17, L18, P3, P4, P17, P18, R4, R17, U6, U7, U10, U11, U14, U15, V7, V10, V11, V14 Signal Name Ball No. VDD (2.5V Core Power Supply, Total of 24) C 8 ,C 1 3 ,D 8 , D9, D12, D13, H3, H4, H17, H18, J 4 ,J 1 7 ,M 4 , M17, N3, N4, N17, N18, U8, U9, U12, U13, V8, V13 V DDQ K20 VI_CLK C20 VI_DATA0 D18 VI_DATA1 C19 VI_DATA2 B20 VI_DATA3 B19 VI_DATA4 A20 VI_DATA5 A19 VI_DATA6 C17 VI_DATA7 B18 VI_DATA8 A18 VI_DATA9 B17 VI_DVALID A17 VO_CLK J19 VO_DATA0 P20 VO_DATA1 N19 VO_DATA2 N20 VO_DATA3 M18 VO_DATA4 M19 VO_DATA5 M20 VO_DATA6 K19 VO_DATA7 J20 VO_IO1 J18 VO_IO2 H20 VREF_PCI F2 VREF_PERIPH C18 V SS (Ground Con- nection, Total of 55) C 5 ,C 1 6 ,D 4 , D5, D16, D17, E3, E4, E17, E18, H8, H9, H10, H11, H12, H13, J8, J9, J10, J11, J12, J13, K8, K9, K10, K11, K12, K13, L8, L9, L10, L11, L12, L13, M8, M9, M10, M11, M12, M13, N8, N9, N10, N11, N12, N13, T3, T4, T17, U4, U5, U16, U17, V5, V16, V SSQ L19 Signal Name Ball No.

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2.2 SIGNAL DESCRIPTIONS

2.2.1 System Interface Signals

No. Type Description TRI_CLKIN L20 I Main Input Clock.The SDRAM clock outputs (MM_CLK0 and MM_CLK1) can be set to 2x or 3x this frequency. The on-chip DSPCPU clock (DSPCPU_CLK) can be set to 1x, 5/4, 4/3, 3/2 or 2x the SDRAM clock frequency. The maximum recommended ppm level is ±100 ppm or lower to improve jitter on generated clocks. The duty cycle should not exceed 30/70% asymmetry. The operating limits of the internal PLLs are:  27 MHz < Output of the SDRAM PLL < 200 MHz  33 MHz < Output of the CPU PLL < 266 MHz These are not the speed grades of the chips, just the PLL limits. TRI_USERIRQ G20 I General Purpose Level/Edge Interrupt Input.Vectored interrupt source number 4. TRI_TIMER_CLK H19 I External General Purpose Clock Source for Timers. Maximum 40 MHz. TRI_RESET# G19 I CS1301/CS1311 RESET Input.This pin can be tied to the PCI_RST# signal in the PCI bus systems. Upon releasing RESET, CS1301/CS1311 initiates its boot protocol. VREF_PCI F2 PWR PCI Voltage Reference.Determines the mode of operation of the PCI pins. VREF_PCI must be connected to VSS (0V) for use in 3.3V PCI sig- naling environment, as is the case for a Geode SCx200 system. The supply to this pin should be AC bypassed and provide 40 mA of DC sink or source capability. VREF_PERIPH C18 PWR Peripheral Voltage Reference.Determines the mode of operation of the I/O pins listed in Section 2.3 "Reference Voltages" on page 22. VREF_PERIPH must be connected to 5.0V if the designated I/O pins listed in Section 2.3 should be 5.0V input voltage capable. VREF_PERIPH must be connected to VSS (0V) if the designated I/O pins listed in Section 2.3 are 3.3V only inputs. The supply to this pin should be AC bypassed and provide 40 mA of DC sink or source capability.

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2.2.2 Memory Interface Signals

No. Type Description MM_CLK0 Y10 O SDRAM Output Clock (at 2x or 3x TRI_CLKIN frequency).Two identi- cal outputs are provided to reliably drive several small memory configu- rations without external glue. A series terminating resistor close to CS1301/CS1311 is required to reduce ringing. For driving a 50Ω trace, a resistor of 27 to 33Ω is recommended. The use of higher impedance traces in the SDRAM signals is not recom- mended. MM_CLK1 W10 MM_A[13:00] See Table 2-3 on page 12 O Address Bus. Used for row and column addresses. WARNING: Do not connect MM_A[13:11] directly to SDRAM A[13:11] pins. Refer to Chapter 12 SDRAM Memory System of the Philips Semi- conductorPNX1300 Series Media Processors Data Bookfor accurate connection diagrams. MM_DQ[31:00] See Table 2-3 on page 12 I/O 32-Bit Data I/O Bus.The Main Memory Interface module also supports a 16-bit I/O interface. MM_CKE0 Y19 O Clock Enable Output to SDRAMs.Two identical outputs are provided in order to reliably drive several small memory configurations without external glue.MM_CKE1 U1 MM_CS0# U2 O Chip Select for DRAM rank n; active low.The chip select pins may be used as address pins to support the 256-Mbit SDRAM device organized in x16.MM_CS1# U20 MM_CS2# U3 MM_CS3# U19 MM_RAS# W14 O Row Address Strobe; active low. MM_CAS# Y15 O Column Address Strobe; active low. MM_WE# W15 O Write Enable; active low. MM_DQM0 T19 O Data Mask Enable.These are byte-enable signals for the 32-bit MM_DQ bus.MM_DQM1 R18 MM_DQM2 V1 MM_DQM3 V4

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2.2.3 PCI Interface Signals

No. Type Description PCI_CLK T2 I PCI Clock.All PCI input signals are sampled with respect to the rising edge of this clock. All PCI outputs are generated based on this clock. This clock is required for normal operation of the PCI module. PCI_AD[31:00] See Table 2-3 on page 12 I/O Multiplexed Address and Data. PCI_C/BE0# M3 I/O Multiplexed Bus Commands and Byte-Enables. High for command, low for byte-enable.PCI_C/BE1# J3 PCI_C/BE2# D2 PCI_C/BE3# B3 PCI_PAR H1 I/O Parity.Even parity across AD and C/BE# lines. PCI_FRAME# E2 I/O Frame Sustained TRI-STATE.F r a m ei sd r i v e nb yam a s t e rt oi n d i c a t e the beginning and duration of an access. PCI_IRDY# E1 I/O Initiator Ready Sustained TRI-STATE.Initiator Ready indicates that the bus master is ready to complete the current data phase. PCI_TRDY# F3 I/O Target Ready Sustained TRI-STATE.T arget Ready indicates that the bus target is ready to complete the current data phase. PCI_STOP# G2 I/O Stop Sustained TRI-STATE.Indicates that the target is requesting that the master stop the current transaction. PCI_IDSEL A2 I ID Select.Used as chip select during configuration read/write cycles. PCI_DEVSEL# F1 I/O Device Select Sustained TRI-STATE.Indicates whether any device on the bus has been selected. PCI_REQ# B7 O Request.Driven by the CS1301/CS1311 as a PCI bus master to request use of the PCI bus. PCI_GNT# B5 I Grant.Indicates to the CS1301/CS1311 that access to the PCI bus has been granted. PCI_PERR# G1 I/O Parity Error Sustained TRI-STATE.Parity error generated/received by CS1301/CS1311. PCI_SERR# H2 OD System Error.This signal is asserted when operating as a target and detecting an address parity error. PCI_INTA# C9 I/OD P C II n t e r r u p t sA ,B ,C ,a n dD .Can operate as an input (power-up default) or output, as determined by direction control bits in PCI MMIO register INT_CTL. As an input, PCI_INT# can be used to receive PCI interrupt requests (normal PCI use is active low, level-sensitive mode, but the VIC can be set to treat these as a positive edge triggered mode). As an input, PCI_INT# can also be used as a general interrupt request if not needed for PCI. As an output, the value of a PCI_INT# can be programmed through PCI MMIO registers to generate interrupts for other PCI masters. PCI_INTB# A8 I/O/OD PCI_INTC# B8 I/OD PCI_INTD# A7 I/OD Note: Current buffer design allows drive/receive from either 3.3V or 5.0V PCI bus.

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2.2.4 Video In Interface Signals

VI_CLK C20 I/O Clock.This signal can be configured as either an input or an output: If configured as an input (power-up default): A positive transition on this incoming video clock pin samples VI_DATA[09:00] if VI_DVALID is high. If VI_DVALID is low, VI_DAT A[09:00] is ignored. Clock and data rates of up to 81 MHz are supported. The CS1301/CS1311 supports an addi- tional mode where VI_DATA[09:08] in message passing mode are not affected by the VI_DVALID signal. If configured as an output: VI_CLK performs as a programmable output clock to drive an external video A/D converter. It can be programmed to emit integral dividers of DSPCPU_CLK. If used as an output, a board level 27 to 33Ω series resistor is recom- mended to reduce ringing. VI_DVALID A17 I Data Valid.VI_DVALID indicates that valid data is present on VI_DATA[09:00]. If high, VI_DATA will be accepted on the next VI_CLK positive edge. If low, VI_DATA[09:00] will not be sampled. However, the CS1301/CS1311 supports an additional mode where VI_DAT A[9:8] in message passing mode are not affected by the VI_DVALID signal. VI_DATA[07:00] B18, C17, A19, A20, B19, B20, C19, D18 I Data Bus Lines [7:0].CCIR-656 style YUV 4:2:2 data from a digital camera or general purpose high speed data input pins. Sampled on VI_CLK if VI_DVALID is high. VI_DATA[09:08] B17, A18 Data Bus Lines [9:8].Extension high speed data input bits to allow use of 10-bit video A/D converters in raw10 modes. VI_DATA[08] serves as START and VI_DATA[09] as END message input in message passing mode. Sampled on positive transitions of VI_CLK if VI_DVALID is high. The CS1301/CS1311 supports an additional mode where VI_DATA[09:08] in message passing mode are not affected by the VI_DVALID signal. Note: Video In and Audio In are supported by third party software solutions, not by the National solution.

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2.2.5 Video Out Interface Signals

No. Type Description VO_CLK J19 I/O Clock.The VO module emits VO_DATA[07:00] on a positive edge of VO_CLK. VO_CLK can be configured as an input (reset default) or out- put. If configured as an input: VO_CLK is received from external display clock master circuitry. If configured as an output: The CS1301/CS1311 emits a programmable clock frequency. The emitted frequency can be set between approxi- mately 4 and 81 MHz with a sub-Hertz resolution. The clock generated is frequency accurate and has low jitter properties due to a combination of an on-chip DDS (Direct Digital Synthesizer) and VCO/PLL. If used as an output, a board level 27 to 33Ω series resistor is recom- mended to reduce ringing. VO_IO1 J18 I/O Input/Output 1.This pin can function as HS (Horizontal Sync) output or as STMSG (Start Message) output. If set as HS output: VO_IO1 outputs the HS output signal. In message passing mode, VO_IO1 acts as the STMSG output signal. VO_IO2 H20 I/O Input/Output 2.This pin can function as FS (Frame Sync) input, FS out- put or as ENDMSG (End Message) output. If set as FS input, it can be set to respond to positive or negative edge transitions. If the VO module operates in external sync mode and the selected tran- sition occurs, the VO module sends two fields of video data. Note: this works only once after a reset. In message passing mode, this pin acts as ENDMSG output signal. VO_DAT A[07:00] K20, K12, M20, M19, M18, N20, N19, P20 O Data Bus.CCIR-656 style YUV 4:2:2 digital output data, or general pur- pose high-speed data output channel. Output changes on positive edge of VO_CLK.

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2.2.6 Audio In Interface Signals

No. Type Description AI_OSCLK B15 O Over-Sampling Clock.This output can be programmed to emit any fre- quency up to 40 MHz with a sub-Hertz resolution. It is intended for use as the 256f s or 384fs over-sampling clock by external A/D subsystem. A board level 27 to 33Ω series resistor is recommended to reduce ringing. AI_SCK A16 I/O Serial Clock.When the AI module is programmed as a serial-interface timing slave (power-up default), AI_SCK is an input. AI_SCK receives the serial bit clock from the external A/D subsystem. This clock is treated as fully asynchronous to the CS1301/CS1311 main clock. When the AI module is programmed as the serial-interface timing mas- ter, AI_SCK is an output. AI_SCK drives the serial clock for the external A/D subsystem. The frequency is a programmable integral divisor of the AI_OSCLK frequency. AI_SCK is limited to 22 MHz. The sample rate of valid samples embed- ded within the serial stream is variable. If used as an output, a board l e v e l2 7t o3 3Ω series resistor is recommended to reduce ringing. AI_SD C15 I Serial Data. Serial data from external A/D subsystem. Data on this pin is sampled on positive or negative edges of AI_SCK as determined by the CLOCK_EDGE bit in the AI_SERIAL register. AI_WS B16 I/O Word-Select.AI_WS is the word-select or frame-synchronization signal from/to the external A/D subsystem. When the AI module is programmed as the serial-interface timing slave (power-up default), AI_WS acts as an input. AI_WS is sampled on the same edge as selected for AI_SD. When the AI module is programmed as the serial-interface timing mas- ter, AI_WS acts as an output. It is asserted on the opposite edge of the AI_SD sampling edge. Note: The AI module always acts as receiver, but can be master or slave for A/D timing. Video In and Audio In are supported by third party software solutions, not by the National solution.

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2.2.7 Audio Out Interface Signals

No. Type Description AO_OSCLK B14 O Over-Sampling Clock. This output can be programmed to emit any fre- quency up to 40 MHz, with a sub-Hertz resolution. It is intended for use as the 256 or 384 f s over-sampling clock by the external D/A conversion subsystem. A board-level 27 to 33Ω series resistor is recommended to reduce ringing. AO_SCK A14 I/O Serial Clock. When the Audio Out (AO) module is programmed to act as the serial interface timing slave (power-up default), AO_SCK acts as an input. It receives the Serial Clock from the external audio D/A sub- system. The clock is treated as fully asynchronous to the CS1301/CS1311 main clock. When the AO module is programmed to act as the serial interface timing master, AO_SCK acts as an output. It drives the serial clock for the external audio D/A subsystem. The clock frequency is a programmable integral divisor of the AO_OSCLK frequency. AO_SCK is limited to 22 MHz. The sample rate of valid samples embedded within the serial stream is variable. If used as an output, a board-level 27 to 33Ω series resistor is recommended to reduce ringing. AO_SD1 B13 O Serial Data Buses. Serial data to external stereo audio D/A subsystem. The timing of transitions on this output is determined by the CLOCK_EDGE bit in the AO_SERIAL register, and can be on positive or negative AO_SCK edges. AO_SD2 A13 AO_SD3 C12 AO_SD4 B12 AO_WS A15 I/O Word-Select or Frame synchronization. Signal from/to the external D/A subsystem. Each audio channel receives 1 sample for every WS period. When the AO module is programmed as the serial interface timing slave (power-up default), AO_WS acts as an input. AO_WS is sampled on the opposite AO_SCK edge from which AO_SDx are asserted. When the AO module is programmed as serial interface timing master, AO_WS acts as an output. AO_WS is asserted on the same AO_SCK edge as AO_SDx. Note: The AO module always acts as sender, but can be master or slave for D/A timing.

2.2.8 S/PDIF Interface Signals

No. Type Description SPDO A12 O S/PDIF Data Out.Self-clocking serial data stream as per IEC958, with 1937 extensions. Note that the low impedance output buffer requires a 27 to 33Ω series terminator close to CS1301/CS1311 in order to match the board trace impedance. This series terminator must be part of the voltage divider needed to create the coaxial output through the AC isola- tion transformer.

www.national.com 20 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions(Continued) 2.2.9 ACCESS.bus Interface Signals Signal Name Ball No. Type Description IIC_SDA R19 I/OD ACCESS.bus Serial Data. IIC_SCL R20 I/OD ACCESS.bus Serial Clock.

2.2.10 JTAG Interface Signals

No. Type Description JTAG_TDI F20 I JTAG Test Data Input. JTAG_TDO F18 I/O JTAG Test Data Output.This pin can either drive active low, high or float. JTAG_TCK F19 I JTAG Test Clock Input. JTAG_TMS E20 I JTAG Test Mode Select Input.

2.2.11 Test and Measurement Interface Signals

No. Type Description BOOT_CLK T20 I Boot Clock.Used for testing purposes. Must be connected to TRI_CLKIN for normal operation. TESTMODE P19 I Test Mode.Used for testing purposes. Must be connected to VSS for normal operation. SCANCPU D20 I Scan CPU. Used for testing purposes. Must be connected to VSS for normal operation.

Revision 2.2 21 www.national.com Geode™ CS1301/CS1311 Signal Definitions(Continued)

2.2.12 Power, Ground, and No Connections

No. Type Description VDDQ K20 PWR Quiet VDD for the PLL Subsystem.Should be supplied from VDD through a low-Q series inductor. It should be bypassed for AC to VSSQ , using a dual capacitor bypass (high and low frequency AC bypass). VSSQ L19 GND Quiet VSS for the PLL Subsystem.S h o u l db eA Cb y p a s s e dt oVDDQ , otherwise left DC floating. It is connected on-chip to VSS .N oe x t e r n a l coil or other connection to board ground is needed; such a connection would create a ground loop. VDD See Table 2-3 on page 12 PWR 2.5V CS1301 Core Power Connection (Total of 24). 2.2V CS1311 Core Power Connection (Total of 24). VCC See Table 2-3 on page 12 PWR 3.3V I/O Power Connection (Total of 24). VSS See Table 2-3 on page 12 GND Ground Connection (Total of 50). NC A9, A10, A11, B9, B10, B11, E19, D19 --- No Connection.For normal operation, leave unconnected.

www.national.com 22 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions(Continued)

2.3 REFERENCE VOLTAGES

Outputs always drive to a level determined by the 3.3V I/O voltage, with the exception of Open Drain mode outputs. VREF_PERIPH and VREF_PCI determine input voltage clamping, not input signal thresholds or output levels. VREF_PCI Determined Mode VREF_PERIPH Determined Mode SDRAMInterface (3.3V Mode) Inputs (3.3V Mode) Output Only Pins PCI_AD00 PCI_AD27 TRI_USERIRQ MM_CLK0 MM_DQM2 TRI_CLKIN VO_DATA0 PCI_AD01 PCI_AD28 TRI_TIMER_CLK MM_CLK1 MM_DQM3 BOOT_CLK VO_DATA1 PCI_AD02 PCI_AD29 JTAG_TDI MM_A00 MM_DQ13 TESTMODE VO_DATA2 PCI_AD03 PCI_AD30 JTAG_TDO MM_A01 MM_DQ14 SCANCPU VO_DATA3 PCI_AD04 PCI_AD31 JTAG_TCK MM_A02 MM_DQ15 VO_DATA4 PCI_AD05 PCI_CLK JTAG_TMS MM_A03 MM_DQ16 VO_DATA5 PCI_AD06 PCI_C/BE#0 VI_CKL MM_A04 MM_DQ17 VO_DATA6 PCI_AD07 PCI_C/BE#1 VI_DVALID MM_A05 MM_DQ18 VO_DATA7 PCI_AD08 PCI_C/BE#2 VI_DATA0 MM_A06 MM_DQ19 AO_OSCLK PCI_AD09 PCI_C/BE#3 VI_DATA1 MM_A07 MM_DQ20 AO_SCK PCI_AD10 PCI_PAR VI_DATA2 MM_A08 MM_DQ21 AO_SD1 PCI_AD11 PCI_FRAME# VI_DATA3 MM_A09 MM_DQ22 AO_SD2 PCI_AD12 PCI_IRDY# VI_DATA4 MM_A10 MM_DQ23 AO_SD3 PCI_AD13 PCI_TRDY# VI_DATA5 MM_A11 MM_DQ24 AO_SD4 PCI_AD14 PCI_STOP# VI_DATA6 MM_A12 MM_DQ25 SPDO PCI_AD15 PCI_IDSEL VI_DATA7 MM_A13 MM_DQ26 PCI_AD16 PCI_DEVSEL# VI_DA TA8 MM_DQ00 MM_DQ27 PCI_AD17 PCI_REQ# VI_DATA9 MM_DQ01 MM_DQ28 PCI_AD18 PCI_GNT# IIC_SDA MM_DQ02 MM_DQ29 PCI_AD19 PCI_PERR# IIC_SCL MM_DQ03 MM_DQ30 PCI_AD20 PCI_SERR# VO_IO1 MM_DQ04 MM_DQ31 PCI_AD21 PCI_INT A# VO_IO2 MM_DQ05 MM_CKE0 PCI_AD22 PCI_INTB# VO_CLK MM_DQ06 MM_CKE1 PCI_AD23 PCI_INTC# AI_SCK MM_DQ07 MM_CS0# PCI_AD24 PCI_INTD# AI_SD MM_DQ08 MM_CS1# PCI_AD25 TRI_RESET# AI_WS MM_DQ09 MM_CS2# PCI_AD26 AO_SCK MM_DQ10 MM_CS3# AO_WS MM_DQ11 MM_RAS# MM_DQ12 MM_CAS# MM_DQM0 MM_WE# MM_DQM1

Revision 2.2 23 www.national.com Geode™ CS1301/CS1311

3.0 Package Specifications

Figure 3-1. 292-Terminal TEPBGA (Body Size: 27x27x2.33 mm; Pitch: 1.27 mm) NOTES: UNLESS OTHERWISE SPECIFIED. 1) SOLDER BALL COMPOSITION: SN 63%, PB 37%. 2) DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM N. 3) THE MOLD SURFACE AREA MAY INCLUDE DIMPLE FOR A1 BALL CORNER IDENTIFICATION. 4) REFERENCE JEDEC REGISTRATION MS-034, VARIATION BAL-1.

www.national.com 24 Revision 2.2 Geode™ CS1301/CS1311 Appendix A Support Documentation A.1 ORDERING INFORMATION A.2 CUSTOMER SUPPORT National is the primary contact for all technical support issues. For certain software modules listed, National does not have access to source code. For these software modules, National will work directly with intellectual property owners of these software modules to provide customer support. A.3 PRODUCT BRIEF REVISION HISTORY This section is a report of the revision/creation process of the product brief for the Geode CS1301/CS1311. Any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table below. Note: This product brief must be used in conjunction with the Philips SemiconductorPNX1300 Series Media Processors Data Bookfor a complete understanding of the CS1301/CS1311 (posted on National’s IA Developer’s web site). Order Number (NSID) Part Marking Core Frequency (MHz) Core Voltage (V) Temperature (Degree C) Package CS1301 CS1301 180 2.5 0 - 85 TEPBGA CS1311 CS1311 166 2.2 0 - 85 TEPBGA Note: Due to licensing agreements, the CS1301/CS1311 can only be purchased by those customers using a Geode processor-based design. Table A-1. Revision History Revision # (PDF Date) Revisions / Comments 1.0 (November 2001) First draft of product brief. (Confidential) 2.0 (April 2002) Updated to include a list of supported software and software block diagram. (Confidential) 2.1 (July 2002) Updated to include Signal Definitions and Package Specifications sections. (No longer confiden- tial, to be posted on National external web site in the product folders.) 2.2 (August 2002) Replaced “Product Brief” with “Preliminary”. Updated package specifications to use National sup- plied drawing and changed HBGA to TEPBGA. (These changes were made to meet Corporate standard requirements, revision 2.1 was never posted on National external web site.)

Geode™ CS1301/CS1311 Multimedia Companion: Media Data Processor LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. www.national.com National Semiconductor Corporation Americas Email: new.feedback@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 87 90 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Email: nsj.crc@jksmtp.nsc.com