CS1124 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • Dual Channel Capability
  • Built−In Test Mode
  • On−Chip Input V oltage Clamping
  • Works from 5.0 V Supply
  • Accurate Built−In Hysteresis
  • Pb−Free Packages are Available

Figure 1. Block Diagram dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

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http://onsemi.com MAXIMUM RATINGS Rating Value Unit Storage Temperature Range −65 to 150 °C Ambient Operating Temperature −40 to 125 °C Supply Voltage Range (continuous) −0.3 to 7.0 V Input Voltage Range (at any input, R1 = R2 = 22 k) −250 to 250 V Maximum Junction Temperature 150 °C ESD Susceptibility (Human Body Model) 2.0 kV Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 230 peak °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 60 second maximum above 183 °C. ELECTRICAL CHARACTERISTICS (4.5 V < VCC < 5.5 V, −40°C < TA < 125°C, VDIAG = 0; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit VCC SUPPLY Operating Current Supply VCC = 5.0 V − − 5.0 mA Sensor Inputs Input Threshold − Positive VDIAG = Low VDIAG = High 135 135 160 160 185 185 mV mV Input Threshold − Negative VDIAG = Low VDIAG = High −185 135 −160 160 −135 185 mV mV Input Bias Current (INP1, INP2) VIN = 0.336 V −16 −11 −6.0 /C0109A Input Bias Current (DIAG) VDIAG = 0 V − − 1.0 /C0109A Input Bias Current Factor (KI) (INAdj = INP × KI) VIN = 0.336 V, VDIAG = Low VIN = 0.336 V, VDIAG = High 152 100 155 157 %INP %INP Bias Current Matching INP1 or INP2 to INAdj, VIN = 0.336 V −1.0 0 1.0 /C0109A Input Clamp − Negative IIN = −50 /C0109A IIN = −12 mA −0.5 −0.5 −0.25 −0.30 V V Input Clamp − Positive IIN = +12 mA 5.0 7.0 9.0 V Output Low Voltage IOUT = 1.6 mA − 0.2 0.4 V Output High Voltage IOUT = −1.6 mA VCC − 0.5 VCC − 0.2 − V Mode Change Time Delay − 0 − 20 /C0109s Input to Output Delay IOUT = 1.0 mA − 1.0 20 /C0109s Output Rise Time CLOAD = 30 pF − 0.5 2.0 /C0109s Output Fall Time CLOAD = 30 pF − 0.05 2.0 /C0109s Open−Sensor Positive Threshold VDIAG = High, RIN(Adj) = 40 k. Note 2 29.4 54 86.9 k/C0087 Logic Inputs DIAG Input Low Threshold − − − 0.2 × VCC V DIAG Input High Threshold − 0.7 × VCC − − V DIAG Input Resistance VIN = 0.3 × VCC , VCC = 5.0 V VIN = VCC, VCC = 5.0 V 8.0 8.0 k/C0087 k/C0087 2. This parameter is guaranteed by design, but not parametrically tested in production.

http://onsemi.com PACKAGE PIN DESCRIPTION PIN # SOIC−8 PIN SYMBOL FUNCTION 1 INAdj External resistor to ground that sets the trip levels of both channels. Functions for both diagnostic and normal mode

2 IN1 Input to channel 1

3 IN2 Input to channel 2

4 GND Ground

5 DIAG Diagnostic mode switch. Normal mode is low

6 OUT2 Output of channel 2

7 OUT1 Output of channel 1

8 VCC Positive 5.0 volt supply input Device Package Shipping† CS1124YD8 SOIC−8 NB 96 Units / Rail CS1124YD8G SOIC−8 NB (Pb−Free)

96 Units / Rail

CS1124YDR8 SOIC−8 NB 96 Units / Rail CS1124YDR8G SOIC−8 NB (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. OUT1 To /C0109P VCC VCC VCC VCC VCC INP1 INAdj DIAG IN1 RRS VRS Variable Reluctance Sensor COMP1Active Clamp RAdj GND Figure 2. Application Diagram

http://onsemi.com THEORY OF OPERATION NORMAL OPERATION Figure 2 shows one channel of the CS1124 along with the necessary external components. Both channels share the INAdj pin as the negative input to a comparator. A brief description of the components is as follows: VRS − Ideal sinusoidal, ground referenced, sensor output − amplitude usually increases with frequency, depending on loading. RRS − Source impedance of sensor. R1/RAdj − External resistors for current limiting and biasing. INP1/INAdj − Internal current sources that determine trip points via R1/RAdj. COMP1 − Internal comparator with built−in hysteresis set at 160 mV . OUT1 − Output 0 V − 5.0 V square wave with the same frequency as VRS. By inspection, the voltage at the (+) and (−) terminals of COMP1 with VRS = 0V are: V+ /C0043INP1(R1 /C0041RRS) (1) V− /C0043INAdj /C0032RAdj (2) As VRS begins to rise and fall, it will be superimposed on the DC biased voltage at V+. V+ /C0043INP1(R1 /C0041RRS) /C0041VRS (3) To get comparator COMP1 to trip, the following condition is needed when crossing in the positive direction, V+ /C0117V− /C0041VHYS (4) (VHYS is the built−in hysteresis set to 160 mV), or when crossing in the negative direction, V+ /C0116V− /C0042VHYS (5) Combining equations 2, 3, and 4, we get: INP1(R1 /C0041RRS) /C0041VRS /C0117INAdj /C0032RAdj /C0041VHYS (6) therefore, VRS(+TRP) /C0116INAdj /C0032RAdj /C0042INP1(R1 /C0041RRS) /C0041VHYS (7) It should be evident that tripping on the negative side is: VRS(−TRP) /C0116INAdj /C0032RAdj /C0042INP1(R1 /C0041RRS) /C0042VHYS (8) In normal mode, INP1 /C0043INAdj (9) We can now re−write equation (7) as: VRS(+TR) /C0117INP1(RAdj /C0042R1 /C0042RRS) /C0041VHYS (10) By making RAdj /C0043R1 /C0041RRS (11) you can detect signals with as little amplitude as VHYS. A design example is given in the applications section. OPEN SENSOR PROTECTION The CS1124 has a DIAG pin that when pulled high (5.0 V), will increase the INAdj current source by roughly 50%. Equation (7) shows that a larger VRS(+TRP) voltage will be needed to trip comparator COMP1. However, if no V RS signal is present, then we can use equations 1, 2, and 4 (equation 5 does not apply in this mode) to get: INP1(R1 /C0041RRS) /C0117INP1 /C0032KI /C0032RAdj /C0041VHYS (12) Since RRS is the only unknown variable we can solve for RRS, RRS /C0043INP1 /C0032KI /C0032RAdj /C0041VHYS INP1 /C0042R1 (13) Equation (13) shows that if the output switches states when entering the diag mode with V RS = 0, the sensor impedance must be greater than the above calculated value. This can be very useful in diagnosing intermittent sensor. INPUT PROTECTION As shown in Figure 2, an active clamp is provided on each input to limit the voltage on the input pin and prevent substrate current injection. The clamp is specified to handle ±12 mA. This puts an upper limit on the amplitude of the sensor output. For example, if R1 = 20 k, then VRS(MAX) /C004320 k /C003212 mA /C0043240 V Therefore, the VRS(pk−pk) voltage can be as high as 480 V . The CS1124 will typically run at a frequency up to 1.8 MHz if the input signal does not activate the positive or negative input clamps. Frequency performance will be lower when the positive or negative clamps are active. Typical performance will be up to a frequency of 680 kHz with the clamps active.

22 k) (reference the diagram page 1). Figure 3. Minimum Threshold Operation Figure 4. Low−Side Clamp Figure 5. Low− and High−Side Clamps Figure 6. Diagnostic Operation

5.0 V/div

1.0 V/div

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APPLICATION INFORMATION

Referring to Figure 2, the following will be a design example given these system requirements: RRS /C00431.5 k/C0087(/C011712 k/C0087is considered open) VRS(MAX) /C0043120 Vpk VRS(MIN) /C0043250 mVpk FVRS /C004310 kHz @ VRS(MIN) /C004340 Vpk−pk 1. Determine tradeoff between R1 value and power rating. (use 1/2 watt package) PD /C0043 /C0466120 2/C0504/C04672 R1 /C01161/C03242W Set R1 = 15 k. (The clamp current will then be 120/15 k = 8.0 mA, which is less than the 12 mA limit.) 2. Determine RAdj Set RAdj as close to R1 + RRS as possible. Therefore, RAdj = 17 k. 3. Determine VRS(+TRP) using equation (7). VRS(+TRP) /C004311/C0109A /C003217 k /C004211/C0109A(15 k /C00411.5 k) /C0041160 m VRS(+TRP) /C0043166 mV typical (easily meets 250 mV minimum) 4. Calculate worst case VRS(+TRP) Examination of equation (7) and the spec reveals the worst case trip voltage will occur when: VHYS = 180 mV INAdj = 16 /C0109A INP1 = 15 /C0109A R1 = 14.25 k (5% low) RAdj = 17.85 k (5% High) VRS(+)MAX /C004316 /C0109A(17.85 k) /C004215/C0109A(14.25 k /C00411.5 k) /C0041180 mV /C0043229 mV which is still less than the 250 mV minimum amplitude of the input. 5. Calculate C1 for low pass filtering Since the sensor guarantees 40 Vpk−pk @ 10 kHz, a low pass filter using R1 and C1 can be used to eliminate high frequency noise without affecting system performance. Gain Reduction /C00430.29 V 20 V /C00430.0145 /C0043/C004236.7 dB Therefore, a cut−off frequency, f C, of 145 Hz could be used. C1 /C01181 2/C0112fCR1 /C01180.07 /C0109F Set C1 = 0.047 /C0109F. 6. Calculate the minimum RRS that will be indicated as an open circuit. (DIAG = 5.0 V) Rearranging equation (7) gives RRS /C0043 /C0426 VHYS /C0041[INP1 /C0032KI /C0032RAdj] /C0042VRS(+TRP) /C0427 INP1 /C0042R1 But, VRS = 0 during this test, so it drops out. Using the following as worst case Low and High: Worst Case Low (RRS) Worst Case High (RRS) RAdj 16.15 k 17.85 k VHYS 135 mV 185 mV INP1 16 /C0109A 6.0 /C0109A R1 15.75 k 14.25 k KI 1.57 1.53 RRS /C0043135 mV /C004123.6 /C0109A /C003216.15 k 16 /C0109A /C004215.75 k /C004316.5 k Therefore, RRS(MIN) /C004316.5 k (meets 12 k system spec) and, RRS(MAX) /C0043185 mV /C004110.7 /C0109A /C003217.85 k 6.0/C0109A /C004214.25 k /C004348.4 k

http://onsemi.com PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AG SEATING PLANE N J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A B S DH C 0.10 (0.004) DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −X− −Y− G MYM0.25 (0.010) −Z− YM0.25 (0.010) Z S X S M /C0095/C0095/C0095/C0095 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 /C0466mm inches/C0467SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* PACKAGE THERMAL DATA Parameter SOIC−8NB Unit R/C0113JC Typical 45 °C/W R/C0113JA Typical 165 °C/W

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