CS1112 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- 4.0 MHz Serial Input Bus
- Parallel Input Control
- 1.0 Ω DMOS Drivers (typ)
- Power On Reset
- Internal Flyback Clamps
- Status Output
- Fault Protection – 46 V Peak Transient – Power Limiting – Undervoltage – Overvoltage
- Fault Reporting – Open Load – Short Circuit
- 8 Internally Fused Leads http://onsemi.com A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week PIN CONNECTIONS AND MARKING DIAGRAM Device Package Shipping
ORDERING INFORMATION
CS1112YDWF24 SO–24L 31 Units/Rail CS1112YDWFR24 SO–24L 1000 Tape & Reel VDD VPWR OUT0 IN0 GND GND GND GND IN1 OUT1 SI CSB R OSC STATUS IN3 GND GND GND GND IN2 OUT2 SO SCLK OUT3 SO–24L DW SUFFIX CASE 751E 1 24 CS1112 AWLYYWW
http://onsemi.com APPLICATION DIAGRAM R OSC Micro Controller with Bus CMOS Serial Shift Registers and Latches DMOS Low Side Switches and Protection Circuitry Fault Reporting Bias QPOD R OSC SO SCLK SI CSB IN1 IN2 IN3 IN4 VDD VPWR VDD Status 10 kΩ 82 kΩ GND ABSOLUTE MAXIMUM RATINGS* Rating Value Unit DC Supply (VPWR ) –0.3 to 30 V Output DC Voltage (Out 0, 1, 2, 3) 46 V VDD Supply Voltage –0.3 to +7.0 V Peak Transient (1.0 ms rise time, 300 ms period, 32 V Load Dump @ 14 V VPWR ) 46 V Digital Input Voltage –0.3 to VDD + 0.3 V Single Pulse Avalanche Energy (I = 450 mA)(Out 0, 1, 2, 3) 50 mJ Operating Junction Temperature, TJ –40 to 150 °C ESD Capability (Human Body Model) 1.5 kV Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1.) 230 peak °C 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.
http://onsemi.com ELECTRICAL CHARACTERISTICS (9.0 V < VPWR < 17 V, 4.5 V < VDD < 5.5 V, –40°C < TJ < 125°C, 5.5 V < VPWR < 25 V, (Outputs Functional); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Supply Voltages and Currents VDD Power On Reset Threshold Outputs Latched Off By Event 2.5 3.0 3.5 V VDD Power On Reset Hysteresis – – 200 – mV VPWR Undervoltage Outputs Latched Off By Event 4.0 4.5 5.0 V VPWR Overvoltage Lockout Outputs Latched Off By Event 30 35 45 V Digital Supply Current, IV(DD) All Outputs On (@ 350 mA) – – 5.0 mA Analog Supply Current, IV(PWR) All Outputs On (@ 350 mA) – – 5.0 mA Sleep Current, IV(PWR) VDD ≤ 0.5 V – – 10 µA Digital Inputs and Outputs VIN High SI, SCLK, CSB, IN0, IN1, IN2, IN3 70 – – %V DD VIN Low SI, SCLK, CSB, IN0, IN1, IN2, IN3 – – 30 %V DD VIN Hysteresis – – 230 – mV Input Pulldown Current SI, IN0, IN1, IN2, IN3, VIN = 30% VDD – – 25 µA Input Pullup Current CSB, VIN = 70% VDD – – –25 µA Status Low ISTATUS = 0.5 mA – 0.1 0.5 V Fault Detection/Timing Overcurrent Sense Time, tSS Overcurrent Sense Time, ROSC = 82 kΩ 25 62.5 100 µs Overcurrent Shutdown Time Overcurrent Shutdown Time, ROSC = 82 kΩ 1.60 3.94 6.3 ms Fault Duty Cycle After the first fault cycle, Note 1. 1.4 1.56 1.7 % Open Load Trip Point IN = Low 40 50 60 %V DD Open Load Sense Time Open Load Sense Time, ROSC = 82 kΩ 12.5 – 100 µs Power Outputs VDRAIN Clamp ID = 20 mA, tCLAMP = 100 µs 48 52 64 V Drain Leakage Current VDRAIN = 17 V – – 25 µA Drain Leakage Current VDRAIN = 46 V – – 400 µA R DS(ON) VPWR = 13 V, ID = 0.5 A – 1.0 2.0 Ω Current Limit Note 2. 3.0 4.5 6.0 A Reverse Diode Drop Reverse Diode Drop I = 350 mA – – 1.4 V Fall Time Delay, tphl VPWR = 13 V, RLOAD = 33 Ω , Note 3. (see Figure 2) – – 10 µs Rise Time Delay, tplh VPWR = 13 V, RLOAD = 33 Ω, Note 3. (see Figure 2) – – 15 µs Rise Time, tr VPWR = 13 V, RLOAD = 33 Ω 0.4 – 10 µs Fall Time, tf VPWR = 13 V, RLOAD = 33 Ω 0.4 – 10 µs 1. Guaranteed by design. 2. A duty cycle mode will initiate at a minimum of 1.0 A and before the current limit. 3. Output turn on delay and turn off delay from rising edge of CSB to the output reaching 50% of V PWR .
http://onsemi.com ELECTRICAL CHARACTERISTICS (continued) (9.0 V < VPWR < 17 V, 4.5 V < VDD < 5.5 V, –40°C < TJ < 125°C, 5.5 V < VPWR < 25 V, (Outputs Functional); unless otherwise specified.) Characteristic UnitMaxTypMinTest Conditions Serial Peripheral Interface VPWR = 14 V SCLK Clock Period C O = 200 pF 250 – – ns MAX Input Capacitance SI, SCLK, Note 1. – – 12 pF VOUT High SO, IOH = 1.0 mA VDD – 1.0 – – V VOUT Low SO, IOL = 1.0 mA – – 0.5 V SCLK High Time FSCLK = 4.0 MHz, SCLK = 2.0 V to 2.0 V (see Figure 1) 125 – – ns SCLK Low Time FSCLK = 4.0 MHz, SCLK = 0.8 V to 0.8 V (see Figure 1) 125 – – ns SI Setup Time SI = 0.8 V/2.0 V to SCLK = 2.0 V at 4.0 MHz; Note 1. (see Figure 1) 25 – – ns SI Hold Time SCLK = 2.0 V to SI = 0.8 V/2.0 V at 4.0 MHz; Note 1. (see Figure 1) 25 – – ns SO Rise Time C LD = 200 pF (0.1 VDD to 0.9 VDD ); Note 1. – 25 50 ns SO Fall Time C LD = 200 pF (0.9 VDD to 0.1 VDD ); Note 1. – – 50 ns CSB Setup Time CSB = 0.8 V to SCLK = 2.0 V (see Figure 1) Note 1. 60 – – ns CSB Hold Time SCLK = 0.8 V to CSB = 2.0 V (see Figure 1) Note 1. 75 – – ns SO Delay Time SCLK = 0.8 V to SO Data Valid, VDD = 5.0 V C LD = 200 pF at 4.0 MHz (see Figure 1); Note 1. – 65 125 ns Xfer Delay Time CSB rising edge to next falling edge. Note 1. 1.0 – – µs 1. Guaranteed by design. PACKAGE PIN DESCRIPTION PACKAGE PIN #
24 Lead SOIC PIN SYMBOL FUNCTION
1 VDD Input voltage to bias logic and control circuitry. 2 VPWR Input voltage to bias gate drive circuitry. 3 OUT0 Open drain output one. 4 IN0 Parallel input one. 5, 6, 7, 8 17, 18, 19, 20 GND Ground Reference. 9 IN1 Parallel input two. 10 OUT1 Open drain output two. 11 SI SPI serial input. 12 CSB SPI active low chip select. 13 SCLK SPI clock input. 14 SO SPI serial output.
15 OUT2 Open drain output three. 16 IN2 Parallel input three. 22 OUT3 Open drain output four.
23 STATUS Open drain output, which is asserted when an open load or
overcurrent condition occurs at any of the outputs.
24 R OSC 82 kΩ resistor tied to ground to set up accurate internal cur-
the SPI input and the parallel inputs. IN0, IN1, IN2, or IN3 are asserted high (< 70% VDD ). Table 1. SPI Inputs X = Don’t Care; MSB is Transferred first.
http://onsemi.com FAULT MODE OPERATION The CS1112 provides protection for a multitude of system faults and conditions. These include Overvoltage, Current Limit, Open Circuit, Output Short to Power, Output Short to Ground, and Flyback Clamp. Overvoltage The IC is constantly monitoring the voltage on the VPWR pin. If the voltage on this pin exceeds the Overvoltage Shutdown Threshold (typically 35 V), all outputs immediately turn off. The programmed outputs (via serial or parallel input) turn back on once the voltage is brought back down below this level. Current Limit/Short to VBATT When the output current exceeds the Overcurrent (4.5 A typical) for the Short Circuit/Overcurrent Sense Time (typically 62.5 µs) as it would do during an output short to V BATT , its fault status bit will be latched to a logic one. The fault status bit remains latched until the rising edge of CSB. The output will go into a low duty cycle mode (typically 1.56%) as long as the overcurrent condition exists, and the channel is on. This protects the integrated circuit from damaging itself due to its thermal limits. Open Circuit/Short to Ground Open circuit conditions are detected while the outputs are off. A fault bit is set when the Open Load “Off” Detection V oltage (typically 0.5 × V DD ) is present for the Open Load “Off” Sense Time (typically 62.5 µs) as it would do during an output short to ground. Flyback Clamp While the flyback clamp is not a fault mode, it is a protection feature of the CS1112. When driving inductive loads, it is normal to observe high voltage spikes on the output pin due to the stored energy in the windings when the device is turned off. On–chip clamps on the outputs limit the voltage amplitude on the pin to prevent damage to the device. Each output has an Output Clamp which limits the output voltage to 52 V (typical when measured at 20 mA for 100 µs). PIN FUNCTION DESCRIPTION SI The SI (Serial Input) receives serial 8–bit or 16–bit words sent most significant bit first. Data is clocked in on the rising edge of SCLK. An internal active pull–down is connected to this input. CMOS logic levels are required on this pin. SO The SO (Serial Output) can be connected to the serial data input pin of the microprocessor, or it can be daisy–chained to the serial input (SI) of another SPI compatible device. This pin is tri–stated unless a low CSB pin selects the device. The signal on this pin is clocked from the falling edge of the SCLK pin. The serial output data provides fault information for each output and returns most significant bit (bit 7) first. Bits 0 through 3 are output fault bits for outputs 0 through 3, respectively. In 8–bit SPI mode, bits 0–3, under normal conditions return all zeros representing no faults. A 1 indicates a fault. The output from this pin conforms to CMOS logic levels. R OSC An 82 kΩ resistor tied to ground sets up an accurate internal current source. CSB The CSB (Chip Select Bar) is the select pin when the microprocessor wants to communicate with the CS1112. A low on this pin enables the SPI communication with the device and enables the SO pin. After the digital word is clocked into the IC, a transition from low to high on the CSB pin translates the last 4 bits of information turning the outputs on or off. An internal active pull–up is connected to this input. CMOS logic levels are required on this pin. SCLK The SCLK (Serial Clock) clocks the internal shift registers. This pin controls the data being shifted into the SI pin, and data being shifted out of the SO pin. CMOS logic levels are required on this pin. IN0, IN1, IN2, IN3 These pins control their corresponding numbered output. These are the parallel input pins which may be used to PWM the outputs. They have 230 mV of hysteresis. These inputs are OR’d with their corresponding input bit in the serial control byte. An internal active pull–down is connected to these pins. CMOS logic levels are required on these pins. OUT0, OUT1, OUT2, OUT3 These pins are the output low–side driver pins. They all have typically 1.0 Ω RDS(ON) at VPWR = 13 V . Current limit on these pins has a minimum specification of 3.0 A. A low duty cycle mode (1.5% typ.) will initiate at a minimum of 1A and before the current limit. VPWR 14 V Battery voltage input. 5.0 mA (max) is needed. VDD 5.0 V Supply input. 5.0 mA (max) is needed. STATUS Open drain output. This pin goes low when an open load or overcurrent condition occurs on any of the outputs. This provides immediate notification to the controller that a fault is present. The controller can subsequently query the device (serially) to determine its origin.
http://onsemi.com PACKAGE DIMENSIONS SO–24L DW SUFFIX CASE 751E–04 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– –B– P12X D24X 1324 M0.010 (0.25) B M SAM0.010 (0.25) B ST –T– G22X SEATING PLANE K C R X 45 M F J DIM MIN MAX MIN MAX INCHESMILLIMETERS A 15.25 15.54 0.601 0.612 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.41 0.90 0.016 0.035 G 1.27 BSC 0.050 BSC J 0.23 0.32 0.009 0.013 K 0.13 0.29 0.005 0.011 M 0 8 0 8 P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 PACKAGE THERMAL DATA Parameter SO–24L Unit R Θ JC Typical 9 °C/W R Θ JA Typical 55 °C/W
http://onsemi.com Notes
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