CR8F612X STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 89
Technical content
Datasheet sections
- 1 Introduction
- 2 Description
- 3 Block diagram
- 4 Product overview
- 4.1 Central processing unit CR8F
- 4.2 Single wire interface module (SWIM) and debug module (DM)
- 4.3 Interrupt controller
- 4.4 Flash program and data EEPROM memory
- 4.5 Clock controller
- 4.6 Power management
- 4.7 Watchdog timers
- 4.8 Auto wakeup counter
- 4.9 Beeper
- 4.10 TIM1 - 16-bit advanced control timer
- 4.11 TIM5 - 16-bit general purpose timer
- 4.12 TIM6 - 8-bit basic timer
- 4.13 Analog-to-digital converter (ADC1)
- 4.14 Communication interfaces
- 4.14.1 UART1
- 4.14.2 SPI
- 5 Pinout and pin description
- 5.1 Alternate function remapping
- 6 Interrupt vector mapping
- 7 Option bytes
- 8 Memory and register map
Datasheet sections
- 12.2 Software tools
- 12.2.1 CR8F toolset
- 12.2.2 C and assembly toolchains
- 12.3 Programming tools
- 13 Revision history
Features
16 MHz advanced CR8F core with Harvard
architecture and 3-stage pipeline Extended instruction set Memories Program memory: 8 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles Data memory: 640 bytes true data EEPROM; endurance 300 kcycles RAM: 1 Kbytes Clock, reset and supply management 2.95 to 5.5 V operating voltage Flexible clock control, 4 master clock sources: – Low power crystal resonator oscillator – External clock input – Internal, user-trimmable 16 MHz RC – Internal low power 128 kHz RC Clock security system with clock monitor Power management: – Low power modes (wait, active-halt, halt) – Switch-off peripheral clocks individually Permanently active, low consumption power- on and power-down reset Interrupt management Nested interrupt controller with 32 interrupts Up to 28 external interrupts on 7 vectors Timers Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization 16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM) 8-bit basic timer with 8-bit prescaler Auto wake-up timer 2 watchdog timers: Window watchdog and independent watchdog Communications interfaces UART with clock output for synchronous operation, Smartcard, IrDA, LIN master mode SPI interface up to 8 Mbit/s I C interface up to 400 Kbit/s Analog to digital converter (ADC) 10-bit,
1 LSB ADC with up to 7 multiplexed
channels + 1 internal channel, scan mode and analog watchdog I/Os Up to 28 I/Os on a 32-pin package including 21 high sink outputs Highly robust I/O design, immune against current injection Development support – Embedded single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging LQFP32 7x7 VFQFPN32 5x5
9.3.9 I
Table 19. Total current consumption with code execution in run mode at V Table 20. Total current consumption with code execution in run mode at V Table 21. Total current consumption in wait mode at V Table 22. Total current consumption in wait mode at V Table 23. Total current consumption in active halt mode at V Table 24. Total current consumption in active halt mode at V Table 25. Total current consumption in halt mode at V Table 26. Total current consumption in halt mode at V Table 42. I Table 44. ADC accuracy with R Table 45. ADC accuracy with R
1 Introduction
This datasheet contains the description of the CR8F612X features, pinout, electrical characteristics, mechanical data and ordering information. For complete information on the CR8F microcontroller memory, registers and peripherals, please refer to the CR8F microcontroller family reference manual (RM0016). For information on programming, erasing and protection of the internal Flash memory please refer to the CR8F Flash programming manual (PM0051). For information on the debug and SWIM (single wire interface module) refer to the CR8F SWIM communication protocol and debug module user manual (UM0470). For information on the CR8F core, please refer to the CR8F CPU programming manual (PM0044).
2 Description
Table 1. CR8F612X access line features
- Including 21 high sink outputs
- No read-while-write (RWW) capability
10 CR8F6122
3 Block diagram
Figure 1. Block diagram
8 Mbit/s
8 Kbytes
1 Kbytes
4 CAPCOM
400 Kbit/s
3 CAPCOM
The 8-bit CR8F core is designed for code efficiency and performance.
4.1 Central processing unit CR8F
4 Product overview
The following section intends to give an overview of the basic features of the CR8F612X functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers Harvard architecture 3-stage pipeline 32-bit wide program memory bus - single cycle fetching for most instructions X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-Mbyte linear memory space 16-bit stack pointer - access to a 64 K-level stack 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing 20 addressing modes Indexed indirect addressing mode for look-up tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2-byte average instruction size Standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division Bit manipulation Data transfer between stack and accumulator (push/pop) with direct stack access Data transfer using the X and Y registers or direct memory-to-memory transfers
4.2 Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in- circuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real- time by means of shadow registers. R/W to RAM and peripheral registers in real-time R/W access to all resources by stalling the CPU Breakpoints on all program-memory instructions (software breakpoints) Two advanced breakpoints, 23 predefined configurations
4.3 Interrupt controller
Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 28 external interrupts on 7 vectors including TLI Trap and reset interrupts
4.4 Flash program and data EEPROM memory
8 Kbytes of Flash program single voltage Flash memory
unintentional overwriting of memory that could result from a user software malfunction. data EEPROM and option bytes. EEPROM, modify the contents of main program memory or the device option bytes. memory known as UBC (user boot code). Refer to Figure 2. of 1 page (64-byte block) by programming the UBC option byte in ICP mode. IAP and communication routines. Figure 2. Flash memory organisation
Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.
4.5 Clock controller
The clock controller distributes the system clock (f MASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. Master clock sources: Four different clock sources can be used to drive the master clock: – 1-16 MHz high-speed external crystal (HSE) – Up to 16 MHz high-speed user-external clock (HSE user-ext) – 16 MHz high-speed intern al RC oscillator (HSI) – 128 kHz low-speed internal RC (LSI) Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated. Configurable main clock output (CCO): This outputs an external clock for use by the application. Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
4.6 Power management
For efficent power management, the application can be put in one of four different low-power modes. Y ou can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.
4.7 Watchdog timers
The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms. 2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.
Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 µs to 1 s.
4.8 Auto wakeup counter
Used for auto wakeup from active halt mode Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.
4.10 TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver 16-bit up, down and up/down autoreload counter with 16-bit prescaler Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output Synchronization module to control the timer with external signals or to synchronize with TIM5 or TIM6 Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11 TIM5 - 16-bit general purpose timer
16-bit autoreload (AR) up-counter 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768 3 individually configurable capture/compare channels PWM mode Interrupt sources: 3 x input capture/output compare, 1 x overflow/update Synchronization module to control the timer with external signals or to synchronize with TIM1 or TIM6
4.12 TIM6 - 8-bit basic timer
4.13 Analog-to-digital converter (ADC1)
4.14 Communication interfaces
Table 3. TIM timer features
4.14.1 UART1
One Mbit/s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication (UART mode) Full duplex communication - NRZ standard format (mark/space) Programmable transmit and receive baud rates up to 1 Mbit/s (f CPU /16) and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt) Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers SPI master operation 8-bit data communication Maximum speed: 1 Mbit/s at 16 MHz (f CPU /16) LIN master mode Emission: Generates 13-bit synch break frame Reception: Detects 11-bit break frame
4.14.2 SPI
Maximum speed: 8 Mbit/s (f MASTER /2) both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation - selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave/master selection input pin
4.14.3 I C I C master features: – Clock generation – Start and stop generation I C slave features: – Programmable I C address detection – Stop bit detection Generation and detection of 7-bit/10-bit addressing and general call Supports different communication speeds: – Standard speed (up to 100 kHz) – Fast speed (up to 400 kHz)
5 Pinout and pin description
Figure 3. CR8F612X VFQFPN32/LQFP32 pinout
- (HS) high sink capability.
- (T) True open drain (P-buffer and protection diode to V
- [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the
Reset state is shown in bold. Table 4. Legend/abbreviations Table 5. VFQFPN32/LQFP32 pin description
2 PD7/TLI [TIM1_CH4] I/O
1 PD6/AIN6/UART1_RX I/O
3 NRST I/O X Reset
4 PA1/OSCIN
5 PA2/OSCOUT I/O X XX O 1X X Port A2 Resonator/crystal
9 PA3/TIM5_CH3
10 PF4 [UART1_RX] I/O X XO 1 X X Port F4
Table 5. VFQFPN32/LQFP32 pin description (continued)
13 PB5/I2C_SDA
14 PB4/I2C_SCL
15 PB3/AIN3/TIM1_ETR I/O X XX H S O 3X X Port B3
16 PB2/AIN2/TIM1_CH3N I/O X XX H S O 3X X Port B2
17 PB1/AIN1/TIM1_CH2N I/O X XX H S O 3X X Port B1
18 PB0/AIN0/TIM1_CH1N I/O X XX H S O 3X X Port B0
11 PB7 I/O X XX O 1X X Port B7
12 PB6 I/O X XX O 1X X Port B6
21 PC2/TIM1_CH2
22 PC3/TIM1_CH3 [TLI]
24 PC5/SPI_SCK
25 PC6/SPI_MOSI
26 PC7/SPI_MISO
27 PD0/TIM1_BKIN
28 PD1/SWIM I/O X X XH S O 4 X X Port D1 SWIM data
29 PD2 [AIN3] [TIM5_CH3] I/O X XX H S O 3X X Port D2
30 PD3/AIN4/TIM5_CH2/
- I/O pins used simultaneously for high cu rrent source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings ( see Table 15: Current characteristics.
- When the MCU is in Halt/Active-halt mode, PA1 is automatica lly configured in input weak pull up and cannot be used for
if Halt/Active-halt is used in the application.
- In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V
31 PD4/TIM5_CH1/BEEP
32 PD5/AIN5/UART1_TX I/O X XX H S O 3X X Port D5
UART1_RX/AIN6/(HS)PD6 NRST OSCIN/PA1 OSCOUT/PA2 VCAP VDD PD5(HS)/AIN5/UART1_TX PD1(HS)/SWIM PC2(HS)/TIM1_CH2 PC1(HS)/TIM1_CH1/UART1_CK PB0(HS)/AIN0/CH1N_TIM1 PB1(HS)/AIN1/CH2N_TIM1 PB2(HS)/AIN2/CH3N_TIM1 CR8F6122B/M 4Figure6 Option bytes CR8F612X 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to V DD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). CR8F6123 Figure 7 0 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to V DD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).
5.1 Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 7: Option bytes. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). OSCIN/PA1 NRST VSS VDD VCAP OSCOUT/PA2 PD1(HS)/SWIM UART1-RX/AIN6/(HS)PD6 TIM5_CH3/(HS)PA3 I2C_SDA/(T)PB5 I2C_SCL/(T)PB4 PC3(HS)/TIM1_CH3 PC4(HS)/TIM1_CH4/CLK_CC0 PC5(HS)/SPI_SCK PC6(HS)/SPI_MOSI PC7(HS)/SPI_MIS0 PD2(HS) PD3(HS)/AIN4/TIM5_CH2/ADC_ETR PD4(HS)BEEP/TIM5_CH1 PD5 (HS)/AIN5/UART1_TX SOP 2
6 Interrupt vector mapping
Table 6. Interrupt mapping
0 TLI External top level Interrupt - - 0x00 8008
1 AWU Auto wake up from halt - Y es 0x00 800C
2 CLK Clock controller - - 0x00 8010
3 EXTI0 Port A external interrupts Y es
4 EXTI1 Port B external interrupts Y es Y es 0x00 8018
5 EXTI2 Port C external interrupts Y es Y es 0x00 801C
6 EXTI3 Port D external interrupts Y es Y es 0x00 8020
7 EXTI4 Port E external interrupts Y es Y es 0x00 8024
8 EXTI5 Port F interrupt Y es Y es 0x00 8028
9 Reserved - - 0x00 802C
10 SPI End of transfer Y es Y es 0x00 8030
11 TIM1 TIM1 update/overflow/underflow/
12 TIM1 TIM1 capture/compare - - 0x00 8038
13 TIM5 TIM5 update /overflow/trigger - - 0x00 803C
14 TIM5 TIM5 capture/compare - - 0x00 8040
15 Reserved - - 0x00 8044
16 Reserved - - 0x00 8048
17 UART1 Tx complete - - 0x00 804C
18 UART1 Receive register DATA FULL - - 0x00 8050
20 Reserved - - 0x00 8058
21 Reserved - - 0x00 805C
22 ADC1 ADC1 end of conversion/analog
23 TIM6 TIM6 update/overflow/trigger - - 0x00 8064
24 Flash EOP/WR_PG_DIS - - 0x00 8068
7 Option bytes
(OPTx) and a complemented one (NOPTx) for redundancy. shown in Table 7: Option bytes below. ROP option that can only be modified in ICP mode (via SWIM). Table 7. Option bytes
Table 8. Option byte description Flash/EEPROM memory readout protection for details. 1 contain the interrupt vectors. write protection for more details. decriptions of bits [7:2] and [1:0] respectively.
Table 9. CR8F612X alternate function remapping bits [7:2]
- Do not use more than one remapping option in the same port.
1: Port D7 alternate function = TIM1_CH4. 1: Port D0 alternate function = CLK_CCO. 1: Port C3 alternate function = TLI. port D4 alternate function = UART1_CK.
- Refer to pinout description.
Table 8. Option byte description (continued)
Table 10. CR8F612X alternate function remapping bits [1:0]
00 AFR1 and AFR0 remapping options inactive:
- Refer to pinout description.
8 Memory and register map
8.1 Memory map
Figure 4. Memory map
8.2 Register map
Table 11. I/O port hardware register map
Table 12. General hardware register map
Table 12. General hardware register map (continued)
Table 13. CPU/SWIM/debug module/interrupt controller registers
- Accessible by debug module only
Table 13. CPU/SWIM/debug module/interrupt controller registers (continued)
9 Electrical characteristics
9.1 Parameter conditions
9.1.1 Minimum and maximum values
the selected temperature range). mean value plus or minus three times the standard deviation (mean ± 3 Σ).
9.1.2 Typical values
only as design guidelines and are not tested.
9.1.3 Typical curves
9.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 5. Figure 5. Pin loading conditions
9.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 6. Figure 6. Pin input voltage
9.2 Absolute maximum ratings
Table 14. Voltage characteristics
Table 15. Current characteristics
- Data based on characterization results, not tested in production.
) pins must always be connected to the external supply.
- Negative injection disturbs the analog performance of the device. See note in
- When several inputs are submitted to a current injection, the maximum
maximum current injection on four I/O port pins of the device. Table 16. Thermal characteristics
9.3 Operating conditions
Figure 7. f Table 17. General operating conditions
- Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on
1 MHz 470 3300 nF
Jmax is given by the test limit. Above this value the product behavior is not guaranteed.
9.3.1 VCAP external capacitor
Figure 8. External capacitor C
- ESR is the equivalent series resistance and ESL is the equivalent inductance.
Table 18. Operating conditions at power-up/power-down
- Reset is always generated after a t
9.3.2 Supply current characteristics
The current consumption is measured as described in Figure 6 on page 42.
16 MHz
- Data based on characterization results, not tested in production.
- Default clock configuration measured with all peripherals off.
- Data based on characterization results, not tested in production.
- Default clock configuration measured with all peripherals off.
- Data based on characterization results, not tested in production.
- Default clock configuration measured with all peripherals off.
- Data based on characterization results, not tested in production.
- Default clock configuration measured with all peripherals off.
- Data based on characterization results, not tested in production
- Configured by the REGAH bit in the CLK_ICKR register.
- Configured by the AHALT bit in the FLASH_CR1 register.
- Data based on characterization results, not tested in production
- Configured by the REGAH bit in the CLK_ICKR register.
- Configured by the AHALT bit in the FLASH_CR1 register.
- Data based on characterization results, not tested in production
- Data based on characterization results, not tested in production
Table 27. Wakeup times
- Data guaranteed by design, not tested in production.
- Measured from interrupt event to interrupt vector fetch.
- Configured by the REGAH bit in the CLK_ICKR register.
- Configured by the AHALT bit in the FLASH_CR1 register.
- Plus 1 LSI clock depending on synchronization.
Table 28. Total current consumption and timing in forced reset state
- Data guaranteed by design, not tested in production.
- Characterized with all I/Os tied to V
Table 29. Peripheral current consumption
- Data based on a differential I
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
- Data based on a differential I
- Data based on a differential I
conversions. Not tested in production.
Figure 14. Typ I
9.3.3 External clock sources and timing characteristics
Figure 15. HSE external clock source (frequency, package, accuracy...). Table 30. HSE user external clock characteristics
- Data based on characterization results, not tested in production.
Figure 16. HSE oscillator circuit diagram Table 31. HSE oscillator characteristics
- C is approximately equivalent to 2 x crystal Cload.
- The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R
- Data based on characterization results, not tested in production.
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
9.3.4 Internal clock sources and timing characteristics
Figure 17. Typical HSI accuracy at V Table 32. HSI oscillator characteristics
- Refer to application note.
- Data based on characterization results, not tested in production
- Subject to further characteri zation to give better results
- Guaranteeed by design, not tested in production.
9.3.5 Memory characteristics
Table 34. RAM and hardware registers
- Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design, not tested in production. Table 35. Flash program memory/data EEPROM memory
- Data based on characterization results, not tested in production.
- The physical granularity of the memory is 4 byte s, so cycling is performed on 4 bytes even when a
write/erase operation addresses a single byte.
9.3.6 I/O port pin characteristics
an external pull-up or pull-down resistor. Table 36. I/O static characteristics
- Hysteresis voltage between Schmitt trigger switching levels . Based on characterization results, not tested in production.
Figure 23. Typ. V Table 37. Output driving current (standard ports)
- Data based on characterization results, not tested in production
Table 38. Output driving current (true open drain ports)
- Data based on characterization results, not tested in production
Table 39. Output driving current (high sink ports)
- Data based on characterization results, not tested in production
9.3.7 Reset pin characteristics
Figure 33. Typical NRST V Figure 34. Typical NRST pull-up resistance vs V Table 40. NRST pin characteristics
- Data based on characterization results, not tested in production.
- Data guaranteed by design, not tested in production.
9.3.8 SPI serial peripheral interface
Table 41. SPI characteristics
- Parameters are given by se lecting 10 MHz I/O output frequency.
- Data characterization in progress.
- Values based on design simulation and/or charac terization results, and not tested in production.
- Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
- Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Figure 39. SPI timing diagram - master mode
- Measurement points are done at CMOS levels: 0.3V
- The maximum hold time of the start condition has only to be met if the interface does not stretch the low
- The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
Table 43. ADC characteristics
- During the sample time the input capacitance C
- Data characterization in progress.
- ADC accuracy vs. negative injection current: Injecti ng negative current on any of the analog input pins
does not affect the ADC accuracy.
- Data characterization in progress.
9.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization. with the IEC 1000-4-4 standard. table below based on the EMS levels and classes defined in application note AN1709. performance is highly dependent on the user application and the software in particular. prequalification tests in relation with the EMC level requested for his application. to prevent unrecoverable errors occurring (see application note AN1015). Table 46. EMS data
norm SAE J 1752/3 which specifies the board and the loading of each pin. more details, refer to the application note AN1181. standard. For more details, refer to the application note AN1181. Table 47. EMI data
16 MHz/
8 MHz
130 MHz to 1 GHz 5 7
- Data based on characterization results, not tested in production.
Table 48. ESD absolute maximum ratings
- Data based on characterization results, not tested in production
Table 49. Electrical sensitivities
- Class description: A Class is an STMicroelectronics inte rnal specification. All its limits are higher than the
class strictly covers all the JEDEC criteria (international standard).
To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark.
10.1 Package mechanical data
10.1.1 LQFP package mechanical data
Figure 42. 32-pin low profile quad flat package (7 x 7) Table 50. 32-pin low profile quad flat package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits
10.1.2 VFQFPN package mechanical data
Figure 43. 32-lead very thin fine pitch quad flat no-lead package (5 x 5) Table 51. 32-lead very thin fine pitch quad flat no-lead package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
10.2 Thermal characteristics
Table 17: General operating conditions on page 44.
10.2.1 Reference document
convection (still air). Available from www.jedec.org. Table 52. Thermal characteristics
- Thermal resistances are based on JEDEC JESD51- 2 with 4-layer PCB in a natural convection
10.2.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see Section 11: Ordering information on page 84). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: Maximum ambient temperature T Amax = 75 °C (measured according to JESD51-2) I DDmax = 8 mA, V DD = 5 V Maximum 20 I/Os used at the same time in output at low level with I OL = 8 mA, V OL = 0.4 V P INTmax = 8 mA x 5 V = 400 mW P IOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: P INTmax = 400 mW and P IOmax 64 mW: P Dmax = 400 mW + 64 mW Thus: P Dmax = 464 mW Using the values obtained in Table 52: Thermal characteristics on page 82, T Jmax is calculated as follows for LQFP32 59°C/W: T Jmax This is within the range of the suffix 6 version parts (-40 < T J < 105° C). In this case, parts must be ordered at least with the temperature range suffix 6.
CR8F612X CR8F development tools Doc ID 15590 Rev 1 85/88
12 CR8F development tools
Development tools for the CR8F microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the CR8F is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.
12.1 Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, CR8F application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of CR8F microcontrollers via the CR8F single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers. STice key features Occurrence and time profiling and code coverage (new features) Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read/write on the fly of memory during emulation In-circuit debugging/programming via SWIM protocol 8-bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1.62 to 5.5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for CR8F.
12.2.1 CR8F toolset
CR8F development tools CR8F612X 86/88 Doc ID 15590 Rev 1
12.2 Software tools
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for CR8F, which are available in a free version that outputs up to 16 Kbytes of code. CR8F toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST visual develop – Full-featured integrated development environment from ST, featuring Seamless integration of C and ASM toolsets Full-featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST visual programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of your CR8F microcontroller’s Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.
12.2.2 C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include: Cosmic C compiler for CR8F – Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com. Raisonance C compiler for CR8F – Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.raisonance.com.
- CR8F assembler linker – Free assembly toolchain included in the STVD toolset, which allows you to assemble and link your application source code.
12.3 Programming tools
During the development cycle, STice provides in-circuit programming of the CR8F Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your CR8F. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the CR8F fa mily. CR8F development tools are supported by a complete, free software package from
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