CR14 STMICROELECTRONICS | Alldatasheet
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Technical content
Datasheet sections
- 1 Summary description
- 2 Signal description
- 2.1 Oscillator (OSC1, OSC2)
- 2.2 Antenna Output Driver (RFOUT )
- 2.3 Antenna Input Filter (RFIN)
- 2.4 Transmitter Reference Voltage (VREF )
- 2.5 Serial Clock (SCL)
- 2.6 Serial Data (SDA)
- 2.7 Chip Enable (E0, E1, E2)
- 2.8 Power Supply (V
- 3 CR14 registers
- 3.1 Parameter Register (00h)
- 3.2 Input/Output Frame Register (01h)
- 3.3 Slot Marker Register (03h)
- 4 CR14 I²C protocol description
- 4.1 I²C Start Condition
- 4.2 I²C Stop Condition
- 4.3 I²C Acknowledge Bit (ACK)
- 4.4 I²C Data Input
- 4.5 I²C Memory Addressing
- 4.6 CR14 I²C Write Operations
- 4.7 CR14 I²C Read Operations
- 5 Applying the I²C protocol to the CR14 registers
- 5.1 I²C Parameter Register Protocol
- 5.2 I²C Input/Output Frame Register Protocol
- 5.3 I²C Slot Marker Register Protocol
- 5.4 Addresses above Location 06h
Low Cost ISO14443 type-B Contactless Coupler Chip with Anti-Collision and CRC Management Features summary ■ Single 5V ±500mV Supply Voltage ■ SO16N package ■ Contactless Communication – ISO14443 type-B protocol – 13.56MHz Carrier Frequency using an External Oscillator – 106 Kbit/s Data Rate – 36 Byte Input/Output Frame Register – Supports Frame Answer with/without SOF/ EOF – CRC Generation and Check – Automated ST Anti-Collision Exchange ■ I²C Communication – Two Wire I²C Serial Interface – Supports 400kHz Protocol – 3 Chip Enable Pins – Up to 8 CR14 Connected on the Same Bus SO16 (MQ) 150 mils width
Table 13. RF Table 15. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width,
1 Summary description CR14
1 Summary description
The CR14 is a contactless coupler that is compliant with the short range ISO14443 type-B standard. It is controlled using the two wire I²C bus. The CR14 generates a 13.56MHz signal on an external antenna. Transmitted data are modulated using Amplitude Shift Keying (ASK). Received data are demodulated from the PICC (Proximity integrated Coupling Card) load variation signal, induced on the antenna, using Bit Phase Shift Keying (BPSK) of a 847kHz sub-carrier. The Transmitted ASK wave is 10% modulated. The Data transfer rate between the CR14 and the PICC is 106 Kbit/s in both transmission and reception modes. The CR14 follows the ISO14443 type-B recommendation for Radio frequency power and signal interface. The CR14 is specifically designed for short range applications that need disposable and reusable products. The CR14 includes an automated anti-collision mechanism that allows it to detect and select any ST short range memories that are present at the same time within its range. The anti- collision mechanism is based on the STMicroelectronics probabilistic scanning method. The CR14 provides a complete analog interface, compliant with the ISO14443 type-B recommendations for Radio-Frequency power and signal interfacing. With it, any ISO14443 type-B PICC products can be powered and have their data transmission controlled via a simple antenna. The CR14 is fabricated in STMicroelectronics High Endurance Single Poly-silicon CMOS technology. The CR14 is organized as 4 different blocks (see Figure 2):
- The I²C bus controller. It handles the serial connection with the application host. It is compliant with the 400kHz I²C bus specification, and controls the read/write access to all the CR14 registers.
- The RAM buffer. It is bi-directional. . It stores all the request frame Bytes to be transmitted to the PICC, and all the received Bytes sent by the PICC on the answer frame.
- The transmitter. It powers the PICCs by generating a 13.56MHz signal on an external antenna. The resulting field is 10% modulated using ASK (amplitude shift keying) for outgoing data.
- The receiver. It demodulates the signal generated on the antenna by the load variation of the PICC. The resulting signal is decoded by a 847kHz BPSK (binary phase shift keying) sub-carrier decoder. The CR14 is designed to be connected to a digital host (Microcontroller or ASIC). This host has to manage the entire communication protocol in both transmit and receive modes, through the I²C serial bus.
Figure 1. Logic Diagram Table 1. Signal Names
Figure 2. Logic Block Diagram Figure 3. SO Pin Connections
2 Signal description
See Figure 1: Logic Diagram, and Table 1: Signal Names, for an overview of the signals connected to this device.
2.1 Oscillator (OSC1, OSC2)
The OSC1 and OSC2 pins are internally connected to the on-chip oscillator circuit. The OSC1 pin is the input pin, the OSC2 is the output pin. For correct operation of the CR14, it is required to connect a 13.56MHz quartz crystal across OSC1 and OSC2. If an external clock is used, it must be connected to OSC1 and OSC2 must be left open.
2.2 Antenna Output Driver (RFOUT )
The Antenna Output Driver pin, RFOUT , generates the modulated 13.56MHz signal on the antenna. Care must be taken as it will not withstand a short-circuit. RF OUT has to be connected to the antenna circuitry as shown in Figure 4: CR14 Application Schematic The LRC antenna circuitry must be connected across the RFOUT pin and GND.
2.3 Antenna Input Filter (RFIN)
The antenna input filter of the CR14, RFIN, has to be connected to the external antenna through an adapter circuit, as shown in Figure 4. The input filter demodulates the signal generated on the antenna by the load variation of the PICC. The resulting signal is then decoded by the 847kHz BPSK decoder.
2.4 Transmitter Reference Voltage (VREF )
The Transmitter Reference Voltage input, VREF , provides a reference voltage used by the output driver for ASK modulation. The Transmitter Reference Voltage input should be connected to an external capacitor, as shown in Figure 4.
2.5 Serial Clock (SCL)
The SCL input pin is used to strobe all I²C data in and out of the CR14. In applications where this line is used by slave devices to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the Serial Clock (SCL) to V CC . (Figure 5 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull- up resistor is not necessary, provided that the master has a push-pull (rather than open drain) output.
2 Signal description CR14
2.6 Serial Data (SDA)
how the value of the pull-up resistor can be calculated).
2.7 Chip Enable (E0, E1, E2)
(note that the VIL and VIH levels for the inputs are CMOS compatible, not TTL compatible). down resistors connected to each inputs.
2.8 Power Supply (V CC , GND, GND_RF)
Power is supplied to the CR14 using the VCC , GND and GND_RF pins. VCC is the Power Supply pin that supplies the power (+5V) for all CR14 operations. The GND and GND_RF pins are ground connections. They must be connected together. Ground pin and the GND_REF Ground pin to filter the power line, as shown in Figure 4. Figure 4. CR14 Application Schematic
Figure 5. Maximum R L Value versus Bus Capacitance (CBUS ) for an I²C Bus
3 CR14 registers CR14
3 CR14 registers
- Parameter Register
- Input/Output Frame Register
- Slot Marker Register The other 3 registers are located at addresses 02h, 04h and 05h. They are “ST Reserved”, and must not be used in end-user applications. In the I²C protocol, all data Bytes are transmitted Most Significant Byte first, with each Byte transmitted Most significant bit first.
Table 2. CR14 Control Registers W Store and send request frame to the PICC. ST Reserved, must not be used.
3.1 Parameter Register (00h)
ISO14443 type-B configuration. Table 3. Parameter Register Bits Description
3.2 Input/Output Frame Register (01h)
through to Byte 35 (see Table 4). It is located at the I²C address 01h. store the frame length for both transmission and reception.
0 ISO14443 type-B frame management
1 RFU (1)
- RFU = Reserved for Future Use.
0 Answer PICC Frames are delimited by SOF and EOF
1 Answer PICC Frames do not pr ovide SOF and EOF delimiters
FFh, and the data Bytes are discarded and not appended in the register. provided that their data frame exchange is not longer than 35 Bytes in both request and answer. Table 4. Input/Output Frame Register Description
3.3 Slot Marker Register (03h)
the time needed to interrogate the 16 slots of the STMicroelectronics anti-collision mechanism. corresponding Slot_Register is set to FFh. 18 store the corresponding Chip_ID or error code. be accessed by reading the Input/Output Frame Register at the I²C address 01h.
Table 5. Slot Marker Register Description 1: No error detected. The Chip_ID stored in the Slot register is valid.
4 CR14 I²C protocol description CR14
4 CR14 I²C protocol description
interface that uses a bi-directional data bus and serial clock. E0) up to eight CR14 devices can be connected to the I²C bus, and selected individually.
- the Device Code (first four bits)
- plus three bits corresponding to the states of the three Chip Enable inputs, E2, E1 and E0, respectively When data is written to the CR14, the device inserts an acknowledge bit (9th bit) after the bus master’s 8-bit transmission. When the bus master reads data, it also acknowledges the receipt of the data Byte by inserting an acknowledge bit (9th bit). Data transfers are terminated by a STOP condition after an ACK for Write, or after a NoACK for Read. The CR14 supports the I²C protocol, as summarized in Figure 6. Any device that sends data on to the bus, is defined as a transmitter, and any device that reads the data, as a receiver. The device that controls the data transfer is known as the master, and the other, as the slave. A data transfer can only be initiated by the master, which also provides the serial clock for synchronization. The CR14 is always a slave device in all I²C communications. All data are transmitted Most Significant Bit (MSB) first.
Table 6. Device Select Code
CR14 4 CR14 I²C protocol description
4.1 I²C Start Condition
START is identified by a High-to-Low transition of the Serial Data line, SDA, while the Serial Clock, SCL, is stable in the High state. A START condition must precede any data transfer command. The CR14 continuously monitors the SDA and SCL lines for a START condition (except during Radio Frequency data exchanges), and will not respond unless one is sent.
4.2 I²C Stop Condition
STOP is identified by a Low-to-High transition of the Serial Data line, SDA, while the Serial Clock, SCL, is stable in the High state. A STOP condition terminates communications between the CR14 and the bus master. A STOP condition at the end of an I²C Read command, after (and only after) a NoACK, forces the CR14 into its stand-by state. A STOP condition at the end of an I²C Write command triggers the Radio Frequency data exchange between the CR14 and the PICC.
4.3 I²C Acknowledge Bit (ACK)
An acknowledge bit is used to indicate a successful data transfer on the I²C bus. The bus transmitter, either master or slave, releases the Serial Data line, SDA, after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA line Low to acknowledge the receipt of the 8 data bits.
4.4 I²C Data Input
During data input, the CR14 samples the SDA bus signal on the rising edge of the Serial Clock, SCL. For correct device operation, the SDA signal must be stable during the Low-to-High Serial Clock transition, and the data must change only when the SCL line is Low
Figure 6. I²C Bus Protocol
4.5 I²C Memory Addressing
To start up communication with the CR14, the bus master must initiate a START condition. are the Device Type Identifier. For the CR14, these bits are defined as shown in Table 6. corresponding device returns an acknowledgment on the SDA bus during the 9th bit time. No-ACK. They deselect themselves from the bus and go into stand-by mode.
4.6 CR14 I²C Write Operations
Bytes that are to be written. transfer by generating a STOP condition. the Radio Frequency data exchange between the CR14 and the PICC to be started.
- Initial condition: a Radio Frequency data exchange is in progress.
- Step 1: the master issues a START condition followed by the first Byte of the new instruction (Device Select Code plus R/W bit).
- Step 2: if the CR14 is busy, no ACK is returned and the master goes back to Step 1. If the CR14 has completed the Radio Frequency data exchange, it responds with an ACK, indicating that it is ready to receive the second part of the next instruction (the first Byte of this instruction being sent during Step 1).
Figure 7. CR14 I²C Write Mode Sequence
Figure 8. I²C Polling Flowchart using ACK
4.7 CR14 I²C Read Operations
Select Code and the R/W bit set to ’1’. Byte of the addressed register. follows the dummy Write command. master then terminates the transfer with a STOP condition, as shown in Figure 9. and switches to stand-by mode. Figure 9. CR14 I²C Read Modes Sequences
5 Applying the I²C protocol to the CR14 registers CR14
5 Applying the I²C protocol to the CR14 registers
5.1 I²C Parameter Register Protocol
active after the I²C STOP condition. the Parameter Register contents until it receives a NoACK from the I²C Host. Figure 10. Host-to-CR14 Transfer: I²C Write to Parameter Register Figure 11. CR14-to-Host Transfer: I²C Random Address Read from Parameter Register Figure 12. CR14-to-Host Transfer: I²C Current Address Read from Parameter Register
1010 XXX 0 0 h data
1010 XXX
5.2 I²C Input/Output Frame Register Protocol
Output Frame Register. The request frame is over-written by the answer frame. Figure 14 shows how to read an N -Byte PICC answer frame. The two CRC Bytes generated by the PICC are not stored. starts outputting from the start of the Input/Output Frame Register again. Figure 13. Host-to-CR14 Transfer: I²C Write to Input/Output Frame Register for ISO14443B Figure 14. CR14-to-Host Transfer: I²C Random Address Read from Input/Output Frame
1010 X X X 0 1 h N
Figure 15. CR14-to-Host Transfer: I²C Current Address Read from I/O Frame Register
5.3 I²C Slot Marker Register Protocol
loop (See Figure 16 for a description of the command). Input/Output Frame Register. and Current Address Read modes until NoACK is generated by the I²C Host. Register can be read by the host by using I²C Random Address Read. Figure 16. Host-to-CR14 Transfer: I²C Write to Slot Marker Register
Figure 17. CR14-to-Host Transfer: I²C Random Address Read from Slot Marker Register Figure 18. CR14-to-Host Transfer: I²C Current Address Read from Slot Marker Register
5.4 Addresses above Location 06h
during the 9th bit time. The SDA line stays High until the STOP condition is issued. Device Select Code after the START condition, and deselects itself from the bus.
1010 XXX 0 0 h F F h
6 CR14 ISO14443 type-B Radio Frequency data transfer CR14
6 CR14 ISO14443 type-B Radio Frequency data
6.1 Output RF Data Transfer from the CR14 to the PICC (Request
external matching circuit to generate a 13.56MHz sinusoidal carrier frequency on its antenna. The current driven into the antenna coil is directly generated by the CR14 RFOUT output driver. to a Power Supply Voltage by a regulator, and turned into data bits by the ASK demodulator. data transfer rate is 106 kbit/s. Figure 19. Wave Transmitted using ASK Modulation
6.2 Transmission Format of Request Frame Characters
Frame (EOF), constitute a Request Frame, as shown in Figure 26. defined in the ISO14443 type-B. Figure 20. CR14 Request Frame Character Format Table 7. CR14 Request Frame Character Format
6.3 Request Start Of Frame
- a falling edge,
- followed by ten Elementary Time Units (ETU) each containing a logical ‘0’
- followed by a single rising edge
- followed by two ETUs, each containing a logical ‘1’.
Figure 21. Request Start Of Frame
6.4 Request End Of Frame
- a falling edge,
- followed by ten Elementary Time Units (ETU) containing each a logical ‘0’,
- followed by a single rising edge.
Figure 22. Request End Of Frame
6.5 Input RF Data Transfer from the PICC to the CR14 (Answer
decoded by the RFIN circuitry. decodes the information received from the PICC. (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) are encoded by phase shift keying the sub-carrier. Figure 23. Wave Received using BPSK Sub-carrier Modulation
6.6 Transmission Format of Answer Frame Characters
data transfer rate is 106 kbit/s. provided that these Frames are correctly set in the Parameter Register. (See Figure 26).
6.7 Answer Start Of Frame
- Ten or eleven Elementary Time Units (ETU) each containing a logical ‘0’,
- Two ETUs containing a logical ‘1’.
Figure 24. Answer Start Of Frame
6.8 Answer End Of Frame
- Ten or eleven Elementary Time Units (ETU) each containing a logical ‘0’,
- Two ETUs containing a logical ‘1’
Figure 25. Answer End Of Frame
6.9 Transmission Frame
(‘0’) of the Answer SOF (or the start bit ‘0’ of the first data character in non SOF/EOF mode). Figure 26. Example of a Complete Transmission Frame
6.10 CRC
information, please see Appendix A on page 44. CRC is calculated on all the Bytes between the SOF and the CRC Bytes. it is invalid, it discards the frame and does not answer the CR14. is invalid, it stores the value FFh in the Input/Output Frame Register. Figure 27. CRC Transmission Rules
7 Tag access using the CR14 coupler
linked to the logic levels applied to the E2, E1 and E0 pads of the CR14.
7.1 Standard TAG Command Access Description
generate the complete frame, with the command code followed by the command parameters. waits for the PICC to send an answer frame. CR14 checks the CRC and reconnects itself to the I²C bus. on the I²C bus, as specified in Figures 14 and 15. 5 and b6), the Input/Output Frame Register is set as specified in Table 4. Figure 28. Standard TAG Command: Request Frame Transmission
7 Tag access using the CR14 coupler CR14
Figure 29. Standard TAG Command: Answer Frame Reception Figure 30. Standard TAG Command: Complete TAG Access Description
7.2 Anti-Collision TAG Sequence
The CR14 can identify an ST short range memory using a proprietary anti-collision system. the Input/Output Frame Register, as specified in Table 5. read the Input/Output Frame Register to retrieve all the identified Chip_IDs.
Figure 31. Anti-Collision ST short range memory Sequence (1)
Figure 32. Anti-Collision ST short range memory Sequence Continued
8 Maximum rating
Table 8. Absolute Maximum Ratings
- EIAJ IC-121 (Condition C) (200pF, 0Ω)
9 DC and AC parameters CR14
9 DC and AC parameters
measurement conditions when relying on the quoted parameters. Table 9. I²C AC Measurement Conditions Figure 33. I²C AC Testing I/O Waveform Table 10. I²C Input Parameters
- Sampled only, not 100% tested.
Table 11. I²C DC Characteristics
Figure 34. I²C AC Waveforms
Table 12. I²C AC Characteristics
- Sampled only, not 100% tested.
- For a reSTART condition, or following a write cycle.
Figure 35. CR14 Synchronous Timing
Table 13. RFOUT AC Characteristics
- Data specified in the table above are estimated or target values. All values can be updated during product
Table 14. RFIN AC Characteristics
- Data specified in the table above are estimated or target values. All values can be updated during product
The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 36. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package
11 Part numbering
Table 16. Ordering Information Scheme this device, please contact your nearest ST Sales Office.
11 Part numbering CR14
Appendix A ISO14443 type B CRC calculation #include <stdio.h> #include <stdlib.h> #include <string.h> #include <ctype.h> #define BYTEunsigned char #define USHORTunsigned short unsigned short UpdateCrc(BYTE ch, USHORT *lpwCrc) ch = (ch^(BYTE)((*lpwCrc) & 0x00FF)); ch = (ch^(ch<<4)); *lpwCrc = (*lpwCrc >> 8)^((USHORT)ch << 8)^((USHORT)ch<<3)^((USHORT)ch>>4); return(*lpwCrc); void ComputeCrc(char *Data, int Length, BYTE *TransmitFirst, BYTE *TransmitSecond) BYTE chBlock; USHORTt wCrc; wCrc = 0xFFFF; // ISO 3309 do chBlock = *Data++; UpdateCrc(chBlock, &wCrc); } while (--Length); wCrc = ~wCrc; // ISO 3309 *TransmitFirst = (BYTE) (wCrc & 0xFF); *TransmitSecond = (BYTE) ((wCrc >> 8) & 0xFF); return; int main(void) BYTE BuffCRC_B[10] = {0x0A, 0x12, 0x34, 0x56}, First, Second, i; printf("Crc-16 G(x) = x^16 + x^12 + x^5 + 1"); printf("CRC_B of [ "); for(i=0; i<4; i++) printf("%02X ",BuffCRC_B[i]); ComputeCrc(BuffCRC_B, 4, &First, &Second); printf("] Transmitted: %02X then %02X.", First, Second); return(0);
Table 17. Document Revision History 16-Dec-2005 1 Initial release.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America