CPL EATON | Alldatasheet

Document overview

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  • PDF pages: 6

Technical content

  • High current multi-phase inductor applications
  • 50nH per phase coupled inductor
  • CPLA Family features acoustic noise dampening properties
  • CPLE Family features optimized core material for enhanced light load efficiency
  • Ferrite core material
  • Frequency range up to 2MHz
  • Patents pending
  • Halogen free, lead free and RoHS compliant

Applications

  • For exclusive use with Volterra® or Maxim® VPR-Devices Environmental Data
  • Storage temperature range (component): -40°C to +125°C
  • Operating temperature range: -40°C to +125°C (ambient plus self-temperature rise)
  • Solder reflow temperature: J-STD-020D compliant Volterra® is a registered trademark of Volterra Semiconductor, LLC. Maxim® is a registered trademark of Maxim Integrated Devices, Inc. Pb HALOGEN HFFREE CPL,CPLA, and CPLE Multi-phase power inductors

CPL,CPLA, and CPLE Multi-phase power inductors www.eaton.com/elx Product Specifications Function Specifications Test Specifications Part Number4,5 Inductor phases DCR (Ω) Nom. @25°C DCR (Ω) Max. @25°C Rated Inductance per Phase3 (nH) I Rated per Phase3 (ADC) Pin numbers OCL1,2 (nH) Pin numbers OCL1,2 (nH) Magnetizing Inductance2 (nH) @ 5ADC (25°C) CPL Family—Standard CPL-2-50TR-R 2 0.0005 0.0006 50 ± 20% 40 (1-2) 365 ±18% (3-4) 365 ±18% 300 (7-8), (9-10) 12) 365 ±18% 400 CPLA Family—Acoustic Noise Dampening CPLA-2-50TR-R 2 0.0005 0.0006 50 ± 20% 40 (1-2) 365 ±18% (3-4) 365 ±18% 300 CPLE Family—Low Core Loss for Light Load Efficiency CPLE-2-50TR-R 2 0.0005 0.0006 50 ± 20% 40 (1-2) 365 ±18% (3-4) 365 ±18% 300 1. OCL (Open Circuit Inductance) 2. Test parameters: 1MHz, 0.1Vrms, 0.0Adc. @25°C 3. The rated current and rated inductance per phase is determined by Volterra’s testing and circuit design. Additional information can be provided by contacting Volterra. 4. Part Number Definition: CPLx-y-50TR-R-50TR-R

  • CPLx= Product code and size - CPL (standard)/CPLA (acoustic dampening)/CPLE (low core loss)
  • -y= number of phases • -50 = rated inductance value per phase in nH
  • TR= Tape and reel • -R suffix= RoHS compliant 5. This device is licensed for use only when incorporated within a voltage regulator employing power regulating devices manufactured by Volterra Semiconductor, LLC or Maxim Integrated Devices, Inc. No license is granted expressly or by implication to use this device with power regulating devices manufactured by any company other than Volterra or Maxim.

CPL,CPLA, and CPLE Multi-phase power inductors www.eaton.com/elx

8.50 Max

18.0±0.5 3214 7.0 10.0 8.0 5.8 3.2 1.0

4.80 Max

27.0±0.5 3 4 7.0 10.0 3.2 5.8 8.0 1.0 wwllyy R 36.0±0.5 7.0 10.0 3.2 5.8 8.0 1.0 wwllyy R CPLx-5-50 12 3 4 56 7 8 45.0±0.5 Front View 38 74 7.0 9 10 10.0 3.2 5.8 8.0 1.0 wwllyy R Bottom View TopView 54.2±0.5 3 4 10.0 3.2 5.8 8.0 1.0 wwllyy R 7.0 11 12 Pin #1 Pin #1 Pin #1 Pin #1 Pin #1 12 56 12 56 12 56 78 91 01 11 2 Dimensions (mm) Part marking: Pin 1 dot, CPL/CPLA/CPLE= (product code and size), -2,-3,-4,-5, -6= (number of phases), -50 = (inductance value per phase in nH) wwllyy = date code, R = revision level Tolerances are ±0.20 millimeters unless stated otherwise All soldering surfaces to be coplanar within 0.15 millimeter Do not route traces or vias underneath the inductor

CPL,CPLA, and CPLE Multi-phase power inductors www.eaton.com/elx Pad layouts & schematics (mm) Tolerances are ±0.2mm unless otherwise specified. 16.9 CPLx-2-50-R 2 4 9.00 7.9 1.1 9.00 CPLx-3-50-R 2 4 9.00 7.9 1.1 9.00 25.9 CPLx-4-50-R 34.9 1.1 9.00 2 4 9.00 7.9 2 4 9.00 7.9 1.1 9.00 43.9 CPLx-5-50-R 2 4 52.9 7.9 1.1 9.00 CPLx-6-50-R Recommended Pad Layout Schematic Schematic Recommended Pad Layout

CPL,CPLA, and CPLE Multi-phase power inductors www.eaton.com/elx 28.4 ± 0.1 32.0 ± 0.3 1.75 14.2 2.0 1.5Dia 4.0 16.0 Section A-A 5.2 8.9 18.9 2.0 wwllyy RCPLx-2-50 CPLx-2-50 40.4 ± 0.1 44.0 ± 0.3 1.75 20.2 2.0 1.5Dia 4.0 16.0 Section A-A 5.2 8.9 27.9 2.0CPLx-3-50 wwllyy RCPLx-3-50 52.4 ± 0.1 56.0 ± 0.3 1.75 26.2 2.0 1.5Dia 4.0 16.0 Section A-A 5.2 8.9 36.9 2.0CPLx-4-50 wwllyy R CPLx-4-50 68.4 ± 0.1 72.0 ± 0.3 16.0 Section A-A 8.9 45.9 2.0 CPLx-5-50wwllyy R CPLx-5-50 68.4 ± 0.1 72.0 ± 0.3 1.75 34.2 2.0 1.5Dia 4.0 16.0 Section A-A 5.2 8.9 54.9 2.0 User direction of feed CPLx-6-50wwllyy R CPLx-6-50 5.2 Pin #1 Pin #1 Pin #1 Pin #1 Pin #1 Packaging Information (mm) Supplied in tape-and-reel packaging, 750 parts per reel, 13” diameter reel.

1000 Eaton Boulevard

Cleveland, OH 44122 United States www.eaton.com/elx © 2015 Eaton All Rights Reserved Printed in USA Publication No. 4362 BU-SB12070 December 2015 Eaton is a registered trademark. All other trademarks are property of their respective owners. CPL,CPLA, and CPLE Multi-phase power inductors Technical Data 4362 Effective December 2015 Life Support Policy: Eaton does not authorize the use of any of its products for use in life support devices or systems without the express written approval of an officer of the Company. Life support systems are devices which support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Eaton reserves the right, without notice, to change design or construction of any products and to discontinue or limit distribution of any products. Eaton also reserves the right to change or update, without notice, any technical information contained in this bulletin. Temperature t tP ts TC -5°C Time 25°C to Peak Time 25°C Tsmin Tsmax TL TP Preheat A Max. Ramp Up Rate = 3°C/s Max. Ramp Down Rate = 6°C/s Solder reflow profile Reference JDEC J-STD-020D Profile Feature Standard SnPb Solder Lead (Pb) Free Solder Preheat and Soak • Temperature min. (Tsmin) 100°C 150°C

  • Temperature max. (Tsmax) 150°C 200°C
  • Time (Tsmin to Tsmax) (ts) 60-120 Seconds 60-120 Seconds Average ramp up rate Tsmax to Tp 3°C/ Second Max. 3°C/ Second Max. Liquidous temperature (Tl) Time at liquidous (tL) 183°C 60-150 Seconds 217°C 60-150 Seconds Peak package body temperature (TP)* Table 1 Table 2 Time (tp) within 5 °C of the specified classification temperature (T c) 20 Seconds 30 Seconds** Average ramp-down rate (Tp to Tsmax) 6°C/ Second Max. 6°C/ Second Max. Time 25°C to Peak Temperature 6 Minutes Max. 8 Minutes Max. * Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1 - Standard SnPb Solder (Tc) Package Thickness Volume mm3 <350 Volume mm3 ≥350 ≥2.5mm 220°C 220°C Table 2 - Lead (Pb) Free Solder (Tc) Package Thickness Volume mm3 <350 Volume mm3 350 - 2000 Volume mm3 >2000 <1.6mm 260°C 260°C 260°C 1.6 – 2.5mm 260°C 250°C 245°C >2.5mm 250°C 245°C 245°C