82C89_06 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Pin Compatible with Bipolar 8289
- Performance Compatible with:
- Provides Multi-Master System Bus Control and Arbitration
- Provides Simple Interface with 82C88/8288 Bus Controller
- Synchronizes 80C86/8086, 80C88/8088 Processors with Multi-Master Bus
- Bipolar Drive Capability
- Four Operating Modes for Flexible System Configuration
- Low Power Operation
- Operating Temperature Ranges
- Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
TEMP . RANGE (°C) PACKAGE PKG. DWG. # CP82C89 CP82C89 0 to +70 20 Ld PDIP E20.3 CP82C89Z* (Note) CP82C89Z 0 to +70 20 Ld PDIP (Pb-free) E20.3 MD82C89/B MD82C89/B -55 to +125 20 Ld CERDIP F20.3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Pinout 82C89 (PDIP, CERDIP) TOP VIEW
1 VCC
Data Sheet February 27, 2006
2 FN2980.2 February 27, 2006 Functional Diagram Pin Description PIN SYMBOL NUMBER TYPE DESCRIPTION VCC 20 V CC: The +5V Power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling. GND 10 GROUND. S0, S1, S2 1, 18-19 I STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The 82C89 decodes these pins to initiate bus request and surrender actions. (See Table 1). CLK 17 I CLOCK: From the 82C84A or 82C85 clock chip and serv es to establish when bus arbiter actions are initiated. LOCK 16 I LOCK: A processor generated signal which when activate d (low) prevents the arbiter from surrendering the multi- master system bus to any other bus arbiter, regardless of its priority. CRQLCK 15 I COMMON REQUEST LOCK: An active lo w signal which prevents the arbiter from surrendering the multi-master system bus to any other bus arbiter requesting the bus through the CBRQ input pin. RESB 4 I RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a multi-master system bus and a Resident Bus. Strapped high, the multi-master system bus is requested or surrendered as a function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB input is ignored. ANYRQST 14 I ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible). When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Information. If ANYRQST is strapped high and CBRQ is activated, the bus is surrendered at the end of the present bus cycle. Strapping CBRQ low and ANYRQST high forces the 82C89 arbiter to surrender the multi-master system bus after each transfer cycle. Note that when surrender occurs BREQ is driven false (high). IOB 2 I IO BUS: A strapping option which configures the 82C 89 Arbiter to operate in systems having both an IO Bus (Peripheral Bus) and a multi-master system bus. The arbiter requests and surrenders the use of the multi-master system bus as a function of the status line, S2. The multi-master system bus is permitted to be surrendered while the processor is performing IO commands and is requested whenever the processor performs a memory command. Interrupt cycles are assumed as coming from the peripheral bus and are treated as an IO command. AEN 13 O ADDRESS ENABLE: The output of the 82C89 Arbiter to the processor’s address latches, to the 82C88 Bus Controller and 82C84A or 82C85 Clock Generator. AEN serves to instruct the Bus Controller and address latches when to three-state their output drivers. INIT 6 I INITIALIZE: An active low multi-master system bus input signal used to reset all the bus arbiters on the multi- master system bus. After initialization, no arbiters have the use of the multi-master system bus. CONTROL ARBITRATION MULTIBUS INTERFACE LOCAL BUS INTERFACE +5V GND CONTROL/ STRAPPING OPTIONS 80C86/ 80C88 STATUS COMMAND SIGNALS MULTIBUS™ SYSTEM SIGNALS MULTIBUS™ is an Intel Corp. trademark. BPRN SYSB/ RESB INIT BCLK BREQ BPRO BUSY CBRQ AEN CLK RESB ANYRQST LOCK IOB CRQLCK S2 STATUS DECODER 82C89
3 FN2980.2 February 27, 2006 Functional Description The 82C89 Bus Arbiter operates in conjunction with the 82C88 Bus Controller to interface 80C86, 80C88 processors to a multi-master system bus (both the 80C86 and 80C88 are configured in their max mode). The processor is unaware of the arbiter’s existence and issues commands as though it has exclusive use of the system bus. If the processor does not have the use of the multi-master system bus, the arbiter prevents the Bus Controller (82C88), the data transceivers and the address latches from accessing the system bus (e.g. all bus driver outputs are forced into the high impedance state). Since the command sequence was not issued by the 82C88, the system bus will appear as “Not Ready” and the processor will enter wait states. The processor will remain in Wait until the Bus Arbiter acquires the use of the multi-master system bus whereupon the arbiter will allow the bus controller, the data transceivers, and the address latches to access the system. Typically, once the command has been issued and a data transfer has taken place, a transfer acknowledge (XACK) is returned to the processor to indicate “READY” from the accessed slave device. The processor then completes its transfer cycle. Thus the arbiter serves to multiplex a processor (or bus master) onto a multi-master system bus and avoid contention problems between bus masters. Arbitration Between Bus Masters In general, higher priority masters obtain the bus when a lower priority master completes its present transfer cycle. Lower priority bus masters obtain the bus when a higher priority master is not accessing the system bus. A strapping option (ANYRQST) is provided to allow the arbiter to surrender the bus to a lower priority master as though it were a master of higher priority. If there are no other bus masters requesting the bus, the arbiter maintains the bus so long as its processor has not entered the HALT State. The arbiter will not voluntarily surrender the system bus and has to be forced off by another master’s bus request, the HALT State being the only exception. Additional strapping options permit other modes of operation wherein the multi-master system bus is surrendered or requested under different sets of conditions. SYSB/RESB 3 I SYSTEM BUS/RESIDENT BUS: An input signal when t he arbiter is configured in the System/Resident Mode (RESB is strapped high) which determines when the multi-master system bus is requested and multi-master system bus surrendering is permitted. The signal is intended to originate from a form of address-mapping circuitry, such as a decoder or PROM attached to the resident address bus. Signal transitions and glitches are permitted on this pin from θ1 of T4 to θ1 of T2 of the processor cycle. During the period from θ1 of T2 to θ1 of T4, only clean transitions are permitted on this pin (no glitches). If a glitch occurs, the arbiter may capture or miss it, and the multi-master system bus may be requested or surrendered, depending upon the state of the glitch. The arbiter requests the multi-master system bus in the System/Resident Mode when the state of the SYSB/RESB pin is high and permits the bus to be surrendered when this pin is low. CBRQ 12 I/O COMMON BUS REQUEST: An input signal which instructs t he arbiter if there are any other arbiters of lower priority requesting the use of the multi-master system bus. The CBRQ pins (open-drain output) of all the 82C89 Bus Arbiters which surrender to the multi-master system bus upon request are connected together. The Bus Arbiter running the current transfer cycle will not itself pull the CBRQ line low. Any other arbiter connected to the CDRQ line can request the multi-master system bus. The arbiter presently running the current transfer cycle drops its BREQ signal and surrenders the bus whenever the proper surrender conditions exist. Strapping CBRQ low and ANYRQST high allows the multi-master system bus to be surrendered after each transfer cycle. See the pin definition of ANYRQST. BCLK 5 I BUS CLOCK: The multi-master system bus clock to wh ich all multi-master system bus interface signals are synchronized. BREQ 7 O BUS REQUEST: An active low output signal in the Parallel Priority Resolving Scheme which the arbiter activates to request the use of the multi-master system bus. BPRN 9 I BUS PRIORITY IN: The active low signal returned to the arbi ter to instruct it that it may acquire the multi-master system bus on the next falling edge of BCLK. BPRN active indicates to the arbiter that it is the highest priority requesting arbiter presently on the bus. The loss of BPRN instructs the arbiter that it has lost priority to a higher priority arbiter. BPRO 8 O BUS PRIORITY OUT: An active low output signal us ed in the serial priority resolving scheme where BPRO is daisy-chained to BPRN of the next lower priority arbiter. BUSY 11 I/O BUSY: An active low open-drain multi- master system bus interface signal used to instruct all the arbiters on the bus when the multi-master system bus is available. When the multi-master system bus is available the highest requesting arbiter (determined by BPRN) seizes the bus and pulls BUSY low to keep other arbiters off of the bus. When the arbiter is done with the bus, it releases the BUSY signal, permitting it to go high and thereby allowing another arbiter to acquire the multi-master system bus. Pin Description (Continued) PIN SYMBOL NUMBER TYPE DESCRIPTION 82C89
techniques, and rotating priority techniques. any other priority resolving scheme employed to settle.
- Higher priority bus arbiter releases BUSY.
- Higher priority bus arbiter then acquires the bus and pulls BUSY
- Lower priority bus arbiter releases BUSY.
- Higher priority bus arbiter then acquires the bus and pulls BUSY
to the BPRN of the next lower priority. See Figure 3. chance to use the multi-master system bus, over time.
3 TO 8
FIGURE 1. PARALLEL PRIORITY RESOLVING TECHNIQUE FIGURE 2. HIGHER PRIORITY ARBITER OBTAINING THE FIGURE 3. SERIAL PRIORITY RESOLVING arbiters may be daisychained.
5 FN2980.2 February 27, 2006 Which Priority Resolving Technique To Use There are advantages and disadvantages for each of the techniques described above. The rotating priority resolving technique requires substantial external logic to implement while the serial technique uses no external logic but can accommodate only a limited number of bus arbiters before the daisy-chain propagation delay exceeds the multimaster’s system bus clock (BCLK ). The parallel priority resolving technique is in general a good compromise between the other two techniques. It allows for many arbiters to be present on the bus while not requiring too much logic to implement. 82C89 Modes Of Operation There are two types of processors for which the 82C89 will provide support: An Input/Output processor (i.e. an NMOS 8089 IOP) and the 80C86, 80C88. Consequently, there are two basic operating modes in the 82C89 bus arbiter. One, the IOB (I/O Peripheral Bus) mode, permits the processor access to both an I/O Peripheral Bus and a multi-master system bus. The second, the RESB (Resident Bus mode), permits the processor to communicate over both a Resident Bus and a multi-master system bus. An I/O Peripheral Bus is a bus where all devices on that bus, including memory, are treated as I/O devices and are addressed by I/O commands. All memory commands are directed to another bus, the multi-master system bus. A Resident Bus can issue both memory and I/O commands, but it is a distinct and separate bus from the multi-master system bus. The distinction is that the Resident Bus has only one master, providing full availability and being dedicated to that one master. The IOB strapping option configures the 82C89 Bus Arbiter into the IOB mode and the strapping option RESB configures it into the RESB mode. It might be noted at this point that if both strapping options are strapped false, the arbiter interfaces the processor to a multi-master system bus only (see Figure 4). With both options strapped true, the arbiter interfaces the processor to a multi-master system bus, a Resident Bus, and an I/O Bus. In the IOB mode, the processor communicates and controls a host of peripherals over the Peripheral Bus. When the I/O Processor needs to communicate with system memory, it does so over the system memory bus. Figure 5 shows a possible I/O Processor system configuration. The 80C86 and 80C88 processors can communicate with a Resident Bus and a multi-master system bus. Two bus controllers and only one Bus Arbiter would be needed in such a configuration as shown in Figure 6. In such a system configuration the processor would have access to memory and peripherals of both busses. Memory mapping techniques are applied to select which bus is to be accessed. The SYSB/RESB input on the arbiter serves to instruct the arbiter as to whether or not the system bus is to be accessed. The signal connected to SYSB/RESB also enables or disables commands from one of the bus controllers. A summary of the modes that the 82C89 has, along with its response to its status lines inputs, is shown in Table 1. 82C89
FIGURE 4. TYPICAL MEDIUM COMPLEXITY CPU SYSTEM
FIGURE 5. TYPICAL MEDIUM COMPLEXITY IOB SYSTEM
FIGURE 6. 82C89 BUS ARBITER SHOWN IN SYST EM - RESIDENT BUS CONFIGURATION
TABLE 1. SUMMARY OF 82C89 MODES, REQUESTING AND RELINQUISHING THE MULTI-MASTER SYSTEM BUS
- X = Multi-Master System Bus is allowed to be Surrendered.
- † = Multi-Master System Bus is Requested.
*L O C K prevents surrender of Bus to any other arbiter, CRQLCK prevents surrender of Bus to any lower priority arbiter. ** Except for HALT and Passive or IDLE Status. ‡ HPBRQ, Higher priority Bus request or BPRN = 1.
- + is read as “OR” and • as “AND”
- TI = Processor Idle Status S2, S1, S0 = 111
- HLT = Processor Halt Status S2, S1, S0 = 011
10 FN2980.2 February 27, 2006 Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Note 1) θ JA (°C/W) θJC (°C/W) Maximum Junction Temperature *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Die Characteristics CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. TA = 0°C to +70°C (C82C89); TA = -55°C to +125°C (M82C89) SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS VIH Logical One Input Voltage C82C89, M82C89, Note 1 2.0 2.2 V V VIL Logical Zero Input Voltage Note 1 - 0.8 V VIHC CLK Logical One Input Voltage 0.7 VCC - V VILC CLK Logical Zero Input Voltage - 0.2 VCC V VOL Output Low Voltage BUSY, CBRQ IOL = 20mA - 0.45 V AEN IOL = 16mA - 0.45 V BPRO, BREQ IOL = 8mA - 0.45 V VOH1 Output High Voltage BUSY, CBRQ Open-Drain VOH2 Output High Voltage I OH = -2.5mA 3.0 - V All Other Outputs I OH = -100µAV CC -0.4 - V II Input Leakage Current V IN = GND or VCC, DIP Pins 1-6, 9, 14-19 -1.0 1.0 µA IO I/O Leakage V O = GND or VCC, DIP Pins 11-12 -10.0 10.0 µA ICCSB Standby Power Supply V CC = 5.5V, VIN = VCC or GND, Outputs Open - 10 µA ICCOP Operating Power Supply Current V CC = 5.5V, Outputs Open, Note 2 - 1 mA/MHz NOTES: 1. Does not apply to IOB , RESB, or ANYRQST. These are strap options and should be held to VCC or GND. 2. Maximum current defined by CLK or BCLK, wh ichever has the highest operating frequency Capacitance TA = +25°C SYMBOL PARAMETER TEST CONDITIONS TYPICAL UNITS CIN Input Capacitance FREQ = 1MHz, all measurements are referenced to device GND 10 pF COUT Output Capacitance 10 pF CIO I/O Capacitance 15 pF 82C89
11 FN2980.2 February 27, 2006 TA = 0°C to +70°C (C82C89); TA = -55°C to +125°C (M82C89) SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS (1) TCLCL CLK Cycle Period 125 - ns Note 3 (2) TCLCH CLK Low Time 55 - ns Note 3 (3) TCHCL CLK High Time 35 - ns Note 3 (4) TSVCH Status Active Setup 65 TCLCL-10 ns Note 3 (5) TSHCL Status Inactive Setup 50 TCLCL-10 ns Note 3 (6) THVCH Status Inactive Hold 10 - ns Note 3 (7) THVCL Status Active Hold 10 - ns Note 3 (8) TBYSBL BUSY ↓↑ Setup to BCLK↓ 20 - ns Note 3 (9) TCBSBL CBRQ ↓↑ Setup to BCLK↓ 20 - ns Note 3 (10) TBLBL BCLK Cycle Time 100 - ns Note 3 (11) TBHCL BCLK High Time 30 0.65 (TBLBL) ns Note 3 (12) TCLLL1 LOCK Inactive Hold 10 - ns Note 3 (13) TCLLL2 LOCK Active Setup 40 - ns Note 3 (14) TPNBL BPRN ↓↑ to BCLK Setup Time 20 - ns Note 3 (15) TCLSR1 SYSB/RESB Setup 0 - ns Note 3 (16) TCLSR2 SYSB/RESB Hold 30 - ns Note 3 (17) TIVIH Initialization Pulse Width 675 - ns Note 3 (18) TBLBRL BCLK to BREQ Delay↓↑ - 35 ns Note 3 (19) TBLPOH BCLK to BPRO↓↑ - 35 ns Note 1 and 3 (20) TPNPO BPRN ↓↑ to BPRO↓↑ Delay - 22 ns Note 1 and 3 (21) TBLBYL BCLK to BUSY Low - 60 ns Note 3 (22) TBLBYH BCLK to BUSY Float - 35 ns Note 2 and 3 (23) TCLAEH CLK to AEN High - 65 ns Note 3 (24) TBLAEL BCLK to AEN Low - 40 ns Note 3 (25) TBLCBL BCLK to CBRQ Low - 60 ns Note 3 (26) TBLCBH BCLK to CBRQ Float - 40 ns Note 2 and 3 (27) TOLOH Output Rise Time - 20 ns From 0.8V to 2.0V, Note 4 (28) TOHOL Output Fall Time - 12 ns From 2.0V to 0.8V, Note 4 (29) TILIH Input Rise Time - 20 ns From 0.8V to 2.0V (30) TIHIL Input Fall Time - 20 ns From 2.0V to 0.8V NOTES: 1. BCLK generates the first BPRO wherein subsequent BPRO changes lower in the chain are generated through BPRON. 2. Measured at 0.5V above GND. 3. All AC parameters tested as per AC test load circ uits. Input rise and fall times are driven at 1ns/V. 4. Except BUSY and CBRQ. 82C89
12 FN2980.2 February 27, 2006 AC Test Load Circuits BUSY, CBRQ LOAD CIRCUIT AEN LOAD CIRCUIT BPRO , BREQ LOAD CIRCUIT NOTE: Includes Stray and Jig Capacitance AC Testing Input, Output Waveform AC Testing: Inputs are driven at VIH +0.4V for a logic “1” and VIL Timing measurements are made at 1.5V for both a logic “1” and “0”. Burn-In Circuits MD82C89 CERDIP TEST POINT 100pF 102Ω OUTPUT FROM DEVICE UNDER TEST 2.5V (NOTE) TEST POINT 2.9V 100pF OUTPUT FROM DEVICE UNDER TEST 157.2Ω (NOTE) TEST POINT 2.9V 100pF OUTPUT FROM DEVICE UNDER TEST 249.6Ω (NOTE) 1.5V 1.5V VIL -0.4V INPUT VIH +0.4V VOL OUTPUT VOH 1 20F7 F13 F14 F12 VCC VCC/2 VCC VCC/2 F11 F10 82C89
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2980.2 February 27, 2006 Die Characteristics DIE DIMENSIONS: 92.9 x 95.7 x 19 ±1 mils METALLIZATION: Type: Si - Al Thickness: 11kÅ ±2kÅ GLASSIVATION: Type: Nitrox Thickness: 10kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.8 x 105 A/cm2 Metallization Mask Layout 82C89 CLK LOCK CRQLCK ANYRQST SYSB/RESB IOB VCC ANYRQST BPRO BPRN GND BUSY CBRQ AEN RESB BCLK INIT BREQ 82C89