CP82C54-12

82C54_05 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

 8MHz to 12MHz Clock Input Frequency  Compatible with NMOS 8254 - Enhanced Version of NMOS 8253  Three Independent 16-Bit Counters  Six Programmable Counter Modes  Status Read Back Command  Binary or BCD Counting  Fully TTL Compatible  Single 5V Power Supply L o w P o w e r  Operating Temperature Ranges oC to +70oC  Pb-Free Plus Anneal Available (RoHS Compliant) Pinouts 82C54 (PDIP, CERDIP) TOP VIEW 82C54 (PLCC/CLCC) TOP VIEW CLK 0 OUT 0 GATE 0 GND VCC RD CS OUT 2 CLK 1 GATE 1 OUT 1 WR CLK 2 GATE 2 GND NC OUT 1 GATE 1 CLK 1 OUT 0 GATE 0 NC VCC WR RD CS CLK2 NC GATE 2 OUT 2 1234 12 13 14 15 16 17 18 262728 NC CLK 0 Data Sheet FN2970.4

Ordering Information

PKG. DWG. #8MHz 10MHz 12MHz CP82C54 CP82C54-10 CP82C54-12 0 oC to +70oC 24 Lead PDIP E24.6 CP82C54Z (See Note) CP82C54-10Z (See Note) CP82C54-12Z (See Note) 0 oC to +70oC 24 Lead PDIP** (Pb-free) E24.6 CS82C54* CS82C54-10* CS82C54-12 0 oC to +70oC 28 Lead PLCC N28.45 CS82C54Z* (See Note) CS82C54-10Z* (See Note) CS82C54-12Z* (See Note) 0 oC to +70oC 28 Lead PLCC (Pb-free) N28.45 ID82C54 - - -40 oC to +85oC 24 Lead CERDIP F24.6 IP82C54 IP82C54-10 - -40 oC to +85oC 24 Lead PDIP E24.6 IP82C54Z (See Note) IP82C54-10Z (See Note) - -40 oC to +85oC 24 Lead PDIP** (Pb-free) E24.6 IS82C54* IS82C54-10* - -40 oC to +85oC 28 Lead PLCC N28.45 IS82C54Z (See Note) IS82C54-10Z (See Note) - -40 oC to +85oC 28 Lead PLCC (Pb-free) N28.45 MD82C54/B - - -55 oC to +125oC 24 Lead CERDIP F24.6 SMD # 8406501JA - - -55 oC to +125oC 24 Lead CERDIP F24.6 SMD# 84065013A - 84065023A -55 oC to +125oC 28 Lead CLCC J28.A Contact factory for availability. *Add “96” suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products em ploy special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) oC to +150oC (PLCC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 - V CX82C54, IX82C54 2.2 - V MD82C54 VIL Logical Zero Input Voltage - 0.8 V - VOH Output HIGH Voltage 3.0 - V IOH = -2.5mA V CC -0.4 - V IOH = -100 µA VOL Output LOW Voltage - 0.4 V IOL = +2.5mA II Input Leakage Current -1 +1 µA VIN = GND or V CC DIP Pins 9,11,14-16,18-23 IO Output Leakage Current -10 +10 µA VOUT = GND or V CC DIP Pins 1-8 ICCSB Standby Power Supply Current - 10 µAV CC = 5.5V, VIN = GND or VCC , Outputs Open, Counters Programmed ICCOP Operating Power Supply Current - 10 mA V CC = 5.5V, CLK0 = CLK1 = CLK2 = 8MHz, VIN = GND or V CC , Outputs Open Capacitance TA = +25oC; All Measurements Referenced to Device GND, Note 1 SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance 20 pF FREQ = 1MHz COUT Output Capacitance 20 pF FREQ = 1MHz CI/O I/O Capacitance 20 pF FREQ = 1MHz NOTE: 1. Not tested, but characterized at initial design and at major process/design changes.

CONDITIONSMIN MAX MIN MAX MIN MAX READ CYCLE (1) TAR Address Stable Before RD 30 - 25 - 25 - ns 1 (2) TSR CS Stable Before RD 0-0-0-n s 1 (3) TRA Address Hold Time After RD 0-0-0-n s 1 (4) TRR RD Pulse Width 150 - 95 - 95 - ns 1 (5) TRD Data Delay from RD - 120 - 85 - 85 ns 1 (6) TAD Data Delay from Address - 210 - 185 - 185 ns 1 (7) TDF RD to Data Floating 5 85 5 65 5 65 ns 2, Note 1 (8) TRV Command Recovery Time 200 - 165 - 165 - ns WRITE CYCLE (9) TAW Address Stable Before WR 0-0-0-n s (10) TSW CS Stable Before WR 0-0-0-n s (11) TWA Address Hold Time After WR 0-0-0-n s (12) TWW WR Pulse Width 95 - 95 - 95 - ns (13) TDW Data Setup Time Before WR 140 - 95 - 95 - ns (14) TWD Data Hold Time After WR 2 5 -0-0-n s (15) TRV Command Recovery Time 200 - 165 - 165 - ns CLOCK AND GATE (16) TCLK Clock Period 125 DC 100 DC 80 DC ns 1 (17) TPWH High Pulse Width 60 - 30 - 30 - ns 1 (18) TPWL Low Pulse Width 60 - 40 - 30 - ns 1 (19) TR Clock Rise Time - 25 - 25 - 25 ns (20) TF Clock Fall Time - 25 - 25 - 25 ns (21) TGW Gate Width High 50 - 50 - 50 - ns 1 (22) TGL Gate Width Low 50 - 50 - 50 - ns 1 (23) TGS Gate Setup Time to CLK 50 - 40 - 40 - ns 1 (24) TGH Gate Hold Time After CLK 50 - 50 - 50 - ns 1 (25) TOD Output Delay from CLK - 150 - 100 - 100 ns 1 (26) TODG Output Delay from Gate - 120 - 100 - 100 ns 1 (27) TWO OUT Delay from Mode Write - 260 - 240 - 240 ns 1 (28) TWC CLK Delay for Loading 0 55 0 55 0 55 ns 1 (29) TWG Gate Delay for Sampling -5 40 -5 40 -5 40 ns 1 (30) TCL CLK Setup for Count Latch -40 40 -40 40 -40 40 ns 1 NOTE: 1. Not tested, but characterized at initial design and at major process/design changes.

COUNTER INTERNAL BLOCK DIAGRAM Pin Description SYMBOL DIP PIN NUMBER TYPE DEFINITION D7 - D0 1 - 8 I/O DATA: Bi-directional three-stat e data bus lines, connected to system data bus. CLK 0 9 I CLOCK 0: Clock input of Counter 0. OUT 0 10 O OUT 0: Output of Counter 0. GATE 0 11 I GATE 0: Gate input of Counter 0. GND 12 GROUND: Power supply connection. OUT 1 13 O OUT 1: Output of Counter 1. GATE 1 14 I GATE 1: Gate input of Counter 1. CLK 1 15 I CLOCK 1: Clock input of Counter 1. GATE 2 16 I GATE 2: Gate input of Counter 2. OUT 2 17 O OUT 2: Output of Counter 2. CLK 2 18 I CLOCK 2: Clock input of Counter 2. A0, A1 19 - 20 I ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write operations. Normally connected to the system address bus. CS 21 I CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and WR are ignored otherwise. RD 22 I READ: This input is lo w during CPU read operations. WR 23 I WRITE: This input is low during CPU write operations. VCC 24 - V CC : The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended for decoupling. A1 A0 SELECTS 0 0 Counter 0 0 1 Counter 1 1 0 Counter 2 1 1 Control Word Register

Since the Control Word Register and the three Counters have separate addresses (selected by the A1, A0 inputs), and each Control Word specifies the Counter it applies to (SC0, SC1 bits), no special instruction sequence is required. Any programming sequence that follows the conventions above is acceptable. CONTROL WORD FORMAT A1, A0 = 11; CS D7 D6 D5 D4 D3 D2 D1 D0 SC1 SC0 RW1 RW0 M2 M1 M0 BCD SC - SELECT COUNTER SC1 SC0 0 0 Select Counter 0 0 1 Select Counter 1 1 0 Select Counter 2 1 1 Read-Back Command (See Read Operations) RW - READ/WRITE RW1 RW0 0 0 Counter Latch Command (See Read Operations) 0 1 Read/Write least si gnificant byte only. 1 0 Read/Write most significant byte only. 1 1 Read/Write least significant byte first, then most significant byte. M - MODE M2 M1 M0 0 0 0 Mode 0 0 0 1 Mode 1 X 1 0 Mode 2 X 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 BCD - BINARY CODED DECIMAL

0 Binary Counter 16-bit

1 Binary Coded Decimal (BCD) Counter (4 Decades)

NOTE: Don’t Care bits (X) should be 0 to insure compatibility with future products. POSSIBLE PROGRAMMING SEQUENCE A1 A0 Control Word - Counter 0 1 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 0 0 0 Control Word - Counter 1 1 1 LSB of Count - Counter 1 0 1 MSB of Count - Counter 1 0 1 Control Word - Counter 2 1 1 LSB of Count - Counter 2 1 0 MSB of Count - Counter 2 1 0 POSSIBLE PROGRAMMING SEQUENCE A1 A0 Control Word - Counter 0 1 1 Control Word - Counter 1 1 1 Control Word - Counter 2 1 1 LSB of Count - Counter 2 1 0 LSB of Count - Counter 1 0 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 0 0 0 MSB of Count - Counter 1 0 1 MSB of Count - Counter 2 1 0 POSSIBLE PROGRAMMING SEQUENCE A1 A0 Control Word - Counter 2 1 1 Control Word - Counter 1 1 1 Control Word - Counter 0 1 1 LSB of Count - Counter 2 1 0 MSB of Count - Counter 2 1 0 LSB of Count - Counter 1 0 1 MSB of Count - Counter 1 0 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 0 0 0

A new initial count may be written to a Counter at any time without affecting the Counter’s programmed Mode in any way. Counting will be affected as described in the Mode definitions. The new count must follow the programmed count format. If a Counter is programmed to read/write two-byte counts, the following precaution applies. A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter. Otherwise, the Counter will be loaded with an incorrect count. READ OPERATIONS It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the 82C54. There are three possible methods for reading the Counters. The first is through the Read-Back command, which is explained later. The second is a simple read operation of the Counter, which is selected with the A1, A0 inputs. The only requirement is that the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic. Otherwise, the count may be in process of changing when it is read, giving an undefined result. COUNTER LATCH COMMAND The other method for reading the Counters involves a special software command called the “Counter Latch Command”. Like a Control Word, this command is written to the Control Word Register, which is selected when A1, A0 = 11. Also, like a Control Word, the SC0, SC1 bits select one of the three Counters, but two other bits, D5 and D4, distinguish this command from a Control Word. The selected Counter’s output latch (OL) latches the count when the Counter Latch Command is received. This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed). The count is then unlatched automatically and the OL returns to “following” the counting element (CE). This allows reading the contents of the Counters “on the fly” without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one Counter. Each latched Counter’s OL holds its count until read. Counter Latch Commands do not affect the programmed Mode of the Counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued. With either method, the count must be read according to the programmed format; specifically, if the Counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other; read or write or programming operations of other Counters may be inserted between them. Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved; for example, if the Counter is programmed for two byte counts, the following sequence is valid. 1. Read least significant byte. 2. Write new least significant byte. 3. Read most significant byte. 4. Write new most significant byte. If a counter is programmed to read or write two-byte counts, the following precaution applies: A program MUST NOT transfer control between reading the first and second byte to another routine which also reads from that same Counter. Otherwise, an incorrect count will be read. READ-BACK COMMAND The read-back command allows the user to check the count value, programmed Mode, and current state of the OUT pin and Null Count flag of the selected counter(s). The command is written into the Control Word Register and has the format shown in Figure 5. The command applies to POSSIBLE PROGRAMMING SEQUENCE A1 A0 Control Word - Counter 1 1 1 Control Word - Counter 0 1 1 LSB of Count - Counter 1 0 1 Control Word - Counter 2 1 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 1 0 1 LSB of Count - Counter 2 1 0 MSB of Count - Counter 0 0 0 MSB of Count - Counter 2 1 0 NOTE: In all four examples, all counters are programmed to Read/Write two-byte counts. These are only four of many programming sequences. A1, A0 = 11; CS = 0; RD = 1; WR = 0 D7 D6 D5 D4 D3 D2 D1 D0 S C 1 S C 0 00XXXX SC1, SC0 - specify counter to be latched SC1 SC0 COUNTER 00 0 01 1 10 2 1 1 Read-Back Command D5, D4 - 00 designates Counter Latch Command, X - Don’t Care. NOTE: Don’t Care bits (X) should be 0 to insure compatibility with future products.

order, of a Counter’s CLK input. TRIGGER - A rising edge of a Counter’s Gate input. GATE = 1 enables counting; GATE = 0 disables counting. pulses after the initial count is written.

1. Writing the first byte disables counting. Out is set low

immediately (no clock pulse required).

1. Writing the second byte allows the new count to be

loaded on the next CLK pulse. pulses after the new count of N is written. FIGURE 7. READ-BACK COMMAND EXAMPLE

01000 W r i t e i n t o C o u n t e r 0

01001 W r i t e i n t o C o u n t e r 1

01010 W r i t e i n t o C o u n t e r 2

01011 W r i t e C o n t r o l W o r d

00100 R e a d f r o m C ounter 0

00101 R e a d f r o m C ounter 1

00110 R e a d f r o m C ounter 2

00111 N o - O p e r a t i o n ( T h r e e - S t a t e )

FIGURE 8. READ/WRITE OPERATIONS SUMMARY

count. The above process is repeated indefinitely. and then decremented by two on succeeding CLK pulses. high for (N + 1)/2 counts and low for (N - 1)/2 counts. counting sequence is “Triggered” by writing the initial count. GATE = 1 enables counting; GATE = 0 disables counting.

1. Writing the first byte has no effect on counting.
2. Writing the second byte allows the new count to be

loaded on the next CLK pulse. go low for one CLK pulse and then go high again. after any trigger GATE has no effect on OUT. FIGURE 13. MODE 4

and counting will continue from there. state; no CLK pulses are required for this. for binary counting and 104 for BCD counting. continues counting from there. FIGURE 14. MODE 5

0 Disables Counting - Enables Counting

FIGURE 15. GATE PIN OPERATIONS SUMMARY FIGURE 16. MINIMUM AND MAXIMUM INITIAL COUNTS

FIGURE 20. CLOCK AND GATE

DIE DIMENSIONS: 129mils x 155mils x 19mils (3270µm x 3940µm x 483µm) METALLIZATION: Type: Si-Al-Cu Thickness: Metal 1: 8kÅ ± 0.75kÅ Metal 2: 12kÅ ± 1.0kÅ GLASSIVATION: Type: Nitrox Thickness: 10kÅ ± 3.0kÅ Metallization Mask Layout 82C54 CS CLK2 OUT2 GATE2 CLK0 D5 D6 D7 VCC WR RD OUT0 GATE0 GND OUT1 GATE1 CLK1 82C54

Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E24.6 (JEDEC MS-011-AA ISSUE B)

24 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.150 1.290 29.3 32.7 5 D1 0.005 - 0.13 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N2 4 2 4 9 Rev. 0 12/93

Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14)R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10)C -C- D2/E2 CL N28.45 (JEDEC MS-018AB ISSUE A)

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N2 8 2 8 6 Rev. 2 11/97

Ceramic Leadless Chip Carrier Packages (CLCC) D j x 45o B h x 45o A A1 E L L3 e PLANE 2 PLANE 1

0.010 E HS S

0.010 E FS S

-E-

0.007 E FM S HS

-H- -F- J28.A MIL-STD-1835 CQCC1-N28 (C-4)

28 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE

A 0.060 0.100 1.52 2.54 6, 7 A1 0.050 0.088 1.27 2.23 - B ---- - B1 0.022 0.028 0.56 0.71 2, 4 B2 0.072 REF 1.83 REF - B3 0.006 0.022 0.15 0.56 - D 0.442 0.460 11.23 11.68 - D1 0.300 BSC 7.62 BSC - D2 0.150 BSC 3.81 BSC - D3 - 0.460 - 11.68 2 E 0.442 0.460 11.23 11.68 - E1 0.300 BSC 7.62 BSC - E2 0.150 BSC 3.81 BSC - E3 - 0.460 - 11.68 2 e 0.050 BSC 1.27 BSC - e1 0.015 - 0.38 - 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.90 2.41 - L3 0.003 0.015 0.08 0.038 - ND 7 7 3 NE 7 7 3 N2 8 2 8 3 Rev. 0 5/18/94 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maxi- mum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 82C54 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa CA - BM DS S eA F24.6 MIL-STD-1835 GDIP1-T24 (D-3, CONFIGURATION A)

24 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.290 - 32.77 5 E 0.500 0.610 12.70 15.49 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.120 0.200 3.05 5.08 - Q 0.015 0.075 0.38 1.91 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N2 4 2 4 8 Rev. 0 4/94