80C88_08 INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 38

Technical content

Features

  • Compatible with NMOS 8088
  • Direct Software Compatibility with 80C86, 8086, 8088
  • 8-Bit Data Bus Interface; 16-Bit Internal Architecture
  • Completely Static CMOS Design
  • Low Power Operation
  • 1 Megabyte of Direct Memory Addressing Capability
  • 24 Operand Addressing Modes
  • Bit, Byte, Word, and Block Move Operations
  • 8-Bit and 16-Bit Signed/Unsigned Arithmetic
  • Bus-Hold Circuitry Elimi nates Pull-up Resistors
  • Wide Operating Temperature Ranges
  • Pb-Free Available (RoHS Compliant)

Ordering Information

(5MHz) PART MARKING PART NUMBER (8MHz) PART MARKING TEMPERATURE RANGE (°C) PACKAGE PKG. DWG. # CP80C88 CP80C88 CP80C88-2 CP80C88-2 0 to +70 40 LD PDIP E40.6 IP80C88 IP80C88 IP80C88-2 IP80C88-2 -40 to +85 40 LD PDIP E40.6 MD80C88/B MD80C88/B -55 to +125 40 LD CERDIP F40.6 CP80C88Z (Note) CP80C88Z 0 to +70 40 LD PDIP* (Pb-Free) E40.6 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet February 22, 2008

2 FN2949.4 February 22, 2008 Pinouts 80C88 (40 LD PDIP, 40 LD CERIDP) TOP VIEW GND A14 A13 A12 A11 A10 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND V CC A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 MN/MX RD (RQ/GT0) (RQ/GT1) (LOCK) (S2) (S1) (S0) (QS0) (QS1) TEST READY RESET INTA ALE DEN DT/R IO/M WR HLDA HOLD MIN MAX (HIGH) MODEMODE80C88

3 FN2949.4 February 22, 2008 Functional Diagram REGISTER FILE EXECUTION UNIT CONTROL AND TIMING INSTRUCTION QUEUE 4-BYTE FLAGS 16-BIT ALU BUS 8 QS0, QS1 S2, S1, S0 GND VCC CLK RESET READY BUS INTERFACE UNIT RELOCATION REGISTER FILE A19/S6. . . A16/S3 INTA, RD, WR DT/R, DEN, ALE, IO/M SSO/HIGH SEGMENT REGISTERS AND INSTRUCTION POINTER (5 WORDS) DATA POINTER AND INDEX REGS (8 WORDS) TEST INTR NMI HLDA HOLD RQ/GT0, 1 LOCK MN/MX ES CS SS DS IP AH BH CH DH AL BL CL DL SP BP SI DI ARITHMETIC/ LOGIC UNIT B-BUS C-BUS EXECUTION UNIT INTERFACE UNIT BUS QUEUE INSTRUCTION STREAM BYTE EXECUTION UNIT CONTROL SYSTEM FLAGS MEMORY INTERFACE A-BUS AD7-AD0

8 A8-A15

4 FN2949.4 February 22, 2008 Pin Description The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers). SYMBOL PIN NUMBER TYPE DESCRIPTION MAXIMUM OR MINIMUM MODE. THE “LOCAL BUS” IN THESE DESCRIPTIONS IS THE DIRECT MULTIPLEXEDBUS INTERFACE CONNECTION TO THE 80C88 (WITHOUT REGARD TO ADDITIONAL BUS BUFFERS). AD7 thru AD0 9 thru 16 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data (T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last valid level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence” A15, A14 thru A8 39, 2 thru 8 O ADDRESS BUS: These lines provide address bi ts 8 through 15 for the entire bus cycle (T1-T4). These lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”. A19/S6, A18/S5, A17/S4, A16/S3 O O O O ADDRESS/STATUS: During T1, these are the four most significant address lines for memory operations. During I/O operations, these lines are LOW. During memory and I/O operations, status information is available on these lines during T2, T3, TW and T4. S6 is always LOW. The status of the interrupt enable flag bit (S5) is updated at the beginning of each clock cycle. S4 and S3 are encoded as shown. This information indicates whic h segment register is presently being used for data accessing. These lines are held at high impedance to the last valid logic level during local bus “hold acknowledge” or “grant Sequence”. RD 32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending on the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88 local bus. RD is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the 80C88 local bus has floated. This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”. READY 22 I READY: is the acknowledgment from the address me mory or I/O device that it will complete the data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation is not guaranteed if the set up and hold times are not met. INTR 18 I INTERRUPT REQUEST: is a level triggered input whic h is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH. TEST 23 I TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution continues, otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle on the leading edge of CLK. NMI 17 I NONMASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized. RESET 21 I RESET: cases the processor to immediately terminate its present activity. The signal must transition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is internally synchronized. CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing. VCC 40 V CC: is the +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 recommended for decoupling. GND 1, 20 GND: are the ground pins (both pins must be connected to system ground). A 0.1µF capacitor between pins 1 and 20 is recommended for decoupling. MN/MX 33 I MINIMUM/MAXIMUM: indicates the mode in which t he processor is to operate. The two modes are discussed in the following sections. S4 S3 CHARACTERISTICS 0 0 Alternate Data

01 S t a c k

11 D a t a

5 FN2949.4 February 22, 2008 Pin Description The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to the minimum mode are described; all other pin functions are as described above. SYMBOL PIN NUMBER TYPE DESCRIPTION MINIMUM MODE SYSTEM (i.e., MN/MX = VCC) IO/M 28 O STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from an I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus “hold acknowledge”. WR 29 O Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depending on the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active LOW, and is held to high impedance logic one during local bus “hold acknowledge”. INTA 24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and Tw of each interrupt acknowledge cycle. Note that INTA is never floated. ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82/82C83 address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note that ALE is never floated. DT/R 27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87 data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R is equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH, R = LOW). This signal is held to a high impedance logic one during local bus “hold acknowledge”. DEN 26 O DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which uses the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles. For a read or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until the middle of T4. DEN is held to high impedance logic one during local bus “hold acknowledge”. HOLD, HLDA I O HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD must be active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an acknowledgment, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. Hold is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the set up time. SS0 34 O STATUS LINE: is logically equivalent to S0 in the maximum mode. The combination of SS0, IO/M and DT/R allows the system to completely decode the current bus cycle status. SS0 is held to high impedance logic one during local bus “hold acknowledge”. IO/M DT/R SS0 CHARACTERISTICS 1 0 0 Interrupt Acknowledge 1 0 1 Read I/O Port 1 1 0 Write I/O Port 11 1 Halt 0 0 0 Code Access 0 0 1 Read Memory 0 1 0 Write Memory 01 1 P a s s i v e 80C88

6 FN2949.4 February 22, 2008 Pin Description (Continued) The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to the maximum mode are described; all other pin functions are as described above. SYMBOL PIN NUMBER TYPE DESCRIPTION MAXIMUM MODE SYSTEM (i.e., MN/MX = GND). O O O STATUS: is active during clock high of T4, T1 and T2, and is returned to the passive state (1, 1, 1) during T3 or during Tw when READY is HIGH. This status is used by the 82C88 bus controller to generate all memory and I/O access control signals. Any change by S2 , S1 or S0 during T4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T3 or Tw is used to indicate the end of a bus cycle. These signals are held at a high impedance logic one state during “grant sequence”. RQ /GT0, RQ/GT1 I/O REQUEST/GRANT: pins are used by other local bus ma sters to force the processor to release the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may be left unconnected. The request/grant sequence is as follows (see RQ/GT Timing Sequence): 1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to the 80C88 (pulse 1). 2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master (pulse 2), indicates that the 80C88 has allowed the local bus to float and that it will enter the “grant sequence” state at the next CLK. The CPUs bus interface unit is disconnected logically from the local bus during “grant sequence”. 3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold” request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU then enters T4 (or T1 if no bus cycles pending). Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle CLK cycle after bus exchange. Pulses are active LOW. If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conjugations are met: 1. Request occurs on or before T2. 2. Current cycle is not the low bit of a word. 3. Current cycle is not the first acknow ledge of an interrupt acknowledge sequence. 4. A locked instruction is not currently executing. If the local bus is idle when the request is made the two possible events will follow: 1. Local bus will be released during the next clock. 2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied. LOCK 29 O LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is active (LOW). The LOCK signal is activated by the “LOCK” prefix instruction and remains active until the completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one state during “grant sequence”. In Max Mode, LOCK is automatically generated during T2 of the first INTA cycle and removed during T2 of the second INTA cycle. S2 S1 S0 CHARACTERISTICS 0 0 0 Interrupt Acknowledge 00 1 Read I/O Port 01 0 Write I/O Port 01 1 Halt 10 0 Code Access 10 1 Read Memory 1 1 0 Write Memory 1 11 P a s s i v e 80C88

7 FN2949.4 February 22, 2008 Functional Description Static Operation All 80C88 circuitry is static in design. Internal registers, counters and latches are static and require not refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The CMOS 80C88 can operate from DC to the specified upper frequency limit. The processor clock may be stopped in either state (high/low) and held there indefinitely. This type of operation is especially useful for system debug or power critical applications. The 80C88 can be single stepped using only the CPU clock. This state can be maintained as long as is necessary. Single step clock operation allows simple interface circuitry to provide critical information for start-up. Static design also allows very low frequency operation (as low as DC). In a power critical situation, this can provide extremely low power operation since 80C88 power dissipation is directly related to operation frequency. As the system frequency is reduced, so is the operating power until, at a DC input frequency, the power requirement is the 80C88 standby current. Internal Architecture The internal functions of the 80C88 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the CPU block diagram. These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 4-bytes of the instruction stream can be queued while waiting for decoding and execution. The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 1-byte in the queue, the BIU will attempt a byte fetch memory cycle. This greatly reduces “dead time”: on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU. The execution unit receives pre-fetched instructions from the BIU queue and provides unrelocated operand addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes results to the BIU for storage. Memory Organization The processor provides a 20-bit address to memory which locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra, and stack segments of up to 64-bytes each, with each segment falling on 16-byte boundaries. (See Figure 1). QS1, QS0 24, 25 O QUEUE STATUS: provide status to allow external tracking of the internal 80C88 instruction queue. The queue status is valid during the CLK cycle after which the queue operation is performed. Note that the queue status never goes to a high impedance statue (floated). 34 O Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during a “grant sequence”. Pin Description (Continued) The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to the maximum mode are described; all other pin functions are as described above. SYMBOL PIN NUMBER TYPE DESCRIPTION MAXIMUM MODE SYSTEM (i.e., MN/MX = GND). QS1 QS0 CHARACTERISTICS

00 N o O p e r a t i o n

0 1 First Byte of Opcode from Queue 1 0 Empty the Queue 1 1 Subsequent Byte from Queue 80C88

multiplexed bus is desired for the system. these cycles for internal housekeeping. information for the cycle may be latched. address bits and are therefore valid during T2 through T4. bus cycle in forming the address according to Table 3.

1 BYTE INT INSTRUCTION

FIGURE 2. RESERVED MEMORY LOCATIONS

the same manner as memory locations. FIGURE 5. BASIC SYSTEM TIMING

010 Write I/O

011 H a l t

pointer into the interrupt vector lookup table. within the limitations of the enable bit and sample period. enable bit when it restores the flags. S1 and S0, and the 82C88 bus controller issues one ALE. reissues the HALT indicator at the end of the local bus hold. configurations to accomplish “test and set lock” operations. MULTIBUS™ compatible bus control signals. FIGURE 7. INTERRUPT ACKNOWLEDGE SEQUENCE

14 FN2949.4 February 22, 2008 will be available on the bus and the addressed device will drive the READY line HIGH. When the processor returns the read signal to a HIGH level, the addressed device will again three-state its bus drivers. If a transceiver (82C86/82C87) is required to buffer the local bus, signals DT/R and DEN are provided by the 80C88. A write cycle also begins with the assertion of ALE and the emission of the address. The IO/M signal is again asserted to indicate a memory or I/O write operation. In T2, immediately following the address emission, the processor emits the data to be written into the addressed location. This data remains valid until at least the middle of T4. During T2, T3, and Tw, the processor asserts the write control signal. The write (WR ) signal becomes active at the beginning of T2, as opposed to the read, which is delayed somewhat into T2 to provide time for output drivers to become inactive. The basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt acknowledge (INTA ) signal is asserted in place of the read (RD) signal and the address bus is held at the last valid logic state by internal bus-hold devices (see Figure 6. In the second of two successive INTA cycles, a byte of information is read from the data bus, as supplied by the interrupt system logic (i.e., 82C59A priority interrupt controller). This byte identifies the source (type) of the interrupt. It is multiplied by four and used as a pointer into the interrupt vector lookup table, as described earlier. Bus Timing - Medium Complexity Systems For medium complexity systems, the MN/MX pin is connected to GND and the 82C88 bus controller is added to the system, as well as an 82C82/82C83 latch for latching the system address, and an 82C86/82C87 transceiver to allow for bus loading greater than the 80C88 is capable of handling (see Figure 8). Signals ALE, DEN , and DT/R are generated by the 82C88 instead of the processor in this configuration, although their timing remains relatively the same. The 80C88 status outputs (S2 , S1 and S0) provide type of cycle information and become 82C88 inputs. This bus cycle information specifies read (code, data or I/O), write (data or I/O), interrupt acknowledge, or software halt. The 82C88 thus issues control signals specifying memory read or write, I/O read or write, or interrupt acknowledge. The 82C88 provides two types of write strobes, normal and advanced, to be applied as required. The normal write strobes have data valid at the leading edge of write. The advanced write strobes have the same timing as read strobes, and hence, data is not valid at the leading edge of write. The 82C86/82C87 transceiver receives the usual T and OE inputs from the 82C88 DT/R and DEN outputs. The pointer into the interrupt vector table, which is passed during the second INTA cycle, can derive from an 82C59A located on either the local bus or the system bus. If the master 82C59A priority interrupt controller is positioned on the local bus, the 82C86/82C87 transceiver must be disabled when reading from the master 82C59A during the interrupt acknowledge sequence and software “poll”. The 80C88 Compared to the 80C86 The 80C88 CPU is a 8-bit processor designed around the 8086 internal structure. Most internal functions of the 80C88 are identical to the equivalent 80C86 functions. The 80C88 handles the external bus the same way the 80C86 does with the distinction of handling only 8-bits at a time. Sixteen-bit operands are fetched or written in two consecutive bus cycles. Both processors will appear identical to the software engineer, with the exception of execution time. The internal register structure is identical and all instructions have the same end result. Internally, there are three differences between the 80C88 and the 80C86. All changes are related to the 8-bit bus interface.

  • The queue length is 4-bytes in the 80C88, whereas the 80C86 queue contains 6-bytes, or three words. The queue was shortened to prevent overuse of the bus by the BIU when prefetching instructions. This was required because of the additional time necessary to fetch instructions 8-bits at a time.
  • To further optimize the queue, the prefetching algorithm was changed. The 80C88 BIU will fetch a new instruction to load into the queue each time there is a 1-byte space available in the queue. The 80C86 waits until a 2-byte space is available. The internal execution time of the instruction set is affected by the 8-bit interface. All 16-bit fetches and writes from/to memory take an additional four clock cycles. The CPU is also limited by the speed of instruction fetches. This latter problem only occurs when a series of simple operations occur. When the more sophisticated instructions of the 80C88 are being used, the queue has time to fill the execution proceeds as fast as the execution unit will allow. The 80C88 and 80C86 are completely software compatible by virtue of their identical execution units. Software that is system dependent may not be completely transferable, but software that is not system dependent will operate equally as well on an 80C88 or an 80C86. The hardware interface of the 80C88 contains the major differences between the two CPUs. The pin assignments are nearly identical, however, with the following functional changes:
  • A8-A15: These pins are only address outputs on the 80C88. These address lines are latched internally and remain valid throughout a bus cycle in a manner similar to the 8085 upper address lines.
  • B H E has no meaning on the 80C88 and has been eliminated.
  • SS0 provides the S0 status information in the minimum mode. This output occurs on pin 34 in minimum mode 80C88
  • IO/M has been inverted to be compatible with the 8085 bus structure.
  • ALE is delayed by one clock cycle in the minimum mode when entering HALT, to allow the status to be latched with ALE. T1 T2 T3 T4 A7-A0 DATA IN CLK QS1, QS0 S2, S1, S0 A19/S6 - A16/S3 ALE 80C88 AD7 - AD0 DEN S6 - S3 DT/R MRDC 82C84RDY READY 80C88 A19 - A16 A15 - A8

FIGURE 8. MEDIUM COMPLEXITY SYSTEM TIMING

16 FN2949.4 February 22, 2008 Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range θJA (oC/W) Maximum Junction Temperature http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for th rough hole wave solder processing only. They are not intended for use in Reflow solder processing applica- tions. Die Characteristics CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications VCC = 5.0V, ±10%; TA = 0°C to +70°C (C80C88, C80C88-2) VCC = 5.0V, ±10%; TA = -40°C to +85°C (l80C88, I80C88-2) VCC = 5.0V, ±10%; TA = -55°C to +125°C (M80C88) SYMBOL PARAMETER TEST CONDITION MIN MAX UNITS VlH Logical One Input Voltage C80C88, I80C88 (Note 4) 2.0 - V M80C88 (Note 4) 2.2 V VIL Logical Zero Input Voltage - 0.8 V VIHC CLK Logical One Input Voltage V CC - 0.8 - V VILC CLK Logical Zero Input Voltage - 0.8 V VOH Output High Voltage lOH = -2.5mA 3.0 - V lOH = -100µA V CC - 0.4 V VOL Output Low Voltage lOL = +2.5mA - 0.4 V II Input Leakage Current V IN = 0V or VCC Pins 17 thru 19, 21 thru 23 and 33 -1.0 1.0 µA lBHH Input Current-Bus Hold High V IN = - 3.0V (Note 1) -40 -400 µA lBHL Input Current-Bus Hold Low V IN = - 0.8V (Note 2) 40 400 µA IO Output Leakage Current V OUT = 0V (Note 5) - -10.0 µA ICCSB Standby Power Supply Current V CC = 5.5V (Note 3) - 500 µA ICCOP Operating Power Supply Current FREQ = Max, V IN = VCC or GND, Outputs Open -1 0 m A / M H z NOTES: 1. lBHH should be measured after raising V IN to VCC and then lowering to 3.0V on the following pins 2 thru16, 26 thru 32, 34 thru 39. 2. IBHL should be measured after lowering V IN to GND and then raising to 0.8V on the following pins: 2 thru16, 35 thru 39. 3. lCCSB tested during clock high time after HALT instruction executed. VIN = VCC or GND, VCC = 5.5V, Outputs unloaded. 4. MN/MX is a strap option and should be held to VCC or GND. 5. IO should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29 and 32. Capacitance TA = +25°C SYMBOL PARAMETER TEST CONDITIONS TYPICAL UNITS CIN Input Capacitance FREQ = 1MHz. All measur ements are referenced to device GND 25 pF COUT Output Capacitance FREQ = 1MHz. All meas urements are referenced to device GND 25 pF CI/O I/O Capacitance FREQ = 1MHz. All meas urements are referenced to device GND 25 pF 80C88

17 FN2949.4 February 22, 2008 VCC = 5.0V ±10%; TA = -40°C to +85°C (I80C88, I80C88-2) SYMBOL PARAMETER TEST CONDITIONS 80C88 80C88-2 UNITSMIN MAX MIN MAX MINIMUM COMPLEXITY SYSTEM Timing Requirements (1) TCLCL CLK Cycle Period 200 - 125 - ns (2) TCLCH CLK Low Time 118 - 68 - ns (3) TCHCL CLK High Time 69 - 44 - ns (4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V - 10 - 10 ns (5) TCL2CL1 CLK FaIl Time From 3.5V to 1.0V - 10 - 10 ns (6) TDVCL Data In Setup Time 30 - 20 - ns (7) TCLDX1 Data In Hold Time 10 - 10 - ns (8) TR1VCL RDY Setup Time into 82C84A (Notes 6,7) 35 - 35 - ns (9) TCLR1X RDY Hold Time into 82C84A (Notes 6,7) 0- 0 - n s (10) TRYHCH READY Setup Time into 80C88 118 - 68 - ns (11) TCHRYX READY Hold Time into 80C88 30 - 20 - ns (12) TRYLCL READY Inactive to CLK (Note 8) -8 - -8 - ns (13) THVCH HOLD Setup Time 35 - 20 - ns (14) TINVCH lNTR, NMI, TEST Setup Time (Note 7) 30 - 15 - ns (15) TILIH Input Rise Time (Except CLK) From 0.8V to 2.0V - 15 - 15 ns (16) TIHIL Input FaIl Time (Except CLK) From 2.0V to 0.8V - 15 - 15 ns Timing Responses (17) TCLAV Address Valid Delay CL = 100pF 10 110 10 60 ns (18) TCLAX Address Hold Time CL = 100pF 10 - 10 - ns (19) TCLAZ Address Float Delay CL = 100pF TCLAX 80 TCLAX 50 ns (20) TCHSZ Status Float Delay CL = 100pF - 80 - 50 ns (21) TCHSV Status Active Delay CL = 100pF 10 110 10 60 ns (22) TLHLL ALE Width CL = 100pF TCLCH-20 - TCLCH-10 - ns (23) TCLLH ALE Active Delay CL = 100pF - 80 - 50 ns (24) TCHLL ALE Inactive Delay CL = 100pF - 85 - 55 ns (25) TLLAX Address Hold Time to ALE Inactive CL = 100pF TCHCL-10 - TCHCL-10 - ns (26) TCLDV Data Valid Delay CL = 100pF 10 110 10 60 ns (27) TCLDX2 Data Hold Time CL = 100pF 10 - 10 - ns (28) TWHDX Data Hold Time After WR CL = 100pF TCLCL-30 - TCLCL-30 - ns (29) TCVCTV Control Active Delay 1 CL = 100pF 10 110 10 70 ns (30) TCHCTV Control Active Delay 2 CL = 100pF 10 110 10 60 ns (31) TCVCTX Control Inactive Delay CL = 100pF 10 110 10 70 ns (32) TAZRL Address Float to READ Active CL = 100pF 0 - 0 - ns 80C88

18 FN2949.4 February 22, 2008 (33) TCLRL RD Active Delay CL = 100pF 10 165 10 100 ns (34) TCLRH RD Inactive Delay CL = 100pF 10 150 10 80 ns (35) TRHAV RD Inactive to Next Address Active CL = 100pF TCLCL-45 - TCLCL-40 - ns (36) TCLHAV HLDA Valid Delay CL = 100pF 10 160 10 100 ns (37) TRLRH RD Width CL = 100pF 2TCLCL-75 - 2TCLCL-50 - ns (38) TWLWH WR Width CL = 100pF 2TCLCL-60 - 2TCLCL-40 - ns (39) TAVAL Address Valid to ALE Low CL = 100pF TCLCH-60 - TCLCH-40 - ns (40) TOLOH Output Rise Time From 0.8V to 2.0V - 15 - 15 ns (41) TOHOL Output Fall Time From 2.0V to 0.8V - 15 - 15 ns NOTES: 6. Signal at 82C84A shown for reference only. 7. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 8. Applies only to T2 state (8ns into T3). VCC = 5.0V ±10%; TA = -40°C to +85°C (I80C88, I80C88-2) VCC = 5.0V ±10%; TA = -55° to +125°C (M80C88) (Continued) SYMBOL PARAMETER TEST CONDITIONS 80C88 80C88-2 UNITSMIN MAX MIN MAX 80C88

FIGURE 9. BUS TIMING - MINIMUM MODE SYSTEM

  1. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.
  2. Signals at 82C84A are shown for reference only.

FIGURE 10. BUS TIMING - MINI MUM MODE SYSTEM (Continued)

  1. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the
  2. Signals at 82C84A are shown for reference only.

21 FN2949.4 February 22, 2008 VCC = 5.0V±10%; TA = -40°C to +85°C (I80C88, I80C88-2) VCC = 5.0V±10%; TA = -55°C to +125°C (M80C88) MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) SYMBOL PARAMETER TEST CONDITIONS 80C88 80C88-2 UNITSMIN MAX MIN MAX TIMING REQUIREMENTS (1) TCLCL CLK Cycle Period 200 - 125 - ns (2) TCLCH CLK Low Time 118 - 68 - ns (3) TCHCL CLK High Time 69 - 44 - ns (4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V - 10 - 10 ns (5) TCL2CL1 CLK Fall Time From 3.5V to 1.0V - 10 - 10 ns (6) TDVCL Data in Setup Time 30 - 20 - ns (7) TCLDX1 Data In Hold Time 10 - 10 - ns (8) TR1VCL RDY Setup Time into 82C84 (Notes 13,14) 35 - 35 - ns (9) TCLR1X RDY Hold Time into 82C84 (Notes 13,14) 0-0- n s (10) TRYHCH READY Setup Time into 80C88 118 - 68 - ns (11) TCHRYX READY Hold Time into 80C88 30 - 20 - ns (12) TRYLCL READY Inactive to CLK (Note15) -8 - -8 - ns (13) TlNVCH Setup Time for Recognition (lNTR, NMl, TEST) (Note 14) 30 - 15 - ns (14) TGVCH RQ /GT Setup Time 30 - 15 - ns (15) TCHGX RQ Hold Time into 80C88 (Note 16) 40 TCHCL +

30 TCHCL +

(16) TILlH Input Rise Time (Except CLK) From 0.8V to 2.0V -1 5 -1 5 n s (17) TIHIL Input Fall Time (Except CLK) From 2.0V to 0.8V -1 5 -1 5 n s TIMING RESPONSES (18) TCLML Command Active Delay (Note13) CL = 100pF for all 80C88 outputs in addition to internal loads. 53 553 5 n s (19) TCLMH Command Inactive (Note 13) 53 553 5 n s (20) TRYHSH READY Active to Status Passive (Notes 15, 17) -1 1 0- 6 5n s (21) TCHSV Status Active Delay 10 110 10 60 ns (22) TCLSH Status Inactive Delay (Note 17) 10 130 10 70 ns (23) TCLAV Address Valid Delay 10 110 10 60 ns (24) TCLAX Address Hold Time 10 - 10 - ns (25) TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns (26) TCHSZ Status Float Delay - 80 - 50 ns (27) TSVLH Status Valid to ALE High (Note 13)- 2 0 - 2 0 n s (28) TSVMCH Status Valid to MCE High (Note 13)- 3 0 - 3 0 n s (29) TCLLH CLK Low to ALE Valid (Note 13)- 2 0 - 2 0 n s (30) TCLMCH CLK Low to MCE High (Note 13)- 2 5 - 2 5 n s (31) TCHLL ALE Inactive Delay (Note 13) 41 841 8 n s 80C88

22 FN2949.4 February 22, 2008 (32) TCLMCL MCE Inactive Delay (Note 13) CL = 100pF for all 80C88 outputs in addition to internal loads. -1 5 -1 5 n s (33) TCLDV Data Valid Delay 10 110 10 60 ns (34) TCLDX2 Data Hold Time 10 - 10 - ns (35) TCVNV Control Active Delay (Note 13) 54 5 54 5 n s (36) TCVNX Control Inactive Delay (Note 13) 10 45 10 45 ns (37) TAZRL Address Float to Read Active 0- 0- n s (38) TCLRL RD Active Delay 10 165 10 100 ns (39) TCLRH RD Inactive Delay 10 150 10 80 ns (40) TRHAV RD Inactive to Next Address Active TCLCL - 45 - TCLCL - 40 -n s (41) TCHDTL Direction Control Active Delay (Note 13) -5 0 -5 0 n s (42) TCHDTH Direction Control Inactive Delay (Note 1) -3 0 -3 0 n s (43) TCLGL GT Active Delay 08 5 05 0 n s (44) TCLGH GT Inactive Delay 08 5 05 0 n s (45) TRLRH RD Width 2TCLCL - 75 - 2TCLCL - 50 -n s (46) TOLOH Output Rise Time From 0.8V to 2.0V -1 5 -1 5 n s (47) TOHOL Output Fall Time From 2.0V to 0.8V -1 5 -1 5 n s NOTES: 3. Signal at 82C84A or 82C88 shown for reference only. 4. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 5. Applies only to T2 state (8ns into T3). 6. The 80C88 actively pulls the RQ /GT pin to a logic one on the following clock low time. 7. Status lines return to their inactive (log ic one) state after CLK goes low and READY goes high. VCC = 5.0V±10%; TA = -40°C to +85°C (I80C88, I80C88-2) VCC = 5.0V±10%; TA = -55°C to +125°C (M80C88) MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) (Continued) SYMBOL PARAMETER TEST CONDITIONS 80C88 80C88-2 UNITSMIN MAX MIN MAX 80C88

FIGURE 11. BUS TIMING - MAXIMUM MODE (USING 82C88)

  1. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.
  2. Signals at 82C84A or 82C88 are shown for reference only.
  3. Status inactive in state just prior to T4.
  4. The issuance of the 82C88 command and control signals (MRDC

FIGURE 12. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)

  1. Signals at 82C84A or 82C86 are shown for reference only.
  2. The issuance of the 82C88 command and control signals (MRDC
  3. Status inactive in state just prior to T4.
  4. Cascade address is valid between first and second INTA
  5. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown

FIGURE 17. RESET TIMING NOTE: Includes stay and jig capacitance.

  1. All input signals (other than CLK) must switch between VILMAX -50%

VCC -0.4V. Input rise and fall times are driven at 1ns/V.

27 FN2949.4 February 22, 2008 Burn-In Circuits (Continued) COMPONENTS: 5. C = 0.01 μF (Minimum) NOTES: 1. V CC = 5.5V ±0.5V, GND = 0V. 2. Input voltage limits (except clock): VIL (Maximum) = 0.4V VIH (Minimum) = 2.6V, VIH (Clock) = VCC - 0.4V) minimum. 3. VCC/2 is external supply set to 2.7V ±10%. 4. V CL is generated on program card (VCC - 0.65V). 5. Pins 13 - 16 input sequenced instructions from internal hold devices, (DIP Only). 6. F0 = 100kHz ±10%. 7. Node = a 40 μs pulse every 2.56ms.A 80C88

28 FN2949.4 February 22, 2008 Die Characteristics METALLIZATION: Type: Silicon - Aluminum Thickness: 11K Å ±2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: 1.5 x 105 A/cm2 Metallization Mask Layout 80C88 A11 A12 A13 A14 A17/S4 A18/S5 GND A16/S3 VCC A15 A19/S6 SSO MN/MX RD A10 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND RESET READY TEST ALE DEN HOLD HLDA WR IO/M DT/R INTA 80C88

29 FN2949.4 February 22, 2008 Instruction Set Summary MNEMONIC AND

DESCRIPTION

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DATA TRANSFER MOV = MOVE: Register/Memory to/from Register 1 0 0 0 1 0 d w mod reg r/m Immediate to Regis- ter/Memory 1 1 0 0 0 1 1 w mod 0 0 0 r/m data data if w 1 Immediate to Register 1 0 1 1 w reg data data if w 1 Memory to Accumulator 1 0 1 0 0 0 0 w addr-low addr-high Accumulator to Memory 1 0 1 0 0 0 1 w addr-low addr-high Register/Memory to Seg- ment Register †† 1 0 0 0 1 1 1 0 mod 0 reg r/m Segment Register to Reg- ister/Memory 1 0 0 0 1 1 0 0 mod 0 reg r/m PUSH = Push: Register/Memory 1 1 1 1 1 1 1 1 mod 1 1 0 r/m Register 0 1 0 1 0 reg Segment Register 0 0 0 reg 1 1 0 POP = Pop: Register/Memory 1 0 0 0 1 1 1 1 mod 0 0 0 r/m Register 0 1 0 1 1 reg Segment Register 0 0 0 reg 1 1 1 XCHG = Exchange: Register/Memory with Register 1 0 0 0 0 1 1 w mod reg r/m Register with Accumula- tor 1 0 0 1 0 reg IN = Input from: Fixed Port 1 1 1 0 0 1 0 w port Variable Port 1 1 1 0 1 1 0 w OUT = Output to: Fixed Port 1 1 1 0 0 1 1 w port Variable Port 1 1 1 0 1 1 1 w XLAT = Translate Byte to AL 1 1 0 1 0 1 1 1 LEA = Load EA to Register2 1 0 0 0 1 1 0 1 mod reg r/m LDS = Load Pointer to DS 1 1 0 0 0 1 0 1 mod reg r/m LES = Load Pointer to ES 1 1 0 0 0 1 0 0 mod reg r/m LAHF = Load AH with Flags 1 0 0 1 1 1 1 1 SAHF = Store AH into Flags 1 0 0 1 1 1 1 0 PUSHF = Push Flags 1 0 0 1 1 1 0 0 POPF = Pop Flags 1 0 0 1 1 1 0 1 80C88

30 FN2949.4 February 22, 2008 ARITHMETIC ADD = Add: Register/Memory with Register to Either 0 0 0 0 0 0 d w mod reg r/m Immediate to Regis- ter/Memory 1 0 0 0 0 0 s w mod 0 0 0 r/m data data if s:w = 01 Immediate to Accumula- tor 0 0 0 0 0 1 0 w data data if w = 1 ADC = Add with Carry: Register/Memory with Register to Either 0 0 0 1 0 0 d w mod reg r/m Immediate to Regis- ter/Memory 1 0 0 0 0 0 s w mod 0 1 0 r/m data data if s:w = 01 Immediate to Accumula- tor 0 0 0 1 0 1 0 w data data if w = 1 INC = Increment: Register/Memory 1 1 1 1 1 1 1 w mod 0 0 0 r/m Register 0 1 0 0 0 reg AAA = ASCll Adjust for Add 0 0 1 1 0 1 1 1 DAA = Decimal Adjust for Add 0 0 1 0 0 1 1 1 SUB = Subtract: Register/Memory and Register to Either 0 0 1 0 1 0 d w mod reg r/m Immediate from Regis- ter/Memory 1 0 0 0 0 0 s w mod 1 0 1 r/m data data if s:w = 01 Immediate from Accumu- lator 0 0 1 0 1 1 0 w data data if w = 1 SBB = Subtract with Borrow Register/Memory and Register to Either 0 0 0 1 1 0 d w mod reg r/m Immediate from Regis- ter/Memory 1 0 0 0 0 0 s w mod 0 1 1 r/m data data if s:w = 01 Immediate from Accumu- lator 0 0 0 1 1 1 0 w data data if w = 1 DEC = Decrement: Register/Memory 1 1 1 1 1 1 1 w mod 0 0 1 r/m Register 0 1 0 0 1 reg NEG = Change Sign 1 1 1 1 0 1 1 w mod 0 1 1 r/m CMP = Compare: Register/Memory and Register 0 0 1 1 1 0 d w mod reg r/m Immediate with Regis- ter/Memory 1 0 0 0 0 0 s w mod 1 1 1 r/m data data if s:w = 01 Instruction Set Summary (Continued) MNEMONIC AND 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80C88

31 FN2949.4 February 22, 2008 Immediate with Accumu- lator 0 0 1 1 1 1 0 w data data if w = 1 AAS = ASCll Adjust for Subtract 0 0 1 1 1 1 1 1 DAS = Decimal Adjust for Subtract 0 0 1 0 1 1 1 1 MUL = Multiply (Un- signed) 1 1 1 1 0 1 1 w mod 1 0 0 r/m IMUL = Integer Multiply (Signed) 1 1 1 1 0 1 1 w mod 1 0 1 r/m AAM = ASCll Adjust for Multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 DlV = Divide (Unsigned) 1 1 1 1 0 1 1 w mod 1 1 0 r/m IDlV = Integer Divide (Signed) 1 1 1 1 0 1 1 w mod 1 1 1 r/m AAD = ASClI Adjust for Divide 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 CBW = Convert Byte to Word 1 0 0 1 1 0 0 0 CWD = Convert Word to Double Word 1 0 0 1 1 0 0 1 LOGIC NOT = Invert 1 1 1 1 0 1 1 w mod 0 1 0 r/m SHL/SAL = Shift Logi- cal/Arithmetic Left 1 1 0 1 0 0 v w mod 1 0 0 r/m SHR = Shift Logical Right 1 1 0 1 0 0 v w mod 1 0 1 r/m SAR = Shift Arithmetic Right 1 1 0 1 0 0 v w mod 1 1 1 r/m ROL = Rotate Left 1 1 0 1 0 0 v w mod 0 0 0 r/m ROR = Rotate Right 1 1 0 1 0 0 v w mod 0 0 1 r/m RCL = Rotate Through Carry Flag Left 1 1 0 1 0 0 v w mod 0 1 0 r/m RCR = Rotate Through Carry Right 1 1 0 1 0 0 v w mod 0 1 1 r/m AND = And: Reg./Memory and Regis- ter to Either 0 0 1 0 0 0 0 d w mod reg r/m Immediate to Regis- ter/Memory 1 0 0 0 0 0 0 w mod 1 0 0 r/m data data if w = 1 Immediate to Accumula- tor 0 0 1 0 0 1 0 w data data if w = 1 TEST = And Function to Flags, No Result: Register/Memory and Register 1 0 0 0 0 1 0 w mod reg r/m Immediate Data and Reg- ister/Memory 1 1 1 1 0 1 1 w mod 0 0 0 r/m data data if w = 1 Instruction Set Summary (Continued) MNEMONIC AND 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80C88

32 FN2949.4 February 22, 2008 Immediate Data and Ac- cumulator 1 0 1 0 1 0 0 w data data if w = 1 OR = Or: Register/Memory and Register to Either 0 0 0 0 1 0 d w mod reg r/m Immediate to Regis- ter/Memory 1 0 0 0 0 0 0 w mod 1 0 1 r/m data data if w = 1 Immediate to Accumula- tor 0 0 0 0 1 1 0 w data data if w = 1 XOR = Exclusive or: Register/Memory and Register to Either 0 0 1 1 0 0 d w mod reg r/m Immediate to Regis- ter/Memory 1 0 0 0 0 0 0 w mod 1 1 0 r/m data data if w = 1 Immediate to Accumula- tor 0 0 1 1 0 1 0 w data data if w = 1 STRING MANIPULA- TION REP = Repeat 1 1 1 1 0 0 1 z MOVS = Move Byte/Word 1 0 1 0 0 1 0 w CMPS = Compare Byte/Word 1 0 1 0 0 1 1 w SCAS = Scan Byte/Word 1 0 1 0 1 1 1 w LODS = Load Byte/Word to AL/AX 1 0 1 0 1 1 0 w STOS = Stor Byte/Word from AL/A 1 0 1 0 1 0 1 w CONTROL TRANSFER CALL = Call: Direct Within Segment 1 1 1 0 1 0 0 0 disp-low disp-high Indirect Within Segment 1 1 1 1 1 1 1 1 mod 0 1 0 r/m Direct Intersegment 1 0 0 1 1 0 1 0 offset-low offset-high seg-low seg-high Indirect Intersegment 1 1 1 1 1 1 1 1 mod 0 1 1 r/m Instruction Set Summary (Continued) MNEMONIC AND 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80C88

33 FN2949.4 February 22, 2008 JMP = Unconditional Jump: Direct Within Segment 1 1 1 0 1 0 0 1 disp-low disp-high Direct Within Segment- Short 1 1 1 0 1 0 1 1 disp Indirect Within Segment 1 1 1 1 1 1 1 1 mod 1 0 0 r/m Direct Intersegment 1 1 1 0 1 0 1 0 offset-low offset-high seg-low seg-high Indirect Intersegment 1 1 1 1 1 1 1 1 mod 1 0 1 r/m RET = Return from CALL: Within Segment 1 1 0 0 0 0 1 1 Within Seg Adding lmmed to SP 1 1 0 0 0 0 1 0 data-low data-high Intersegment 1 1 0 0 1 0 1 1 Instruction Set Summary (Continued) MNEMONIC AND 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80C88

34 FN2949.4 February 22, 2008 Intersegment Adding Im- mediate to SP 1 1 0 0 1 0 1 0 data-low data-high JE/JZ = Jump on Equal/Zero 0 1 1 1 0 1 0 0 disp JL/JNGE = Jump on Less/Not Greater or Equal 0 1 1 1 1 1 0 0 disp JLE/JNG = Jump on Less or Equal/ Not Greater 0 1 1 1 1 1 1 0 disp JB/JNAE = Jump on Be- low/Not Above or Equal 0 1 1 1 0 0 1 0 disp JBE/JNA = Jump on Be- low or Equal/Not Above 0 1 1 1 0 1 1 0 disp JP/JPE = Jump on Pari- ty/Parity Even 0 1 1 1 1 0 1 0 disp JO = Jump on Overflow 0 1 1 1 0 0 0 0 disp JS = Jump on Sign 0 1 1 1 1 0 0 0 disp JNE/JNZ = Jump on Not Equal/Not Zero 0 1 1 1 0 1 0 1 disp JNL/JGE = Jump on Not Less/Greater or Equal 0 1 1 1 1 1 0 1 disp JNLE/JG = Jump on Not Less or Equal/Greater 0 1 1 1 1 1 1 1 disp JNB/JAE = Jump on Not Below/Above or Equal 0 1 1 1 0 0 1 1 disp JNBE/JA = Jump on Not Below or Equal/Above 0 1 1 1 0 1 1 1 disp JNP/JPO = Jump on Not Par/Par Odd 0 1 1 1 1 0 1 1 disp JNO = Jump on Not Over- flow 0 1 1 1 0 0 0 1 disp JNS = Jump on Not Sign 0 1 1 1 1 0 0 1 disp LOOP = Loop CX Times 1 1 1 0 0 0 1 0 disp LOOPZ/LOOPE = Loop While Zero/Equal 1 1 1 0 0 0 0 1 disp LOOPNZ/LOOPNE = Loop While Not Ze- ro/Equal 1 1 1 0 0 0 0 0 disp JCXZ = Jump on CX Zero 1 1 1 0 0 0 1 1 disp INT = Interrupt Type Specified 1 1 0 0 1 1 0 1 type Type 3 1 1 0 0 1 1 0 0 INTO = Interrupt on Over- flow 1 1 0 0 1 1 1 0 IRET = Interrupt Return 1 1 0 0 1 1 1 1 PROCESSOR CONTROL Instruction Set Summary (Continued) MNEMONIC AND 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80C88

35 FN2949.4 February 22, 2008 CLC = Clear Carry 1 1 1 1 1 0 0 0 CMC = Complement Car- ry 1 1 1 1 0 1 0 1 STC = Set Carry 1 1 1 1 1 0 0 1 CLD = Clear Direction 1 1 1 1 1 1 0 0 STD = Set Direction 1 1 1 1 1 1 0 1 CLl = Clear Interrupt 1 1 1 1 1 0 1 0 ST = Set Interrupt 1 1 1 1 1 0 1 1 HLT = Halt 1 1 1 1 0 1 0 0 WAIT = Wait 1 0 0 1 1 0 1 1 ESC = Escape (to Exter- nal Device) 1 1 0 1 1 x x x mod x x x r/m LOCK = Bus Lock Prefix 1 1 1 1 0 0 0 0 Instruction Set Summary (Continued) MNEMONIC AND 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80C88

36 FN2949.4 February 22, 2008 NOTES: AL = 8-bit accumulator AX = 16-bit accumulator CX = Count register DS= Data segment ES = Extra segment Above/below refers to un- signed value. Greater = more positive; Less = less positive (more negative) signed values if d = 1 then “to” reg; if d = 0 then “from” reg if w = 1 then word instruc- tion; if w = 0 then byte instruction if mod = 11 then r/m is treated as a REG field if mod = 00 then DISP = 0†, disp-low and disp-high are absent if mod = 01 then DISP = disp-low sign-extended 16-bits, disp-high is ab- sent if mod = 10 then DISP = disp-high:disp-low if r/m = 000 then EA = (BX) + (SI) + DISP if r/m = 001 then EA = (BX) + (DI) + DISP if r/m = 010 then EA = (BP) + (SI) + DISP if r/m = 011 then EA = (BP) + (DI) + DISP if r/m = 100 then EA = (SI) + DISP if r/m = 101 then EA = (DI) + DISP if r/m = 110 then EA = (BP) + DISP † if r/m = 111 then EA = (BX) + DISP DISP follows 2nd byte of instruction (before data if required) † except if mod = 00 and r/m = 110 then EA = disp-high: disp- low. †† MOV CS, REG/MEM- ORY not allowed. if s:w = 01 then 16-bits of immediate data form the operand. if s:w = 11 then an immediate data byte is sign extended to form the 16-bit operand. if v = 0 then “count” = 1; if v = 1 then “count” in (C x = don't care z is used for string primitives for comparison with ZF FLAG. SEGMENT OVERRIDE PREFIX 001 reg 11 0 REG is assigned according to the following table: 16-BIT (w = 1) 8-BIT (w = 0) SEGMENT

000 AX 000 AL 00 ES

001 CX 001 CL 01 CS

010 DX 010 DL 10 SS

011 BX 011 BL 11 DS

100 SP 100 AH

101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file: FLAGS = X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF) Mnemonics © Intel, 1978 Instruction Set Summary (Continued) MNEMONIC AND 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80C88

37 FN2949.4 February 22, 2008 80C88 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.980 2.095 50.3 53.2 5 D1 0.005 - 0.13 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N4 0 4 0 9 Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2949.4 February 22, 2008 80C88 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead di mensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa CA - BM DS S eA F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)

40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 2.096 - 53.24 5 E 0.510 0.620 12.95 15.75 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N4 0 4 0 8 Rev. 0 4/94