CP3SP33SMS/NOPB

CP3SP33 TI1 | Alldatasheet

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www.ti.com SNOSCW5 –MAY 2013 ConnectivityProcessorwithCache,DSP,andBluetooth®,USB,andDualCANInterfaces Check forSamples: CP3SP33

1 Introduction

1.1 Features

– Two ACCESS.bus serialbus interfaces(I2C• CPU Features compatible)– FullystaticRISC processorcore,capableof – Two 8/16-bitSPI,Microwire/Plusserialoperatingfrom 0 to96 MHz withzero interfaceswait/holdstate – I2S digitalaudio bus interface– Minimum 10.4ns instructioncycletimewith a 96-MHz internalclockfrequency,based on – Four UniversalAsynchronous a 12-MHz externalinput Receiver/Transmitter(UART) channels,one channel has USART capability– 4K-byte,4-way set-associativeinstruction cache – Advanced Audio Interface(AAI)toconnect toexternal8/13-bitPCM Codecs as wellas– 69 independentlyvectoredperipheral toISDN-Controllersthrough theIOM-2interrupts interface(slaveonly)• DSP Features – Two CVSD/PCM converters,forsupporting– Capable ofoperatingup to96 MHz two bidirectionalaudio connectionsM– 16-bitfixed-pointarithmetic,dual-MAC • ExternalBus InterfaceShared Between CPUarchitecture and DSP– 32-bitinterfaceto4K-byteRAM shared with – 16/32-bitdatabusbus interfaceCPU – 23-bitaddress bus– 32-bitexternalbus interface – 3 programmable chipselectoutputs– Bus master interfacetoaudio peripherals – Up to96M bytesexternalmemoryand I/O – 8-levelwritebuffer• Memory

• General-PurposeHardware Peripherals– 4K bytesCPU instructioncache – 10-channel,10-bitA/D Converter(ADC)– 32K bytesCPU dataRAM – 16-channelDMA controller– 4K bytesCPU/DSP shared RAM – Dual 16-bitMulti-FunctionTimer (MFT)– 24K bytesDSP program RAM – Dual VersatileTimer Units(VTU),each with– 24K bytesDSP dataRAM fourindependenttimers– 8K bytesBluetooth® sequencer and data – Timing and Watchdog UnitRAM
• ExtensivePower and Clock Management– Addresses up to96M bytes(FBGA-224 Supportpackage) or 8M bytes(FBGA-144 package) of externalmemory – Two Phase Locked Loops (PLL)for synthesizingindependentsystem and audio• Broad Range ofHardware Communications peripheralclocksPeripherals – Two independentoscillatorsforActivemode– BluetoothLower LinkController(LLC) (12MHz) and Power Save mode (32.768kHz)includinga shared 7K byteBluetoothdata clocksRAM and 1K byteBluetoothSequencer RAM – Low-power modes (Power Save,Idle,and– UniversalSerialBus (USB) 2.0On-The-Go Halt)forslowingor stoppingclocksto– Audio/telematicscodec withdualADC optimizepower consumption whilemeetinginputsand high qualitystereoDAC output applicationneeds– Two CAN interfaceswith15 message buffers conforming toCAN specification2.0B active Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Bluetoothisa registeredtrademarkofBluethoothSIG,Inc. 3Teak isa registeredtrademarkofParthusCeva,Inc. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2013,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.

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• FlexibleI/O – Multi-fileC source editor,source debugger, and projectmanager– Up to64 general-purposeI/Opins(shared withon-chipperipheralI/O) – Comprehensive, integrated,one-stop technicalsupport– Programmable I/Opincharacteristics:TRI- STATE output,push-pulloutput,weak • BluetoothProtocolStack pullup/pulldowninput,high impedance – Applicationscan interfacetothehigh-level input,high-speeddrivecapability protocolsor directlytothelow-levelHost – Schmitttriggerson general-purposeinputs ControllerInterface(HCI) – Multi-InputWake-Up (MIWU) capability… – TransportlayersupportallowsHCI command-based interfaceover UART port• Power Supply – Baseband (LinkController)hardware– I/Oportoperationat3.0–3.3V minimizesthebandwidth demand on the– Core logicoperationat1.8V CPU– On-chip power-on reset – LinkManager (LM)• Temperature Range – LogicalLinkControland Adaptation– –40°C to+85°C (Industrial) Protocol(L2CAP)• Packages – ServiceDiscoveryProtocol(SDP)– FBGA-224, FBGA-144 – RFCOMM SerialPortEmulationProtocol• Complete Development Environment – Allpackettypes,piconet,and scatternet– Pre-integratedhardware and software functionalitysupportforrapidprototypingand production

1.2 CP3SP33 ConnectivityProcessor SelectionGuide

Speed On-Chip Maximum ExternalData General PackageNSID Temp. Range(MHz) RAM ExternalMemory Bus Width Purpose I/O Type CP3SP33SMS 96 –40°C to+85°C 32K 96M 32 64 FBGA-224 CP3SP33SMR 96 –40°C to+85°C 32K 8M 16 36 FBGA-144

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CPU Core AHB Bus (32-Bit)

12 MHz and 32 kHz

Seq. RAMCR16CPlus CPU Core with 4K Bytes Instr. Cache 32K Bytes Static RAM USB 2.0 On-The-Go Nexus Trace Module Teak DSP AHB Bus (32-Bit) Memory Interface Unit Teak 16-Bit Fixed-Point DSP 24K Bytes Data RAM DMA Controller 24K Bytes Program RAM X Y Z P External Bus Interface Unit 4K Bytes Shared RAM Peripheral Bus Controller Shared Audio Peripheral APB Bus (32-Bit)CPU Peripheral APB Bus (32-Bit) Peripheral Bus Controller Interrupt Control Unit Dual Versatile Timer Unit Dual Multi- Function Timer GPIO Multi-Input Wake-Up Microwire/ SPI 0 USART 0 UART 1/2 ACCESS .bus 0 UART 3ACCESS .bus 1 Microwire/ SPI 1 DS325 Telematics Codec Dual CVSD/PCM Converter Advanced Audio Interface I2S Interface Power M anagem ent Unit Timing and Watchdog Unit 10-Channel 10-Bit A/D Converter DMA Controller Dual CAN 2.0B Controller Real-Time Clock CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

2 Description

The CP3SP33 connectivityprocessorcombines highperformancewiththemassiveintegrationneeded for embedded Bluetoothapplications.A powerfulRISC corewith4Kbyteinstructioncache and a Teak® DSP coprocessorprovideshigh computing bandwidth,DMA-driven hardware communicationsperipherals providehighI/Obandwidth,and an externalbus providessystemexpandability. On-chipcommunicationsperipheralsinclude:BluetoothLower LinkController,UniversalSerialBus (2.0) OTG node and hostcontroller,dualCAN, dualMicrowire/Plus/SPI,dualACCESS.bus, quad UART, 10-bit A/D converter,and telematics/audiocodec.Additionalon-chipperipheralsincludeDMA controller,dual CVSD/PCM conversionmodule,I2S and AAI digitalaudiobus interfaces,Timingand Watchdog Unit,dual VersatileTimerUnit,dualMulti-FunctionTimer,and Multi-InputWake-Up (MIWU) unit. Inadditiontoprovidingthefeaturesneeded forthenextgenerationofembedded Bluetoothproducts,the CP3SP33 isbacked up by thesoftwareresourcesthatdesignersneed forrapidtime-to-market,including an operatingsystem,Bluetoothprotocolstackimplementation,peripheraldrivers,referencedesigns,and an integrateddevelopmentenvironment.Combined withan externalprogram memory and a Bluetooth radiotransceiversuch as National’s LMX5252, the CP3SP33 providesa complete Bluetoothsystem solution. NationalSemiconductoroffersa completeand industryprovenapplicationdevelopmentenvironmentfor CP3SP33 applications,includingtheIAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator,BluetoothDevelopmentBoard,Bluetoothprotocolstack,and applicationexamples.

2.1 Block Diagram

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3 Device Overview

The CP3SP33 connectivityprocessorisan advanced microcomputerwithsystem timing,interruptlogic, instructioncache,datamemory, and I/Oportsincludedon-chip,making itwell-suitedtoa wide range of embedded applications.The Section2.1shows themajoron-chipcomponents oftheCP3SP33.

3.1 CR16CPlus CPU Core

The CP3SP33 containsa CR16CPlus CPU core.Thiscoreimprovesupon theperformanceofprevious CP3000 devicesby addinga 4-Kbyteinstructioncache and doublingtheCPU coredatabus bandwidth. The cache greatlyreducesinstruction-fetchbandwidthon the32-bitsystem bus,which leavesmore bus bandwidthavailableforDMA-based I/O.The cache moves theaverageexecutionrateclosertothepeak rateof one instructionper clockcycle,especiallywhen executingfrom off-chipprogram memory. The DMA controllerprovidesefficientsharingof the CPU core bus between the CPU and high-bandwidth peripheralssuch as wiredand wirelesscommunicationinterfaces. For informationon theinstructionsetarchitecture,refertotheCR16C Programmer’s ReferenceManual (document number 424521772-101,which may be downloaded from Texas Instrumentsweb siteat http://www.ti.com).

3.2 Teak DSP Core

The Teak 16-bitfixed-pointDSP core isdesignedforlowpower,high-speeddigitalsignalprocessing applications,includingacousticecho cancellation,noisereduction,and MP3/WMA decoding.Itfeaturesa four-bus,dual-MAC,enhanced Harvardarchitecture.The DSP has 24K bytesofdedicatedprogram RAM, 24K bytesofdataRAM, and a 4K-byteRAM sharedwiththeCPU. The DSP has a bus masterinterfaceto the 4K-byteshared RAM and an externalmemory bus.Italsohas a bus master interfaceto a shared audio peripheralbus. The DSP isslaveon the CPU peripheralbus, fordownloadingsoftwareto the programRAM. The DSP has itsown DMA controllerforI/Oand memory access.

3.3 AMBA Bus Architecture

The CPU and DSP core buses implementAMBA-compatible AHB high-performance32-bitbuses with burstingand splittransactions.The CPU peripheralbus and CPU/DSP shared audio peripheralbus implementAMBA-compatible32-bitAPB buses.The CPU and DSP buses operateatindependentrates up to96 MHz. The APB buses operateata ratewhichisa factorof1,2,or4 slowerthantheCPU AHB bus.

3.4 ExternalBus InterfaceUnit

The ExternalBus InterfaceUnit(EBIU)providesprogrammabletiming,memory type,base address,size, and bus width(8,16,or32 bits)forthreeregionsofup to32M bytes.An 8-levelwritebufferreleasesthe bus mastertocontinueexecutionwithoutwaitingforwritecyclestocomplete.

3.5 Memory

The CP3SP33 devicessupporta uniformlinearaddressspace.Three typesofon-chipmemory occupy specificregionswithinthisaddressspace,alongwithany externalmemory:

• 32K bytesofCPU RAM
• 4K bytesofCPU/DSP sharedRAM
• 8K bytesofBluetoothsequencerand dataRAM
• Up to96M bytesofexternalmemory A non-volatileexternalprogrammemory isused tostoretheapplicationprogram,Bluetoothprotocolstack, and real-timeoperatingsystem. Copyright© 2013,Texas InstrumentsIncorporated DeviceOverview 7 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com The 32K bytesof CPU RAM are used fortemporarystorageof data and forthe program stackand interruptstack.Read and writeoperationscan be byte-wideor word-wide,dependingon theinstruction executedby theCPU.

3.6 BluetoothLLC

The integratedhardware BluetoothLower LinkController(LLC) compliesto the BluetoothSpecification Version1.2and integratesthefollowingfunctions:

• 7K-bytededicatedBluetoothdataRAM
• 1K-bytededicatedBluetoothsequencerRAM
• Supportof allBluetooth1.2 packettypesand extended Synchronous Connection-Oriented(eSCO) links
• Supportforfastfrequencyhoppingof1600 hops/s
• Access code correlationand slottimingrecoverycircuit
• Power Management ControlLogic
• BlueRF-compatibleinterface(mode 2/3)toconnectwithNational’s LMX5252 and otherRF transceiver chips

3.7 USB

The full-speedUniversalSerialBus (USB) node and hostcontrolleriscompatiblewithUSB Specification 2.0and USB On-The-Go.ItintegratestherequiredUSB transceiver,theSerialInterfaceEngine(SIE),and USB endpointFIFOs. A totalof seven endpointpipes are supported:one bidirectionalpipe forthe mandatorycontrolEP0 and an additionalsixpipesforunidirectionalendpointstosupportUSB interrupt, bulk,and isochronousdatatransfers. The on-chipUSB transceiverfeaturesan integratedpullupresistoron theD+ linetoUVCC. Thispullup resistorcan be switchedinor outby theUSB VBUS sense input(VBUS), which eliminatestheneed for externalcomponents.

3.8 CAN Interface

The two CAN modules supportFullCAN 2.0Bclass,CAN serialbus interfacesforapplicationsthatrequire a highspeed(upto1 Mbitspersecond)ora low-speedinterfacewithCAN bus mastercapability.The data transferbetween CAN and theCPU isestablishedby 15 memory-mapped message buffers,whichcan be individuallyconfiguredas receiveortransmitbuffers.An incomingmessage isfilteredby two masks, one forthefirst14 message buffersand anotherone forthe15thmessage buffertoprovidea basicCAN path. A prioritydecoderallowsany buffertohave thehighestor lowesttransmitpriority.Remote transmission requestscan be processedautomaticallyby automaticreconfigurationtoa receiveraftertransmissionor by automatedtransmitschedulingupon reception.Inaddition,a 16-bittimestamp countersupportsreal- timeapplications. The CAN modules allowsingle-cyclebyteorword read/writeaccess.A setofdiagnosticfeatures(suchas loopback,listenonly,and erroridentification)supportthedevelopmentwiththeCAN modules and provide a sophisticatederrormanagement tool. The CAN receiverscan triggera wake-up conditionoutoflow-powermodes throughtheMulti-InputWake- Up unit.

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3.9 Audio/TelematicsCodec

The on-chipcodec isdesignedforvoiceinputand stereoaudioplayback.Itincludesdualmono ADC channelsoperatingat a sample rateof 8–24 kHz (125× oversamplingclockrequired).A stereoDAC operatesatselectedsample ratesfroma 125× or128× oversamplingclock,drivingtwo configurable,gain- programmable differentiallinedriveroutputs.The DAC featuresclickand pop reduction,zero-crossing detection,tone/compensationfilter,sidetoneinjectionfromtheADC, and internalpower management. The ADCs acceptdifferentialor single-endedanalogmicrophoneinputs.The DAC employs fullydifferential signalingfor high PSRR and low crosstalk.DMA transfersare supportedto allow for fastCPU- independentreceiveand transmit.

3.10 CVSD/PCM Conversion Modules

The two CVSD/PCM modules performconversionbetween CVSD dataand PCM data,inwhichtheCVSD encodingisas definedintheBluetoothspecificationand thePCM datacan be 8-bitµ-Law,8-bitA-Law,or 13-bitto16-bitLinear.

3.11 I2S DigitalAudio Bus

The Inter-ICSound (I2S) interfaceisa synchronousserialinterfaceintendedforthe transferof digital audiodata.The I2S interfacecan be configuredas a masterora slave,and itsupportsallthreecommon dataformats:I2S-mode, left-justified,and right-justified.Ithas programmableword lengthfrom8 to32 bits and programmablevaliddataresolutionfrom8 to24 bits.

3.12 Advanced Audio Interface

The Advanced Audio Interface(AAI)providesa serialsynchronous,full-duplexinterfaceto codecs and similarserialdevices.Transmitand receivepaths operateasynchronouslywithrespectto each other. Each pathuses threesignalsforcommunication:shiftclock,framesynchronization,and data. When thereceiverand transmitteruse externalshiftclocksand framesync signals,theinterfaceoperates initsasynchronousmode. Alternatively,thetransmitand receivepathcan sharethesame shiftclockand framesyncsignalsforsynchronousmode operation.

3.13 Analog toDigitalConverter

Thisdevicecontainsa 10-channel,multiplexedinput,successiveapproximation,10-bitAnalog-to-Digital Converter.Itsupportsbothsingle-endedand differentialmodes ofoperation. The integrated10-bitADC providesthefollowingfeatures:

• 10-channel,multiplexedinput
• 5 differentialchannels
• Single-endedand differentialexternalfilteringcapability
• 12-bitresolution;10-bitaccuracy
• Signbit
• 10-microsecondconversiontime
• Externalstarttrigger
• Programmable startdelayafterstarttrigger
• Pollorinterrupton conversioncompletion The ADC providesseveraloptionsforthe voltagereferencesource.The positivereferencecan be ADVCC (internal),VREF, ADC0, or ADC1. The negativereferencecan be AD-VCC (internal),ADC2, or ADC3. Two specificanalogchannelselectionmodes aresupported.These areas follows:
• Allow any specificchannel to be selectedat one time.The A/D Converterperformsthe specific conversionrequestedand stops. Copyright© 2013,Texas InstrumentsIncorporated DeviceOverview 9 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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• Allowany differentialchannelpairtobe selectedatone time.The A/D Converterperformsthespecific differentialconversionrequestedand stops. In both single-endedand differentialmodes, thereisthe capabilityto connectthe analog multiplexer outputand A/D converterinputtoexternalpins.Thisprovidestheabilitytoexternallyconnecta common filter/signalconditioningcircuitfortheA/D Converter.

3.14 Quad UART

Four UART modules supporta wide range of programmable baud ratesand data formats,parity generation,and severalerrordetectionschemes. The baud rateisgeneratedon-chip,under software control.AllUART modules supportDMA and hardwareflowcontrol.One module has USART capability (synchronousmode).The maximum speed is3.072Mbaud ineithersynchronousorasynchronousmode. The UARTs offera wake-up conditionfromthelow-powermodes usingtheMulti-InputWake-Up module.

3.15 Microwire/SPI

The two Microwire/SPI(MWSPI) interfacemodules supportsynchronousserialcommunicationswithother devicesthatconformtoMicrowireorSerialPeripheralInterface(SPI)specifications.Itsupports8-bitand 16-bitdatatransfers.The maximum bus clockfrequencyis12 MHz. The Microwireinterfacesallowsseveraldevicestocommunicate overa singlesystem consistingoffour wires:serialin,serialout,shiftclock,and slaveenable.Atany giventime,theMicrowireinterfacesoperate as a master or a slave.The Microwireinterfacessupportsthe fullset of slaveselectformulti-slave implementation. Inmastermode, theshiftclockisgeneratedon-chipundersoftwarecontrol.Inslavemode, a wake-up out ofa low-powermode may be triggeredusingtheMulti-InputWakeUp module. 3.16 Dual ACCESS.BUS Interface The two ACCESS.bus (ACB) interfacemodules supporta two-wireserialinterfacecompatiblewiththe ACCESS.bus physicallayer.ItisalsocompatiblewithIntel’s System Management Bus (SMBus) and Philips’I2C bus.The ACB modules can be configuredas a bus masteror slave,and theycan maintain bidirectionalcommunicationswithboth multiplemaster and slavedevices.The maximum bus clock frequencyis400 kHz (Fast-mode). The ACCESS.bus receiverscan triggera wake-up conditionout of the low-powermodes throughthe Multi-InputWake-Up module.

3.17 Dual Multi-FunctionTimer

The two Multi-FunctionTimer (MFT) modules each containa pairof16-bittimer/counterregisters.Each timer/counterunitcan be configuredtooperateinany ofthefollowingmodes:

• Processor-IndependentPulseWidth Modulation(PWM) mode: Generatespulsesofa specifiedwidth and dutycycleand providesa general-purposetimer/counter.
• Dual InputCapture mode: Measures the elapsedtime between occurrencesof externalevent and providesa general-purposetimer/counter.
• Dual IndependentTimer mode: Generatessystem timingsignalsor countsoccurrencesof external events.
• SingleInputCaptureand SingleTimer mode: Providesone externaleventcounterand one system timer.

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3.18 VersatileTimer Units

The two VersatileTimer Unit(VTU) modules each containfourindependenttimersubsystems,which operateas a dual8-bitPWM configuration,a single16-bitPWM timer,or a 16-bitcounterwithtwo input capturechannels.Each of the timersubsystems offeran 8-bitclockprescalerto accommodate a wide rangeoffrequencies.

3.19 Timing and Watchdog Module

The Timingand Watchdog Module (TWM) containsa Real-Timetimerand a Watchdog unit.The Real- Time ClockTimingfunctioncan be used togenerateperiodicreal-timebased system interrupts.The timer outputisone of16 inputstotheMulti-InputWake-Up module whichcan be used toexitfroma low-power mode. The Watchdog unitisdesignedtodetecttheapplicationprogram gettingstuckinan infiniteloop resultinginlossof program controlor “runaway” programs.When the watchdog triggers,itresetsthe device.The TWM isclockedby thelow-speedSlow Clock.

3.20 Power Management

The Power Management Module (PMM) improvestheefficiencyofthedeviceby changingtheoperating mode and power consumptiontomatch therequiredlevelofactivity. The devicecan operateinany offourpower modes:

• Active:The deviceoperatesatfullspeed usingthehigh-frequencyclock.Alldevicefunctionsarefully operational.
• Power Save: The deviceoperatesat reduced speed using the Slow Clock.The CPU and some modules can continuetooperateatthislowspeed.
• Idle:The deviceisinactiveexceptforthe Power Management Module and Timing and Watchdog Module,whichcontinuetooperateusingtheSlow Clock.
• Halt:The deviceisinactivebutstillretainsitsinternalstate(RAM and registercontents). The PMM providesa mechanism tohandleBluetooth-specificpower management modes, foroptimizing power consumptionduringspecialBluetoothstates,likePark,Page Scan,InquiryScan,etc.

3.21 Multi-InputWake-up

The Multi-InputWake-Up (MIWU) featureisused toreturn(wake-up)thedevicefromlow-powermodes to theactivemode. The 64-channelMIWU unitreceiveswake-up signalsfrom variousinternaland external sources.Inadditiontothewake-up function,theMIWU unitcan generateup toeightinterruptrequests. Each MIWU channelcan be individuallyprogrammed toactivateone oftheinterruptrequests.

3.22 Input/OutputPorts

The devicehas 64 software-configurableI/Opins(36intheFBGA-144 package),organizedintofourports calledPortE, PortF, PortG, and PortH. Each pincan be configuredtooperateas a general-purpose inputor general-purposeoutput.In addition,many I/Opinscan be configuredto operateas inputsor outputsforon-chipperipheralmodules such as theUARTs ortimers. The I/O pin characteristicsare fullyprogrammable.Each pin can be configuredto operateas a TRI- STATE output,push-pulloutput,weak pullup/pulldowninput,high-speeddrive,orhigh-impedanceinput.

3.23 Clock and Reset Module

The Clockand Resetmodule generatesa 12-MHz Main Clockfroman externalcrystalnetworkorexternal clockin-put.Main Clockmay be used as a referenceclockfortwo PLL-based clockmultipliersavailable forgeneratinghigher-speedclocks. Copyright© 2013,Texas InstrumentsIncorporated DeviceOverview 11 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Most modules operatefrom clocksderivedfrom Main Clock or a PLL clock.Modules on the CPU core AHB bus operatefrom HCLK Clock,whilemodules on the peripheralAPB buses operatefrom PCLK Clock.PCLK Clockisgeneratedby dividingHCLK Clockby 1,2,or4.Some peripheralmodules may use one of severalauxiliaryclocks,which alsoare derivedfrom Main Clock or a PLL clockusing12-bit programmableprescalers. In Power-Save mode, HCLK Clock is drivenby Slow Clock,which is typicallya 32.768 kHz signal generatedfroman externalclocknetworkora prescaledMain Clockmay be used toeliminatethe32.768 kHz crystalnetwork,forthe most cost-sensitiveapplications.In the most power-sensitiveapplications, operationfroman external32.768kHz crystalnetworkallowsthehigh-frequencyoscillatorand PLLs tobe shutdown. Inaddition,theClockand Reset module generatesthedeviceresetby usingresetinputsignalscoming froman externalreset,thewatchdogtimer,ortheSDI debugginginterface.A power-onreset(POR) circuit eliminatestheneed foran externalRC network.The POR circuitgeneratesan internalresetofsufficient lengthifthepower supplyrisetimespecificationismet.

3.24 DMA Controller

The DirectMemory Access Controller(DMAC) can speed up data transferbetween memory and I/O devicesorbetween two regionsofmemory, as compared todatatransfersperformeddirectlyby theCPU. Cycle stealingallowsthe CPU and the DMAC to interleaveaccess to the CPU core bus forgreater utilizationof the availablebandwidth.The followingon-chipmodules can asserta DMA requestto the DMA controller:

• USART 0 (2requestchannels)
• UART 1/2/3(6requestchannels
• Advanced AudioInterface(6requestchannels)
• CVSD/PCM Converter0/1(8requestchannels)
• Microwire/SPI0/1(4requestchannels)
• ACCESS.bus 0/1(2requestchannels)
• Codec (4requestchannels)
• I2SInterface(4requestchannels) The DSP has itsown DMA controllerwhich can be configuredtoacceptDMA requestsfrom peripherals on thesharedaudioperipheralAPB bus.

3.25 SerialDebug Interface

The SerialDebug Interfacemodule (SDI module) providesa JTAG-based seriallinkto an external debugger,forexample runningon a PC. Inaddition,theSDI module integratesan on-chipdebug module, whichallowstheusertosetup toeighthardwarebreakpointson instructionexecutionand datatransfer. The SDI module can actas a CPU bus mastertoaccess allmemory-mapped resources,such as RAM and peripherals.Thereforeitalsoallowsforfastprogramcode downloadusingtheJTAG interface.

3.26 Development Support

Inadditiontoprovidingthefeaturesneeded forthenextgenerationofembedded Bluetoothproducts,the CP3SP33 devicesare backed up by the softwareresourcesthatdesignersneed forrapidproduct development,includingan operatingsystem,Bluetoothprotocolstackimplementation,peripheraldrivers, referencedesigns,and an integrateddevelopment environment.Combined withNational’s LMX5252 Bluetoothradiotransceiver,theCP3SP33 devicesprovidea totalBluetoothsystemsolution. Texas Instrumentsoffersa complete and industry-provenapplicationdevelopment environmentfor CP3SP33 applications,includingtheIAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator,BluetoothDevelopment Board,BluetoothProtocolStack,and ApplicationSoftware.See your Texas Instrumentssalesrepresentativeforcurrentinformationon availabilityand featuresof emulation equipmentand evaluationboards.

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32.768 kHz Crystal VCC RESET X1CKI X1CKO IOVCC XD[31:0] PE0/RXD0/TIO0_1 PE1/TXD0 PE4/CKX0/TIO0_2 ENV1/TSTCLK1 CP3SP33MS (FBGA-224)

12 MHz

PE11/MWCS0/TIO0_7 PH3/CAN0TX/TIO1_8 PE2/RTS0/TIO0_3 PE3/CTS0 TMS TDI TDO TCK RDY XCS0 XCS1 XOE XCS2 XWE XBE[3:0] CPU JTAG Interface GND Operating Environment UVCC UGND PLLVCC PLLGND XA[22:0] USART0/ VTU0 Microwire/Plus SPI 0 NMI ADC ADC[9:0] VREF PE6/CAN1RX PE7/CAN1TX PF7/ASYNC/TB0 PH2/CAN0RX/TIO1_7 PE13/IDPULLUP/TIO1_1 PE14/DRVVBUS/TIO1_3 IOGND ADVCC ADGND MCKO MSEO NEXUS Auxilliary Port and Teak DSP JTAG Interface SCL1 SDA1 TCADCVCC TCADCGND TCDACVCC TCDACGND TCVCM1 TCMIC1P ,TCMIC1N TCMIC2P ,TCMIC2N TCLP ,TCLN TCRP ,TCRN TCVCM2 TCVBUF1 TCVBUF2 TCVRFP TCVRFN DSPTMS/MDO0 DSPTDI/MDO1 DSPTDO/MDO2 DSPTCK/MDO3 VBUS PG4/MSK1 PG5/MDIDO1 PG6/MDODI1 PG7/MWCS1/TA1 PG14/RXD3/TB1 PG15/TXD3 PG10/SFS/TCIO1 PG11/STD/DIGMIC2 PG12/SRD PG13/SRCLK/CTS3 Microwire /Plus SPI 1 UART3 AAI PG8/SRFS/RTS3 PG9/SCK/DIGMIC1 PE15/IDDIG/TIO1_5 RFVCC RFGND CLKIN/RFCK External Bus Interface USB Codec RF Interface CAN0 CAN1 ACCESS.bus 1 Power Supply /4 /10 /4/12/12 /32 /23 Reset PF12/RXD2/TIO0_8 PF13/TXD2 PF14/RTS2/TIO1_2 PF15/CTS2 UART2 PH1/SDA0/TIO1_6 PE12/SCL0/TIO0_5 ACCESS .bus 0 PG0/I2SCLK PG1/I2SWS PG2/I2SSDI PG3/I2SSDO I2S PH0/TIO1_4VTU1 PH[15:4]WUI /12 /2/2/2/2 PF1/SCLK RFDA TA PF0/RFSYNC RFCE PF3/SLE PF4/BTSEQ1 PF2/SDA T PF5/BTSEQ2 PF6/BTSEQ3 PF8/RXD1/TIO0_4 PF9/TXD1 PF10/RTS1/TIO0_6 PF11/CTS1 UART1 VTU0 X2CKI X2CKO 32.768 kHz Crystal VCC RESET X1CKI X1CKO IOVCC XD[15:0] PE0/RXD0/TIO0_1 PE1/TXD0 ENV1/TSTCLK1 CP3SP33MR (FBGA-144)

12 MHz Crystal

PE11/MWCS0/TIO0_7 PH3/CAN0TX/TIO1_8 PE2/RTS0/TIO0_3 PE3/CTS0 TMS TDI TDO TCK RDY XCS0 XCS1 XOE XWE XBE[1:0] CPU JTAG Interface GND Operating Environment UVCC UGND PLLVCC PLLGND XA[20:0] USART0/ VTU0 Microwire /Plus SPI 0 NMI ADC ADC[1:0] PE6/CAN1RX PE7/CAN1TX PH2/CAN0RX/TIO1_7 PE13/IDPULLUP/TIO1_1 PE14/DRVVBUS/TIO1_3 IOGND ADVCC ADGND TCADCVCC TCADCGND TCDACVCC TCDACGND TCVCM1 TCMIC1P ,TCMIC1N TCMIC2P ,TCMIC2N TCLP ,TCLN TCRP ,TCRN TCVCM2 TCVBUF1 TCVBUF2 TCVRFP TCVRFN VBUS PE15/IDDIG/TIO1_5 RFVCC RFGND CLKIN/RFCK External Bus Interface USB Codec RF Interface CAN0 CAN1 Power Supply /4 /4/6/6 /16 /21 Reset PH1/SDA0/TIO1_6 PE12/SCL0/TIO0_5ACCESS.bus 0 PG0/I2SCLK PG1/I2SWS PG2/I2SSDI PG3/I2SSDO I2S PH[10:7]WUI /4 /2/2/2/2 PF1/SCLK RFDA TA PF0/RFSYNC RFCE PF3/SLE PF4/BTSEQ1 PF2/SDA T PF8/RXD1/TIO0_4 PF9/TXD1 PF10/RTS1/TIO0_6 PF11/CTS1 UART1 VTU0 CP3SP33 www.ti.com SNOSCW5 –MAY 2013

4 SignalDescriptions

Figure4-1.CP3SP33 Device Signals Some pinsmay be enabledas general-purposeI/O-portpinsor as alternatefunctionsassociatedwith specificperipheralsor interfaces.These pinsmay be individuallyconfiguredas portpins,even when the associatedperipheralorinterfaceisenabled. Table4-1 describesthedevicesignals.When thenumber ofsignalsdiffersbetween packages,thefirst number inthe Pins column isforthe FBGA-224 package and the second number isforthe FBGA-144 package. Copyright© 2013,Texas InstrumentsIncorporated SignalDescriptions 13 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table4-1.CP3SP33 SignalDescriptions ALTERNATENAME PINS I/O PRIMARY FUNCTION I/O ALTERNATE FUNCTIONNAME CLKIN 1 Input 12 MHz ClockInput RFCK Input RF InterfaceClock X1CKI 1 Input 12 MHz OscillatorInput None None None X1CKO 1 Output 12 MHz OscillatorOutput None None None X2CKI 1 Input 32 kHz OscillatorInput None None None X2CKO 1 Output 32 kHz OscillatorOutput None None None RESET 1 Input Chipgeneralreset None Input None Specialmode selectinputwithinternalENV0 1 Input TSTCLK0 Output InternalClockOutputpullupduringreset Specialmode selectinputwithinternalENV1 1 Input TSTCLK1 Output InternalClockOutputpullupduringreset VCC 4 Input Core Logic,1.8VPower Supply None None None GND 4 Input Core Ground None None None IOVCC 12/6 Input I/O3.3VPower Supply None None None IOGND 12/6 Input I/OGround None None None PLLVCC 1 Input PLL 1.8VPower Supply None None None PLLGND 1 Input PLL Ground None None None ADVCC 1 Input ADC 1.8VPower Supply None None None ADGND 1 Input ADC Ground None None None TCDACVC 1 Input Codec 3.3VPower Supply None None NoneC TCDACGN 1 Input Codec 3.3VGround None None NoneD TCADCVC 1 Input Codec 1.8VPower Supply None None NoneC TCADCGN 1 Input Codec 1.8VGround None None NoneD RFVCC 1 Input RF InterfacePower Supply None None None RFGND 1 Input RF InterfaceGround None None None UVCC 1 Input USB 3.3VTransceiverSupply None None None UGND 1 Input USB 3.3VTransceiverGround None None None CPU JTAG TestMode Select(withinternalTMS 1 Input None None Noneweak pullup) CPU JTAG TestClockInput(withinternalTCK 1 Input None None Noneweak pullup) CPU JTAG TestData Input(withinternalTDI 1 Input None None Noneweak pullup) TDO 1 Output CPU JTAG TestData Output None None None RDY 1 Output NEXUS Ready Output None None None MCKO 1/0 Output NEXUS TraceClockOutput None None None MSEO 1/0 Output NEXUS TraceEnd ofMessage Output None None None DSP JTAG TestMode Select(withinternalDSPTMS 1/0 Input MDO0 Output NEXUS TraceData Outputweak pullup) DSP JTAG TestData Input(withinternalDSPTDI 1/0 Input MDO1 Output NEXUS TraceData Outputweak pullup) DSPTDO 1/0 Output DSP JTAG TestData Output MDO2 Output NEXUS TraceData Output DSP JTAG TestClockInput(withinternalDSPTCK 1/0 Input MDO3 Output NEXUS TraceData Outputweak pullup) RFDATA 1 I/O RF InterfaceData None None None RFCE 1 Output RF InterfaceChipEnable None None None VBUS 1 Input USB VSENSE (5V tol.) None None None

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www.ti.com SNOSCW5 –MAY 2013 Table4-1.CP3SP33 SignalDescriptions(continued) ALTERNATENAME PINS I/O PRIMARY FUNCTION I/O ALTERNATE FUNCTIONNAME D+ 1 I/O USB D+ Upstream Port None None None D – 1 I/O USB D – Upstream Port None None None ADC0 1 Input ADC InputChannel0 None None None ADC1 1 Input ADC InputChannel1 None None None ADC2 1/0 Input ADC InputChannel2 None None None ADC3 1/0 Input ADC InputChannel3 None None None ADC4 1/0 Input ADC InputChannel4 MUXOUT0 Output AnalogMultiplexerOutput0 ADC5 1/0 Input ADC InputChannel5 MUXOUT1 Output AnalogMultiplexerOutput1 ADC6 1/0 Input ADC InputChannel6 None None None ADC7 1/0 Input ADC InputChannel7 ADCIN Input ADC Input(inMUX mode) ADC8 1/0 Input ADC InputChannel8 None None None ADC9 1/0 Input ADC InputChannel9 None None None VREF 1/0 Input ADC VoltageReference None None None Codec ADC1 ExternalFilterCapacitorPinTCVBUF1 1 Input None None None(1.5V) Codec ADC2 ExternalFilterCapacitorPinTCVBUF2 1 Input None None None(1.5V) Codec ADC1 ExternalFilterCapacitorPinTCVCM1 1 Input None None None(0.9V) Codec ADC2 ExternalFilterCapacitorPinTCVCM2 1 Input None None None(0.9V) Codec ADC1/ADC2 1.5VReference TCVRFP 1 Output (bufferedversiontoprovidemicrophone None None None bias) Codec ADC1/ADC2 ReferenceGroundTCVRFN 1 Input None None None(connectto0V) TCMIC1P 1 Input Codec Microphone1 Input(+) None None None TCMIC1N 1 Input Codec Microphone1 Input(–) None None None TCMIC2P 1 Input Codec Microphone2 Input(+) None None None TCMIC2N 1 Input Codec Microphone2 Input(–) None None None TCRP 1 Output Codec RightChannelOutput(+) None None None TCRN 1 Output Codec RightChannelOutput(–) None None None TCLP 1 Output Codec LeftChannelOutput(+) None None None TCLN 1 Output Codec LeftChannelOutput(–) None None None SCL1 1 I/O ACCESS.bus 1 Clock None None None SDA1 1 I/O ACCESS.bus 1 SerialData None None None RXD0 Input UART 0 ReceiveData Input PE0 1 I/O GenericI/O TIO0_1 I/O VersatileTimerUnit0 Input1 PE1 1 I/O GenericI/O TXD0 Output UART 0 TransmitData Output RTS0 Output UART 0 Ready-To-SendOutput PE2 1 I/O GenericI/O TIO0_3 I/O VersatileTimerUnit0 Input3 PE3 1 I/O GenericI/O CTS0 Input UART 0 Clear-To-SendInput CKX0 I/O UART 0 ClockInput PE4 1/0 I/O GenericI/O TIO0_2 I/O VersatileTimerUnit0 Input2 TA0 I/O Multi-FunctionTimer0 PortA PE5 1 I/O GenericI/O NMI Input Non-MaskableInterrupt PE6 1 I/O GenericI/O CAN1RX Input CAN 1 ReceiveInput PE7 1 I/O GenericI/O CAN1TX Output CAN 1 TransmitOutput PE8 1 I/O GenericI/O MSK0 I/O Microwire/SPI0 ShiftClock Copyright© 2013,Texas InstrumentsIncorporated SignalDescriptions 15 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table4-1.CP3SP33 SignalDescriptions(continued) ALTERNATENAME PINS I/O PRIMARY FUNCTION I/O ALTERNATE FUNCTIONNAME Microwire/SPI0 MasterInSlavePE9 1 I/O GenericI/O MDIDO0 I/O Out Microwire/SPI0 MasterOutPE10 1 I/O GenericI/O MDODI0 I/O SlaveIn Microwire/SPI0 SlaveSelectMWCS0 I/O InputPE11 1 I/O GenericI/O TIO0_7 I/O VersatileTimerUnit0 Input7 SCL0 I/O ACCESS.bus 0 Clock PE12 1 I/O GenericI/O TIO0_5 I/O VersatileTimerUnit0 Input5 IDPULLUP Output USB OTG ID PullupEnable PE13 1 I/O GenericI/O TIO1_1 I/O VersatileTimerUnit1 Input6 DRVVBUS Output USB OTG VBUS DriverEnable PE14 1 I/O GenericI/O TIO1_3 I/O VersatileTimerUnit1 Input3 IDDIG Input USB OTG ID Input PE15 1 I/O GenericI/O TIO1_5 I/O VersatileTimerUnit1 Input5 RF InterfaceFrequency PF0 1 I/O GenericI/O RFSYNC Output Correlation/DCCompensation Output PF1 1 I/O GenericI/O SCLK Output RF InterfaceShiftClockOutput PF2 1 I/O GenericI/O SDAT I/O RF InterfaceData PF3 1 I/O GenericI/O SLE Output RF InterfaceLoad Enable PF4 1 I/O GenericI/O BTSEQ1 Output BluetoothSequencerStatus PF5 1/0 I/O GenericI/O BTSEQ2 Output BluetoothSequencerStatus PF6 1/0 I/O GenericI/O BTSEQ3 Output BluetoothSequencerStatus ASYNC Input ADC ExternalStartTrigger PF7 1/0 I/O GenericI/O TB0 Input Multi-FunctionTimer0 PortB RXD1 Input UART 1 ReceiveData Input PF8 1 I/O GenericI/O TIO0_4 I/O VersatileTimerUnit0 Input4 PF9 1 I/O GenericI/O TXD1 Output UART 1 TransmitData Output RTS1 Output UART 1 Ready-To-SendOutput PF10 1 I/O GenericI/O TIO0_6 I/O VersatileTimerUnit6 Input6 PF11 1 I/O GenericI/O CTS1 Input UART 1 Clear-To-SendInput RXD2 Input UART 2 ReceiveData Input PF12 1/0 I/O GenericI/O TIO0_8 I/O VersatileTimerUnit0 Input8 PF13 1/0 I/O GenericI/O TXD2 Output UART 2 TransmitData Output RTS2 Output UART 2 Ready-To-SendOutput PF14 1/0 I/O GenericI/O TIO1_2 I/O VersatileTimerUnit1 Input2 PF15 1/0 I/O GenericI/O CTS2 Input UART 2 Clear-To-SendInput PG0 1 I/O GenericI/O I2SCLK I/O I2S SerialClock PG1 1 I/O GenericI/O I2SWS I/O I2S Word Select PG2 1 I/O GenericI/O I2SSDI Input I2S SerialData Input PG3 1 I/O GenericI/O I2SSDO Output I2S SerialData Output PG4 1/0 I/O GenericI/O MSK1 I/O Microwire/SPI1 ShiftClock Microwire/SPI1 MasterInSlavePG5 1/0 I/O GenericI/O MDIDO1 I/O Out Microwire/SPI1 MasterOutPG6 1/0 I/O GenericI/O MDODI1 I/O SlaveIn

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www.ti.com SNOSCW5 –MAY 2013 Table4-1.CP3SP33 SignalDescriptions(continued) ALTERNATENAME PINS I/O PRIMARY FUNCTION I/O ALTERNATE FUNCTIONNAME Microwire/SPI1 SlaveSelectMWCS1 I/O InputPG7 1/0 I/O GenericI/O TA1 I/O Multi-FunctionTimer1 PortA SRFS I/O AAI SerialReceiveFrame Sync PG8 1/0 I/O GenericI/O RTS3 Output UART 3 Ready-To-SendOutput SCK I/O AAI SerialTransmitClock PG9 1/0 I/O GenericI/O DIGMIC1 Input DigitalMicrophoneInput1 SFS I/O AAI SerialTransmitFrame Sync PG10 1/0 I/O GenericI/O TCIO1 I/O Codec GPIO STD Output AAI SerialTransmitData PG11 1/0 I/O GenericI/O DIGMIC2 Input DigitalMicrophoneInput2 PG12 1/0 I/O GenericI/O SRD Input AAI SerialReceiveData SRCLK I/O AAI SerialReceiveClock PG13 1/0 I/O GenericI/O CTS3 Input UART 3 Clear-To-SendInput RXD3 Input UART 3 ReceiveData Input PG14 1/0 I/O GenericI/O TB1 Input Multi-FunctionTimer1 PortB PG15 1/0 I/O GenericI/O TXD3 Output UART 3 TransmitData Output PH0 1/0 I/O GenericI/O TIO1_4 I/O VersatileTimerUnit1 Input4 SDA0 I/O ACCESS.bus 0 SerialData PH1 1 I/O GenericI/O TIO1_6 I/O VersatileTimerUnit1 Input6 CAN0RX Input CAN 0 ReceiveInput PH2 1 I/O GenericI/O TIO1_7 I/O VersatileTimerUnit1 Input7 CAN0TX Output CAN 0 TransmitOutput PH3 1 I/O GenericI/O TIO1_8 I/O VersatileTimerUnit1 Input8 PH4 1/0 I/O GenericI/O None None None PH5 1/0 I/O GenericI/O None None None PH6 1/0 I/O GenericI/O None None None PH7 1 I/O GenericI/O None None None PH8 1 I/O GenericI/O None None None PH9 1 I/O GenericI/O None None None PH10 1 I/O GenericI/O None None None PH11 1/0 I/O GenericI/O None None None PH12 1/0 I/O GenericI/O None None None PH13 1/0 I/O GenericI/O None None None PH14 1/0 I/O GenericI/O None None None PH15 1/0 I/O GenericI/O None None None XWE 1 Output ExternalBus WriteEnable None Output None XOE 1 Output ExternalBus OutputEnable None Output None XBE[3:0] 4/2 Output ExternalBus ByteEnables None Output None XCS[2:0] 3/2 Output ExternalBus ChipSelects None Output None XA[22:0] 23/21 Output ExternalAddressBus None Output None XD[31:0] 32/16 I/O ExternalData Bus None I/O None Copyright© 2013,Texas InstrumentsIncorporated SignalDescriptions 17 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Dedicated Address Registers 31 PC Processor Status Register PSR General-Purpose Registers 15 0 R10 R11 R12 R13 RA SP Configuration Register CFG ISPL USPL INTBASEL ISPH USPH INTBASEH DS004 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

5 CPU Architecture

The CP3SP33 uses the CR16CPlus third-generation16-bitCompactRISC processorcore.The CPU implementsa Reduced InstructionSet Computer (RISC) architecturethatallowsan effectiveexecution rateofup toone instructionperclockcycle.For a detaileddescriptionoftheCR16CPlus architecture,see theCompactRISC CR16C Programmer’s ReferenceManual which isavailableon theTexas Instruments web site(http://www.ti.com). The CR16CPlus CPU coreincludestheseinternalregisters:

• General-purposeregisters(R0-R13,RA, and SP)
• Dedicatedaddressregisters(PC,ISP,USP, and INTBASE)
• ProcessorStatusRegister(PSR)
• ConfigurationRegister(CFG) The R0-R11,PSR, and CFG registersare16 bitswide.The R12, R13, RA, SP, ISP and USP registersare 32 bitswide.The PC registeris24 bitswide.Figure5-1shows theCPU registers. Figure5-1.CPU Registers Some registerbitsaredesignatedas “reserved.”Softwaremust writea zerotothesebitlocationswhen it writestotheregister.Read operationsfromreservedbitlocationsreturnundefinedvalues.

5.1 General-PurposeRegisters

The CompactRISC CPU features16 general-purposeregisters.These registersare used individuallyas 16-bitoperandsoras registerpairsforoperationson addressesgreaterthan16 bits.

• General-purposeregistersaredefinedas R0 throughR13, RA, and SP.
• Registersare grouped intopairsbased on the settingof the ShortRegisterbitinthe Configuration Register(CFG.SR).When theCFG.SR bitisset,thegroupingofregisterpairsisupward-compatible withthearchitectureoftheearlierCR16A/B CPU cores:(R1,R0),(R2,R1)...(R11,R10),(R12_L,R11), (R13_L,R12_L),(R14_L,R13_L) and SP. (R14_L,R13_L) isthesame as (RA,ERA).
• When theCFG.SR bitisclear,registerpairsare grouped inthemanner used by nativeCR16CPlus software:(R1,R0),(R2,R1)...(R11,R10),(R12_L,R11),R12, R13, RA, SP. R12, R13, RA, and SP are 32-bitregistersforholdingaddressesgreaterthan16 bits.

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www.ti.com SNOSCW5 –MAY 2013 With the recommended callingconventionforthe architecture,some of these registersare assigned specialhardware and softwarefunctions.RegistersR0 to R13 are forgeneral-purposeuse, such as holdingvariables,addresses,or indexvalues.The SP registerholdsa pointerto the program run-time stack.The RA registerholdsa subroutinereturnaddress.The R12 and R13 registersareavailabletohold base addressesused intheindexaddressingmode. Ifa general-purposeregisterisspecifiedby an operationthatis8 bitslong,onlythe lowerbyteof the registerisused;the upper partisnot referencedor modified.Similarly,forword operationson register pairs,onlythelowerword isused.The upperword isnotreferencedormodified.

5.2 DedicatedAddress Registers

The CR16CPlus has fourdedicatedaddressregisterstoimplementspecificfunctions:thePC, ISP,USP, and INTBASE registers.

5.2.1 Program Counter (PC)Register

The 24-bitvalueinthe PC registerpointsto the firstbyteof the instructioncurrentlybeingexecuted. CR16CPlus instructionsare alignedto even addresses,thereforethe leastsignificantbitof the PC is always 0. At reset,the PC isinitializedto 0 or an optionalpredeterminedvalue.When a warm reset occurs,valueofthePC priortoresetissaved inthe(R1,R0)general-purposeregisterpair.

5.2.2 InterruptStack Pointer(ISP)

The 32-bitISP registerpointstothetopoftheinterruptstack.Thisstackisused by hardwaretoservice exceptions(interruptsand traps).The stackpointermay be accessedas theISP registerforinitialization. The interruptstackcan be locatedanywhere intheCPU addressspace.The ISP cannotbe used forany purposeotherthantheinterruptstack,whichisused forautomaticstorageoftheCPU registerswhen an exceptionoccursand restorationof these registerswhen the exceptionhandlerreturns.The interrupt stackgrows downward in memory. The leastsignificantbitand the 8 most significantbitsof the ISP registerarealways0.

5.2.3 User Stack Pointer(USP)

The USP registerpointstothetopoftheuser-modeprogram stack.Separatestacksareavailableforuser and supervisormodes, tosupportprotectionmechanisms formultitaskingsoftware.The processormode iscontrolledby theU bitinthePSR register(whichiscalledPSR.U intheshorthandconvention).Stack grow downward inmemory. Ifthe USP registerpointsto an illegaladdress(any addressgreaterthan 0x00FF_FFFF) and theUSP isused forstackaccess,an IAD trapistaken.

5.2.4 InterruptBase Register(INTBASE)

The INTBASE registerholdstheaddressofthedispatchtableforexceptions.The dispatchtablecan be locatedany where intheCPU addressspace.When loadingtheINTBASE register,bits31 to24 and bit0 must writtenwith0.

5.3 Processor StatusRegister(PSR)

15 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved I P E 0 N Z F 0 U L T C C The Carrybitindicateswhethera carryorborrowoccurredafteradditionorsubtraction. 0 – No carryorborrowoccurred. 1 – Carryorborrowoccurred. T The Tracebitenablesexecutiontracing,inwhicha Tracetrap(TRC) istakenaftereveryinstruction. Tracingisautomaticallydisabledduringtheexecutionofan exceptionhandler. 0 – Tracingdisabled. 1 – Tracingenabled. Copyright© 2013,Texas InstrumentsIncorporated CPU Architecture 19 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com L The Low bitindicatestheresultofthelastcomparisonoperation,withtheoperandsinterpretedas unsignedintegers. 0 – Second operandgreaterthanorequaltofirstoperand. 1 – Second operandlessthanfirstoperand. U The User Mode bitcontrolswhethertheCPU isinuserorsupervisormode. Insupervisormode, the SP registerisused forstackoperations.Inusermode, theUSP registerisused instead.User mode isenteredby executingtheJump USR instruction.When an exceptionistaken,theexception handlerautomaticallybeginsexecutioninsupervisormode. The USP registerisaccessibleusingthe Load ProcessorRegister(LPR/LPRD) instructioninsupervisormode. Inusermode, an attemptto accesstheUSP registergeneratesa UND trap.0 – CPU isexecutinginsupervisormode. 1 – CPU isexecutinginusermode. F The Flagbitisa generalconditionflagforsignalingexceptionconditionsordistinguishingtheresults ofan instruction,among otherthinguses.Forexample,integerarithmeticinstructionsuse theF bit toindicatean overflowconditionafteran additionorsubtractionoperation Z The Zerobitisused by comparisonoperations.Ina comparisonofintegers,theZ bitissetifthetwo operandsareequal.Iftheoperandsareunequal,theZ bitiscleared. 0 – Sourceand destinationoperandsunequal. 1 – Sourceand destinationoperandsequal. N The Negativebitindicatestheresultofthelastcomparisonoperation,withtheoperandsinterpreted as signedintegers. 0 – Second operandgreaterthanorequaltofirstoperand. 1 – Second operandlessthanfirstoperand. E The LocalMaskableInterruptEnablebitenablesordisablesmaskableinterrupts.Ifthisbitand the GlobalMaskableInterruptEnable(I)bitarebothset,allinterruptsareenabled.Ifeitherofthesebits isclear,onlythenonmaskableinterruptisenabled.The E bitissetby theEnableInterrupts(EI) instructionand clearedby theDisableInterrupts(DI)instruction. 0 – Maskableinterruptsdisabled. 1 – Maskableinterruptsenabled. P The TraceTrapPendingbitisused togetherwiththeTrace(T)bittopreventa Trace(TRC) trap fromoccurringmore thanonce forone instruction.Atthebeginningoftheexecutionofan instruction,thestateoftheT bitiscopiedintotheP bit.IftheP bitremainssetattheend ofthe instructionexecution,theTRC trapistaken. 0 – No tracetrappending. 1 – Tracetrappending. I The GlobalMaskableInterruptEnablebitisused toenableordisablemaskableinterrupts.Ifthisbit and theLocalMaskableInterruptEnable(E)bitarebothset,allmaskableinterruptsaretaken.If eitherbitisclear,onlythenon-maskableinterruptistaken.UnliketheE bit,theIbitisautomatically clearedwhen an interruptoccursand automaticallysetupon completionofan interrupthandler. 0 – Maskableinterruptsdisabled. 1 – Maskableinterruptsenabled. BitsZ, C, L, N, and F of the PSR are referencedfrom assembly language by the conditioncode in conditionalbranchinstructions.A conditionalbranchinstructionmay cause a branchinprogramexecution, based on thevalueofone or more ofthesePSR bits.For example,one oftheBcond instructions,BEQ (BranchEQual),causesa branchifthePSR.Z bitisset. On reset,bits0 through11 ofthePSR arecleared,exceptforthePSR.E bit,whichisset.On warm reset, thevaluesofeach bitbeforeresetare copiedintotheR2 general-purposeregister.Bits4 and 8 ofthe PSR have a constantvalueof0.Bits12 through15 arereserved.Ingeneral,statusbitsaremodifiedonly by specificinstructions.Otherwise,statusbitsmaintaintheirvaluesthroughoutinstructionswhich do not implicitlyaffectthem.

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5.4 ConfigurationRegister(CFG)

The CFG registerisused to enableor disablevariousoperatingmodes and to controloptionalon-chip caches.AllCFG bitsareclearedon reset. 15 10 9 8 7 6 5 4 3 2 1 0 Reserved SR ED 0 0 LIC IC Reserved 0 0 IC The InstructionCache bitcontrolswhetherthe4K-byteinstructioncache isenabledforsatifying instructionfetchesby theCPU. When theinstructioncache isdisabled,everyinstructionfetchis propagatedtotheCPU corebus.Disablingthecache automaticallyinvalidatesallofthecache entries.When thecache isenabled,instructionfetchesthatarecache hitsdo notresultinbus cycleson theCPU corebus. 0 – Instructioncache disabled. 1 – Instructioncache enabled. LIC The Lock InstructionCache bitcontrolswhetherthe4K-byteinstructioncache islocked.When the instructioncache islocked,no new entriesareallocatedas a resultofcache misses,however cache hitscontinuetobe handledby thecache. 0 – Instructioncache isnotlocked. 1 – Instructioncache islocked. ED The ExtendedDispatchbitselectswhetherthesizeofan entryintheinterruptdispatchtable(IDT) is16 or32 bits.Each entryholdstheaddressoftheappropriateexceptionhandler.When theIDT has 16-bitentries,and allexceptionhandlersmust resideinthefirst128K oftheaddressspace. The locationoftheIDT isheldintheINTBASE register,whichisnotaffectedby thestateofthe ED bit. 0 – Interruptdispatchtablehas 16-bitentries. 1 – Interruptdispatchtablehas 32-bitentries. SR The ShortRegisterbitenablesa compatibilitymode fortheCR16B largemodel.IntheCR16CPlus core,registersR12, R13, and RA areextendedto32 bits.IntheCR16B largemodel,onlythe lower16 bitsoftheseregistersareused,and these“shortregisters”arepairedtogetherfor32-bit operations.Inthismode, the(RA,R13) registerpairisused as theextendedRA register,and addressdisplacementsrelativetoa singleregisteraresupportedwithoffsetsof0 and 14 bitsin placeoftheindexaddressingwiththesedisplacements. 0 – 32-bitregistersareused. 1 – 16-bitregistersareused (CR16B mode).

5.5 Addressing Modes

The CR16CPlus CPU core implements a load/storearchitecture,in which arithmeticand logical instructionsoperateon registeroperands.Memory operandsaremade accessibleinregistersusingload and store instructions.For effIcientimplementationof I/O-intensiveembedded applications,the architecturealsoprovidesa setofbitoperationsthatoperateon memory operands. The load and storeinstructionssupportthese addressingmodes: register/pair,immediate,relative, absolute,and indexaddressing.When registerpairsare used, the lowerbitsare in the lowerindex registerand the upper bitsare inthe higherindexregister.When the CFG.SR bitisclear,the 32-bit registersR12, R13, RA, and SP arealsotreatedas registerpairs. Referencesto registerpairsin assembly language use parentheses.With a registerpair,the lower numbered registerpairmust be on theright.Forexample, jump (r5,r4) load$4(r4,r3),(r6,r5) load$5(r12),(r13) The instructionsetsupportsthefollowingaddressingmodes: Copyright© 2013,Texas InstrumentsIncorporated CPU Architecture 21 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Register/Pair Inregister/pairmode, theoperandisheldina general-purposeregister,orina general- Mode purposeregisterpair.Forexample,thefollowinginstructionadds thecontentsofthe lowbyteofregisterr1tothecontentsofthelowbyteofr2,and placestheresultinthe lowbyteregisterr2.The highbyteofregisterr2isnotmodified. ADDB R1, R2 Immediate Inimmediatemode, theoperandisa constantvaluewhichisencoded intheinstruction. Mode Forexample,thefollowinginstructionmultipliesthevalueofr4by 4 and placesthe resultinr4. MULW $4,R4 RelativeMode Inrelativemode, theoperandisaddressedusinga relativevalue(displacement) encoded intheinstruction.ThisdisplacementisrelativetothecurrentProgram Counter (PC),a general-purposeregister,ora registerpair. Inbranchinstructions,thedisplacementisalwaysrelativetothecurrentvalueofthePC Register.Forexample,thefollowinginstructioncausesan unconditionalbranchtoan address10 ahead ofthecurrentPC. BR *+10 Inanotherexample,theoperandresidesinmemory. Itsaddressisobtainedby addinga displacementencoded intheinstructiontothecontentsofregisterr5.The address calculationdoes notmodifythecontentsofregisterr5. LOADW 12(R5),R6 The followingexample calculatestheaddressofa sourceoperandby addinga displacementof4 tothecontentsofa registerpair(r5,r4)and loadsthisoperandinto theregisterpair(r7,r6).r7receivesthehighword oftheoperand,and r6receivesthe lowword. LOADD 4(r5,r4),(r7,r6) IndexMode Inindexmode, theoperandaddressiscalculatedwitha base addressheldineither R12 orR13. The CFG.SR bitmust be cleartouse thismode.

• Forrelativemode operands,thememory addressiscalculatedby addingthe valueofa registerpairand a displacementtothebase address.The displacement can be a 14 or20-bitunsignedvalue,whichisencoded intheinstruction.
• Forabsolutemode operands,thememory addressiscalculatedby addinga 20-bit absoluteaddressencoded intheinstructiontothebase address. Inthefollowingexample,theoperandaddressisthesum ofthedisplacement4,the contentsoftheregisterpair(r5,r4),and thebase addressheldinregisterr12.The word atthisaddressisloadedintoregisterr6. LOADW [r12]4(r5,r4),r6 Absolute Inabsolutemode, theoperandislocatedinmemory, and itsaddressisencoded inthe Mode instruction(normally20 or24 bits). Forexample,thefollowinginstructionloadsthebyteataddress4000 intothelower8 bitsofregisterr6. LOADB 4000,r6 Foradditionalinformationon theaddressingmodes, see theCompactRISC CR16C Programmer's ReferenceManual.

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5.6 Stacks

A stackisa last-in,first-outdatastructurefordynamic storageofdataand addresses.A stackconsistsof a blockofmemory used toholdthedataand a pointertothetopofthestack.As more dataispushed ontoa stack,thestackgrows downward inmemory. The CR16CPlus supportstwo typesofstacks:the interruptstackand programstacks.

5.6.1 InterruptStack

The processoruses the interruptstackto save and restorethe program stateduringthe exception handling.Hardware automaticallypushes thisdataontotheinterruptstackbeforeenteringan exception handler.When the exceptionhandlerreturns,hardware restoresthe processorstatewithdata popped fromtheinterruptstack.The interruptstackpointerisheldintheISP register.

5.6.2 Program Stack

The program stackisnormallyused by softwaretosave and restoreregistervalueson subroutineentry and exit,holdlocaland temporaryvariables,and holdparameterspassed between thecallingroutineand thesubroutine.The onlyhardwaremechanisms whichoperateon theprogram stackarethePUSH, POP, and POPRET instructions.

5.6.3 User and SupervisorStack Pointers

To supportmultitaskingoperatingsystems,supportisprovidedfortwo program stackpointers:a user stackpointerand a supervisorstackpointer.When thePSR.U bitisclear,theSP registerisused forall program stackoperations.Thisisthedefaultmode when theuser/supervisorprotectionmechanism isnot used,and itisthesupervisormode when protectionisused. When thePSR.U bitisset,theprocessorisinusermode, and theUSP registerisused as theprogram stackpointer.User mode can onlybe enteredusingtheJUSR instruction,whichperformsa jump and sets the PSR.U bit.User mode isexitedwhen an exceptionistaken and re-enteredwhen the exception handlerreturns.In user mode, the LPRD instructioncannotbe used to change the stateof processor registers(suchas thePSR).

5.7 InstructionSet

Table5-1liststheoperandspecifiersfortheinstructionset,and Table3 isa summary ofallinstructions. Foreach instruction,thetableshows themnemonic and a briefdescriptionoftheoperationperformed. Inthemnemonic column,thelower-caseletter“i”isused toindicatethetypeofintegerthattheinstruction operateson,either“B” forbyteor “W ” forword.For example,thenotationADDi forthe“add” instruction means thattherearetwo formsofthisinstruction,ADDB and ADDW, whichoperateon bytesand words, respectively. Similarly,thelower-casestring“cond” isused toindicatethetypeofconditiontestedby theinstruction. For example,the notationJcond representsa classof conditionaljump instructions:JEQ forJump on Equal,JNE forJump on Not Equal,etc.For detailedinformationon allinstructions,see theCompactRISC CR16C Programmer'sReferenceManual. Table5-1.Key toOperand Specifiers OPERAND SPECIFIER DESCRIPTION abs Absoluteaddress disp Displacement(numericsuffixindicatesnumber ofbits) imm Immediateoperand(numericsuffixindicatesnumber ofbits) Iposition Bitpositioninmemory Rbase Base register(relativemode) Rdest Destinationregister Copyright© 2013,Texas InstrumentsIncorporated CPU Architecture 23 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table5-1.Key toOperand Specifiers(continued) OPERAND SPECIFIER DESCRIPTION Rindex Indexregister RPbase, RPbasex Base registerpair(relativemode) RPdest Destinationregisterpair RPlink Linkregisterpair Rposition Bitpositioninregister Rproc 16-bitprocessorregister Rprocd 32-bitprocessorregister RPsrc Sourceregisterpair RPtarget Targetregisterpair Rsrc,Rsrc1,Rsrc2 Sourceregister Table5-2.InstructionSet Summary MNEMONIC OPERANDS DESCRIPTION MOVi Rsrc/imm,Rdest Move MOVXB Rsrc,Rdest Move withsignextension MOVZB Rsrc,Rdest Move withzeroextension MOVXW Rsrc,RPdest Move withsignextension MOVZW Rsrc,RPdest Move withzeroextension MOVD imm, RPdest Move immediatetoregister-pair RPsrc,RPdest Move between register-pairs ADD[U]i Rsrc/imm,Rdest Add ADDCi Rsrc/imm,Rdest Add withcarry ADDD RPsrc/imm,RPdest Add withRP orimmediate. MACQWa Rsrc1,Rsrc2,RPdest MultiplysignedQ15: M RPdest :=RPdest + (Rsrc1× Rsrc2) MACSWa Rsrc1,Rsrc2,RPdest Multiplysignedand add result:M RPdest :=RPdest + (Rsrc1× Rsrc2) MACUWa Rsrc1,Rsrc2,RPdest Multiplyunsignedand add result:M RPdest :=RPdest + (Rsrc1× Rsrc2) MULi Rsrc/imm,Rdest Multiply:Rdest(8):=Rdest(8)× Rsrc(8)/imm Rdest(16):=Rdest(16)× Rsrc(16)/imm MULSB Rsrc,Rdest Multiply:Rdest(16):=Rdest(8)× Rsrc(8) MULSW Rsrc,RPdest Multiply:RPdest :=RPdest(16)× Rsrc(16) MULUW Rsrc,RPdest Multiply:RPdest :=RPdest(16)× Rsrc(16); SUBi Rsrc/imm,Rdest Subtract:(Rdest:=RdestRsrc/imm) SUBD RPsrc/imm,RPdest Subtract:(RPdest:=RPdest RPsrc/imm) SUBCi Rsrc/imm,Rdest Subtractwithcarry:(Rdest:=RdestRsrc/imm) CMPi Rsrc/imm,Rdest Compare RdestRsrc/imm CMPD RPsrc/imm,RPdest Compare RPdest RPsrc/imm BEQ0i Rsrc,disp Compare Rsrcto0 and branchifEQUAL BNE0i Rsrc,disp Compare Rsrcto0 and branchifNOT EQUAL ANDi Rsrc/imm,Rdest LogicalAND: Rdest:=Rdest& Rsrc/imm ANDD RPsrc/imm,RPdest LogicalAND: RPdest :=RPsrc & RPsrc/imm ORi Rsrc/imm,Rdest LogicalOR: Rdest:=Rdest|Rsrc/imm ORD RPsrc/imm,RPdest LogicalOR: Rdest:=RPdest |RPsrc/imm Scond Rdest Save conditioncode as boolean XORi Rsrc/imm,Rdest LogicalexclusiveOR: Rdest:=Rdest^ Rsrc/imm XORD RPsrc/imm,RPdest LogicalexclusiveOR: Rdest:=RPdest ^ RPsrc/imm ASHUi Rsrc/imm,Rdest Arithmeticleft/rightshift ASHUD Rsrc/imm,RPdest Arithmeticleft/rightshift

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www.ti.com SNOSCW5 –MAY 2013 Table5-2.InstructionSet Summary (continued) MNEMONIC OPERANDS DESCRIPTION LSHi Rsrc/imm,Rdest Logicalleft/rightshift LSHD Rsrc/imm,RPdest Logicalleft/rightshift SBITi Iposition,disp(Rbase) Seta bitinmemory (Becausethisinstructiontreatsthedestinationas a readmodify-writeoperand,itIposition,disp(RPbase) notbe used tosetbitsinwrite-onlyregisters.) Iposition,(Rindex)disp(RPbasex) Iposition,abs Iposition,(Rindex)abs CBITi Iposition,disp(Rbase) Cleara bitinmemory Iposition,disp(RPbase) Iposition,(Rindex)disp(RPbasex) Iposition,abs Iposition,(Rindex)abs TBIT TBITi Rposition/imm,Rsrc Testa bitina register Testa bitinmemoryIposition,disp(Rbase) Iposition,disp(RPbase) Iposition,(Rindex)disp(RPbasex) Iposition,abs Iposition,(Rindex)abs LPR Rsrc,Rproc Load processorregister LPRD RPsrc,Rprocd Load doubleprocessorregister SPR Rproc,Rdest Storeprocessorregister SPRD Rprocd,RPdest Store32-bitprocessorregister Bcond disp9 Conditionalbranch disp17 disp24 BAL RPlink,disp24 Branchand link BR disp9 Branch disp17 disp24 EXCP vector Trap(vector) Jcond RPtarget ConditionalJump toa largeaddress JAL RA, RPtarget, Jump and linktoa largeaddress RPlink,RPtarget JUMP RPtarget Jump JUSR RPtarget Jump and setPSR.U RETX Returnfromexception PUSH imm, Rsrc,RA Push “imm ”number ofregisterson userstack,startingwithRsrcand possibly includingRA POP imm, Rdest,RA Restore“imm ”number ofregistersfromuserstack,startingwithRdestand possiblyincludingRA POPRET imm, Rdest,RA Restoreregisters(similartoPOP) and JUMP RA LOADi disp(Rbase),Rdest Load (registerrelative) abs,Rdest Load (absolute) (Rindex)abs,Rdest Load (absoluteindexrelative) (Rindex)disp(RPbasex),Rdest Load (registerrelativeindex) disp(RPbase),Rdest Load (registerpairrelative) Copyright© 2013,Texas InstrumentsIncorporated CPU Architecture 25 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table5-2.InstructionSet Summary (continued) MNEMONIC OPERANDS DESCRIPTION LOADD disp(Rbase),Rdest Load (registerrelative) abs,Rdest Load (absolute) (Rindex)abs,Rdest Load (absoluteindexrelative) (Rindex)disp(RPbasex),Rdest Load (registerpairrelativeindex) disp(RPbase),Rdest Load (registerpairrelative) STORi Rsrc,disp(Rbase) Store(registerrelative) Rsrc,disp(RPbase) Store(registerpairrelative) Rsrc,abs Store(absolute) Rsrc,(Rindex)disp(RPbasex) Store(registerpairrelativeindex) Rsrc,(Rindex)abs Store(absoluteindex) STORD RPsrc,disp(Rbase) Store(registerrelative) RPsrc,disp(RPbase) Store(registerpairrelative) RPsrc,abs Store(absolute) RPsrc,(Rindex)disp(RPbasex) Store(registerpairindexrelative) RPsrc,(Rindex)abs Store(absoluteindexrelative) STOR IMM imm4, disp(Rbase) Storeunsigned4-bitimmediatevalueextendedtooperandlengthinmemory imm4, disp(RPbase) imm4, (Rindex)disp(RPbasex) imm4, abs imm4, (Rindex)abs LOADM imm3 Load 1 to8 registers(R2-R5,R8-R11) frommemory startingat(R0) LOADMP imm3 Load 1 to8 registers(R2-R5,R8-R11) frommemory startingat(R1,R0) STORM STORM imm3 Store1 to8 registers(R2-R5,R8-R11) tomemory startingat(R2) STORMP imm3 Store1 to8 registers(R2-R5,R8-R11) tomemory startingat(R7,R6) DI Disablemaskableinterrupts EI Enablemaskableinterrupts EIWAIT Enablemaskableinterruptsand waitforinterrupt NOP No operation WAIT Waitforinterrupt CINV [i] Invalidateinstructioncache

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6 Memory

The CP3SP33 supportsa uniform256M-bytelinearaddressspace.Program memory must resideinthe first16M bytesoftheaddressspace.Table6-1liststhetypesofmemory and peripheralsthatoccupy this memory space.Reservedaddressesmust notbe readorwritten. Table6-1.CP3SP33 Memory Map START ADDRESS END ADDRESS SIZE IN BYTES DESCRIPTION 0000 0000h 0000 7FFFh 32K System RAM 0000 8000h 0000 FFFFh 32K Reserved 0001 0000h 0001 0FFFh 4K CPU/DSP Shared RAM 0001 1000h 0001 1FFFh 4K Reserved 0001 2000h 0001 207Fh 128 BluetoothRegisters 0001 2080h 0001 20FFh 128 Reserved 0001 2100h 0001 24FFh 1K BluetoothSequencerRAM 0001 2500h 0001 3DBFh 6336 BluetoothData RAM (SharedRAM) 0001 3DC0h 0001 FFFFh 49,728 Reserved 0002 0000h 00FE FFFFh 16M 192K AvailableforExternalBus Devices 00FF 0000h 00FF 03FFh 1K ExternalBus InterfaceUnitRegisters 00FF 0400h 00FF 07FFh 1K DMA ControllerRegisters 00FF 0800h 00FF 0FFFh 2K USB Controller 00FF 1000h 00FF 3FFFh 12K Reserved 00FF 4000h 00FF 43FFh 1K I2SDigitalAudioInterface 00FF 4400h 00FF 47FFh 1K AudioCodec 00FF 4800h 00FF 4BFFh 1K CVSD/PCM Converter0 00FF 4C00h 00FF 4FFFh 1K CVSD/PCM Converter1 00FF 5000h 00FF 53FFh 1K Advanced AudioInterface 00FF 5400h 00FF 57FFh 1K ACCESS.bus 1 Interface 00FF 5800h 00FF 5BFFh 1K Microwire/SPI1 Interface 00FF 5C00h 00FF 5FFFh 1K UART3 00FF 6000h 00FF 63FFh 1K Multi-FunctionTimer1 00FF 6400h 00FF 67FFh 1K PortG 00FF 6800h 00FF 6BFFh 1K AudioSubsystem Controller 00FF 6C00h 00FF 7FFFh 5K Reserved 00FF 8000h 00FF 83FFh 1K ACCESS.bus 0 Interface 00FF 8400h 00FF 87FFh 1K Microwire/SPI0 Interface 00FF 8800h 00FF 8BFFh 1K VersatileTimerUnit0 00FF 8C00h 00FF 8FFFh 1K VersatileTimerUnit1 00FF 9000h 00FF 93FFh 1K Multi-FunctionTimer0 00FF 9400h 00FF 97FFh 1K USART0 00FF 9800h 00FF 9BFFh 1K UART1 00FF 9C00h 00FF 9FFFh 1K UART2 00FF A000h 00FF A3FFh 1K Timingand Watchdog Module 00FF A400h 00FF A7FFh 1K Power Management Module 00FF A800h 00FF ABFFh 1K Real-TimeClock 00FF AC00h 00FF AFFFh 1K Analog/DigitalConverter 00FF B000h 00FF B7FFh 2K Reserved 00FF B800h 00FF BBFFh 1K CAN0 Buffersand Registers 00FF BC00h 00FF BFFFh 1K CAN1 Buffersand Registers 00FF C000h 00FF C3FFh 1K Multi-InputWake-Up Unit Copyright© 2013,Texas InstrumentsIncorporated Memory 27 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Line 0 Entry 0 Entry 1 Entry 2 Entry 3 Line 1 Entry 4 Entry 5 Entry 6 Entry 7 Line 63 Entry 252 Entry 253 Entry 254 Entry 255 Way 0 Way 1 Way 2 Way 3 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Table6-1.CP3SP33 Memory Map (continued) START ADDRESS END ADDRESS SIZE IN BYTES DESCRIPTION 00FF C400h 00FF C7FFh 1K PortE 00FF C800h 00FF CBFFh 1K PortF 00FF CC00h 00FF CFFFh 1K PortH 00FF D000h 00FF EBFFh 7K Reserved 00FF EC00h 00FF EFFFh 1K Teak Access Port 00FF F000h 00FF F3FFh 1K Reserved 00FF F400h 00FF F7FFh 1K System Configuration 00FF F800h 00FF FBFFh 1K Reserved 00FF FC00h 00FF FFFFh 1K InterruptControlUnit(registersstartat00FF FE00h) 0100 0000h FFFF FFFFh 4G 16M AvailableforExternalBus Devices(dataspace only)

7 InstructionCache

The CPU instructioncache has thefollowingfeatures:

• 4K bytesdatamemory
• 4-way set-associativeorganization
• Criticalword first,withwrappingcache entryfill
• Pseudo LeastRecentlyUsed (PLRU) allocationpolicy
• Cache lockingsupport
• Cache invalidationsupport The instructioncache isenabledby settingtheIC bitintheCFG register.At reset,thecache isdisabled by default.When cachingisenabled,the instructioncache greatlyacceleratesprogram executionby satisfyingmost instructionfetches.Italsogreatlyreducesbus traffictoexternalmemory, whichincreases thebandwidthavailablefortheDMA controllersand DSP. The cache isorganizedas fourways of64 entrieseach,as shown inFigure7-1.Each entryholds16 data bytes(8instructions). Figure7-1.CPU InstructionCache Organization Each entryconsistsof:
• ValidBit— Indicateswhethertheentryholdsvaliddata.The validbitisclearedwhen thecache is disabled,when theCINV [i]instructionisexecuted,and atreset.The validbitissetwhen theentryis loaded.
• AddressTag— Holdsaddressbits31:10associatedwiththeentry.The addresstagisloadedwhen a cache entryisallocatedon a cache miss.
• Data— Eightbytesofdata.The dataispassed totheCPU on a cache hit,and itisloadedwhen a cache entryisallocatedon a cache miss.

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www.ti.com SNOSCW5 –MAY 2013 On an instructionfetch,addressbits9:4selectone ofthelines.Any ofthefourways may holdthetarget of the instructionfetch.The tags in each of the fourways are compared againstbits32:10 of the instructionaddressto determinewhich way (ifany) holdsthe data.Ifone of the entrieshas matching addressbitsand itsvalidbitisset,theinstructionfetchisa cache hit,and thecache dataispassed tothe CPU tosatisfytheinstructionfetch. Ifnone ofthevalidtagsmatch theinstructionaddressbits,theinstructionfetchisa cache miss,and a bus cyclewillbe generatedon the CPU core bus to read the memory locationcontainingthe targetof the instructionfetch.When thememory dataisreceived,itisloadedintothecache and passed totheCPU, which releasesthe CPU to continueexecution.Three subsequentbus cyclesread the remainderof an aligned16-byteblocktofilla cache entry. A PLRU algorithmisused toallocatea cache entryinone ofthefourways toreceivetheblock.For each line,thereare threebitsB2:0 used by the algorithm.These bitsare not directlyvisibleto application software,buttheymay be indirectlyvisibleby theireffecton theexecutionspeed ofsome programs.(It wouldbe unusualforexecutionspeed tobe significantlyaffected.) The way selectedby thePLRU bitsisshown inTable7-1. Table7-1.Way SelectedforAllocationon Cache Miss B2:0 Way SelectedforAllocation

0 Way 0

1 Way 2

10 Way 1

11 Way 2

100 Way 0

101 Way 3

110 Way 1

111 Way 3

The PLRU bitsare clearedwhen thecache isdisabled,and theyare updatedon a cache hit.Table7-2 shows thenextstateofthePLRU bitswhen theyareupdated. Table7-2.Next StateofPLRU Bitson Cache Hit Way Selectedby Cache Hit B2 B1 B0 Way 0 Unchanged 1 1 Way 1 Unchanged 0 1 Way 2 1 Unchanged 0 Way 3 0 Unchanged 0

7.1 Cache Locking

Cache lockingistypicallyused forperformance-sensitivealgorithms,toassurethattheprogram memory willbe inthe cache duringexecution.Itmay alsobe used when deterministicbehaviorisrequired,to ensurethatprogramsalwaysexecuteinthesame number ofcycles. When thecache islocked,thecontentsofthecache do notchange.The cache islockedby settingthe LIC bitintheCFG register. When a cache miss occurswhilethecache islocked,no cache entryisallocatedon a cache miss,and thePLRU bitsarenotupdated. Copyright© 2013,Texas InstrumentsIncorporated InstructionCache 29 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com When a cache hitoccurswhilethecache islocked,thecache dataispassed totheCPU, and thePLRU bitsare up-dated.However, the PLRU bitshave no effectwhilethe cache islocked,because no new cache entriesareallocated.

7.2 Cache Invalidation

The cache does notsnoop any bus cycles.Softwareisresponsibleforinvalidatingthecache when the CPU or any otherdevicewritestoprogram memory. The cache isinvalidatedby executingtheCINV [i] instruction.Thisclearsthevalidbitsforallofthecache entries. The cache isautomaticallyinvalidatedatresetand when itisdisabled.

8 CPU Core Bus Arbitration

The CPU coreAHB bus can be controlledby eitheroftwo bus masters:

• CPU Core
• CPU DMA Controller The bus arbiterimplementstwo levelsofpriorityarbitrationamong thepotentialbus masters:
• Group Priority— each potentialbus masterisassignedtoone offourprioritygroups.The priority among groupsislinear,withgroupA athighestpriorityand groupD atlowestpriority.
• Prioritywithina Group— eitheroftwo arbitrationpoliciesmay be selectedfora group:linearpriorityand round-robin.Linearprioritygivesbus ownershiptotherequestingdevicewiththelowestmaster number.Round-robinassignsbus ownershipina cyclicsequence (forexample,2-3-4-2-3-4)among requestingdevices. Group priorityisalwaysconsideredbeforeprioritywithina group.Prioritywithina groupisonlyconsidered afterthegroupisselected. With onlytwo potentialbus masters,the bus arbitrationmechanism may seem excessivelycomplex, however thisarchitectureisdesignedforscalabilitytofuturedeviceswhichmay have a greaternumber of potentialbus masters. The defaultregistersettingsforthebus arbiterprovidean efficientarbitrationpolicyacrossa widerangeof applications:
• One Group— allpotentialbus mastersareassignedtogroupA.
• Round-RobinArbitration— a round-robinpolicyavoidsstarvingany potentialbus masterofbandwidth.
• DefaultBus MasterisCPU — when no potentialbus masterassertsa requestforcontrolofthebus,the CPU isgivenownershipofthebus.ThisavoidsstallingtheCPU when itneeds toaccessan idlebus. When a linearprioritypolicyis selectedfora prioritygroup,the master number is used to resolve arbitrationamong deviceswithinthatgroup,withlowernumbers receivinghigherpriority.Table8-1shows theassignmentofmasternumbers. Table8-1.Master Number Assignment POTENTIAL BUS MASTER MASTER NUMBER CPU 2 CPU DMA Controller 3 Whether ornotany defaultsettingsarechanged,softwareshouldlockthebus arbiterconfigurationduring systeminitializationby writing1 totheLOCK bitintheARBCFGLK register.

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8.1 Bus ArbiterRegisters

The bus arbiterregisterscontroland providestatusforcertainaspectsofthebus arbiter.The bus arbiter registersarelistedinTable8-2. Table8-2.Bus ArbiterRegisters NAME ADDRESS DESCRIPTION MASTGP FF F000h MasterGroup Register ARBALGO FF F004h ArbitrationAlgorithmRegister DFTMAST FF F008h DefaultMasterRegister ARBCFGLK FF F00ch ArbiterConfigurationLock Register

8.1.1 Master Group Register(MASTGP)

The MASTGP registerisa 32-bit,read/writeregisterthatselectstheprioritygroupforeach potentialbus master.Afterreset,thisregisterisclear. 31 6 5 4 3 2 1 0 Reserved MAS4 MAS3 MAS2 MASn The Masterfieldselectstheprioritygroupforthecorrespondingpotentialbus master. 00 – Group A. 01 – Group B. 10 – Group C. 11 – Group D.

8.1.2 ArbitrationAlgorithmRegister(ARBALGO)

The ARBALGO registerisa 32-bit,read/writeregisterthatselectsthe arbitrationpolicyused foreach prioritygroup.A terreset,thisregisterisinitializedto0000 0001h.31 31 4 3 2 1 0 Reserved GRD GRC GRB GRA GRn The Group bitselectsthearbitrationpolicyforthecorrespondinggroup. 0 – Linearprioritybased on masternumber. 1 – Round-robin.

8.1.3 DefaultMaster Register(DFTMAST)

The DFTMAST registerisa 32-bit,read/writeregisterthatselectsthemasternumber ofthedefaultbus master.Afterreset,thisregisterisinitializedto0000 0002h. 31 4 3 0 Reserved DFTMAST DFTMAST The DefaultMasterfieldspecifiesthemasternumber.Therearetwo definedvalues: 2h – CPU. 3h – CPU DMA controller. Copyright© 2013,Texas InstrumentsIncorporated CPU Core Bus Arbitration 31 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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8.1.4 ArbiterConfigurationLock Register(ARBCFGLK)

The ARBALGO registerisa 32-bit,read/writeregisterthatisused tolockthebus arbiterconfiguration. When the configurationislocked,writesto the bus arbiterregistersare ignored.Reads are unaffected. Once locked,theconfigurationmay notbe unlockeduntilthedeviceisreset.Afterreset,thisregisteris initializedto0000 0000h. 31 1 0 Reserved LOCK LOCK The Lock bitcontrolswhetherthebus arbiterregistersarelocked. 0 – Unlocked. 1 – Locked.

9 DSP and Audio Peripherals

The CP3SP33 includesa Teak DSP forsupportinghigh-performanceaudioapplications.DSP software packages are availablefrom Texas Instrumentsforsignalprocessingoperationscommonly used to processaudiodata. The DSP implements16-bitfixed-pointarithmeticwitha 4bus (X,Y,Z,and Program)Harvardarchitecture. The fastDSP core(96 MHz) and largeon-chip24K-byteprogram and 24K-bytedatamemories satisfya wide range of compute-intensiveapplications.The DSP has a 32-bithigh-bandwidthbus separatefrom thatoftheCPU, and ithas an independentDMA controller,forefficientbus utilization. The CPU hosthas a register-basedinterfaceforcontrollingtheDSP and accessingtheDSP program and datamemory space.The CPU can resettheDSP, interrupttheDSP, and asserta DSP DMA request.The DSP can assertan interruptrequesttotheCPU, and itcan wake theCPU froma low-powermode. Figure9-1shows thearchitectureoftheDSP and audioperipherals.The DSP DMA controllerisa slave on theCPU APB bus,so thattheCPU hostcan use a DMA channelfordownloadingsoftwaretotheDSP program and datamemories.Once releasedtobeginexecution,theDSP isbus masteron itsown 32-bit, high-bandwidthbus,whichtheDSP uses toaccessthreetypesofslavedevices:

• 4K-byteShared RAM — datamemory whichismapped intoCPU and DSP addressspaces.
• ExternalBus Interface— interfacetoexternal(off-chip)memory devices.
• Shared AudioPeripheralAPB Bus— peripheralssharedbetween theCPU and DSP (codec,I2S interface,etc.). The Audio Subsystem Controller(ASC) providesmultiplexingof interruptand DMA signalsbetween sharedperipheralsand theindependentinterruptand DMA controllersoftheCPU and DSP.

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CPU Core AHB Bus (32-Bit) Teak DSP AHB Bus (32-Bit) Memory Interface Unit Teak 16-Bit Fixed-Point DSP 24K Bytes Data RAM DSP Interrupt Controller 24K Bytes Program RAM X Y Z P 4K Bytes Shared RAM External Bus Interface Unit Peripheral Bus Controller Shared Audio Peripheral APB Bus (32-Bit)CPU Peripheral APB Bus (32-Bit) Peripheral Bus Controller UART 3ACCESS .bus 1 Microwire/ SPI 1 DS437 Telematics Codec Dual CVSD/PCM Converter Advanced Audio Interface I2S Interface CR16CPlus CPU Core with 4K Bytes Instr. Cache CPU DMA Controller CPU Interrupt Controller DSP DMA Controller Audio Subsystem Controller Interrupt Requests DMA Requests DMA Acknowledgements CPU Host Interface CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure9-1.DSP and Audio Peripherals Copyright© 2013,Texas InstrumentsIncorporated DSP and AudioPeripherals 33 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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9.1 DSP Memory Spaces

The DSP has a four-busarchitecture.Instructionsarereceivedon the16-bitP bus,theDSP datamemory isaccessed throughthe16-bitX and Y buses,and externalmemory and DSP peripheralsare accessed throughtheZ bus.Word addressingisused forallbuses.Table9-1shows themapping oftheDSP data memory space. Table9-1.DSP Data Memory Map ADDRESS RANGE BUS DESCRIPTION 0000h to17FFh X On-chip6K-worddatamemory 1800h toDFFFh Z Availableformapping totheexternalmemory bus 8000h to87FFh Memory-mapped I/Oregistersused by peripheralsthatareonlydirectlyaccessibleby theDSP.Z(Defaultaddressafterreset) The base addressofthisregioncan be reprogrammed by theDSP software. E000h toF7FFh Y On-chip6K-worddatamemory F800h toFFFFh Z Availableformapping totheexternalmemory bus The DSP program space isimplementedas two blocks,as shown inTable9-2.WhiletheDSP executes from one block,the otherblock can be accessed by the DMA controllerwithoutdegradingDSP performance. Table9-2.DSP Program Memory Map ADDRESS RANGE DESCRIPTION 0000h to0FFFh 4K-wordprogrammemory block 1000h to3FFFh Reserved 4000h to5FFFh 8K-wordprogrammemory block 6000h toFFFFh Reserved The DSP accesses peripheralsshared withthe CPU indirectly,throughthe DSP DMA controlleror the memorymapped I/Oregisters(MMIO).

9.2 CPU/DSP Interface

The CPU has readand writeaccesstotheentireDSP datamemory space (X,Y, Z),and writeaccessto theDSP program memory space.The CPU/DSP interfacemakes use oftheDSP DMA controllertoavoid interruptingtheDSP when servicingtheCPU. The interfaceishardcodedtouse DSP DMA channel0 for DMA transfersbetween itsFIFOs and DSP memory. ThisDMA channelhas a slaveinterfaceon theCPU peripheraldatabus. The CPU/DSP interfacealsoincludeshardwarefeaturestosupportinterprocessorcommunicationssuch as a command/replyinterfaceand semaphores.Italsoprovidesmechanisms forthe CPU and DSP to interrupteach other. Data istransferredbetween theCPU and theDSP memory spaces througha setofindirectaddressand dataregisters.An auto-incrementaddressfunctioneliminatestheneed toresendtheaddressforevery word transferred.By default,the number of transactionsislimitedto 65535 (thedefaultDMA transfer size).The interfacecontainsa 16-wordread FIFO and a 16-word writeFIFO to buffertransfers.These FIFOs can be programmed to generateinterruptsto the CPU on particularevents(full,empty, etc.). Additionally,the PBUSY bitinthe ADMAS registerindicateswhen the interfacecannotacceptanother access,forexample ifthe writeFIFO is fullor a new operationis initiatedbeforethe currentone completes. The CPU/DSP interfacecannotbe used when HCLK ClockorPCLK ClockisfasterthanDSP clock.

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9.2.1 DSP Reset

Therearetwo resetbitsfortheDSP:

• ADMAC.DSPRSTN — thisbitinthe CPU/DSP interfaceassertsa resetsignalthatisexternalto the DSP module.
• PCFG.DSPR — thisbitwithintheDSP module can be used toholdtheDSP inreset. The ADMAC.DSPRSTN bitislikea power-on reset,which shouldbe used when completeresetof the DSP isrequired.The DSP memories cannotbe accessedwhiletheADMAC.DSPRSTN bitisclear(reset asserted).The DSP clock(AuxiliaryClock 7) must be enabled forat leasttwo cyclesbeforethe ADMAC.DSPRSTN bitisset(resetdeasserted).Afterdeassertingreset,thePSTS.PRST bitcan be polled todeterminewhen theDSP has completeditsresetsequence. The PCFG.DSPR bitcan be used to hold the processorin resetwhileaccessingthe DSP block,for example whiledownloadingsoftwareto the DSP program memory. When asserted,itmust be heldfor eightDSP clockcyclesbeforebeingdeasserted.

9.2.2 Downloading toDSP Program Memory

The CPU interfacecan be used todownload softwaretotheDSP memories.Afterpower-on-resetorother system resets,the DSP willbe heldinresetwiththe DSP clock(AuxiliaryClock 7) enabled.The DSP clockmust be enabledduringresettoproperlyresettheDSP. 1. EnabletheclocktotheDSP (ifnecessary). 2. SettheDSPR bitinthePCFG register.ThiswillholdtheDSP inreset. 3. DeasserttheresetsignaltotheDSP module by settingtheDSPRSTN bitintheADMAC register.A delayofatleasttwo DSP clocksmust be maintainedbetween enablingtheDSP clockand deasserting theresetsignal. 4. PollthePRST bitinthePSTS registeruntila 1 to0 transitionisobserved,whichindicatesthatthe MMIO registersthatcontrola DMA transferhave been reset. 5. Setup and performthetransfer. 6. CleartheDSPR bitinthePCFG register,whichrestartstheDSP.

9.2.3 Audio Subsystem Controller(ASC)

As shown inFigure9-2, the ASC multiplexesthe interruptand DMA signalsbetween the independent interruptand DMA controllersforthe CPU and DSP. Peripheralscapableof requestinginterruptsfrom boththeCPU and DSP must have theirselectionsprogrammed intheASCINTSEL register,inadditionto havingtheirrequestsenabledinthe interruptcontrollers.Peripheralscapableof requestingDMA from boththeCPU and DSP must have theirselectionsprogrammed intheASCDMASELn registers,inaddition to havingtheirrequestsenabled in the DMA controllers.By defaultafterreset,allinterruptand DMA requestsareroutedtotheCPU interruptand DMA controllers. The DSP DMA controllerprovideseightDMA requestinputsand eightDMA acknowledge outputs.For each DSP DMA channel,a 5-bitfieldintheone oftheASCDDMASELn registersselectswhichofthe21 sourcesofDMA requestsisservicedby thatchannel. Copyright© 2013,Texas InstrumentsIncorporated DSP and AudioPeripherals 35 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

CPU Interrupt ControllerShared Peripheral 0 DMA Acknowledge 0 Shared Peripheral N DSP Interrupt Controller Enable Enable DMA Request N DMA Acknowledge N DMA Requests DMA Acknowledgements DMA Requests DMA Acknowledgemants Audio Subsystem Controller ASCDMASEL0/ASCDMASEL1 Interrupt Request 0 ASCINTSEL CPU DMA Controller Interrupt Request N /11 Interrupt Requests /21 /11 /21 DSP DMA Controller CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure9-2.Audio Subsystem Controller The ASC multiplexesinterruptrequestsignalsfromdevicescapableofrequestinginterruptsfromeitherof theCPU and DSP interruptcontrollers.These requestsareassignedtoASC interruptchannels0 to10,as shown inTable9-3. The ASC multiplexesDMA request/acknowledgesignalsfrom devicescapableof requestingDMA from eitheroftheCPU and DSP DMA controllers.These requestsareassignedtoASC DMA channels0 to20, as shown inTable9-4. Table9-3.ASC InterruptChannel Assignment CHANNEL PERIPHERAL

0 Microwire/SPI1

1 ACCESS.bus 1

2 UART3 TX

3 UART3 RX

4 CVSD/PCM 1

5 CVSD/PCM 0

6 I2SInterface

7 AAI

8 TelematicsCodec

9 MultifunctionTimer1 TB1

10 MultifunctionTimer1 TA1

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www.ti.com SNOSCW5 –MAY 2013 Table9-4.ASC DMA Channel Assignment CHANNEL R/W PERIPHERAL REGISTER

0 R UART3 RXBUF3

1 W UART3 TXBUF3

2 R CVSD/PCM0 PCMOUT0

3 W CVSD/PCM0 PCMIN0

4 R CVSD/PCM1 PCMOUT1

5 W CVSD/PCM1 PCMIN1

6 R AAI Slot0 ARDR0

7 W AAI Slot0 ATDR0

8 R AAI Slot1 ARDR1

9 W AAI Slot1 ATDR1

10 R Codec ADC1 TCDCADC1

11 R Codec ADC2 TCDCADC2

12 W Codec LeftDAC TCDCLEFT

13 W Codec RightDAC TCDCRIGHT

14 R I2SLeft I2SRXDATALEFT

15 R I2SRight I2SRXDATARIGHT

16 W I2SLeft I2STXDATALEFT

17 W I2SRight I2STXDATARIGHT

18 R MWSPI1 MWDAT

19 W MWSPI1 MWDAT

20 R/W ACB1 ACB1SDA

9.3 DSP and ASC Registers

The DSP and ASC registerscontroland providestatusfortheinterfacebetween theCPU and theDSP. The DSP and ASC registersarelistedinTable9-5. Table9-5.DSP and ASC Registers NAME ADDRESS DESCRIPTION ADMAC FF 6820h ASC DSP ControlRegister ADMAS FF 681Ch ASC DSP StatusRegister PDATA FF EC00h DSP DMA Channel0 Data Register PADR FF EC04h DSP DMA Channel0 AddressRegister PCFG FF EC08h CPU/DSP InterfaceConfigurationRegister PSTS FF EC0Ch CPU/DSP InterfaceStatusRegister PSEM FF EC10h CPU-to-DSP Semaphore Register PMASK FF EC14h CPU InterruptMask Register PCLEAR FF EC18h CPU-to-DSP Semaphore ClearRegister APBP_SEM FF EC1Ch DSP-to-CPU Semaphore Register APBP_COM0 FF EC20h CPU-to-DSP Command Register0 APBP_REP0 FF EC24h DSP-to-CPU ReplyRegister0 APBP_COM1 FF EC28h CPU-to-DSP Command Register1 APBP_REP1 FF EC2Ch DSP-to-CPU ReplyRegister1 APBP_COM2 FF EC30h CPU-to-DSP Command Register2 APBP_REP2 FF EC34h DSP-to-CPU ReplyRegister2 ASCDMASEL0 FF 6800h ASC DMA ControllerSelectRegister0 ASCDMASEL1 FF 6804h ASC DMA ControllerSelectRegister1 Copyright© 2013,Texas InstrumentsIncorporated DSP and AudioPeripherals 37 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table9-5.DSP and ASC Registers(continued) NAME ADDRESS DESCRIPTION ASCDDMASEL0 FF 6808h ASC DSP DMA ChannelSelectRegister0 ASCDDMASEL1 FF 680Ch ASC DSP DMA ChannelSelectRegister1 ASCDDMASEL2 FF 6810h ASC DSP DMA ChannelSelectRegister2 ASCDDMASEL3 FF 6814h ASC DSP DMA ChannelSelectRegister3 ASCINTSEL FF 6818h ASC InterruptControllerSelectRegister

9.3.1 ASC DSP ControlRegister(ADMAC)

The ADMAC registerisa 16-bit,read/writeregisterused by theCPU toresettheDSP. Afterreset,this registeris0000h. 15 1 0 Reserved DSPRSTN DSPRSTN The DSP Resetbitisused toassertresettotheDSP. The DSP resetsignalistheOR functionofthisbitand theCPU resetsignal.CPU softwaremust setthisbittoenablethe DSP. 0 – DSP module reset. 1 – DSP module may run(ifPCFG.DSPR isclear).

9.3.2 ASC DSP StatusRegister(ADMAS)

The ADMAS registerisa 16-bit,read-onlyregisterthatindicateswhethertheCPU hostinterfacetothe DSP DMA controllerisbusy and whethertheDSP inreset.Afterreset,thisregisteris0000h. 15 2 1 0 Reserved RRSTN PBUSY PBUSY The PortBusy bitindicateswhethertheCPU hostinterfacetotheDSP DMA controlleris busy.IftheDSP writeFIFO isfull,theDSP readFIFO isempty (anda readhas been requested),orthePADR registerhas been written,thisbitwillbe set.Softwaremust pollthe PBUSY bitbeforeusingtheCPU hostinterfacetoaccesstheDSP memory space. 0 – CPU hostinterfaceisready. 1 – CPU hostinterfaceisbusy. RRSTN The ReflectedResetbitindicateswhethertheDSP isbeingheldinreset. 0 – DSP isinreset. 1 – DSP isnotinreset.

9.3.3 DSP DMA Channel 0 Data Register(PDATA)

The PDATA registerisa 16-bit,read/writeregisterthatprovidesthe CPU withaccess to the read and writeFIFOs forDSP DMA channel0.WritingtheregisterloadsthewriteFIFO, and readingtheregister unloadsthereadFIFO. 15 1 PDATA

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9.3.4 DSP DMA Channel 0 Address Register(PADR)

The PADR registerisa 16-bit,write-onlyregisterthatprovidesthelower16 addressbitsforDSP DMA Channel0.The page address(page0)must be programmed intheDSP DMA controller.Inautoincrement mode (PCFG.AIM = 1),thisaddressisautoincrementedon everyDMA cycle.Afterreset,thisregisteris clear. 15 1 PADR

9.3.5 CPU/DSP InterfaceConfigurationRegister(PCFG)

The PADR registerisa 16-bit,read/writeregisterthatcontrolstheconfigurationoftheCPU/DSP interface. Afterreset,thisregisterisclear. 15 12 11 10 9 8 7 6 5 4 3 2 1 0 MEMSEL RRIE2 RRIE1 RRIE0 WFEIE WFFIE RFNEIE RFFIE RS DRS AIM DSPR DSPR The DSP Resetbit,when set,resetstheDSP. To properlyresettheDSP, thisbitmust remainsetfor8 DSP clockcycles. 0 – DSP resetisnotasserted. 1 – DSP resetisasserted. AIM The AutoincrementMode bitenablesautomaticincrementoftheaddresscounterwhen the CPU uses DSP DMA channel0 (thehostinterfaceused fordownloadingtotheDSP). 0 – No incrementoftheDMA address. 1 – Automaticincrementenabled. DRS The Data Read Selectfieldselectsthetransfermode used on the32-bithigh-performance DSP bus toreaddataforsatisfyinga CPU readrequest.ThisfieldisignorediftheRS bitis clear. 00 – Singlereadtransfer. 01 – 8-wordburstreadtransfer. 10 – 16-wordburstreadtransfer. 11 – Freerunning(continuous). RS SettingtheRead Startbitinitiatesa readtransferofthetypespecifiedintheDRS field. ClearingthebitflushesthereadFIFO and terminatesany readtransferinprogress. 0 – No transferisinitiatedorinprogress. 1 – Write1 toinitiatea readtransfer. RFFIE The Read FIFO FullInterruptEnablebitassertsIRQ60 totheCPU interruptcontrollerwhen thereadFIFO becomes full. 0 – Interruptdisabled. 1 – Interruptenabled RFNEIE The Read FIFO Not Empty InterruptEnablebitassertsIRQ60 totheCPU interruptcontroller when thereadFIFO holdsvaliddata. 0 – Interruptdisabled. 1 – Interruptenabled. WFFIE The WriteFIFO FullInterruptEnablebitassertsIRQ60 totheCPU interruptcontrollerwhen thewriteFIFO isfull. 0 – Interruptdisabled. 1 – Interruptenabled. WFEIE The WriteFIFO Empty InterruptEnablebitassertsIRQ60 totheCPU interruptcontroller when thewriteFIFO isempty. 0 – Interruptdisabled. 1 – Interruptenabled. Copyright© 2013,Texas InstrumentsIncorporated DSP and AudioPeripherals 39 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com RRIE0 The ReplyRegister0 InterruptEnablebitassertsIRQ60 totheCPU interruptcontrolleron DSP writestotheAPBP_REP0 register. 0 – Interruptdisabled. 1 – Interruptenabled. RRIE1 The ReplyRegister1 InterruptEnablebitassertsIRQ60 totheCPU interruptcontrolleron DSP writestotheAPBP_REP1 register. 0 – Interruptdisabled. 1 – Interruptenabled. RRIE2 The ReplyRegister2 InterruptEnablebitassertsIRQ60 totheCPU interruptcontrolleron DSP writestotheAPBP_REP2 register. 0 – Interruptdisabled. 1 – Interruptenabled. MEMSEL The Memory SelectfieldselectstheDSP memory space accessedby theCPU. Valuesother thanthoselistedbelowarereserved.0000 – DSP datamemory. 0001 – MMIO registers. 0101 – DSP programmemory. 0110 – Expansionbus (16M EBIU region). 0111 – Expansionbus (240M EBIU region).

9.3.6 CPU/DSP InterfaceStatusRegister(PSTS)

The PSTS registerisa 16-bit,read-onlyregisterthatprovidesstatusbitsfortheCPU/DSP interface. 7 6 5 4 3 2 1 0 WFFI RFNEI RFFI Reserved PRST WTIP RTIP 15 14 13 12 11 10 9 8 RCOMIM2 RCOMIM1 RCOMIM0 RRI2 RRI1 RRI0 PSEMI WFEI RTIP The Read TransferinProgressbitindicateswhen a readtransferisinprogress.A read transfercan be terminatedwhileitisinprogressby writing0 tothePCFG.RS bit. 0 – No transferisinprogress. 1 – A transferisinprogress. WTIP The WriteTransferInProgressbitindicateswhen a writetransferisinprogress. 0 – No transferisinprogress. 1 – A transferisinprogress. PRST The PeripheralResetIndicatorbitisassertedfromthestartofDSP reset(PCFG.DSPR = 1) untiltheresethas completed.When thebitgoes clear,theMMIO registershave received theirresetvalues.The CPU must pollthisbitbeforedownloadingsoftwaretotheDSP. 0 – DSP isnotinreset. 1 – DSP resetinprogress. RFFI The Read FIFO FullIndicatorbitisassertedwhen thereadFIFO isfull. 0 – FIFO isnotfull. 1 – FIFO isfull. RFNEI The Read FIFO Not Empty Indicatorbitisassertedwhen thereadFIFO holdsvaliddata. 0 – FIFO isempty. 1 – FIFO holdsvaliddata. WFFI The WriteFIFO FullIndicatorbitisassertedwhen thewriteFIFO isfull. 0 – FIFO isnotfull. 1 – FIFO isfull.

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www.ti.com SNOSCW5 –MAY 2013 WFEI The WriteFIFO Empty Indicatorbitisassertedwhen thewriteFIFO isempty. 0 – FIFO isnotempty. 1 – FIFO isempty. PSEMI The PeripheralSemaphore Access Indicatorbitissetwhen a bitintheAPBP_SEM register has been setby theDSP and thecorrespondingbitinthePMASK registerisclear. 0 – No unmasked semaphore bitisset. 1 – An unmasked semaphore bitisset. PRI0 The ReplyRegister0 Indicatorbitissetwhen theDSP writestheAPBP_REP0 register.The RRI0 bitisclearedwhen theCPU readstheAPBP_REP0 register. 0 – APBP_REP0 has notbeen written. 1 – APBP_REP0 was writtenbutnotread. RRI1 The ReplyRegister1 Indicatorbitissetwhen theDSP writestheAPBP_REP1 register.The RRI1 bitisclearedwhen theCPU readstheAPBP_REP1 register. 0 – APBP_REP1 has notbeen written. 1 – APBP_REP1 was writtenbutnotread. RRI2 The ReplyRegister2 Indicatorbitissetwhen theDSP writestheAPBP_REP2 register.The RRI2 bitisclearedwhen theCPU readstheAPBP_REP2 register. 0 – APBP_REP2 has notbeen written. 1 – APBP_REP2 was writtenbutnotread. RCOMIM0 The Read Command Register0 Indicatorbitissetwhen theCPU writestheAPBP_COM0 register.The RCOMIM0 bitisclearedwhen theDSP orCPU readstheAPBP_COM0 register. 0 – APBP_COM0 has notbeen written. 1 – APBP_COM0 was writtenbutnotread. RCOMIM1 The Read Command Register1 Indicatorbitissetwhen theCPU writestheAPBP_COM1 register.The RCOMIM1 bitisclearedwhen theDSP orCPU readstheAPBP_COM1 register. 0 – APBP_COM1 has notbeen written. 1 – APBP_COM1 was writtenbutnotread. RCOMIM2 The Read Command Register2 Indicatorbitissetwhen theCPU writestheAPBP_COM2 register.The RCOMIM2 bitisclearedwhen theDSP orCPU readstheAPBP_COM2 register. 0 – APBP_COM2 has notbeen written. 1 – APBP_COM2 was writtenbutnotread.

9.3.7 CPU-to-DSP Semaphore Register(PSEM)

The PSEM registerisa 16-bit,read/writeregisterused by theCPU toassertan interrupttotheDSP. Ifa bitinthisregisterissetand thecorrespondingbitintheAPBP_MASK register(onlyvisibletotheDSP) is clear,theDSP isinterrupted.Afterreset,thisregisterisclear. 15 1 PSEM Copyright© 2013,Texas InstrumentsIncorporated DSP and AudioPeripherals 41 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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9.3.8 CPU InterruptMask Register(PMASK)

The PMASK registerisa 16-bit,read/writeregisterused by theCPU tomask interruptrequestsfromthe DSP. IftheDSP setsa bitintheAPBP_SEM registerand thecorrespondingbitinthePMASK registeris clear,theCPU isinterrupted.Afterreset,thisregisterisclear. 15 1 PMASK

9.3.9 CPU-to-DSP Semaphore ClearRegister(PCLEAR)

The PCLEAR registerisa 16-bit,write-onlyregisterused by theCPU toclearinterruptrequestsfromthe DSP. Writing1 tobitsinthePCLEAR registerclearsthecorrespondingbitsintheAPBP_SEM register. 15 1 PCLEAR

9.3.10 DSP-to-CPU Semaphore Register(APBP_SEM)

The APBP_SEM registerisa 16-bit,read-onlyregisterwhich indicatesinterruptrequestsfrom theDSP. When theDSP setsa bitinthisregisterwhilethecorrespondingbitinthePMASK registerisclear,an interruptisassertedtotheCPU. Afterreset,thisregisterisclear. 15 1 APBP_SEM

9.3.11 CPU-to-DSP Command Registern (APBP_COMn)

The APBP_COMn registersare 16-bitregistersthatare read/writetotheCPU and read-onlytotheDSP (asMMIO registers).Afterreset,theseregistersareclear. 15 1 APBP_COMn

9.3.12 DSP-to-CPU Reply Registern (APBP_REPn)

The APBP_REPn registersare 16-bitregistersthatare read/writeto the DSP (as MMIO registers)and read-onlytotheCPU. Afterreset,theseregistersareclear. 15 1 APBP_REPn

9.3.13 ASC DMA ControllerSelectRegistern (ASCDMASELn)

The ASCDMASELn registersare16-bit,read/writeregistersthatselectbetween theCPU and DSP DMA controllersfortheASC DMA channels(listedinTable9-4).Bits15:0ofASCDMASEL0 correspondtoASC DMA channels15:0,and bits4:0ofASCDMASEL1 correspondtoASC DMA channels20:16.Clearbits selecttheCPU DMA controller,and setbitsselecttheDSP DMA controller.Afterreset,theseregistersare clear. 15 1 DCH15:0

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www.ti.com SNOSCW5 –MAY 2013 15 5 4 3 2 1 0 Reserved DCH20 DCH19 DCH18 DCH17 DCH16 DCHn The DMA ControllerSelectbitcontrolswhichDMA controllerreceivestheDMA requestand returnstheDMA acknowledgesignalforthecorrespondingASC DMA channel. 0 – CPU DMA controllerisselected. 1 – DSP DMA controllerisselected.

9.3.14 ASC DSP DMA Channel SelectRegistern (ASCDDMASELn)

The ASCDDMASELn registersare 16-bit,read/writeregistersthatprovide5-bitfieldsforspecifyingthe ASC DMA channels(listedin Table 12) thatactivatethe correspondingDSP DMA channels.Each ASCDDMASELn registerprovidesfieldsfortwo DMA channels.ASCDDMASEL0 controlschannels0 and 1, ASCDDMASEL1 controlschannels 2 and 3, ASCDDMASEL2 controlschannels 4 and 5, and ASCDDMASEL3 controlschannels6 and 7.Afterreset,theseregistersareclear. 15 13M M 12 8M M 7 5M M 4 0 Reserved DDMA(2n+1) Reserved DDMA(2n) DDMA The ASCDDMASELn registersare16-bit,read/writeregistersthatprovide5-bitfieldsfor specifyingtheASC DMA channels(listedinTable9-4)thatactivatethecorrespondingDSP DMA channels.Each ASCDDMASELn registerprovidesfieldsfortwo DMA channels. ASCDDMASEL0 controlschannels0 and 1,ASCDDMASEL1 controlschannels2 and 3, ASCDDMASEL2 controlschannels4 and 5,and ASCDDMASEL3 controlschannels6 and 7. Afterreset,theseregistersareclear.

9.3.15 ASC InterruptSelectRegister(ASCINTSEL)

The ASCINTSEL registerisa 16-bit,read/writeregisterthatselectsbetween theCPU and DSP interrupt controllersforthe ASC interruptchannels(listedin Table 9-3).Clear bitsselectthe CPU interrupt controller,and setbitsselecttheDSP interruptcontroller.Afterreset,thisregisterisclear. 15 11M M 10 0 Reserved ICH ICH The InterruptControllerSelectbitcontrolswhichinterruptcontrollerreceivestheinterrupt requestfromthecorrespondingASC interruptchannel. 0 – CPU interruptcontrollerisselected. 1 – DSP interruptcontrollerisselected. Copyright© 2013,Texas InstrumentsIncorporated DSP and AudioPeripherals 43 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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10 ExternalBus InterfaceUnit

The ExternalBus InterfaceUnit(EBIU) providesa memory bus interfacethatsupportsthreetypesof externalmemory:

• AsynchronousRAM
• Page-Mode FlashMemory
• ROM Because theCP3SP33 does nothave on-chipnon-volatilememory, theEBIU istypicallyused toadd at leastone non-volatilememory deviceforholdingthebootcode.The EBIU providesprogrammable chip selectoutputsXCSn fortwo or threememory devices,dependingon package type.The memory type, base address,width(8,16,or32 bits),size,and timingareindependentlyprogrammableforeach ofthe memory devices. The physicaladdressspace availableon theexternalbus does notoccupy a fixedlocationintheaddress space oftheCPU orTeak on-chip32-bitbuses.The location(s)areprogrammableintheEBIU registers. The EBIU assertsa chipselecttoan externalmemory devicewhen an on-chipbus uses a regionofits addressspace mapped toan externalmemory device.There aretwo regionsintheon-chipbus address space whichareavailableforexternaldevices:
• 0002 0000h to00FE FFFFh — a 16M-bytespace,minus a 128K space atthebottomand a 64K space atthetop
• 0100 0000h to0FFF FFFFh — a 240M-bytespace (256M,minus a 16M space atthebottom) The EBIU does not relocatethe addresspassed from the on-chipAHB buses to the externalbus.The mapping onlyaffectsactivationofthechipselectsignals.Any ofthechipselectsmay be configuredfor eitheroftwo regions.

10.1 ExternalBus Signals

There are 6 typesof bus signals.The number of signalsvarieswiththe package type,as shown in Table10-1. Table10-1.ExternalBus Signals PACKAGE PIN COUNT NAME DESCRIPTION FBGA-224 FBGA-144 XAn 23 21 AddressBus XDn 32 16 Data Bus XWE 1 1 WriteEnable XOE 1 1 OutputEnable XBEn 4 2 ByteEnables XCSn 3 2 ChipSelects The byteorderislittle-endian(LSB atlowestaddress).The EBIU shiftstheaddresstocorrespondtothe widthof the externalmemory device,so the XA address may be eithera byte,word, or doubleword address.Mixingofmemory typesisallowed.

10.2 DefaultMemory Configuration

The defaultconfigurationafterresetfortheexternalmemory devicesisshown inTable10-2.Bootingfrom an 8-bitexternalmemory isnotsupported. The cycletimesarequotedinHCLK Clockperiods.By default,theHCLK Clockfrequencyfollowingreset istheinputclockfrequency(X1CLKI/X1CLKO orCLKIN) dividedby 16.

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www.ti.com SNOSCW5 –MAY 2013 Table10-2.DefaultMemory Configuration CHIP SELECT PARAMETER XCS2 XCS1 XCS0 Memory Type RAM RAM RAM Base Address 0100 0000h 0080 0000h 0040 0000h Memory Size 16M Bytes 8M Bytes 8M Bytes Memory Width 16 Bits 32 Bits 16 Bits Read CycleTime 22 Cycles 22 Cycles 22 Cycles RAM WriteAddressSetupTime 1 Cycle 1 Cycle 1 Cycle RAM WriteAddressand Data HoldTime 1 Cycle 1 Cycle 1 Cycle RAM WritePulseWidth 4 Cycles 4 Cycles 4 Cycles Bus TurnaroundTime 2 Cycles 2 Cycles 2 Cycles Page-Mode Disabled Disabled Disabled Page-Mode Read CycleTime 4 Cycles 3 Cycles 1 Cycle Page Size 4 Words 4 Words 4 Words Memory Read PipeStages 0 0 0

10.3 ExternalBus Cycle Timing

Figure10-1shows thetimingofa readcycleon theexternalmemory bus. Figure10-1.Read Cycle Timing Copyright© 2013,Texas InstrumentsIncorporated ExternalBus InterfaceUnit 45 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Figure10-2shows thetimingofa writecycleon theexternalmemory bus. Figure10-2.WriteCycle Timing An 8-levelwritebufferallowstheEBIU toaccepta writecycleand releasethebus master(CPU, DSP, or one of the DMA controllers)to continueexecutionwithoutwaitingforthe writedata to propagateto externalmemory. A read cycleisnot allowedto propagateto externalmemory whilethereare any writespendinginthe writebuffer.The readcycleisstalleduntilthewritebufferhas been flushedtomemory. Thismechanism enforcesmemory coherencywhen the targetof a read ismodifiedby a pendingwrite.In some cases, softwareperformancecan be optimizedby groupingwritestogether(forexample,by loopunrolling)to avoidalternatingbetween readsand writes.

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XA[n:2] XBEn XDn Address tPRCtRC Data10Data01Data00 Data11 XOE XA[1:0] 100100 11 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure10-3shows thetimingofpage-mode readcycles. Figure10-3.Page-Mode Read Cycle Timing Figure10-4shows theread-to-writeand write-to-readbus turn-aroundtiming. Copyright© 2013,Texas InstrumentsIncorporated ExternalBus InterfaceUnit 47 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

XDn (in) Address A tBTA Data B XOE tBTA XDn (out) Data A XCSn Address B CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure10-4.Bus Turnaround Timing

10.4 EBIU Registers

Forallregisters,thecontentsshouldonlybe changed once,intheinitializationroutineafterreset. The EBIU has two globalcontrolregisters,two registersspecifictoeach chipselect,and 3 registersfor defining3 setsoftimingparameters.Any ofthechipselectsmay use any ofthetimingparameters. Table10-3.Bus ControlRegisters NAME ADDRESS DESCRIPTION SMCTLR FF 00A4h StaticMemory ControlRegister SCSLR0 FF 0014h ChipSelectRegister0 SMSKR0 FF 0054h Mask Register0 SCSLR1 FF 0018h ChipSelectRegister1 SMSKR1 FF 0058h Mask Register1 SCSLR2 FF 001Ch ChipSelectRegister2 SMSKR2 FF 005Ch Mask Register2 SMTMGR_SET0 FF 0094h StaticMemory TimingRegister0 SMTMGR_SET1 FF 0098h StaticMemory TimingRegister1 SMTMGR_SET2 FF 009Ch StaticMemory TimingRegister2 FLASH_TRPDR FF 00A0h FlashtRPD TimingRegister

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10.4.1 StaticMemory ControlRegister(SMCTLR)

The SMCTLR registerisa 32-bit,read/writeregisterthatselectsthe bus widthof the memory devices associatedwiththe chipselects.At reset,the registerisinitializedto 0000 0401h, which selects16-bit widthforXCS2 and XCS0, and 32-bitwidthforXCS1. The registerformatisshown below. 31 16M M 15 13M M 12 10M M 9 7M M 6 0 Reserved SM_DW_S2 SM_DW_S1 SM_DW_S0 Reserved SM_DW_S0 The StaticMemory Data Bus WidthfieldselectsthewidthoftheXCS0 device. 000 – 16 bits. 001 – 32 bits. 100 – 8 bits. SM_DW_S1 The StaticMemory Data Bus WidthfieldselectsthewidthoftheXCS1 device. 000 – 16 bits. 001 – 32 bits. 100 – 8 bits. SM_DW_S2 The StaticMemory Data Bus WidthfieldselectsthewidthoftheXCS2 device. 000 – 16 bits. 001 – 32 bits. 100 – 8 bits.

10.4.2 Chip SelectRegistern (SCSLRn)

The SCSLRn registersare 32-bit,read/writeregistersthatspecifybase addressesforthe chipselects. Only bits31:16can be used,because theminimum memory devicesizeis64K bytes.Additionalbitsare masked offifthesizeexceeds 64K. At reset,theSCSLR0 registerisinitializedto0040 0000h,SCSLR1 is initializedto0080 0000h,and SCSLR2 isinitializedto0100 0000h.The registerformatisshown below. 31 16M M 15 0 EXT_BASE_ADDR Reserved EXT_BASE_ADDR The ExternalBase Addressfieldspecifiesthebase addressoftheexternalmemory deviceenabledby thechipselect. Copyright© 2013,Texas InstrumentsIncorporated ExternalBus InterfaceUnit 49 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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10.4.3 Mask Registern (SMSKRn)

The SMSKRn registersare 32-bit,read/writeregistersthatspecifytimingparameters,memory type,and memory sizeforthechipselects.At reset,theSMSKR0 registerisinitializedto0000 0028h,SMSKR1 is initializedto0000 0128h,and SMSKR2 isinitializedto0000 0229h.The registerformatisshown below. 31 11M M 10 8M M 7 5M M 4 0M Reserved REG_SEL MEM_TYPE MEM_SIZE MEM_SIZE The Memory SIzefieldspecifiesthesizeoftheexternalmemory device.Valuesof12h to 1Fh arereserved. 00000 – No memory connected. 00001 – 64K bytes. 00010 – 128K bytes. 00011 – 256K bytes. 00100 – 512K bytes. 00101 – 1M bytes. 00110 – 2M bytes. 00111 – 4M bytes. 01000 – 8M bytes. 01001 – 16M bytes. 01010 – 32M bytes. 01011 – 64M bytes. 01100 – 128M bytes. 01101 – 256M bytes. 01110 – 512M bytes. 01111 – 1G bytes. 10000 – 2G bytes. 10001 – 4G bytes MEM_TYPE The Memory Type fieldspecifiesthetypeofexternalmemory device. 000 – Reserved. 001 – RAM. 010 – Flashmemory. 011 – ROM. REG_SEL The RegisterSelectfieldspecifiestimingparametersinone ofthethreeSMTMGR_SETn registerstobe used withtheexternalmemory device. 000 – SMTMGR_SET0 register. 001 – SMTMGR_SET1 register. 010 – SMTMGR_SET2 register.

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10.4.4 StaticMemory Timing Registern (SMTMGR_SETn)

The SMTMGR_SETn registersare 32-bit,read/writeregistersthatspecifytimingparametersthatcan be selectedby the REG_SEL fieldin the SMSKRn registers.Any SMSKRn registermay selectany SMTMGR_SETn register.At reset,the SMTMGR_SET0 registeris initializedto 0002 0D45h, the SMTMGR_SET1 registerisinitializedto 0012 0D45h, and the SMTMGR_SET2 registerisinitializedto 001A 0D45h. The registerformatisshown below. 31 30 29 28 27 26 25 24 23 22 19 18 16 15 10 9 8 7 6 5 0 Res. SMRP Res. PS PM T_PRC T_BTA T_WR T_WR T)AS T_RC T_RC The tRC field+ 1 specifiesthenumber ofHCLK Clockcyclesina readcycle T_AS The tAS fieldspecifiesthenumber ofHCLK Clockcyclesinthewriteaddresssetuptime. 00 – Reserved. 01 – 1 cycle. 10 – 2 cycles. 11 – 3 cycles. T_WR The tWR fieldspecifiesthenumber ofHCLK Clockcyclesinthewriteaddressdataholdtime. T_WP The tWP field+ 1 specifiesthenumber ofHCLK Clockcyclesina writepulse. T_BTA The tBTA field+ 1 specifiesthenumber ofHCLK Clockcyclesinthebus turnaroundtime.The same valueisused forread-to-writeand write-to-readturnaround. T_PRC The tPRC field+ 1 specifiesthenumber ofHCLK Clockcyclesinthepage-mode readcycle time. PM The Page Mode bitspecifieswhetherpage mode isused toaccessthedevice 0 – Page mode disabled. 1 – Page mode enabled. PS The Page Sizefieldspecifiesthepage size.Ifthepage sizeislargerthan64 bytes,thePS fieldshouldbe setto11b. 00 – 8 bytes. 01 – 16 bytes. 10 – 32 bytes. 11 – 64 bytes. SMRP The StaticMemory Read Pipefieldspecifiesthenumber ofregistersinsertedintothereaddata pathforcorrectlylatchingthedata.

10.4.5 FlashtRPD Timing Register(FLASH_TRPDR)

The FLASH_TRPDR registerisa 32-bit,read/writeregisterthatspecifiesthe number of clockcycles between flashmemory reset/power-downand thefirstflashread/writecycle.At reset,theFLASH_TRPDR registerisinitializedto0000 00C8h. 31 12M M 11 0 Reserved T_RPD T_RPD The tRPD field+ 1 specifiesthenumber ofclockcyclesbetween flashmemory reset/power- down and thefirstflashmemory read/writecycles.Atreset,thedefaultis201 cycles (value= C8h = 200d). Copyright© 2013,Texas InstrumentsIncorporated ExternalBus InterfaceUnit 51 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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10.5 Usage Notes

The EBIU registersmust be programmed inthefollowingsequence: 1. SCSLRn 2. SMSKRn 3. SMTMGR_SETn 4. FLASH_TRPDR 5. SMCTRL

11 System Configuration

11.1 OperatingEnvironment

The operatingenvironmentcontrolstheresetvector(bootaddress).InERE16 mode, thevectoris0040 0000h.InERE32 mode, thevectoris0080 0000h. The operatingmode ofthedeviceiscontrolledby thestatessampled fromtheENV[1:0]pinsatreset,as shown inTable11-1.Internalpullupson theENV[1:0]pinsselectERE16 mode ifthesepinsareallowed tofloat. Table11-1.OperatingEnvironment Selection ENV[1:0] OPERATING ENVIRONMENT

11 ERE16 mode (bootfrom0040 0000h)

10 ERE32 mode (bootfrom0080 0000h)

11.2 FreezeMode

Fordebuggingpurposes,a Freezemode isavailablewhichhas thefollowingeffects:

• Disablesmaskableinterrupts.
• Suspends DMA transactions.
• Inhibitscertainstatechanges inthefollowingmodules (seeindividualmodule descriptionsfordetails): Advanced Audio Interface,A/D Converter,Codec, CVSD/ PCM Converters,Multi-FunctionTimers, Timingand Watchdog Module,and VersatileTimerUnits.
• Inhibitsautomaticclear-on-readfunctionappliedtotheregisterbitslistedinTable11-2. Table11-2.RegisterBitsAffectedBy FreezeMode MODULE REGISTERS BITS ACCESS.bus ACBnST SDAST ADC_DONE, ADC_OFLW,A/D Converter ADCRESLT SIGN, ADC_RESULT ARSCR RXO, RXE, RXF, RXAF Advanced AudioInterface(AAI) ATSCR TXU, TXF, TXE, TXAE Codec TCDCADCn ADCDATA CVSD/PCM Converter CVSTATn PCMINT, CVE, CVF Microwire/SPI MWnDAT RBF Timingand Watchdog Module T0CSR TC URBUFn URBF USART0, UART 1,2,3 USTATn UPE, UFE, UDOE, UBKD

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www.ti.com SNOSCW5 –MAY 2013 Freeze mode can be enteredby settingthe FREEZE bitinthe MCFG registeror usinga mechanism enabled throughthe SerialDebug Interface(SDI).Freeze mode does not directlyaffectthe DSP subsystem. NOTE Debugging toolsmay assertFreeze mode togatherinformation,which may cause periodic fluctuationsinresponse(bus availability,interruptlatency,etc.).Anomalous behavioroften may be tracedtotheactivityofthesetools.

11.3 System ConfigurationRegisters

The system configurationregisterscontroland providestatusforcertainaspectsof devicesetup and operation,such as indicatingthe statessampled from the ENV[1:0]inputs.The system configuration registersarelistedinTable11-3. Table11-3.System ConfigurationRegisters NAME ADDRESS DESCRIPTION MCFG FF F400h Module ConfigurationRegister MSTAT FF F404h Module StatusRegister SWRESET FF F408h SoftwareResetRegister SYSCFG FF F40Ch System ConfigurationRegister

11.4 Module ConfigurationRegister(MCFG)

The MCFG registerisa byte-wide,read/writeregisterthatselectstheclockoutputfeaturesofthedevice and enablesFreeze mode. The MCFG registerformatisshown below.At reset,the MCFG registeris initializedto00h. 7 6 5 4 3 2 1 0 Reserved FREEZE Reserved ENV1SEL ENV0SEL ENV1OE ENV0OE ENV0OE The ENV0 OutputEnablebitenablesdrivingan internalclocksignalselectedby the ENV0SEL biton theENV0 pin.Ifno signalisdrivenon theENV0 pin,itwillbe undriven (highimpedance)afterreset. 0 – ENV0 isundrivenafterreset. 1 – ENV0 isdrivenby an internalclocksignal. ENV1OE The ENV1 OutputEnablebitenablesdrivingan internalclocksignalselectedby the ENV1SEL biton theENV1 pin.Ifno signalisdrivenon theENV1 pin,itwillbe undriven (highimpedance)afterreset. 0 – ENV1 isundrivenafterreset. 1 – ENV1 isdrivenby an internalclocksignal. ENV0SEL The ENV0 Selectbitselectsan internalclocksignaltobe availablefordrivingon theENV0 pin.The ENV0OE bitmust be settoenabledrivingtheselectedsignalon theENV0 pin. 0 – Slow Clockisavailabletodriveon ENV0. 1 – PLL1 Clockisavailabletodriveon ENV0. ENV1SEL The ENV1 Selectbitselectsan internalclocksignaltobe availablefordrivingon theENV1 pin.The ENV1OE bitmust be settoenabledrivingtheselectedsignalon theENV1 pin. 0 – Main Clockisavailabletodriveon ENV1. 1 – PLL2 Clockisavailabletodriveon ENV1. Copyright© 2013,Texas InstrumentsIncorporated System Configuration 53 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com FREEZE The FreezebitcontrolswhetherthedeviceisplacedinFreezemode, whichisa debugging mode thatinhibitscertainautomaticstatechanges inregisterbits,such as timersand clear- on-readregisters.See Section11.2formore informationaboutFreezemode. The Serial Debug Interface(SDI)alsohas thecapabilityofputtingthedeviceinFreezemode through a separatemechanism. 0 – Freezemode disabled. 1 – Freezemode enabled.

11.5 Module StatusRegister(MSTAT)

The MSTAT registerisa byte-wide,read-onlyregisterthatindicatesthegeneralstatusofthedevice.The MSTAT registerformatisshown below.At reset,theMSTAT registerisinitializedto00h,exceptforbits0 and 1 whicharesampled fromtheENV pins. 7 6 5 2M M 1 0M ISPRST WDRST Reserved OENV OENV The OperatingEnvironmentbitsholdthestatessampled fromtheENV[1:0]inputpinsatreset. These statesarecontrolledby externalhardwareatresetand areheldconstantintheregister untilthenextreset. WDRST The Watchdog Resetbitindicatesthata Watchdog timerresethas occurred.Writea 1 tothis bittoclearit.Power-onresetalsoclearsthisbit. 0 – No Watchdog timerresethas occurredsincethisbitwas lastcleared. 1 – A Watchdog timerresethas occurredsincethisbitwas lastcleared. ISPRST The SoftwareISP Resetbitindicatesthata SWRESET(ISP) resethas occurredsincethebit was lastcleared.Thisbitisclearedby a SWRESET(CLR) sequence ora power-onreset.See thedescriptionoftheSWRESET registerformore information. 0 – No SWRESET(ISP) resethas occurredsincethisbitwas lastcleared. 1 – A SWRESET(ISP) resethas occurredsincethisbitwas lastcleared.

11.6 SoftwareReset Register(SWRESET)

The SWRESET registerisan 8-bit,write-onlyregisterwhichprovidesa mechanism forsoftwaretoinitiate a reset.There aretwo softwareresetsequences,calledSWRESET(ISP) and SWRESET(CLR), whichare providedforcompatibilitywithotherCP3000 devicesthathave an in-systemprogramming (ISP)mode, however theCP3SP33 does nothave an ISP mode. To initiatea SWRESET(ISP) reset,writethe valueE1h to the SWRESET register,followedwithin127 PCLK Clock cycles by writingthe value 3Eh. The reset then followsimmediately.After the SWRESET(ISP) resetoccurs,theISPRST bitintheMSTAT registerisset. To initiatea SWRESET(CLR) reset,writethe valueE1h to the SWRESET register,followedwithin127 PCLK Clock cycles by writingthe value 0Eh. The reset then followsimmediately.After the SWRESET(CLR) resetoccurs,theISPRST bitintheMSTAT registerisclear.

11.7 System ConfigurationRegister(SYSCFG)

The SYSCFG registerisa byte-wide,read/writeregisterthatindicatesthegeneralstatusofthedevice. The SYSCFG registerformatisshown below.Atreset,theSYSCFG registerisinitializedto00h. 7 6 4 3 2 1 0 XDPUDIS Reserved USBIDDIGPUEN USBHCLKDIS BTHCKLDIS RFCKEN

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www.ti.com SNOSCW5 –MAY 2013 RFCKEN The RF ClockEnablebitcontrolswhetherMain Clockisdrivenon theCLKIN/RFCK pin. 0 – Main Clockisnotdrivenon CLKIN/RFCK. 1 – Main Clockisdrivenon CLKIN/RFCK. BTHCLKDIS The BluetoothClockDisablebitcontrolswhetherHCLK ClocktotheBluetooth module isdisabled. 0 – HCLK ClockisavailabletotheBluetoothmodule. 1 – HCLK ClockisnotavailabletotheBluetoothmodule. USBHCLKDIS The USB ClockDisablebitcontrolswhethertheHCLK ClocktotheUSB module is disabled. 0 – HCLK ClockisavailabletotheUSB module. 1 – HCLK ClockisnotavailabletotheUSB module. USBIDDIGPUEN The USB IDDIG PullupEnablebitcontrolswhethertheUSB module can enablethe internalpullupon thePE15 portpin.Thismode onlyapplieswhen theIDDIG alternatefunctionforPE15 isenabled. 0 – Internalpullupon PE15 isdisabledwhen IDDIG alternatefunctionisselected. 1 – USB module controlsinternalpullupon PE15 when IDDIG alternatefunctionis selected. XDPUDIS The XD PullupDisablebitcontrolswhetherweak pullupresistorsareenabledon the XD externaldatabus. 0 – Weak pullupson XD bus. 1 – No pullupson XD bus.

12 CPU DMA Controller

The CPU DMA controller(DMAC) can be used toaccelerateperipheral-to-memory,memory-to-peripheral, and memory-to-memory blocktransfers.Because ituses cyclestealingtointerleavebus cycleswiththe CPU, DMA-based datamovement uses theavailablebandwidthon theCPU corebus more efficientlythan software-baseddatamovement The DMAC provides16 DMA channels,which may be assignedto any of 34 peripheralregisters.For registersthatare loadedby the peripheral(suchas a UART receiveregister),the DMAC getsa DMA requestwhen theregisterisloaded.Itthenreadstheregisterand writesthedatatomemory. Forregisters thatare unloadedby theperipheral(suchas a UART transmitregister),theDMAC getsa DMA request when theregisterisempty.Itthenreadsdatafrommemory and writesthedatatotheregister.Only one registerata timemay be enabledtouse a DMA channel.Any channelwhichisnotenabledforperipheral DMA may be used forsoftwareDMA (memory-to-memoryblocktransfers). The DMAC has a register-basedprogramming interface(asopposed toI/Ocontrolblocks).Afterloading theregisterswithsourceand destinationaddresses,as wellas blocksizeand typeofoperation,a DMAC channelisreadytorespondtoDMA transferrequests.A requestcan onlycome fromonchipperipherals orsoftware,notexternalperipherals.On receivinga DMA transferrequest,ifthechannelisenabled,the DMAC performsthefollowingoperations: 1. Arbitratestobecome masteroftheCPU corebus. 2. Determinespriorityamong theDMAC requests.Priorityislinear,withchannel0 havingthehighest priority. 3. Executesdatatransferbus cycle(s)specifiedby theprogrammingofthecontrolregistersforthe channelbeingserviced.Thismay be a singlecycleora fourcycleburst. 4. IftheDMA transfercycleiscomplete,theDMAC does thefollowing: – Updatestheterminationbits. – Assertsan interrupt(ifenabled). 5. ReturnscontroloftheCPU corebus totheCPU, even ifa DMA requestcontinuestobe asserted. Priorityamong DMA channelsisre-determinedaftereverycycle. Copyright© 2013,Texas InstrumentsIncorporated CPU DMA Controller 55 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com AllDMA transfersare indirectmode, in which the data isread from the source intoa DMAC buffer register,thenwrittenfromthebufferregistertothedestination. Each DMAC channelhas ten 32-bitcontroland statusreg-isters.DMAC registersare named withthe suffixn,inwhichn is0 to15,representingthechannelnumber. Ifallof the channelsare disabled(DMACNTn.CHEN = 0),the clockto the DMA module isdisabledto reducepower consumption.

12.1 DMA-Capable Peripherals

Table12-1shows theDMA-capable peripherals,whichmay be assignedtoany ofthe16 DMA channels by programmingtheSRCRQ fieldoftheDMACNTn registers.The SRCRQ fieldonlyselectsthesourceof theDMA requestsignaland thereceiverfortheDMA acknowledgesignal.Itisstillnecessarytosetup the addressoftheperipheral,thetransferdirection,and otherDMA channelcontrolsettings. Table12-1.DMA-Capable Peripherals SRCRQ PERIPHERAL TRANSACTION REGISTER ASC CHANNEL

0 UART3 R RXBUF3 0

1 UART3 W TXBUF3 1

2 CVSD/PCM0 R PCMOUT0 2

3 CVSD/PCM0 W PCMIN0 3

4 CVSD/PCM1 R PCMOUT1 4

5 CVSD/PCM1 W PCMIN1 5

6 AAI Slot0 R ARDR0 6

7 AAI Slot0 W ATDR0 7

8 AAI Slot1 R ARDR1 8

9 AAI Slot1 W ATDR1 9

10 Codec ADC1 R TCDCADC1 10

11 Codec ADC2 R TCDCADC2 11

12 Codec DAC Left W TCDCLEFT 12

13 Codec DAC Right W TCDCRIGHT 13

14 I2S Left R I2SRXDATL 14

15 I2S Right R I2SRXDATR 15

16 I2S Left W I2STXDATL 16

17 I2S Right W I2STXDATR 17

18 MWSPI1 R MWDAT 18

19 MWSPI1 W MWDAT 19

20 ACCESS.bus 1 R/W ACBSDA 20

21 USART0 R RXBUF0

22 USART0 W TXBUF0

23 UART1 R RXBUF1

24 UART1 W TXBUF1

25 UART2 R RXBUF2

26 UART2 W TXBUF2

27 CVSD/PCM0 R CVSDOUT0

28 CVSD/PCM0 W CVSDIN0

29 CVSD/PCM1 R CVSDOUT1

30 CVSD/PCM1 W CVSDIN1

31 AAI Slot2 R ARDR2

32 AAI Slot2 W ATDR2

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www.ti.com SNOSCW5 –MAY 2013 Table12-1.DMA-Capable Peripherals(continued) SRCRQ PERIPHERAL TRANSACTION REGISTER ASC CHANNEL

33 MWSPI0 R MWDAT

34 MWSPI0 W MWDAT

35 ACCESS.bus 0 R/W ACBSDA The DMA requestand DMA acknowledgesignalsforperipheralssharedwiththeDSP DMA controllerare sentthroughthe Audio Subsystem Controller(ASC),which multiplexesthesesignalsbetween the CPU DMA controllerand the DSP DMA controller.In Table 12-1, the ASC channel number refersto the multiplexerchannelused to selectthe DMA controllerthathandlesthe DMA requestand acknowledge signalsforthatperipheral.

12.2 TransferTypes

The DMAC supportsthreetransfertypes:

• SingleTransfers— A singlereadcyclefollowedby a singlewritecycle.
• BurstTransfers— A four-cycleburstreadfrommemory followedby a four-cycleburstwritetomemory. SoftwareDMA requests(memory-to-memoryblocktransfers)arealwaysbursttransfers.
• Data CollectionTransfers— A four-cycleburstreadfrommemory followedby foursingle-cyclewritesto a peripheral,or foursingle-cyclereads from a peripheralfollowedby a four-cycleburstwriteto memory. Priorityamong DMA requestsislinearfortransfersof the same type(channel0 has highestpriority), however bursttransfersand datacollectiontransfershave priorityoversingletransfers. Duringa singletransfer,thetransfercyclesize(number ofbytesper cycle)iscontrolledby theWMODE and TCS bitsoftheDMACNTn register,as shown inTable12-2.Duringa burst,thetransfercyclesizeis always4 bytes. Table12-2.TransferCycle Size TRANSFER CYCLE SIZE WMODE TCS

1 Byte 0 0

2 Bytes 0 1

4 Bytes 1 X

The transfertype is selectedby the SWRQ and BBE bitsin the DMACNTn register,as shown in Table12-3.Onlychannels0 and 1 supportdatacollectionmode. Table12-3.DMA TransferTypes TRANSFER TYPE SWRQ BBE SingleCycle 0 0 Data Collection 0 1 Burst 1 X Copyright© 2013,Texas InstrumentsIncorporated CPU DMA Controller 57 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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12.2.1 DMA BufferFlush

When datacollectionmode has been used toread datafrom a peripheral,thenumber ofbytesreceived from theperipheralmightnotcorrespondtoan integralnumber ofbursts.To flushdataremaininginthe buffer,performthefollowingsteps: 1. DisabletheperipheralDMA request.Do notcleartheDMA channelenablebit(theCHEN bitinthe DMACNTn register),because clearingthisbitwillclearthebuffer. 2. Read theBNE bitand theBLV fieldintheDMASTATn register.The BNE bitindicateswhetherthereis validdatainthebuffer.The BLV fieldindicatesthenumber ofvalidbytesinthebuffer. 3. CleartheBBE bitintheDMACNTn register.Thisenablesa burstwritetomemory, even thoughthe bufferisnotfull.Invalidentriesinthebufferarewrittentomemory withundefineddata. A bufferflushwillonlyoccurwhen the DIR bitinthe DMACNTn registerisclear,and the bufferisnot empty (theBNE bitin the DMASTATn registerisset).Ifthe DIR bitisset,the data in the bufferis discarded.

12.3 TransferModes

A DMAC channelmay be used inone ofthreedifferenttransfermodes:

• SingleBuffer— The transferperformedforthe channelisspecifiedby the statessampled from the controlregisterswhen thelastDMA requestwas enabled.
• Double Buffer— The transferperformedforthe channelisspecifiedby the statessampled from the controlregisterswhen thelastDMA requestwas enabled.A new setofstatesisloadedintothecontrol registerstospecifythenexttransfertobe performedforthechannel.
• Auto-initialize— The transferperformedforthe channelisspecifiedin itscontrolregisters,and the operationisrepeatedas longas thechannelisenabled. The OT bitintheDMACNTn registerisclearforsinglebufferand doublebuffermode. The OT bitissetto enableauto-initializemode. Double buffermode isobtainedby reloadingtheDMAC channelcontrolregistersaftera DMA requesthas been enabled.A DMA requestisenabledby loadingtheDMACNTn registerwitha setCHEN bit.After enablinga DMA request,theDMA controlregistersmay be loadedwithnew states.The BLTRn register must be writtenlast,because loadingthisregistersetsthe VLD bitinthe DMASTATn register,which indicatesthatnew valueshave been loadedintothecontrolregisters. When thePF bitintheDMACNTn registerisclear,theDMAC istheflowcontrollerforthetransfer.When thePF bitisset,theperipheralistheflowcontroller.Indoublebuffermode withtheperipheralas theflow controller,theBLTRn registermust be writtenso thattheVLD bitbecomes set,even thoughthevaluein theBLTRn registerisnotused.

12.3.1 SingleBufferMode

Thismode providesthesimplestway toaccomplisha singledatatransfer. 12.3.1.1Initialization 1. Selecttheperipheraldeviceby writingtheSRCRQ fieldintheDMACNTn register. 2. Writetheblocktransferaddressesand bytecountintothecorrespondingADCAn, ADCBn, and BLTCn counters. 3. CleartheDMACNTn.OT bittoselectnon-auto-initializemode. CleartheDMASTAT.VLD bitby writing a 1 toit. 4. SettheDMACNTn.CHEN bittoactivatethechanneland enableittorespondtoDMA transfer requests.IftheDMACNTn registerisloadedforany otherreason,theDMACNTn.CHEN bitmust be cleartoavoidprematurelystartinga new DMA transfer.

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www.ti.com SNOSCW5 –MAY 2013 12.3.1.2Termination When the DMAC isthe flowcontroller,the transferterminateswhen the transfercount in the BLTCn registerreacheszero.When theperipheralistheflowcontroller,theperipheralsignalstheend oftransfer. On termination: 2. An interruptisassertedifenabledby theDMACNTn.ETC orDMACNTn.EOVR bits.

12.3.2 Double BufferMode

Thismode allowssoftwaretosetup thenextDMA transferwhilethecurrenttransferproceeds. 12.3.2.1Initialization 1. Selecttheperipheraldeviceby writingtheSRCRQ fieldintheDMACNTn register. 2. Writetheblocktransferaddressesand bytecountintotheADCAn, ADCBn, and BLTCn counters. 3. CleartheDMACNTn.OT bittoselectnon-auto-initializemode. CleartheDMASTAT.VLD bitby writing a 1 toit. 4. SettheDMACNTn.CHEN bit.Thisactivatesthecha neland enablesittorespondtoDMA transfer requests.IftheDMACNTn registerisloadedforany otherreason,theDMACNTn.CHEN bitmust be cleartoavoidprematurelystartinga new DMA transfer. 5. Whilethecurrentblocktransferproceeds,writetheaddressesand bytecountforthenextblockinto theADRAn, ADRBn, and BLTRn registers.The BLTRn registermust be writtenlast,because writing thisregistersetstheDMASTAT.VLD bitwhichindicatestotheDMAC thattheparametersforthenext transferhave been updated. 12.3.2.2Continuation/Termination When the BLTCn counterreaches 0 (DMACNTn.PF = 0) or the lastrequesthas been processed (DMACNTn.PF = 1): 1. IftheDMACNTn.PF bitisclear,theDMASTATn.TC bitisset. 2. Ifenabledby theDMACNTn.ETC bit,an interruptisasserted. 3. The DMAC channelcheckstheDMASTAT.VLD bit. IftheDMASTAT.VLD bitisset: 1. The channelcopiestheADRAn, ADRBn, and BLTRn valuesintotheADCAn, ADCBn, and BLTCn registers. 2. The DMASTAT.VLD bitiscleared. 3. The nextblocktransferisstarted. IftheDMASTAT.VLD bitisclear: 1. The transferoperationterminates. 2. The channelsetstheDMASTAT.OVR bit. 3. The DMASTAT.CHAC bitiscleared. 4. Ifenabledby theDMACNTn.EOVR bit,an interruptisasserted. Copyright© 2013,Texas InstrumentsIncorporated CPU DMA Controller 59 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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12.3.3 Auto-InitializeMode

This mode causes the DMA channel to repeat the same operationcontinuouslywithoutsoftware intervention.The operationisrepeateduntilthechannelisdisabled. 12.3.3.1Initialization 1. Selecttheperipheraldeviceby writingtheSRCRQ fieldintheDMACNTn register. 2. Writetheblockaddressesand bytecountintotheADCAn, ADCBn, and BLTCn counters,as wellas theADRAn, ADRBn, and BLTRn registers. 3. SettheDMACNTn.OT bittoselectauto-initializemode. 4. SettheDMACNTn.CHEN bittoactivatethechanneland enableittorespondtoDMA transfer requests.IftheDMACNTn registerisloadedforany otherreason,theDMACNTn.CHEN bitmust be cleartoavoidprematurelystartinga new DMA transfer. 12.3.3.2Continuation When the BLTCn counterreaches 0 (DMACNTn.PF = 0) or the lastrequesthas been processed (DMACNTn.PF = 1): 1. The contentsoftheADRAn, ADRBn, and BLTRn registersarecopiedtotheADCAn, ADCBn, and BLTCn counters. 2. The DMAC channelchecksthevalueoftheDMASTAT.TC bit. IftheDMASTAT.TC bitissetand theDMACNTn.PF bitisclear: 1. The DMASTAT.OVR bitisset. 2. Ifenabledby theDMACNTn.EOVR bit,an interruptisasserted. 3. The DMAC operationisrepeated. IftheDMASTAT.TC and DMACNTn.PF bitsareclear: 1. The DMASTAT.TC bitisset. 2. Ifenabledby theDMACNTn.ETC bit,an interruptisasserted. 3. The DMAC operationisrepeated. 12.3.3.3Termination The DMA transferisterminatedwhen theDMACNTn.CHEN bitiscleared.

12.4 SoftwareDMA Request

In additionto the hardware requestsfrom peripherals,a DMA transferrequestcan alsobe initiatedby software.A softwareDMA transferrequestisused formemory-to-memoryblocktransfers. When theDMACNTn.SWRQ bitisset,thecorrespondingDMA channelreceivesa softwareDMA request. When theDMACNTn.SWRQ bitisclear,thesoftwareDMA requestforthechannelisinactive. A softwareDMA requestmay onlybe assertedwhen theassociatedperipheralDMA requestisdisabled and thechannelisinactive.Softwarecan polltheDMASTAT.CHAC bittodeterminewhetherthechannel iscurrentlyactive. When theDMACNTn.DIR bitis0,thefirstbus cyclereadsdatafromthesourceusingtheADCAn counter, whilethe second bus cyclewritesthe data intothe destinationusingthe ADCBn counter.When the DMACNTn.DIR bitisset,thefirstbus cyclereadsdatafrom thesourceusingtheADCBn counter,while thesecond bus cyclewritesthedataintothedestinationaddressedby theADCAn counter.

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Register (RQTRn) Request Timeout Counter Register (RQTCNTn) DS427 10-Bit Prescaler System Clock TOEN InterruptTC CP3SP33 www.ti.com SNOSCW5 –MAY 2013

12.5 DMA Request Timeout

Each DMA channelmay asserta timeoutinterruptiftoomuch timeoccursbetween DMA requests.A 10- bitprescalerdividestheHCLK Clockby 1024 toprovidea timebasefora timeoutcounter,as shown in Figure12-1. Figure12-1.DMA Request Timeout Counter Softwareloadsa timeoutintervalintheRQTRn register.When a DMA requestisreceived,theRQTCNTn registerisloadedwiththecontentsoftheRQTRn register.IftheTOEN bitisset,theRQTCNTn register decrementson everyclockreceivedfromtheprescaler.When theRQTCNTn registerreachesitsterminal count,an interruptisasserted. Once the timeoutinterruptisenabledand a DMA requestisreceived,the timeoutinterruptwilloccur unless:the next DMA requestisreceivedbeforethe end of the timeoutinterval,or the TOEN bitis cleared.

12.6 ErrorResponse

When an erroroccurs,the DMASTATn.ERR bitisset,and the DMASTATn.CHAC bitiscleared.The currenttransfercycleiscompletedorterminated,and thechannelcannotbe used againuntiltheERR bit iscleared(by writing1 to it).An errormay occurbecause the addresswas invalidor an incremental accessgoes outofbounds.

12.7 FreezeMode

When theFreezemode isentered,allDMA operationsarestopped.Pendingoperationsarestoppedafter completionof the currenttransfer.They willstartagain when the Freeze mode isexited.This allows breakpointstobe used indebug systems.

12.8 RegisterProgramming

The DMAC onlyhandlesaddress-alignedtransfers.The addressesloadedintoADCAn, ADRAn, ADCBn, and ADRBn must be multiplesof the transfercyclesize.Do not writethe counterregistersADCAn, ADCBn, or BLTCn whilethe channelisactive(DMASTAT.CHAC = 1).When a channelisactivatedfor DMAC flowcontrol,theBLTCn and BLTRn registersmust holdvaluesgreaterthan0.

12.9 DMA ControllerRegisterSet

Thereare16 identicalsetsof10 DMA controllerregisters,as listedinTable12-4. Table12-4.DMA ControllerRegisters Name Address Description Name Address Description ADCA0 FF 0400h DeviceA AddressCounterRegister ADRB4 FF 050Ch DeviceB AddressRegister ADRA0 FF 0404h DeviceA AddressRegister BLTC4 FF 0510h BlockLengthCounterRegister ADCB0 FF 0408h DeviceB AddressCounterRegister BLTR4 FF 0514h BlockLengthRegister ADRB0 FF 040Ch DeviceB AddressRegister RQTR4 FF 0518h RequestTimeoutRegister Copyright© 2013,Texas InstrumentsIncorporated CPU DMA Controller 61 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table12-4.DMA ControllerRegisters(continued) Name Address Description Name Address Description BLTC0 FF 0410h BlockLengthCounterRegister RQTCNT4 FF 051Ch RequestTimeoutCounterRegister BLTR0 FF 0414h BlockLengthRegister DMACNT4 FF 0520h DMA ControlRegister RQTR0 FF 0418h RequestTimeoutRegister DMASTAT4 FF 0524h DMA StatusRegister RQTCNT0 FF 041Ch RequestTimeoutCounterRegister ADCA5 FF 0540h DeviceA AddressCounterRegister DMACNT0 FF 0420h DMA ControlRegister ADRA5 FF 0544h DeviceA AddressRegister DMASTAT0 FF 0424h DMA StatusRegister ADCB5 FF 0548h DeviceB AddressCounterRegister ADCA1 FF 0440h DeviceA AddressCounterRegister ADRB5 FF 054Ch DeviceB AddressRegister ADRA1 FF 0444h DeviceA AddressRegister BLTC5 FF 0550h BlockLengthCounterRegister ADCB1 FF 0448h DeviceB AddressCounterRegister BLTR5 FF 0554h BlockLengthRegister ADRB1 FF 044Ch DeviceB AddressRegister RQTR5 FF 0558h RequestTimeoutRegister BLTC1 FF 0450h BlockLengthCounterRegister RQTCNT5 FF 055Ch RequestTimeoutCounterRegister BLTR1 FF 0454h BlockLengthRegister DMACNT5 FF 0560h DMA ControlRegister RQTR1 FF 0458h RequestTimeoutRegister DMASTAT5 FF 0564h DMA StatusRegister RQTCNT1 FF 045Ch RequestTimeoutCounterRegister ADCA6 FF 0580h DeviceA AddressCounterRegister DMACNT1 FF 0460h DMA ControlRegister ADRA6 FF 0584h DeviceA AddressRegister DMASTAT1 FF 0464h DMA StatusRegister ADCB6 FF 0588h DeviceB AddressCounterRegister ADCA2 FF 0480h DeviceA AddressCounterRegister ADRB6 FF 058Ch DeviceB AddressRegister ADRA2 FF 0484h DeviceA AddressRegister BLTC6 FF 0590h BlockLengthCounterRegister ADCB2 FF 0488h DeviceB AddressCounterRegister BLTR6 FF 0594h BlockLengthRegister ADRB2 FF 048Ch DeviceB AddressRegister RQTR6 FF 0598h RequestTimeoutRegister BLTC2 FF 0490h BlockLengthCounterRegister RQTCNT6 FF 059Ch RequestTimeoutCounterRegister BLTR2 FF 0494h BlockLengthRegister DMACNT6 FF 05A0h DMA ControlRegister RQTR2 FF 0498h RequestTimeoutRegister DMASTAT6 FF 05A4h DMA StatusRegister RQTCNT2 FF 049Ch RequestTimeoutCounterRegister ADCA7 FF 05C0h DeviceA AddressCounterRegister DMACNT2 FF 04A0h DMA ControlRegister ADRA7 FF 05C4h DeviceA AddressRegister DMASTAT2 FF 04A4h DMA StatusRegister ADCB7 FF 05C8h DeviceB AddressCounterRegister ADCA3 FF 04C0h DeviceA AddressCounterRegister ADRB7 FF 05CCh DeviceB AddressRegister ADRA3 FF 04C4h DeviceA AddressRegister BLTC7 FF 05D0h BlockLengthCounterRegister ADCB3 FF 04C8h DeviceB AddressCounterRegister BLTR7 FF 05D4h BlockLengthRegister ADRB3 FF 04CCh DeviceB AddressRegister RQTR7 FF 05D8h RequestTimeoutRegister BLTC3 FF 04D0h BlockLengthCounterRegister RQTCNT7 FF 05DCh RequestTimeoutCounterRegister BLTR3 FF 04D4h BlockLengthRegister DMACNT7 FF 05E0h DMA ControlRegister RQTR3 FF 04D8h RequestTimeoutRegister DMASTAT7 FF 05E4h DMA StatusRegister RQTCNT3 FF 04DCh RequestTimeoutCounterRegister ADCA8 FF 0600h DeviceA AddressCounterRegister DMACNT3 FF 04E0h DMA ControlRegister ADRA8 FF 0604h DeviceA AddressRegister DMASTAT3 FF 04E4h DMA StatusRegister ADCB8 FF 0608h DeviceB AddressCounterRegister ADCA4 FF 0500h DeviceA AddressCounterRegister ADRB8 FF 060Ch DeviceB AddressRegister ADRA4 FF 0504h DeviceA AddressRegister BLTC8 FF 0610h BlockLengthCounterRegister ADCB4 FF 0508h DeviceB AddressCounterRegister BLTR8 FF 0614h BlockLengthRegister RQTR8 FF 0618h RequestTimeoutRegister ADCB12 FF 0708h DeviceB AddressCounterRegister RQTCNT8 FF 061Ch RequestTimeoutCounterRegister ADRB12 FF 070Ch DeviceB AddressRegister DMACNT8 FF 0620h DMA ControlRegister BLTC12 FF 0710h BlockLengthCounterRegister DMASTAT8 FF 0624h DMA StatusRegister BLTR12 FF 0714h BlockLengthRegister ADCA9 FF 0640h DeviceA AddressCounterRegister RQTR12 FF 0718h RequestTimeoutRegister ADRA9 FF 0644h DeviceA AddressRegister RQTCNT12 FF 071Ch RequestTimeoutCounterRegister ADCB9 FF 0648h DeviceB AddressCounterRegister DMACNT12 FF 0720h DMA ControlRegister ADRB9 FF 064Ch DeviceB AddressRegister DMASTAT12 FF 0724h DMA StatusRegister BLTC9 FF 0650h BlockLengthCounterRegister ADCA13 FF 0740h DeviceA AddressCounterRegister BLTR9 FF 0654h BlockLengthRegister ADRA13 FF 0744h DeviceA AddressRegister RQTR9 FF 0658h RequestTimeoutRegister ADCB13 FF 0748h DeviceB AddressCounterRegister RQTCNT9 FF 065Ch RequestTimeoutCounterRegister ADRB13 FF 074Ch DeviceB AddressRegister

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www.ti.com SNOSCW5 –MAY 2013 Table12-4.DMA ControllerRegisters(continued) Name Address Description Name Address Description DMACNT9 FF 0660h DMA ControlRegister BLTC13 FF 0750h BlockLengthCounterRegister DMASTAT9 FF 0664h DMA StatusRegister BLTR13 FF 0754h BlockLengthRegister ADCA10 FF 0680h DeviceA AddressCounterRegister RQTR13 FF 0758h RequestTimeoutRegister ADRA10 FF 0684h DeviceA AddressRegister RQTCNT13 FF 075Ch RequestTimeoutCounterRegister ADCB10 FF 0688h DeviceB AddressCounterRegister DMACNT13 FF 0760h DMA ControlRegister ADRB10 FF 068Ch DeviceB AddressRegister DMASTAT13 FF 0764h DMA StatusRegister BLTC10 FF 0690h BlockLengthCounterRegister ADCA14 FF 0780h DeviceA AddressCounterRegister BLTR10 FF 0694h BlockLengthRegister ADRA14 FF 0784h DeviceA AddressRegister RQTR10 FF 0698h RequestTimeoutRegister ADCB14 FF 0788h DeviceB AddressCounterRegister RQTCNT10 FF 069Ch RequestTimeoutCounterRegister ADRB14 FF 078Ch DeviceB AddressRegister DMACNT10 FF 06A0h DMA ControlRegister BLTC14 FF 0790h BlockLengthCounterRegister DMASTAT10 FF 06A4h DMA StatusRegister BLTR14 FF 0794h BlockLengthRegister ADCA11 FF 06C0h DeviceA AddressCounterRegister RQTR14 FF 0798h RequestTimeoutRegister ADRA11 FF 06C4h DeviceA AddressRegister RQTCNT14 FF 079Ch RequestTimeoutCounterRegister ADCB11 FF 06C8h DeviceB AddressCounterRegister DMACNT14 FF 07A0h DMA ControlRegister ADRB11 FF 06CCh DeviceB AddressRegister DMASTAT14 FF 07A4h DMA StatusRegister BLTC11 FF 06D0h BlockLengthCounterRegister ADRA15 FF 07C4h DeviceA AddressRegister BLTR11 FF 06D4h BlockLengthRegister ADCB15 FF 07C8h DeviceB AddressCounterRegister RQTR11 FF 06D8h RequestTimeoutRegister ADRB15 FF 07CCh DeviceB AddressRegister RQTCNT11 FF 06DCh RequestTimeoutCounterRegister BLTC15 FF 07D0h BlockLengthCounterRegister DMACNT11 FF 06E0h DMA ControlRegister BLTR15 FF 07D4h BlockLengthRegister DMASTAT11 FF 06E4h DMA StatusRegister RQTR15 FF 07D8h RequestTimeoutRegister ADCA12 FF 0700h DeviceA AddressCounterRegister RQTCNT15 FF 07DCh RequestTimeoutCounterRegister ADRA12 FF 0704h DeviceA AddressRegister DMACNT15 FF 07E0h DMA ControlRegister ADCA15 FF 07C0h DeviceA AddressCounterRegister DMASTAT15 FF 07E4h DMA StatusRegister

12.9.1 Device A Address Counter Registern (ADCAn)

The Device A Address Counterregisterisa 32-bit,read/writeregister.Itholdsthe currentaddressof eitherthe source data item or the destinationlocation,depending on the stateof the DIR bitin the DMACNTn register.The ADA bitof DMACNTn registercontrolswhether to adjustthe pointerin the ADCAn registerby thestepsizespecifiedintheINCA fieldofDMACNTn register. 31 0 DeviceA AddressCounter

12.9.2 Device A Address Registern (ADRAn)

The DeviceA Address registerisa 32-bit,read/writeregister.Itholdsthestartingaddressofeitherthe next source data block,or the next destinationdata area,accordingto the DIR bitin the DMACNTn register. 31 0 DeviceA Address

12.9.3 Device B Address Counter Registern (ADCBn)

The DeviceB Address Counterregisterisa 32-bit,read/writeregister.Itholdstheaddressofeitherthe source data item,or the destinationlocation,accordingto the DIR bitin the DMACNTn register.The ADCBn registerisupdatedaftereach transfercycleby INCB fieldoftheDMACNTn registeraccordingto ADB bitoftheDMACNTn register. Copyright© 2013,Texas InstrumentsIncorporated CPU DMA Controller 63 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 31 0 DeviceB AddressCounter

12.9.4 Device B Address Registern (ADRBn)

The DeviceB Address registerisa 32-bit,read/writeregister.Itholdsthestartingaddressofeitherthe next source data blockor the next destinationdata area,accordingto the DIR bitin the DMACNTn register. 31 0 DeviceB Address

12.9.5 Block Length Counter Registern (BLTCn)

The BlockLength Counterregisterisa 32-bit,read/writeregister.Itholdsthe currentnumber of DMA transferstobe executedinthecurrentblock.0000 0000h isinterpretedas 232-1transfercycles.BLTCn is decrementedby one aftereach transfercycle.A DMA transfermay consistof1,2,or4 bytes,as selected by theTCS and WMODE bitsintheDMACNTn register. 32 0 BlockLengthCounter

12.9.6 Block Length Registern (BLTRn)

The Block Length registerisa 32-bit,read/writeregister.Itholdsthe number of DMA transfersto be performedforthe next block.0000 0000h isinterpretedas 232-1 transfercycles.Writingthisregister automaticallysetstheDMASTAT.VLD bit. 15 0 BlockLength

12.9.7 Request Timeout Registern (RQTRn)

The Request Timeout registerisa 32-bit,read/writeregister.Itholdsthe timeouttime.Afterreset,the RQTRn registersareclear. 31 15M M 8 0 Reserved Timeout

12.9.8 Request Timeout Counter Registern (RQTCNTn)

The Request TimeoutCount registerisa 32-bit,read-onlyregister.Itholdsthecurrenttimeoutcount.A RQTCNTn registerisloadedfrom itscorrespondingRQTRn registerwhen itsDMA requestisasserted. The RQTCNTn registeris decremented ifthe DMACNT.TOEN bitis set.Afterreset,the RQTCNTn registersareclear. 31 15M M 8 0 Reserved TimeoutCounter

12.9.9 DMA ControlRegistern (DMACNTn)

The DMA Controlregisterisa 32-bit,read/writeregisterthatcontrolstheoperationofDMA channeln.This registerisinitializedto000C 0000h atreset.Reservedbitsmust be writtenwith0.

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www.ti.com SNOSCW5 –MAY 2013 7 6 5 4 3 2 1 0 Reserved OT DIR TCS DTO EOVR ETC CHEN 15 14 13 12 11 10 9 8 WMODE INCB ADB INCA ADA SWRQ 7 6 5 4 3 2 1 0 Reserved OT DIR TCS DTO EOVR ETC CHEN 31 12M M 11 0 Reserved SRCRQ CHEN The ChannelEnablebitmust be settoenableany DMA operationon thischannel.Writinga 1 tothisbitstartsa new DMA transfereven ifitiscurrentlya 1.IfallDMACNTn.CHEN bits areclear,theDMA clockisdisabledtoreducepower. 0 – Channeldisabled. 1 – Channelenabled. ETC IftheEnableInterrupton TerminalCount bitisset,itenablesan interruptwhen the DMASTAT.TC bitisset. 0 – Interruptdisabled. 1 – Interruptenabled EOVR IftheEnableInterrupton OVR bitisset,itenablesan interruptwhen theDMASTAT.OVR bit isset. 0 – Interruptdisabled. 1 – Interruptenabled. ETO IftheEnableInterrupton Timeoutbitisset,itenablesan interruptwhen theDMASTAT.TO bitisset. 0 – Interruptdisabled. 1 – Interruptenabled. TCS The TransferCycleSizebitspecifiesthenumber ofbytestransferredineach DMA transfer cycle.Thisbitwillbe overriddeniftheWMODE bitisset. 0 – Bytetransfers(8bitspercycle). 1 – Word transfers(16bitspercycle). DIR The TransferDirectionbitspecifiesthedirectionofthetransferrelativetoDeviceA. 0 – DeviceA (addressedby theADCAn register)isthesource. 1 – DeviceA isthedestination OT The OperationType bitspecifiestheoperationmode oftheDMA controller. 0 – Single-buffermode ordouble-buffermode enabled. 1 – Auto-Initializemode enabled. SWRQ The SoftwareDMA Requestbitiswrittenwitha 1 toinitiatea softwareDMA request.Writing a 0 tothisbitdeactivatesthesoftwareDMA request.The SWRQ bitmust onlybe written when theperipheralDMA requestsforthechannelaredisabledand thechannelisinactive (DMASTAT.CHAC = 0). 0 – SoftwareDMA requestisinactive. 1 – SoftwareDMA requestisactive. ADA IftheDeviceA AddressControlbitisset,itenablesupdatingtheDeviceA address. 0 – ADCAn addressunchanged. 1 – ADCAn addressincrementedordecremented,as controlledby theINCA fieldand WMODE and TCS bits. INCA The Increment/DecrementADCAn fieldtogetherwiththeWMODE and TCS bitscontrolthe stepsizefortheDeviceA addressincrement/decrement. Copyright© 2013,Texas InstrumentsIncorporated CPU DMA Controller 65 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com INCA WMODE TCS Step Size 0 0 0 1 1 0 0 2 10 0 0 -1 11 0 0 -2 0 0 1 2 1 0 1 4 10 0 1 -2 11 0 1 -4 0X 1 X 4 1X 1 X -4 IftheDeviceB AddressControlbitisset,itenablesupdatingtheDeviceB Address. 0 – ADCBn addressunchanged. 1 – ADCBn addressincrementedordecremented,as controlledby theINCB fieldand WMODE and TCS bits. INCB The Increment/DecrementADCBn fieldspecifiesthestepsizefortheDeviceB address increment/decrement. INCB WMODE TCS Step Size 0 0 0 1 1 0 0 2 10 0 0 -1 11 0 0 -2 0 0 1 2 1 0 1 4 10 0 1 -2 11 0 1 -4 0X 1 X 4 1X 1 X -4 WMODE The 32-bitWord Mode bitcontrolswhetherthetransfercyclesizeis32 bits.Ifset,it overridestheTCS bit. 0 – Transfercyclesizeselectedby theTCS bit. 1 – Transfercyclesizeis32 bits. BBE The BurstBufferEnablebitcontrolswhetherSingletransfertypeordatacollection/burst transfertypeisused.Onlychannels0 and 1 have burstbuffers.Fortheotherchannels,the BBE bitisreserved. 0 – Singletransfertype. 1 – Data collectionorbursttransfertype. PF The PeripheralFlow bitcontrolswhethertheDMAC ortheperipheralistheflowcontroller. 0 – The DMAC istheflowcontroller.The DMA transferisterminatedwhen theBLTCn registercountsdown tozero. 1 – The peripheralistheflowcontroller. HPROT The HPROT fieldmust be 0011b (defaultvalue). TOEN The EnableTimeoutbitcontrolswhetherDMA requesttimeoutmonitoringisenabled. 0 – Timeoutdisabled. 1 – Timeoutenabled. SRCRQ The SourceRequestfieldspecifiesa peripheralregisterused as thesourceordestinationfor a DMA transfer.

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12.9.10 DMA StatusRegistern (DMASTATn)

The DMA statusregisterisa 32-bitregisterthatholdsthestatusinformationfortheDMA channel.This registerisclearedatreset.The reservedbitsalwaysreturnzerowhen read.The ERR, VLD, OVR, and TC bitsaresticky(oncesetby theoccurrenceofthespecificcondition,theyremainsetuntilexplicitlycleared by software).These bitscan be clearedby writing1 totheirbitpositionsintheDMASTAT registertobe cleared.Writing0 tothesebitshas no effect. 31 16 15 14 13 12 8 7 6 5 4 3 2 1 0 Reserved Reserved BLV Reserved BNE ERR VLD CHAC OVR TC TC The TerminalCount bitindicateswhetherthetransferwas completedby a terminalcount condition(BLTCn Registerreached0 and thePF bitwas clear). 0 – Terminalcountconditiondidnotoccur. 1 – Terminalcountconditionoccurred. OVR The behavioroftheChannelOverrunbitdepends on theoperationmode (singlebuffer, doublebuffer,orauto-initialize)oftheDMA channel. Indouble-bufferedmode (DMACNTn.OT = 0):The OVR bitissetwhen thepresenttransfer iscompleted(BLTCn = 0),buttheparametersforthenexttransfer(addressand block length)arenotvalid(DMASTATn.VLD = 0). Inauto-initializemode (DMACNTn.OT = 1):The OVR bitissetwhen thepresenttransferis completed(BLTCn = 0),and theDMASTATn.TC bitisstillset. Insingle-buffermode: Operatesinthesame way as double-buffermode. Insingle-buffered mode, theDMASTATn.VLD bitshouldalwaysbe clear,so itwillalsobe setwhen the DMASTATn.TC bitisset.Therefore,theOVR bitcan be ignoredinthismode. CHAC The ChannelActivebitcontinuouslyindicatestheactiveorinactivestatusofthechannel,and therefore,itisread-only.Data writtentotheCHAC bitisignored. 0 – Channelinactive. 1 – Indicatesthatthechannelisactive(CHEN bitintheCNTLn registeris1 and BLTCn > 0) VLD The TransferParametersValidbitindicateswhetherthetransferparametersforthenext blocktobe transferredarevalid.WritingtheBLTRn registerautomaticallysetsthisbit.The bitisclearedinthefollowingcases:

• The presenttransferiscompletedand theADRAn, ADRBn, and BLTRn registershave been loadedtotheADCAn, ADCBn, and BLTCn registers.
• Writing1 totheVLD bit. ERR The Errorbitindicateswhetheran errorresponsehas been detectedduringthelasttransfer. Thismay occurbecause theaddresswas invalidoran incrementalaccessgoes outof bounds. 0 – Errorconditiondidnotoccur. 1 – Errorconditionoccurred. BNE The BufferNot Empty bitindicateswhetherthereisvaliddataintheburstbuffer. 0 – Burstbufferisempty. 1 – Burstbufferholdsvaliddata. BLV The BurstBufferLevelfieldindicatesthenumber ofvalidbytesintheburstbuffer. TO The Timeoutbitindicatesthata timeouteventoccurred(RQTCNTn reacheditsterminal count).ThisbitisclearedeverytimetheDMA requestforthischannelisasserted. 0 – No timeoutoccurredsincethisbitwas lastcleared. 1 – A timeoutoccurred. Copyright© 2013,Texas InstrumentsIncorporated CPU DMA Controller 67 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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13 Interrupts

The InterruptControlUnit(ICU) receivesinterruptrequestsfrom internaland externalsources and generatesinterruptstotheCPU. The highest-priorityinterruptistheNonMaskable Interrupt(NMI),whichis triggeredby a fallingedge receivedon theNMI inputpin. The maskable interrupts(IRQn)have a fixed,linearpriorityfromIRQ0 throughIRQ70, inwhichIRQ0 has the lowestpriorityand IRQ70 has the highestpriority.IRQ0 isnot implemented,so IRQ1 isthe lowest prioritymaskableinterruptthatmay occurinnormaloperation.

13.1 Non-Maskable Interrupts

The InterruptControlUnit(ICU)receivestheexternalNMI inputand generatestheNMI signaldrivento the CPU. The NMI inputisan asynchronousinputwithSchmitttriggercharacteristicsand an internal synchronizationcircuit,thereforeno externalsynchronizingcircuitisneeded. The NMI pin triggersan exceptionon itsfallingedge.

13.1.1 Non-Maskable InterruptProcessing

At reset,NMI interruptsaredisabledand must remaindisableduntilsoftwareinitializestheinterrupttable, interruptbase register(INTBASE), and the interruptmode. The externalNMI interruptisenabled by settingtheEXNMI.ENLCK bitand willremainenableduntila resetoccurs.Alternatively,theexternalNMI interruptcan be enabledby settingtheEXNMI.EN bitand willremainenableduntilan NMI interruptora resetoccurs.

13.2 Maskable Interrupts

The IRQn interruptchannelsarelevel-sensitive.Any edge sensitivitymust be implementedattheinterrupt source.The IRQ interruptsare enabledand disabledby the E and I bitsinthe PSR register.Both bits must be settoenablemaskable interrupts.The EI and DI instructionsareused toset(enable)and clear (disable)theE bit. Each interruptsourcecan be individuallyenabledor disabledunder softwarecontrolthroughthe IENR registerand alsothroughinterruptenablebitsintheperipheralsthatrequesttheinterrupts.

13.2.1 Maskable InterruptProcessing

The IVECT registerholds the interruptvectornumber of the enabled and pending interruptwiththe highestpriority,mapped totherange10h to56h.IRQ0 ismapped to10h,whileIRQ70 ismapped to56h. The CPU performsan interruptacknowledgebus cycleon receivinga maskable interruptrequestfromthe ICU.Duringtheinterruptacknowledgecycle,a byteisreadfromaddressFF FE00h (theIVECT register). The byteisused as an indexintotheDispatchTabletodeterminetheaddressoftheinterrupthandler. Because IRQ0 isnot connectedto any interruptsource,the interruptvectornumber 10h shouldnot be generated.However, an entryshouldbe providedforthisvectorinthe dispatchtablethatpointsto a defaultinterrupthandler.One possibleconditioninwhichthisvectornumber may occurisdeassertionof an interruptatitssourcebeforetheinterruptcontrollergeneratesan interruptacknowledgecycle.

13.2.2 Maskable InterruptSources

Table13-1shows theinterruptsourcesassignedtothemaskableinterrupts. Table13-1.Maskable InterruptsAssignment IRQn DESCRIPTION ASC CHANNEL IRQ70 RTI (Timer0) IRQ69 Real-TimeClock IRQ68 BluetoothLLC 0

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www.ti.com SNOSCW5 –MAY 2013 Table13-1.Maskable InterruptsAssignment (continued) IRQn DESCRIPTION ASC CHANNEL IRQ67 BluetoothLLC 1 IRQ66 BluetoothLLC 2 IRQ65 BluetoothLLC 3 IRQ64 BluetoothLLC 4 IRQ63 BluetoothLLC 5 IRQ62 Reserved IRQ61 USB Interrupt IRQ60 Teak DSP IRQ59 DMA Channel0 IRQ58 DMA Channel1 IRQ57 DMA Channel2 IRQ56 DMA Channel3 IRQ55 DMA Channel4 IRQ54 DMA Channel5 IRQ53 DMA Channel6 IRQ52 DMA Channel7 IRQ51 DMA Channel8 IRQ50 DMA Channel9 IRQ49 DMA Channel10 IRQ48 DMA Channel11 IRQ47 DMA Channel12 IRQ46 DMA Channel13 IRQ45 DMA Channel14 IRQ44 DMA Channel15 IRQ43 Reserved IRQ42 Reserved IRQ41 CAN0 IRQ40 USART0 Rx IRQ39 USART0 Tx IRQ38 USART0 CTS IRQ37 TA0 (MFT0 PortA) IRQ36 TB0 (MFT0 PortB) IRQ35 TA1 (MFT1 PortA) 10 IRQ34 TB1 (MFT1 PortB) 9 IRQ33 VTU0A (VTU InterruptRequest1) IRQ32 VTU0B (VTU InterruptRequest2) IRQ31 VTU0C (VTU InterruptRequest3) IRQ30 VTU0D (VTU InterruptRequest4) IRQ29 Microwire/SPI0 Rx/Tx IRQ28 Codec 8 IRQ27 Advanced AudioInterface 7 IRQ26 I2S Interface 6 IRQ25 CVSD/PCM Converter0 5 IRQ24 CVSD/PCM Converter1 4 IRQ23 ACCESS.bus 0 IRQ22 VTU1A (VTU InterruptRequest1) IRQ21 VTU1B (VTU InterruptRequest2) Copyright© 2013,Texas InstrumentsIncorporated Interrupts 69 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table13-1.Maskable InterruptsAssignment (continued) IRQn DESCRIPTION ASC CHANNEL IRQ20 VTU1C (VTU InterruptRequest3) IRQ19 VTU1D (VTU InterruptRequest4) IRQ18 CAN1 IRQ17 UART1 Rx IRQ16 UART1 Tx IRQ15 UART2 Rx IRQ14 UART2 Tx IRQ13 UART3 Rx 3 IRQ12 UART3 Tx 2 IRQ11 ACCESS.bus 1 1 IRQ10 Microwire/SPI1 Rx/Tx 0 IRQ9 ADC (Done) IRQ8 MIWU Interrupt0 IRQ7 MIWU Interrupt1 IRQ6 MIWU Interrupt2 IRQ5 MIWU Interrupt3 IRQ4 MIWU Interrupt4 IRQ3 MIWU Interrupt5 IRQ2 MIWU Interrupt6 IRQ1 MIWU Interrupt7 IRQ0 Reserved Allreservedinterruptvectorsmust pointtodefaultorerrorinterrupthandlers.

13.3 InterruptPriorityGroups

When more thanone interruptisasserted,two levelsofpriorityare used todeterminewhich interruptis taken:

• Group Priority— each interruptbelongstoone offourprioritygroupsnumbered from 0 to3,inwhich lowergroupnumbers have higherpriority.
• Channel Priority— each channelhas a uniquechannelnumber,inwhichhigherchannelnumbers have higherpriority. Group priorityalways takesprecedence over channelpriority.Channel priorityisonlyused to resolve priorityamong interruptsinthesame group. Any interruptmay belongto any group,as programmed inthe INTGPAR and INTGPBR registers.The correspondingbitsin each registerassignthe interruptchannel to one of the groups,as shown in Table13-2. Table13-2.InterruptPriorityGroup Assignment PriorityGroup forIRQn INTGPBRn INTGPARn Group 0 (highestpriority) 0 0 Group 1 0 1 Group 2 1 0 Group3 (lowestpriority) 1 1

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Increasing Channel Priority Increasing Group Priority CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Forexample,ifINTGPAR6:1 isloadedwith011101b and INTGPBR6:1 isloadedwith010001b,thepriority groupsfortheseinterruptsareassignedas shown inFigure13-1. Figure13-1.InterruuptPriorityGroups IfthesixIRQ1 throughIRQ6 interruptsareasserted,thenIRQ6 istakenbecause thisinterruptbelongsto thehighestprioritygroup(lowestgroupnumber),and ithas thehighestchannelnumber withinthatgroup. IfonlyIRQ1 and IRQ5 are asserted,thenIRQ5 istakenbecause thisisthehighestpriorityinterruptin group3 and thereareno assertedinterruptsinothergroups.

13.4 Nested Interrupts

Nested NMI interruptsare permanentlyenabledwhen the ENLCK bitinthe EXNMI registerisused to enableNMI interrupts.When nestingisnotdesired,theEN bitmay be settoenableone occurrenceofthe NMI interrupt,afterwhichNMI interruptsaredisableduntiltheEN bitissetagain. Nested maskable interruptsaredisabledby default,because theIbitinthePSR isautomaticallycleared when theinterruptisacknowledged.An interrupthandlercan allownestedmaskable interruptsby setting theIbitusingtheLPR instruction. Nestingof specificmaskable interruptscan be selectivelyenabledor disabledusingthe IENR register, beforesettingtheIbit.Any number oflevelsofnestedinterruptsareallowed,limitedonlyby theavailable memory fortheinterruptstack.

13.5 SoftwareInterrupts

Settinga bitinthe SOFTR registerrequeststhe correspondingmaskable interrupt.The requeststays activeuntilthebitisclearedby softwareora devicereset.Softwareinterruptrequestsaremaskableinthe IENR registers,and activeinterrupts(fromeitherhardwareorsoftwaresources)areindicatedintheISTR register.

13.6 InterruptControllerRegisters

Table13-3liststheinterruptcontrollerregisters. Copyright© 2013,Texas InstrumentsIncorporated Interrupts 71 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table13-3.InterruptControllerRegisters NAME ADDRESS DESCRIPTION IVECT FF FE00h InterruptVectorRegister NMISTAT FF FE04h Non-MaskableInterruptStatusRegister EXNMI FF FE08h ExternalNMI TrapControland StatusRegister ISTR0 FF FE10h InterruptStatusRegister0 ISTR1 FF FE14h InterruptStatusRegister1 ISTR2 FF FE18h InterruptStatusRegister2 IENR0 FF FE20h InterruptEnableand Mask Register0 IENR1 FF FE24h InterruptEnableand Mask Register1 IENR2 FF FE28h InterruptEnableand Mask Register2 SOFTR0 FF FE40h SoftwareInterruptRegister0 SOFTR1 FF FE44h SoftwareInterruptRegister1 SOFTR2 FF FE48h SoftwareInterruptRegister2 INTGPAR0 FF FE50h InterruptPriorityGroup A Register0 INTGPAR1 FF FE58h InterruptPriorityGroup A Register1 INTGPAR2 FF FE60h InterruptPriorityGroup A Register2 INTGPBR0 FF FE54h InterruptPriorityGroup B Register0 INTGPBR1 FF FE5Ch InterruptPriorityGroup B Register1 INTGPBR2 FF FE64h InterruptPriorityGroup B Register2 IDBG FF FEFCh InterruptDebug Register

13.6.1 InterruptVectorRegister(IVCT)

The IVCT registerisa 32-bit,read-onlyregisterwhich reportsthe encoded valueof the highestpriority maskable interruptthatisbothassertedand enabled.The registerisreadby theCPU duringan interrupt acknowledgebus cycle,and INTVECT isvalidduringthattime.Itmay containinvaliddatawhileINTVECT isupdated.The registerisinitializedto0000 0010h atreset. 31 8M 7 0 Reserved INTVECT INTVECT The InterruptVectorfieldindicatesthehighestpriorityinterruptwhichisbothassertedand enabled.The validrangeisfrom10h to56h.

13.6.2 Non-Maskable InterruptStatusRegister(NMISTAT)

The NMISTAT registerisa 32-bit,read-onlyregister.Itholdsthe statusof the currentpending Non- Maskable Interrupt(NMI)requests.On the CP3SP33, the externalNMI inputisthe onlysourceof NMI interrupts.The NMISTAT registerisclearedon resetand each timeitscontentsareread. 31 1M 0 Reserved EXT EXT The ExternalNMI requestbitindicateswhetheran externalnon-maskableinterruptrequesthas occurred.RefertothedescriptionoftheEXNMI registerbelowforadditionaldetails. 0 – No externalNMI request. 1 – ExternalNMI requesthas occurred.

13.6.3 ExternalNMI Trap Controland StatusRegister(EXNMI)

The EXNMI registerisa 32-bit,read/writeregister.Itindicatesthe currentvalueof the NMI pin and controlstheNMI interrupttrapgenerationbased on a fallingedge oftheNMI pin.ENCLK, PIN,and EN areclearedon reset.When writingtothisregister,allreservedbitsmust be writtenwith0 forthedeviceto functionproperly

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www.ti.com SNOSCW5 –MAY 2013 31 3 2 1 0 Reserved ENLCK PIN EN EN The EXNMI trapenablebitisone oftwo bitsthatcan be used toenableNMI interrupts.The bit isclearedby hardwareatresetand whenever theNMI interruptoccurs(EXNMI.EXT set).Itis intendedforapplicationswhere theNMI inputtogglesfrequentlybutnestedNMI trapsarenot desired.Fortheseapplications,theEN bitneeds tobe re-enabledbeforeexitingthetrap handler.When used thisway,theENLCK bitshouldneverbe set.The EN bitcan be setand clearedby software(softwarecan setthisbitonlyifEXNMI.EXT iscleared),and shouldonlybe setaftertheinterruptbase registerand theinterruptstackpointerhave been setup. 0 – NMI interruptsnotenabledby thisbit(butmay be enabledby theENLCK bit). 1 – NMI interruptsenabled. PIN The PIN bitindicatesthestate(non-inverted)on theNMI inputpin.Thisbitisread-only,data writtenintoitisignored. 0 – NMI pinnotasserted. 1 – NMI pinasserted. ENLCK The EXNMI trapenablelockbitisused topermanentlyenableNMI interrupts.Onlya device resetcan cleartheENLCK bit.ThisallowstheexternalNMI featuretobe enabledafterthe interruptbase registerand theinterruptstackpointerhave been setup.When theENLCK bitis set,theEN bitisignored. 0 – NMI interruptsnotenabledby thisbit(butmay be enabledby theEN bit). 1 – NMI interruptsenabled.

13.6.4 InterruptEnable and Mask Register0 (IENR0)

The IENR0 registerisa 32-bit,read/writeregisterwhichholdsbitsthatindividuallyenableand disablethe maskableinterruptsourcesIRQ1 toIRQ31.The registerisinitializedto0000 0000h atreset. 31 1M 0 IEN0 Reserved IEN0 Each InterruptEnablebitenablesordisablesthecorrespondinginterruptchannelsIRQ1 through IRQ31.Because IRQ0 isnotused,bit0 isignored. 0 – Interruptisdisabled. 1 – Interruptisenabled.

13.6.5 InterruptEnable and Mask Register1 (IENR1)

The IENR1 registerisa 32-bit,read/writeregisterwhichholdsbitsthatindividuallyenableand disablethe maskableinterruptsourcesIRQ63 toIRQ32.The registerisinitializedto0000 0000h atreset. 31 0 IEN1 IEN1 Each InterruptEnablebitenablesordisablesthecorrespondinginterruptchannelsIRQ32 throughIRQ63. 0 – Interruptisdisabled. 1 – Interruptisenabled.

13.6.6 InterruptEnable and Mask Register2 (IENR2)

The IENR2 registerisa 32-bit,read/writeregisterwhichholdsbitsthatindividuallyenableand disablethe maskable interruptsources IRQ70 to IRQ64. Only bits6:0 of thisregisterare used. The registeris initializedto0000 0000h atreset. Copyright© 2013,Texas InstrumentsIncorporated Interrupts 73 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 31 0 IEN2 IEN2 Each InterruptEnablebitenablesordisablesthecorrespondinginterruptchannelsIRQ64 throughIRQ70. 0 – Interruptisdisabled. 1 – Interruptisenabled.

13.6.7 InterruptStatusRegister0 (ISTR0)

The ISTR0 registerisa 32-bit,read-onlyregister.Itindicateswhich maskable interruptinputsIRQ31 to IRQ1 are active.These bitsare notaffectedby thestateofthecorrespondingIENR0 bits.Because the IRQ0 interruptisnotused,bit0 alwaysreadsas 0. 31 1M 0 IST0 Reserved IST0 The InterruptStatusbitsindicateifa maskableinterruptsourceissignAlingan interruptrequest. 0 – Interruptisnotactive. 1 – Interruptisactive.

13.6.8 InterruptStatusRegister1 (ISTR1)

The ISTR1 registerisa 32-bit,read-onlyregister.Itindicateswhich maskable interruptinputsIRQ63 to IRQ31 areactive.These bitsarenotaffectedby thestateofthecorrespondingIENR1 bits. 31 0 IST1 IST1 The InterruptStatusbitsindicateifa maskableinterruptsourceissignalingan interruptrequest. 0 – Interruptisnotactive. 1 – Interruptisactive.

13.6.9 InterruptStatusRegister2 (ISTR2)

The ISTR2 registerisa 32-bit,read-onlyregister.Itindicateswhich maskable interruptinputsIRQ70 to IRQ64 areactive.These bitsarenotaffectedby thestateofthecorrespondingIENR2 bits.Only bits6:0 ofthisregisterareused. 31 0 IST2 IST2 The InterruptStatusbitsindicateifa maskableinterruptsourceissignalingan interrupt request. 0 – Interruptisnotactive. 1 – Interruptisactive.

13.6.10 SoftwareInterruptRegister0 (SOFTR0)

The SOFTR0 registeris a 32-bit,read/writeregister.Settinga bitin thisregisteractivatesthe correspondingmaskable interruptIRQ31 to IRQ1. Bit0 of thisregisteris reserved.The registeris initializedto0000 0000h atreset. 31 1M 0 SOFT0 Reserved

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www.ti.com SNOSCW5 –MAY 2013 SOFT0 The SoftwareInterruptbitsactivatethecorrespondingmaskableinterruptwhen writtenwith1. 0 – Interruptisnotactive. 1 – Interruptisactive.

13.6.11 SoftwareInterruptRegister1 (SOFTR1)

The SOFTR1 registeris a 32-bit,read/writeregister.Settinga bitin thisregisteractivatesthe correspondingmaskableinterruptIRQ63 toIRQ31.The registerisinitializedto0000 0000h atreset. 31 0 SOFT1 SOFT1 The SoftwareInterruptbitsactivatethecorrespondingmaskableinterruptwhen writtenwith1. 0 – Interruptisnotactive. 1 – Interruptisactive.

13.6.12 SoftwareInterruptRegister2 (SOFTR2)

The SOFTR2 registeris a 32-bit,read/writeregister.Settinga bitin thisregisteractivatesthe correspondingmaskable interruptIRQ70 toIRQ64. Only bits6:0ofthisregisterareused.The registeris initializedto0000 0000h atreset. 31 0 SOFT2 SOFT2 The SoftwareInterruptbitsactivatethecorrespondingmaskableinterruptwhen writtenwith1. 0 – Interruptisnotactive. 1 – Interruptisactive.

13.6.13 InterruptPriorityGroup A Register0 (INTGPAR0)

The INTGPAR0 registerisa 32-bit,read/writeregister.Bitsinthisregisterspecifytheleastsignificantbit forselectingthe prioritygroup of the correspondinginterruptIRQ31 to IRQ1. Bit0 of thisregisteris reserved.The registerisinitializedto0000 0000h atreset. 31 1M 0 INTGPA0 Reserved INTGPA0 The InterruptPriorityGroup A bitsspecifytheleastsignificantbitforselectingone offour interruptprioritygroups. 0 – Interruptbelongstogroup0 or2. 1 – Interruptbelongstogroup1 or3.

13.6.14 InterruptPriorityGroup A Register1 (INTGPAR1)

The INTGPAR1 registerisa 32-bit,read/writeregister.Bitsinthisregisterspecifytheleastsignificantbit forselectingtheprioritygroupofthecorrespondinginterruptIRQ63 toIRQ31. The registerisinitializedto 0000 0000h atreset. 31 0 INTGPA1 Copyright© 2013,Texas InstrumentsIncorporated Interrupts 75 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com INTGPA1 The InterruptPriorityGroup A bitsspecifytheleastsignificantbitforselectingone offour interruptprioritygroups. 0 – Interruptbelongstogroup0 or2. 1 – Interruptbelongstogroup1 or3.

13.6.15 InterruptPriorityGroup A Register2 (INTGPAR2)

The INTGPAR2 registerisa 32-bit,read/writeregister.Bitsinthisregisterspecifytheleastsignificantbit forselectingtheprioritygroupofthecorrespondinginterruptIRQ70 toIRQ64. Only bits6:0ofthisregister areused.The registerisinitializedto0000 0000h atreset. 31 0 INTGPA2 INTGPA2 The InterruptPriorityGroup A bitsspecifytheleastsignificantbitforselectingone offour interruptprioritygroups. 0 – Interruptbelongstogroup0 or2. 1 – Interruptbelongstogroup1 or3.

13.6.16 InterruptPriorityGroup B Register0 (INTGPBR0)

The INTGPBR0 registerisa 32-bit,read/writeregister.Bitsinthisregisterspecifythemost significantbit forselectingthe prioritygroup of the correspondinginterruptIRQ31 to IRQ1. Bit0 of thisregisteris reserved.The registerisinitializedto0000 0000h atreset. 31 1M 0 INTGPB0 Reserved INTGPB0 The InterruptPriorityGroup B bitsspecifythemost significantbitforselectingone offour interruptprioritygroups. 0 – Interruptbelongstogroup0 or1. 1 – Interruptbelongstogroup2 or3.

13.6.17 InterruptPriorityGroup B Register1 (INTGPBR1)

The INTGPBR1 registerisa 32-bit,read/writeregister.Bitsinthisregisterspecifythemost significantbit forselectingtheprioritygroupofthecorrespondinginterruptIRQ63 toIRQ31. The registerisinitializedto 0000 0000h atreset. 15 1 INTGPB1 INTGPB1 The InterruptPriorityGroup B bitsspecifythemost significantbitforselectingone offour interruptprioritygroups. 0 – Interruptbelongstogroup0 or1. 1 – Interruptbelongstogroup2 or3.

13.6.18 InterruptPriorityGroup B Register2 (INTGPBR2)

The INTGPBR2 registerisa 32-bit,read/writeregister.Bitsinthisregisterspecifythemost significantbit forselectingtheprioritygroupofthecorrespondinginterruptIRQ70 toIRQ64. Only bits6:0ofthisregister areused.The registerisinitializedto0000 0000h atreset. 31 0 INTGPB2

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www.ti.com SNOSCW5 –MAY 2013 INTGPB2 The InterruptPriorityGroup B bitsspecifythemost significantbitforselectingone offour interruptprioritygroups. 0 – Interruptbelongstogroup0 or1. 1 – Interruptbelongstogroup2 or3.

13.6.19 InterruptDebug Register(IDBG)

The IDBG registerisa 32-bit,read-onlyregister.Fieldsinthisregisterindicatetheinterruptnumber ofthe highestprioritycurrentlyassertedinterruptand theinterruptnumber returnedtotheCPU duringthelast interruptacknowledgecycle.(These may differifa higher-priorityinterruptisassertedaftertheinterrupt acknowledgecycle.)The registerisinitializedto0000 0000h atreset. 31 16 15 8 7 0 Reserved IRQVECT INTVECT INTVECT The INTVECT fieldindicatestheinterruptvectornumber ofthehighestprioritycurrently assertedinterrupt. IRQVECT The IRQVECT fieldindicatestheinterruptvectornumber returnedtotheCPU duringthelast interruptacknowledgecycle.

13.7 Usage Notes

The recommended initializationsequence is: 1. InitializetheINTBASE registeroftheCPU. 2. Preparetheinterruptroutinesoftherelevantinterrupts. 3. Setup theinterruptconditionsintheperipherals. 4. Settherelevantbitsintheinterruptenable/maskregisters(IENRn). 5. SettheIbitinthePSR. Clearingan interruptrequestbeforeitisservicedcan cause a spuriousinterrupt,(i.e.,theCPU detectsan interruptnotreflectedby IVECT).Softwaremust clearinterruptrequestsonlyafterinterruptsaredisabled. Clearingany oftheinterruptenablebitsshouldbe performedwhiletheIbitinthePSR registerisclear.

14 Clock Generation

The clockcircuitryincludesoscillatorsforgeneratinga 12MHz Main Clock and an optional32.768-kHz Slow Clockfromexternalcrystalnetworks.Alternatively,eitherclockmay be replacedby an externalclock source. Two identicalPLLs areavailabletoprovidehigherclockfrequencies(upto96 MHz) usingMain Clockas a referencefrequency.The PLLs alsomay be used tosynchronizewithan externalclockdrivenon the I2Sinterface(I2SCLK). Most of the functionalblocksof the deviceoperatefrom one of the globalclocksgeneratedby this module:

• Main Clock— 12-MHz clockgeneratedby an on-chiposcillatororreceivedfroman externalclock source.
• PLL1 Clock— clocksynthesizedby PLL1 fromMain ClockortheexternalI2SCLK clockinput.
• PLL2 Clock— clocksynthesizedby PLL2 fromMain ClockortheexternalI2SCLK clockinput.
• HCLK Clock— clockused by theCPU and deviceson theCPU coreAHB bus.HCLK Clockis generatedby a prescalerfromMain Clock,PLL1 Clock,orPLL2 Clock.Availableprescalefactorsare 1 to2048 inincrementsof1/2clockperiod.InPower Save mode, HCLK Clockisdrivenby Slow Clock.
• PCLK Clock— clockused by deviceson theperipheralAPB bus.PCLK Clockisgeneratedby a prescalerfromHCLK Clock.Availableprescalefactorsare1,2,and 4. Copyright© 2013,Texas InstrumentsIncorporated ClockGeneration 77 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

P MMP LL2CTL1.P LLIP S E L P LL1 P MMP LL1CTL1.P LLIP S E L Peripheral Bus Clock 2-Bit Prescaler Slow Clock 14-Bit Prescaler P MMCK CTL.FCLK S RC P MMP RS HC.HP HCLK P MMP RS P C.DIV P CLK P MMP RS S C.HP S CLK P MMCK CTL.S CLK PLL1 Clock PLL2 Clock HCLK Clock PCLK Clock Slow Clock Power S ave Mode CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

• Slow Clock— 32.768kHz clockused inlow-powermodes. Slow Clockisgeneratedby an on-chip oscillator,receivedfroman externalclocksourceorgeneratedby a prescalerfromMain Clock. Availableprescalefactorsare1 to8192 inincrementsof1/2clockperiod. Figure14-1isblockdiagramoftheglobalclockgenerationlogic. Figure14-1.GlobalClock Generation

14.1 ExtrnalCrystalNetworks

An externalcrystalnetworkisconnectedto the X1CKI and X1CKO pinsto generatethe Main Clock, unlessan externalclocksignalisdrivenon theCLKIN pin.A similarexternalcrystalnetworkmay be used at pinsX2CKI and X2CKO forthe Slow Clock.Ifan externalcrystalnetworkisnot used forthe Slow Clock,theSlow Clockisgeneratedthrougha prescalerfromMain Clock. The crystalnetworkyou choose may requireexternalcomponents differentfromtheones specifiedinthis datasheet.Inthiscase,consultwithNational’s engineersforthecomponent specifications The crystalsand other oscillatorcomponents must be placed close to the X1CKI/X1CKO and X2CKI/X2CKO deviceinputpinstokeep thetracelengthstoan absoluteminimum.

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www.ti.com SNOSCW5 –MAY 2013 Figure14-2 shows theexternalcrystalnetworkfortheX1CKI and X1CKO pins.The crystalmust be an AT-cuttype.Figure14-3shows theexternalcrystalnetworkfortheX2CKI and X2CKO pins.The crystal may be an N-cutor XY-bar type.Table14-1 shows thecomponent specificationsforthe12-MHz crystal network,and Table14-2shows thecomponent specificationsforthe32.768kHz crystalnetwork. Figure14-2.12 MHz OscillatorCrystalNetwork Table14-1.12 MHz OscillatorComponent Values SYMBOL COMPONENT PARAMETER MIN TYP MAX f Crystal ResonantFrequency 12 MHz Rm Crystal MotionalResistance(ESR) 50 Ω C0 Crystal Case Capacitance 7 pF C1, C2 Capacitors ExternalCapacitance 22 pF CL Capacitors Load Capacitance 11 pF Copyright© 2013,Texas InstrumentsIncorporated ClockGeneration 79 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

32.768 kHz Crystal GND X2CKI X2CKO DS327 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure14-3.32.768kHz OscillatorCrystalNetwork Table14-2.32.768kHz OscillatorComponent Values SYMBOL COMPONENT PARAMETER MIN TYP MAX f Crystal ResonantFrequency 32.768kHz Cm Crystal MotionalResistance 1.7pF Rm Crystal MotionalResistance(ESR) 65 kΩ C0 Crystal ShuntCapacitance 1.3pF Q Crystal Q Factor 40000 CL Capacitors Load Capacitance 25 pF

14.2 Main Clock

Main Clockisgeneratedby the12-MHz high-frequencyoscillatorordrivenby an externalsignal(typically theLMX5251 orLMX5252 Bluetoothradiochip).Itcan be stoppedby thePower Management Module to reducepower consumptionduringperiodsofreducedactivity.When theMain Clockisstartedorrestarted, a 14-bittimergeneratesa start-updelaytodeterminewhen thehigh-frequencyoscillatorisstable. An externalclockcan be drivenon the X1CKI input,but itmust not exceed 1.8V.Alternatively,a 3.3V externalclockcan be drivenon the CLKIN pin,inwhich case the X1CKI inputmust be tiedlow.The frequencymust be a multipleof12 MHz, up to96 MHz. (Ifa frequencyotherthan12 MHz ischosen,the timingof the externalbus must be compatiblewiththe externalmemory deviceused to boot up the system.)IfthePower Management Module indicatesthehigh-frequencyoscillatorshouldbe stopped,the on-chipMain Clocksignalisstoppedeven ifitwas drivenby an externalclocksignalon CLKIN orX1CKI thatcontinuestoggling.

14.3 Slow Clock

Slow Clockisnecessaryforoperatingthedeviceinreducedpower modes and toprovidea clocksource formodules such as theTimingand Watchdog Module. The low-frequencyoscillatormay be used togenerateSlow Clockina manner similartotheMain Clock.It can be stopped by the Power Management Module to reduce power consumptionduringperiodsof reducedactivity.When theSlow Clockisstartedor restarted,a 6-bittimergeneratesa start-updelayto determinewhen thelow-frequencyoscillatorisstable.

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www.ti.com SNOSCW5 –MAY 2013 For systemsthatdo notrequirea reducedpower consumptionmode, theexternalcrystalnetworkmay be omittedforthelow-frequencyoscillator.Inthiscase,Slow Clockissynthesizedby dividingtheMain Clock by a prescalerfactor.The prescalerconsistsofa 14-bitprescaler.Thisallowsa choiceofclockdivisors rangingfrom1 to8192 inincrementsof1/2Main Clockperiod.The resultingSlow Clockfrequencymust notexceed 100 kHz. A software-controlledmultiplexerselectseithertheprescaledMain Clockor the32.768kHz oscillatoras the Slow Clock.At reset,the prescaledMain Clock isselected,ensuringthatthe Slow Clock isalways presentinitially.Selectionof the 32.768 kHz oscillatoras the Slow Clock source disablesthe clock prescaler,and itmay allowthehigh-frequencyoscillatortobe turnedoffinsome low-powermodes, for minimum power consumptionand radiatedemissions.The high-frequencyoscillatorcannotbe disabled when theprescalerisselectedas thesourceforSlow Clock. An externalclockmay be drivenon theX2CKI input.Itmust notexceed 1.8V.

14.4 PLL Clocks

The CP3SP33 has two identicalPLLs forgeneratingclocks.These are two purposesforprovidingPLL clockgenerators:

• HigherFrequency— the PLLs can generateclockfrequenciesup to 96 MHz usingthe 12 MHz Main Clock as a reference.Frequenciesabove 12 MHz are needed to run the CPU and DSP at their maximum speed.Also,theUSB peripheralrequiresa 60 MHz clock.
• SynchronizationwithExternalDevices— some devices(suchas externalcodecs)requireoperationata precisefrequencywhich is not an integermultipleof a standardCP3SP33 clockfrequency.By synchronizinga PLL withthe externaldevice,itcan be interfaceddirectlywithouttreatingitsI/Oas asynchronoussignals. Afterreset,the PLLs are powered down. Softwarecan program and enable the PLLs to startthem running.Each PLL has a programmablestart-upcountertoindicatewhen thePLL has become stable.By default,thestart-upcounterwillindicatethePLL has become stableafter32K cyclesofthePLL Clock. To enablethePLL afterresetorafterPLL power down, performthefollowingsequence: 1. SetthedividerratiosinthePMMPLLnMDIV, PMMPLLnNDIV, PMMPLLnNMOD, and PMMPLLnPDIV registerstoacceptablevaluesforthedesiredoutputfrequency.Ifthenumber ofPLL cyclestoallowfor stabilizationshouldbe differentfromthedefaultvalue(32K cycles),setthePLL StartupCounter register(PMMPLLnSTUP). 2. Power up thePLL by settingthePMMPLLnCTL1.PLLEN fieldto01b. 3. WaituntilthePMMPLLnCTL2.PLLCLKSTB bithas become set,whichindicatesthePLL isstable. 4. The PMMCKCTL.FCLKSRC fieldcan thenbe loadedwith00b toselectPLL1 Clockas thesourcefor theHCLK Clock.Itcan be loadedwith01b toselectPLL2 Clockas thesource.The switchonlyoccurs iftheselectedPLL isstable.To switchfromPLL1 ClocktoPLL2 Clock,Main Clockmust be selected as theclocksourceduringan intermediatestep(directswitchingbetween thetwo PLL Clocksisnot allowed). Ifany ofthedivisors(PMMPLLnMDIV, PMMPLLnNDIV, PMMPLLnNMOD, and PMMPLLnPDIV) areto be changed,theHCLK Clocksourcemust be switchedtoMain Clock(ifthePLL was drivingHCLK Clock),and thePLL must be powered down (forexample,by clearingthePMMPLLnCTL1.PLLEN field).Then,theprocedureabove may be performedtorestartthePLL afterloadingnew valuesinthe registers.

14.4.1 PLL Programming

The PLLs have the structureshown in Figure 14-4. The PMMPLLnMDIV, PMMPLLnNDIV, PMMPLLnNMOD, and PMMPLLnPDIV registersspecifythe M, N, and P divisorswhich controlthe operationof the PLL. The N divisorhas an integerpartspecifiedinthe PMMPLLnNDIV registerand a fractionalpartspecifiedinthePMMPLLnNMOD register. Copyright© 2013,Texas InstrumentsIncorporated ClockGeneration 81 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

M Divisor P DivisorN Divisor N Mod CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure14-4.PLL Module

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§ · ¨ ¸ u ¨ ¸ u¨ ¸ ¨ ¸ © ¹ VCO IN NMODF F 32 MDIV (2 )/( ) 2( )cos2 S ' ' S S ³ t n D s t nwc H w dw w CP3SP33 www.ti.com SNOSCW5 –MAY 2013 The referencefrequencyFREF isderivedfrom the inputfrequencyFIN, as describedby the following equation: (1) The voltage-controlledoscillatoroutputfrequencyFVCO is derivedfrom the inputfrequencyFIN, as describedby thefollowingequation: (2) FREF must be between 2 and 4 MHz. FVCO must notexceed 153 MHz. The outputfrequencyFO UT is derivedfrom the inputfrequencyFIN, as describedby the following equation: (3) Itispossibleforsoftwareto load divisorsthatresultin unstableor marginallystablePLL operation. Therefore,only divisorsrecommended in Table 14-3 and Table 14-4 should be used. Ifany other frequenciesaredesired,contactTexas Instruments. Table14-3.Recommended HCLK Clock Divisors FIN FOUTM Div. N Div. N Mod. P Div.(MHz) (MHz) 12 4 32 0 4 24 12 6 64 0 4 32 12 4 48 0 4 36 12 4 32 0 2 48 12 3 30 0 2 60 12 6 64 0 2 64 12 4 48 0 2 72 12 4 30 0 1 90 12 3 24 0 1 96 The PLLs are designedtodrivethetelematicscodec and otherdeviceswithaudiosample rates(Fs) of 44.1 kHz and 48 kHz (as wellas 32 kHz, 24 kHz, 22.05 kHz, etc.)and 125× or 250× oversampling. Therefore,the two common clockrequirementsare 11.025 MHz (44.1kHz × 250) and 12.000 MHz (48 kHz × 250).These frequenciescan be obtainedfrom any common inputclockratebetween 10 MHz and 20 MHz as shown inTable14-4. Table14-4.Recommended Audio Clock Divisors FS FINSOURCE M Div. N Div. N Mod. P Div.(kHz) (MHz) System 44.1 11 5 55 4 11 System 44.1 11.2896 4 46 2 12 System 44.1 12 5 55 3 12 System 44.1 13 5 55 4 13 System 44.1 14.4 4 30 20 10 Copyright© 2013,Texas InstrumentsIncorporated ClockGeneration 83 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table14-4.Recommended Audio Clock Divisors(continued) FS FINSOURCE M Div. N Div. N Mod. P Div.(kHz) (MHz) System 44.1 16.2 5 30 20 9 System 44.1 16.8 4 26 8 10 System 44.1 19.2 4 26 8 10 System 44.1 19.44 6 30 20 9 System 44.1 19.8 6 36 24 11 System 48 11 4 48 0 11 System 48 12 4 40 0 10 System 48 12.288 6 46 28 8 System 48 13 13 96 0 8 System 48 14.4 6 40 0 8 System 48 16.2 6 40 0 9 System 48 16.8 7 40 0 8 System 48 19.2 6 30 0 8 System 48 19.44 9 50 0 9 System 48 19.8 6 40 0 11 I2S 48 1.536 1 78 4 10 I2S 44.1 1.4112 1 78 4 10 BT/USB 11.025 12 4 36 24 40 BT/USB 32 12 4 32 0 12 GSM 22.05 13 21 102 16 21

14.5 HCLK Clock

HCLK Clock drivesthe CPU and the modules on the CPU core AHB bus.Itisgeneratedby a 12-bit prescalerfrom Main Clock,PLL1 Clock,or PLL2 Clock.The prescalerallowssettingthe HCLK Clock periodtoany lengthbetween 1 and 2048 periodsoftheclocksource,inincrementsof1/2period.The defaultsettingfortheHCLK Clockperiodis16 clocksourceperiods. Softwaremay configureSlow ClocktodriveHCLK ClockduringPower Down and Idlemodes.

14.6 PCLK Clock

PCLK Clockdrivesthemodules on theperipheralAPB bus.Itisgeneratedby a 2-bitprescalerfromHCLK Clock,fora divisionfactorof1,2,or4.The defaultis1.The maximum PCLK Clockfrequencyis48 MHz.

14.7 AuxiliaryClocks

Independentclocksare availableforcertainperipheralsthatmay requireclockfrequenciesdifferentfrom those providedas globalclocks.An auxiliaryclockalso may be used forperipheralsthatrequire independencefrom theclock-switchingmechanism appliedtoHCLK Clockand PCLK Clockduringlow- power modes. Eightauxiliaryclockgeneratorsareprovidedfortheseperipherals.Some peripheralshave clockmultiplexerstoallowselectionamong severalavailableclocksources. Each auxiliaryclockgeneratorhas an inputmultiplexerforselectingan inputclocksource:

• Main Clock
• PLL1 Clock
• PLL2 Clock

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2 F PMMAUXnPRSC 1 F

§ · u ¨ ¸ © ¹ CP3SP33 www.ti.com SNOSCW5 –MAY 2013 A 12-bitprescalerprovidesa prescalefactorsfrom1 to2048 clockperiodsoftheinputclockinincrements of1/2clockperiod.For example,iftheselectedclocksourceis12 MHz and thedesiredauxiliaryclock frequencyis 1 MHz, the divisorshould be 2 × 12 or 24. However, the value loaded in the PMMAUXnPRSC prescalerregisterisbiasedby 1,so theactualvalueloadedintotheregisterwillbe 23 (decimal). (4) Zero isan undefinedvalue,so theshortestperiodthatan auxiliaryclockmay have is2 half-clocks,which resultsinthesame clockrateas theprescalerinputclock. By default,theauxiliaryclocksaredisabledfollowingreset,excepttheDSP clock(AuxiliaryClock7). Each auxiliaryclockisavailableforone ormore peripherals,as listedinTable14-5. Table14-5.AuxiliaryClocks AvailabletoPeripherals AUXILIARY PERIPHERAL COMMENTSCLOCK 1 Bluetooth,ADC, AAI BluetoothLLC requiresan accurate12 MHz clock,inadditiontoa variableAuxiliaryClock1. 2 CVSD/PCM Converter0 Supportsa 2-MHz mode inwhichdataisprocessedata fixedrate.Alsosupportsa free- runningmode inwhichdataisprocessedon demand. The free-runningmode does notrequirea specificclockfrequency.The CVSD modules may3 CVSD/PCM Converter1 operatefromindependentclocks. TelematicsCodec ADC 1,4 Requiresan accurateclockfrequency,typically125× or128× thePCM framerate.ADC 2,and StereoDACs

5 I2S Interface

6 USB Requiresan accurate60 MHz clock.Alsorequiresa HCLK Clock>30 MHz.

7 DSP Up to96 MHz

Requiresan accuratefrequencytomatch thebitclockand framesyncrequiredby theexternal8 AAI codec. Copyright© 2013,Texas InstrumentsIncorporated ClockGeneration 85 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Converter (ADC) ADCACR.CLKSEL Bluetooth Interface PLL1 Clock PLL2 Clock Main Clock PCLK Clock Auxiliary Clock 3 12-Bit Prescaler CVSD/PCM Converter 1PMMAUX3CTL.AUXCLKSRC PMMAUX3PRSC.HPACLK Auxiliary Clock 8 12-Bit Prescaler Advanced Audio Interface (AAI) ACCR.CSS PMMAUX8CTL.AUXCLKSRC PMMAUX8PRSC.HPACLK PMMAUX1CTL.AUXCLKSRC PMMAUX1PRSC.HPACLK Auxiliary Clock 2 12-Bit Prescaler CVSD/PCM Converter 0PMMAUX2CTL.AUXCLKSRC PMMAUX2PRSC.HPACLK Telematics Codec ADC 1 TCDCADCCLK1.ADCCLKSRCAuxiliary Clock 4 12-Bit Prescaler Telematics Codec Stereo DACs TCDCDACCLK.DACCLKSRC Telematics Codec ADC 2 TCDCADCCLK2.ADCCLKSRC I2SCLK SCK PMMAUX4CTL.AUXCLKSRC PMMAUX4PRSC.HPACLK Auxiliary Clock 5 12-Bit Prescaler I2S Interface I2SCLK.CLKSEL PMMAUX5CTL.AUXCLKSRC PMMAUX5PRSC.HPACLK Auxiliary Clock 6 12-Bit Prescaler Universal Serial Bus (USB) PMMAUX6CTL.AUXCLKSRC PMMAUX6PRSC.HPACLK Auxiliary Clock 7 12-Bit Prescaler Digital Signal Processor (DSP) PMMAUX7CTL.AUXCLKSRC PMMAUX7PRSC.HPACLK TCIO1 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure14-5isblockdiagramoftheauxiliaryclockgenerationlogic. Figure14-5.AuxiliaryClock Generators

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14.8 Clock GenerationRegisters

Table14-6liststheclockgenerationregisters. Table14-6.Clock and Reset Registers NAME ADDRESS DESCRIPTION PMMCKCTL FF A400h Clockand ResetControlRegister PMMSR FF A408h ClockStatusRegister PMMPRSHC FF A40Ch HCLK ClockPrescalerRegister PMMPRSPC FF A410h PCLK ClockPrescalerRegister PMMPRSSC FF A414h Low FrequencyClockPrescalerRegister PMMPLL1CTL1 FF A420h PLL1 ControlRegister1 PMMPLL1CTL2 FF A424h PLL1 ControlRegister2 PMMPLL1MDIV FF A428h PLL1 M DividerPrescalerRegister PMMPLL1NDIV FF A42Ch PLL1 N DividerPrescalerRegister PMMPLL1NMOD FF A434h PLL1 N DividerPrescalerRegister PMMPLL1PDIV FF A430h PLL1 P DividerPrescalerRegister PMMPLL1STUP FF A438h PLL1 Start-UpCounterRegister PMMPLL2CTL1 FF A440h PLL2 ControlRegister1 PMMPLL2CTL2 FF A444h PLL2 ControlRegister2 PMMPLL2MDIV FF A448h PLL2 M DividerPrescalerRegister PMMPLL2NDIV FF A44Ch PLL2 N DividerPrescalerRegister PMMPLL2NMOD FF A454h PLL2 N DividerPrescalerRegister PMMPLL2PDIV FF A450h PLL2 P DividerPrescalerRegister PMMPLL2STUP FF A458h PLL2 Start-UpCounterRegister PMMAUX1CTL FF A500h AuxiliaryClock1 ControlRegister PMMAUX1PRSC FF A504h AuxiliaryClock1 PrescalerRegister PMMAUX2CTL FF A510h AuxiliaryClock2 ControlRegister PMMAUX2PRSC FF A514h AuxiliaryClock2 PrescalerRegister PMMAUX3CTL FF A520h AuxiliaryClock3 ControlRegister PMMAUX3PRSC FF A524h AuxiliaryClock3 PrescalerRegister PMMAUX4CTL FF A530h AuxiliaryClock4 ControlRegister PMMAUX4PRSC FF A534h AuxiliaryClock4 PrescalerRegister PMMAUX5CTL FF A540h AuxiliaryClock5 ControlRegister PMMAUX5PRSC FF A544h AuxiliaryClock5 PrescalerRegister PMMAUX6CTL FF A550h AuxiliaryClock6 ControlRegister PMMAUX6PRSC FF A554h AuxiliaryClock6 PrescalerRegister PMMAUX7CTL FF A560h AuxiliaryClock7 ControlRegister PMMAUX7PRSC FF A564h AuxiliaryClock7 PrescalerRegister PMMAUX8CTL FF A570h AuxiliaryClock8 ControlRegister PMMAUX8PRSC FF A574h AuxiliaryClock8 PrescalerRegister Copyright© 2013,Texas InstrumentsIncorporated ClockGeneration 87 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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14.8.1 Clock and Reset ControlRegister(PMMCKCTL)

The PMMCKCTL registerisa byte-wide,read/writeregisterthatcontrolstheclockselectionand contains thepower-onresetstatusbit.Atreset,thePMMCKCTL registerisinitializedas describedbelow: 7 5 4 3 2 1 0 Reserved FCLKSRC SCLK Reserved POR POR The Power-On-Resetbitissetwhen a power-onconditionhas been detected.Thisbitcan onlybe clearedby software,notset.Writinga 1 tothisbitwillbe ignored,and theprevious valueofthebitwillbe unchanged. 0 – Softwareclearedthisbit. 1 – Softwarehas notclearedhisbitsincethelastreset. SCLK The Slow ClockSelectbitcontrolstheclocksourceused fortheSlow Clock.Ifsetwhile thelow-frequencyoscillatorisnotstable,thisbitwillreadas 1 buttheclocksourcewillnot switchuntilthelow-frequencyoscillatorisstable.Thisbitcannotbe clearedwhilethehigh- frequencyoscillatorisnotstable.Atreset,thisbitiscleared. 0 – Slow Clockdrivenby prescaledMain Clock. 1 – RequestassertedtodriveSlow Clockfromthe32.768kHz oscillator. FCLKSRC The FastClockSourcefieldselectstheclocksourceused togenerateHCLK Clock.After reset,theMain Clockisselected.Requestinga switchtoa PLL Clockwhilethe correspondingPMMPLLn.CTL2.PLLCLKSTB bitisclear(PLL Clocknotstable)willbe stalleduntilthePLL Clockisstable.When switchingbetween PLL Clocks,theremust be an intermediatestepinwhichMain Clockisselected.Atreset,thisfieldisinitializedto11b. 00 – PLL1. 01 – PLL2. 10 – Reserved. 11 – Main Clock.

14.8.2 Clock StatusRegister(PMMSR)

The PMMSR registerisa byte-wideread-onlyregisterthatholdsthetwo bitswhich indicatewhetherthe high-frequencyoscillatorand thelow-frequencyoscillatorarestable. 7 2 1 0 Reserved MCLKSTB SCLKSTB SCLKSTB The Slow ClockStablebitindicateswhetherthelow-frequencyoscillatorisproducinga stableclock. 0 – Low-frequencyoscillatorisunstable,disabled,ornotoscillating. 1 – Low-frequencyoscillatorisavailable. MCLKSTB The Main ClockStablebitindicateswhetherthehigh-frequencyoscillatorisproducinga stableclock. 0 – High-frequencyoscillatorisunstable,disabled,ornotoscillating. 1 – High-frequencyoscillatorisavailable.

14.8.3 HCLK Clock PrescalerRegister(PMMPRSHC)

The PMMPRSHC registeris a 16-bitread/writeregisterthatholds the 12-bitprescaleravailableto generateHCLK Clock.The registerisinitializedto001Fh atreset. 15 12M M 11 0 Reserved HPHCLK

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www.ti.com SNOSCW5 –MAY 2013 HPHCLK The HalfPeriodsHighFrequencyClockfieldholdsthedivisor(expressedinhalf-periodsof theinputclocksource)fortheprescalerused togenerateHCLK Clock.The clocksourceis dividedby ((HPHCLK + 1)÷ 2)toobtaintheHCLK Clock.The fieldisbiasedby 1,so the defaultvalueofthisfieldspecifies32 half-periods,whichisa divisorof16.Zeroisan undefinedvalueforthisfield.

14.8.4 PCLK Clock PrescalerRegister(PMMPRSPC)

The PMMPRSPC registerisa byte-wide,read/writeregisterthatholdsthe divisorforgeneratingPCLK ClockfromHCLK Clock.The maximum PCLK Clockfrequencyis48 MHz. The registerisinitializedto00h atreset. 7 2M 1 0 Reserved DIVPCLK DIVPCLK The DivisorPCLK Clockfieldhas fourdefinedvalues: 00b – ÷1 01b – ÷2 10b – ÷4 11b – Reserved.

14.8.5 Slow Clock PrescalerRegister(PMMPRSSC)

The PMMPRSSC registeris a 16-bit,read/writeregisterthatholds the 14-bitprescaleravailableto generateSlow ClockfromMain Clock.The registerisinitializedto02DBh atreset. 31 14M 13 0 Reserved HPSCLK HPSCLK The HalfPeriodsSlow Clockfieldholdsthedivisor(expressedinhalf-periodsoftheinput clocksource)fortheprescalerused togenerateSlow Clock.The Main Clockisdividedby ((HPSCLK + 1)÷ 2)toobtaintheSlow Clock.Atreset,theHPSCLK registerisinitializedto 02DBh, whichgeneratesa Slow Clockrateof32.786885kHz.Thisisabout0.5% faster thana Slow Clockgeneratedfroman external32.768kHz crystalnetwork.Zeroisan undefinedvalueforthisfield.

14.8.6 PLLn ControlRegister1 (PMMPLLnCTL1)

The PMMPLLnCNT1 registersare16-bit,read/writeregistersthatholdcontrolfieldsforthecorresponding PLL.The registersareinitializedto00h atreset. 15 5 4 3 2 1 0 Reserved PLLIPSEL PLLDCOE PLLEN PLLEN The PLL EnablefieldcontrolswhetherthePLL isenabledordisabled.Beforesoftwarecan power down a PLL used togenerateHCLK Clockoran AuxiliaryClock,theclocksmust be switchedtoanotherclocksource. 00 – PLL disabled. 01 – PLL enabled. 10 – Reserved. 11 – Reserved. PLLDCOE The PLL DirectClockOutputEnablebitcontrolsthecorrespondingPLL output.The PLL Clockoutputisdrivenonlywhen thisbitissetand thePLL Clockisstable. 0 – PLL Clockoutputdisabled. 1 – PLL Clockisenabledwhen stable. Copyright© 2013,Texas InstrumentsIncorporated ClockGeneration 89 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com PLLIPSEL The PLL InputSelectfieldselectstheinputclocksourceforthecorrespondingPLL. 00 – Main Clock. 01 – I2SCLK pin. 10 – Reserved. 11 – Reserved

14.8.7 PLLn ControlRegister2 (PMMPLLnCTL2)

The PMMPLLnCNT2 registersare16-bit,read/writeregistersthatholdcontrolfieldsforthecorresponding PLL.The registersareinitializedto00h atreset. 15 3 2 1 0 Reserved HCCPLL DPLLC PLLCLKSTB PLLCLKSTB The PLL ClockStablebitindicateswhen thecorrespondingPLL Clockisstable. 0 – PLL Clocknotstable. 1 – PLL Clockisstable. DPLLC The DisablePLL ClockEnablebitcontrolswhetherthecorrespondingPLL isdisabled when enteringthePower Save orIdlemodes. Thisbitisclearedwhen a hardwarewake- up eventoccurs. 0 – PLL may be enabledinPower Save and Idlemodes. 1 – PLL isalwaysdisabledinPower Save and Idlemodes. HCCPLL The Hardware ClockControlPLL bitenablesthehardwareclockcontrolmechanism, See Section16.5formore information. 0 – Hardware clockcontroldisabled. 1 – Hardware clockcontrolenabled.

14.8.8 PLLn M DividerRegister(PMMPLLnMDIV)

The PMMPLLnMDIV registersare byte-wide,read/writeregistersthathold the 8-bitM divisorforthe correspondingPLL.The registersareinitializedto00h atreset. 7 0 MDIV MDIV The M Divisorfieldspecifiesan integerdivisor.See Section14.4.1formore information.

14.8.9 PLLn N DividerRegister(PMMPLLnNDIV)

The PMMPLLnNDIV registersare byte-wide,read/writeregistersthatholdthe8-bitintegerpartoftheN divisor.The registersareinitializedto00h atreset. 7 0 NDIV NDIV The N DivisorfieldspecifiestheintegerpartoftheN divisor.See Section14.4.1formore information.

14.8.10 PLLn N Mod Register(PMMPLLnNMOD)

The PMMPLLnNMOD registersare 16-bit,read/writeregistersthatholdthe5-bitfractionalpartoftheN divisorforthecorrespondingPLL and a controlfieldforthelevelofditheringineffect.The registersare initializedto00h atreset. 15 14 13 8 7 0 NMOD_DITH Reserved NMOD

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www.ti.com SNOSCW5 –MAY 2013 NMOD The N Mod fieldspecifiesthefractionalpartoftheN divisor.See Section14.4.1PLL Programming formore information. NMOD_DITH The N Mod Ditheringfieldspecifiesthelevelofditheringtobe appliedtothePLL Clock tosuppresstoneartifactsthatmay occurinsome audioapplications.The defaultlevel issufficientfora widerangeofapplications. 00 – Medium (default). 01 – Low. 10 – High. 11 – No dithering.

14.8.11 PLLn P DividerRegister(PMMPLLnPDIV)

The PMMPLLnPDIV registersare byte-wide,read/writeregistersthathold the 8-bitP divisorforthe correspondingPLL.The registerisinitializedto00h atreset. 7 0 PDIV PDIV The P Divisorfieldspecifiesan integerdivisor.See Section14.4.1PLL Programming formore information.

14.8.12 PLLn Start-UpCounter Register(PMMPLLnSTUP)

The PMMPLLnSTUP registersare16-bit,read/writeregistersthatspecifya 10-bitintegernumber ofclock periodsthatmust occurbeforethecorrespondingPLL Clockisconsideredstable.The PLL Clockoutputis not drivenunlessthe PLL is stableand the PMMPLLnCTL1.PLLDCOE bitis set.The registersare initializedto007Fh atreset. 15 10M M 9 0 Reserved CLKCNT CLKCNT The CLKCNT fieldspecifiesthenumber ofPLL Clockcycleswhichmust occurbeforethePLL isconsideredstable.The number ofcyclesis(256× (CLKCNT + 1)),thereforethedefaultis 32,768cycles.

14.8.13 AuxiliaryClock n ControlRegister(PMMAUXnCTL)

The PMMAUXnCTL registersare byte-wide,read/writeregistersthat controlthe AuxiliaryClock generators.The registersareinitializedto06h atreset,exceptPMMAUX7CTL whichisinitializedto07h. 7 3 2 1 0 Reserved AUXCLKSRC AUXCLKEN AUXCLKEN The AuxiliaryClockEnablebitenablesthecorrespondingAuxiliaryClockoutput. 0 – PLL Clockoutputdisabled. 1 – PLL Clockisenabledwhen stable. AUXCLKSRC The AuxiliaryClockSourcefieldselectstheinputclocksourceforthecorresponding AuxiliaryClockgenerator.When switchingfromone PLL toanother,theremust be an intermediatestepinwhichMain Clockisselected. 00 – PLL1 Clock. 01 – PLL2 Clock. 10 – Reserved. 11 – Main Clock. Copyright© 2013,Texas InstrumentsIncorporated ClockGeneration 91 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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14.8.14 AuxiliaryClock n PrescalerRegister(PMMAUXnPRSC)

The PMMAUXnPRSC registersare 16-bitread/writeregistersthat hold the 12-bitclock divisors (expressedin halfclocks)forthe prescalersused to generatethe correspondingAuxiliaryClocks from Main Clock,PLL1 Clock,or PLL2 Clock (as selectedby the PMMAUXnCTL.AUXCLKSRC field).The registersareinitializedto00FFh atreset,exceptPMMAUX7PRSC whichisinitializedto0001h. 15 12M M 11 0 Reserved HPACLK HPACLK The HalfPeriodsPer AuxiliaryClockfieldspecifiesthenumber ofhalf-clocksused for generatingtheAuxiliaryClock.The clocksourceisdividedby ((HPACLK + 1)÷ 2)toobtaintheauxiliaryclock.Zeroisan undefinedvalueforthisfield.

15 Reset

Therearefivesourcesofreset:

• Power-On Reset— on-chippower-ondetectorand timer.
• ExternalReset— assertionoftheRESET input.
• SoftwareReset— enabledby writingspecialcode sequencestotheSWRESET register.
• Timingand Watchdog Module (TWM) — overflowofthewatchdogtimer
• SDI Reset— resetfromtheSerialDebug Interface(SDI)

15.1 Power-On Reset

The on-chipPower On Reset (POR) circuitgeneratesa positiveedge on theinternalresetsignalwhen VCC risesabove VTRIP (typically1.38V).The VCC risetime from 0V to VTRIP must not exceed the maximum tTRIP specification.AftertriggeringthePOR circuit,therisetimefromVTRIP toa stableVCC must notexceed themaximum tD specification.Afterresethas occurred,thePOR isspecifiedtorearm when VCC fallsbelow 400 mV (althoughitmay rearm at a highervoltage,up to 600 mV), and itwillbe retriggeredwhen VCC again risesabove VTRIP. There must be a delay of at least950 µs before retriggeringthePOR. VCC ramp-up must reachitsnominallevelbeforeorsimultaneouswithIOVCC ramp-up,otherwisespikes may be drivenon GPIO-capablepins.

15.2 Reset InputTiming

The CP3SP33 has specifictimingrequirementsthatmust be met topreventimproperprogram behavior, such as corruptionof an externalflashmemory programming operationinprogresswhen the resetis received.Thistimingsequence shown inFigure15-1. Allresetcircuitsmust ensurethatthistimingsequence isalwaysmaintainedduringpower-upand power- down. The designofthepower supplyalsoaffectshow thissequence isimplemented. The power-upsequence is: 1. The RESET pinmust be heldlowuntilbothIOVCC and VCC have reachedtheminimum levels specifiedintheDC Characteristicssection.VCC must reachitsnominallevelatorbeforeIOVCC. 2. Afterbothofthesesupplyvoltagerailshave met thiscondition,thentheRESET pinmay be driven high.Atpower-upan internal14-bitcounterissetto3FFFh and beginscountingdown to0 afterthe crystaloscillatorbecomes stable.When thiscounterreaches0,theonchipRESET signalisdrivenhigh unlesstheexternalRESET pinisstillbeingheldlow.ThispreventstheCP3SP33 fromcoming outof resetwithan unstableclocksource. The power-down sequence is: 1. The RESET pinmust be drivenlowas soon as eithertheIOVCC orVCC voltagerailreachesthe minimum levelsspecifiedintheDC Characteristics.

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2.97V 1.62V CP3SP33 www.ti.com SNOSCW5 –MAY 2013 2. The RESET pinmust thenbe heldlowuntiltheMain Clockisstopped.The Main Clockwilldecay with thesame profileas IOVCC. Meetingthepower-down resetconditionsensuresthatsoftwarewillnotbe executedatvoltagelevelsthat may cause incorrectprogram executionor corruptionof the flashmemories. This situationmust be avoidedbecause theMain Clockdecays withtheIOVCC supplyratherthanstoppingimmediatelywhen IOVCC fallsbelowtheminimum specifiedlevel. The externalresetcircuitspresentedinthe followingsectionsprovidevaryinglevelsof additionalfault toleranceand expandabilityand are presentedas possibleexamples of solutionsto be used withthe CP3SP33. Itisimportanttonote,however,thatany designfortheresetcircuitand power supplymust meet thetimingrequirementsshown inFigure15-1. Figure15-1.Power-On Reset Timing

15.2.1 Simple ExternalReset

A simple externalreset circuitwith brown-out and glitchprotectionbased on the LM809 3-Pin MicroprocessorReset Circuitisshown inFigure15-2. The LM809 producesa 240-ms logiclow reset pulsewhen thepower supplyrisesabove a thresholdvoltage.Variousresetthresholdsare availablefor theLM809, however theoptionsfor2.93V and 3.08V are most suitablefora CP3SP33 deviceoperating froman IO-VCC at3.0Vto3.3V. Copyright© 2013,Texas InstrumentsIncorporated Reset 93 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Figure15-2.Simple ExternalReset

15.2.2 Manual and SDI ExternalReset

An externalresetcircuitbased on theLM3724 5-PinMicroprocessorResetCircuitisshown inFigure15-3. The LM3724 producesa 190-ms logiclow resetpulsewhen the power supplyrisesabove a threshold voltageor a manual resetbuttonispressed.Variousresetthresholdsare availableforthe LM3724, however theoptionfor3.08Vismost suitablefora CP3SP33 deviceoperatingfroman IOVCC at3.3V. Figure15-3.Manual and SDI ExternalReset The LM3724 providesa debounced inputfora manual pushbuttonresetswitch.Italsohas an open-drain outputwhichcan be used forimplementinga wire-ORconnectionwitha resetsignalfroma serialdebug interface.This circuitis typicalof a design to be used in a development or evaluationenvironment, however itis a good recommendation forallgeneralCP3SP33 designs.Ifan SDI interfaceis not implemented,an LM3722 withactivepullupmay be used.

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(1.8V) VCC GPIO Reset Output Power Fail Output (PFO) Low Line Output (LLO) Watchdog Input (WDI) Power Fail Input (PFI) CP3SP33 www.ti.com SNOSCW5 –MAY 2013

15.2.3 Fault-TolerantExternalReset

An externalreset circuitbased on the LM3710 MicroprocessorSupervisoryCircuitis shown in Figure15-4.Itprovidesa highleveloffaulttoleranceinthatitprovidestheabilitytomonitorboththeVCC supplyforthecorelogicand theIO-VCC supply.Italsoprovidesa low-voltageindicationfortheIOVCC supplyand an externalwatchdogtimer. Figure15-4.Fault-TolerantExternalReset The signalsshown inFigure15-4are:

• Core VCC — the1.8Vpower supplyrailforthecorelogic.
• IOVCC — the3.0–3.3Vpower supplyrailfortheI/Ologic.
• Watchdog Input(WDI)— thissignalisassertedby theCP3SP33 atregularintervalstoindicatenormal operation.A general-purposeI/O (GPIO) portmay be used to providethissignal.Ifthe internal watchdog timerinthe CP3SP33 isused,then the LM3704 MicroprocessorSupervisoryCircuitcan providethesame featuresas theLM3710 butwithoutthewatchdogtimer.
• RESET — an active-lowresetsignaltotheCP3SP33. The LM3710 isavailableinversionswithactive pulluporan open-drainRESET output.
• Power-FailInput(PFI)— thisisa voltagelevelderivedfromtheCore VCC power supplyrailthrougha simpleresistordividernetwork.
• Power-FailOutput(PFO)— thissignalisassertedwhen thevoltageon PFI fallsbelow 1.225V.PFO is connectedtothenon-maskableinterrupt(NMI)inputon theCP3SP33. A system shutdown routinecan thenbe invokedby theNMI handler.
• Low Line Output (LLO)— thissignalisassertedwhen the main IOVCC levelfailsbelow a warning thresholdvoltagebutremainsabove a resetdetectionthreshold.Thissignalmay be routedtotheNMI inputon theCP3SP33 ortoa separateinterruptinput. These additionalstatusand feedbackmechanisms allowtheCP3SP33 torecoverfromsoftwarehangs or performsystemshutdownfunctionsbeforebeingplacedintoreset. The standardresetthresholdforthe LM3710 is3.08V withotheroptionsfordifferentwatchdog timeout and resettimeouts.The selectionofthesevaluesaremuch more application-specific.The combinationof a watchdogtimeoutperiodof1600 ms and a resetperiodof200 ms isa reasonablestartingpoint. Copyright© 2013,Texas InstrumentsIncorporated Reset 95 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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16 Power Management Module

The Power Management Module (PMM) improves the efficiencyof the CP3SP33 by changing the operatingmode (and thereforethepower consumption)accordingtotherequiredlevelofdeviceactivity. The deviceimplementsfourpower modes:

• ActiveMode — CPU and corebus peripheralsoperatefromHCLK Clock,whichisgeneratedby a prescalerfromMain Clock,PLL1 Clock,orPLL2 Clock.EitherPLL may be powered down ifitsoutput isnotused togene ateHCLK Clockorany AuxiliaryClock.
• Power-Save Mode — CPU and corebus peripheralsoperatefromSlow Clock.Any ofthePLLs and high-frequencyoscillatormay be powered down, ifitsoutputisnotused togenerateSlow Clockorany AuxiliaryClock.
• IdleMode — CPU and most orallperipheralsarepowered down. A watchdogtimeout(froma timer runningon Slow Clock),externalreset,orMIWU inputcan breakoutofthismode.
• HaltMode — onlyan externalresetorMIWU inputcan breakoutofthismode. Table16-1 summarizes thedifferencesbetween power modes: thestateofthehigh-frequencyoscillator (on or off),PLLs, HCLK Clocksource(clockused by CPU and corebus peripherals),and clocksource used by theTimingand Watchdog Module (TWM). Table16-1.Power Mode OperatingSummary MODE HIGH-FREQUENCY OSCILLATOR PLLs HCLK CLOCK SOURCE TWM CLOCK SOURCE Active On On orOff Prescaler Slow Clock Power Save On orOff On orOff Slow Clock Slow Clock Idle On orOff On orOff None Slow Clock Halt Off Off None None The low-frequencyoscillatorcontinuesto operate in allfourmodes and power must be provided continuouslytothedevicepower supplypins.InHaltmode, however,Slow Clockdoes nottoggle,and as a result,theTimingand Watchdog Module does notoperate.For thePower Save and Idlemodes, the high-frequencyoscillatorcan be turnedon or offunder softwarecontrol,ifthelow-frequencyoscillatoris used todriveSlow Clock. Softwarecan configureeitherPLL tobe powered down inActive,Power Save,and Idlemode, as longas itisnotdrivingHCLK Clockoran AuxiliaryClockgenerator. Table 16-2 shows the clocksourcesused by the CP3SP33 devicemodules and theirbehaviorineach power mode. Table16-2.Module ActivitySummary POWER MODE MODULE CLOCK SOURCE(s) ACTIVE POWER SAVE IDLE HALT CPU On On/Off Off Off HCLK Clock MIWU On On On Active PCLK Clock PMM On On On Active Slow Clock TWM On On On Off Slow Clock Bluetooth On/Off On/Off On/Off Off Aux Clk1 A/D Converter On/Off On/Off On/Off Off(1) Aux Clk1,PCLK Clock CVSD/PCM 0 On/Off On/Off On/Off Off Aux Clk2 CVSD/PCM 1 On/Off On/Off On/Off Off Aux Clk3 Codec On/Off On/Off On/Off Off Aux Clk1,Aux Clk4,PCLK Clock,PLL1 Clk,PLL2 Clk,I2SCLK,AAI SCK, TCIO1 (1) The Analog/DigitalConverter(ADC) module isnotautomaticallydisabledby enteringHaltmode, however itsclockisstoppedso no conversionsmay be performedinHaltmode. Formaximum power savings,softwaremust disabletheADC module beforeenteringHalt mode.

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www.ti.com SNOSCW5 –MAY 2013 Table16-2.Module ActivitySummary (continued) POWER MODE MODULE CLOCK SOURCE(s) ACTIVE POWER SAVE IDLE HALT I2SInterface On/Off On/Off On/Off Off Aux Clk5,PCLK Clock,TCIO1 USB On/Off On/Off On/Off Off Aux Clk6 DSP On/Off On/Off On/Off Off Aux Clk7 AAI On/Off On/Off On/Off Off Aux Clk1,Aux Clk8 AllOthers On/Off On/Off Off Off HCLK Clock,PCLK Clock A module shown as On/OffinTable16-2 may be enabledor disabledby software.A module shown as Activecontinuesto operateeven whileitsclockis suspended, which allowswake-up events to be processedduringIdleand Haltmodes.

16.1 ActiveMode

InActivemode, thehigh-frequencyoscillatorisactiveand generatesthe12-MHz Main Clock.IfthePLL Clocksarenotneeded,thePLLs may remainpowered off.Most deviceson theCPU corebus aredriven by HCLK Clock,and most APB bus devicesaredrivenby PCLK Clock. When enteringActivemode from a mode inwhich thehigh-frequencyoscillator,PLLs, or low-frequency clockwere powered down, themode switchwillbe stalleduntilthehigh-frequencyoscillator,any enabled PLL,and thelow-frequencyoscillator(ifenabled)areproducingstableclocks. The activityofperipheralmodules iscontrolledby theirenablebits.Power consumptioncan be reducedin Activemode by selectivelydisablingmodules and by executingthe WAIT instruction.When the WAIT instructionisexecuted,theCPU stopsexecutingnew instructionsuntilitreceivesan interruptsignal.

16.2 Power Save Mode

In Power Save mode, Slow Clock is used as the HCLK Clock which drivesthe CPU and core bus modules.Power Save mode isintendedforapplicationsinwhich a low levelof processingisrequired duringlow-powerstandby,forexample ifsoftwareneeds todetecteventsforwhichno hardwarewake-up signalisavailable. IfSlow Clockisdrivenby the32.768kHz oscillatorand no on-chipmodule currentlyrequiresthe12-MHz Main Clock,softwarecan disablethehigh-frequencyoscillatortofurtherreducepower consumption.The auxiliaryclockscan be turnedoffunder softwarecontrolbeforeswitchingtoa reducedpower mode, or theymay remainactiveas longas theyhave an activeclocksource. Ifa PLL Clockisnotused togenerateHCLK Clockor an auxiliaryclock,thecorrespondingPLL can be powered down. Controlover whether Main Clock and the PLLs are runningcan be controlledby the BluetoothcontrollerthroughtheHardware ClockControlfunction(describedinSection),ifenabled. InPower Save mode, some modules aredisabledortheiroperationisrestricted.Othermodules,including theCPU, continuetofunctionnormally,butoperateata reducedclockrate.See themodule descriptions fordetailsofeach module’s activityinPower Save mode.

16.3 IdleMode

InIdlemode, theHCLK Clockand PCLK Clockare disabledand thereforetheclockisstoppedtomost modules ofthedevice.Idlemode isintendedforapplicationsinwhich no processingisrequiredduring low-powerstandby,butthecapabilityisneeded tobreakoutofthemode due toactivityon theBluetooth interfaceorexpirationofthewatchdogtimer.Idlemode can onlybe enteredfromPower Save mode. Copyright© 2013,Texas InstrumentsIncorporated Power Management Module 97 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com The PLLs and the high-frequencyoscillatormay be disabledas controlledby registerbits.The low- frequencyoscillatorremains active.The Power Management Module (PMM) and the Timing and Watchdog Module (TWM) continuetooperatefromtheSlow Clock.The auxiliaryclockscan be turnedoff undersoftwarecontrolbeforeswitchingtoa low-powermode, ortheyremainactiveas longas theyhave an active clock source (Main Clock, PLL1 Clock, or PLL2 Clock, as selected by the PMMCKCTL.FCLKSRC bit).Alternatively,generationofMain Clockand thePLL Clockscan be controlled by the Bluetoothcontrollerthroughthe Hardware Clock Controlfunction(describedinSection16.5),if enabled.

16.4 HaltMode

InHaltmode, allthedeviceclocks,includingtheMain Clock,PLL1 Clock,PLL2 Clock,HCLK Clock,PCLK Clock,and Slow Clock,aredisabled.Haltmode isintendedforapplicationsinwhichan externalwake-up signalcan be used topower-upthesystemthroughtheRESET inputoran MIWU input. The high-frequencyoscillatorand PLLs are turnedoff.Thisistheonlymode inwhich thelow-frequency oscillatormay be disabled,however itscircuitryis optimizedto ensure lowest possiblepower consumption.Thismode allowsthe deviceto reach the absoluteminimum power consumptionwithout losingitsstate(memory,registers,etc.).

16.5 Hardware Clock Control

The Hardware ClockControl(HCC) mechanism givestheBluetoothLower LinkController(LLC)individual controloverthehigh-frequencyoscillatorand thePLLs.The BluetoothLLC can entera Sleepmode fora specifiednumber of low-frequencyclockcycles.While the BluetoothLLC is in Sleep mode and the CP3SP33 isinPower Save orIdlemode, theHCC mechanism may be used tocontrolwhetherthehigh- frequencyoscillatororPLLs arepowered. The PMMSTCTL.HCCM bitenablescontrolby theBluetoothLLC overthehigh-frequencyoscillator,and thePMMPLLnCTL2.HCCPLL bitsenablecontroloverthecorrespondingPLLs.IftheHCCM bitisset,then controlisenabledoverboththehigh-frequencyoscillatorand thePLLs,and theHCCPLL bitsareignored. (ThePLLs cannotbe enabledwhilethehigh-frequencyoscillatorisdisabled.) Altogether,three mechanisms controlwhether the high-frequencyoscillatoris active,and four mechanisms controlwhetherthePLLs areactive:

• HCC bits— theHCC bits(PMMSTCTL.HCCM and PMMPLLnCTL2.HCCPLL) allowtheBluetoothLLC to disablethe high-frequencyoscillatorand PLLs duringPower Save and Idlemodes when the BluetoothLLC goes intoSleep mode. The HCC bitsare automaticallyclearedwhen Activemode is entered.
• Disable bits— the disablebits(PMMSTCTL.DMC and PMMPLLnCTL2.DPLLC) force the high- frequencyoscillatorand PLLs tobe disabledwhen enteringthePower Save and Idlemodes. When set,thesebitsoverridetheHCC mechanism. The DMC and DPLLC bitsareautomaticallyclearedby a hardwarewake-up event.
• Power Management Mode — Haltmode disablesthehigh-frequencyoscillatorand PLLs,withoutregard toany registerbits.Activemode enablesthehigh-frequencyoscillator,againwithoutregardtoany bits. EnteringActivemode willrestartany PLLs enabledtorun.
• PLL enablefields— The PMMPLLnCTL1.PLLEN fieldsenablethecorrespondingPLLs torun.

16.6 SwitchingBetween Power Modes

Switchingfroma highertoa lowerpower consumptionmode isperformedby writingan appropriatevalue to the Power Management ControlRegister(PMMSTCTL). Switchingfrom a lowerpower consumption mode to the Activemode isusuallytriggeredby a hardware event.Figure16-1 shows the fourpower modes and theeventsthattriggera transitionfromone mode toanother.

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HA L T = 1 & WB P S M = 1 & "WA IT" IDLE = 1 & "WAIT" HW Event or P S M = 1 & DHC = 0 & DM C = 0 HW Event HW Event Note: HW Event = MIWU wake-up, NMI, or interrupt acknowledge while PMMSTCTL.WACK = 1 HALT = 1 & "WAIT" PSM = 1 & WB P S M = 0 or P S M = 1 & WB P S M = 1 & "WA IT" Power Save Mode Idle Mode Halt Mode DS444 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure16-1.Power Mode StateDiagram Softwarechanges thepower mode ineitheroftwo ways,as controlledby thePMMSTCTL.WBPSM bit:

• Immediate transition(WBPSM = 0)— new clocksources take effectas soon as stableclocksare available.Onlyallowedwhen goingfromActivetoPower Save mode.
• TransitionatnextWAIT instruction(WBPSM = 1)— devicecontinuestooperateinActivemode untilit executesa WAIT instruction.At executionoftheWAIT instruction,thedeviceentersthenew mode, and theCPU waitsforthenextinterruptevent. A transitiontoIdleorHaltmode must use thesecond method (WBPSM = 1). Some ofthepower-uptransitionsarebased on theoccurrenceofa wake-up event:
• Multi-InputWake-Up Event— most general-purposeI/O portpins,certainperipheralpins(thatdon’t sharefunctionalitywitha GPIO port),and certainperipheraleventscan be programmed intheMIWU module totriggera wake-up event.
• Non-MaskableInterrupt(NMI)— an NMI interruptisa wake-up event.
• InterruptAcknowledge Cycle— when the WACK bitin the PMMSTCTL registerisset,any interrupt acknowledgecycleisa wake-up event. Once a wake-up eventisdetected,itislatcheduntilan interruptacknowledgecycleorresetoccurs. A wake-up eventcauses a transitiontotheActivemode and restoresnormalclockoperation,butdoes not startexecutionoftheprogram.Itistheinterrupthandlerassociatedwiththewake-up source(MIWU, NMI, orany interrupt)thatcausesprogramexecutiontoresume.

16.6.1 ActiveMode toPower Save Mode

A transitionfrom Activemode toPower Save mode isperformedby writinga 1 tothePMMSTCTL.PSM bit.The transitionto Power Save mode occurs immediatelyor at the executionof the next WAIT instruction,depending on the stateof the PMMSTCTL.WBPSM bit.The PSM bitoperatesdifferently dependingon thismode:

• WBPSM = 0— PSM bitreads as 1 afterthe transitionto the Power Save mode occurs.Ifthe high- frequencyoscillatoror PLLs are notproducinga stableoutput,thistransitionmay be stalled.Inthis mode, thePSM bitindicateswhen thetransitionhas been completed.
• WBPSM = 1— PSM bitreads as 1 afteritiswrittenwith1, even beforethe WAIT instructionhas executedand thetransitiontoPower Save mode has occurred. Copyright© 2013,Texas InstrumentsIncorporated Power Management Module 99 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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16.6.2 EnteringIdleMode

Idlemode can only be enteredfrom Power Save mode. Idlemode is enteredby writing1 to the PMMSTCTL.IDLE bitand thenexecutinga WAIT instruction.

16.6.3 DisablingtheHigh-FrequencyClock

When the low-frequencyoscillatoris used to generatethe Slow Clock,power consumptioncan be reduced furtherin the Power Save or Idlemode by disablingthe high-frequencyoscillator.This is accomplishedby writinga 1 tothePMMSTCTL.DMC bitbeforeexecutingtheWAIT instructionthatputs thedeviceinthePower Save or Idlemode. The high-frequencyclockisturnedoffonlyafterthedevice entersthePower Save orIdlemode. The CPU operatesfrom Slow ClockinPower Save mode. Itcan turnoffthehigh-frequencyoscillatorat any timeby writinga 1 to the PMMSTCTL.DMC bit.The high-frequencyoscillatorisalways enabledin Activemode and isalwaysdisabledinHaltmode, withoutregardtothePMMSTCTL.DMC bit. Immediatelyafterpower-upand entryintoActivemode, softwaremust waitforthelow-frequencyoscillator to become stablebefore it can put the device in Power Save mode. It should monitor the PMMSR.SCLKSTB bitforthispurpose.Once thisbitisset,the low-frequencyoscillatorisstableand Power Save mode can be entered. Slow Clock must come from the low-frequencyoscillatoror an externalclock(drivenon X2CKI),not derivedfromMain Clock,ifthehigh-frequencyoscillatorwillbe disabled.

16.6.4 EnteringHaltMode

Halt mode can only be entered from the Activeand Power Save modes. In Activemode, the PMMSTCTL.WBPSM bitmust be setbeforeenteringHaltmode. Haltmode isenteredby writing1 tothe PMMSTCTL.HALT bitand thenexecutinga WAIT instruction.

16.6.5 Software-ControlledTransitiontoActiveMode

A transitionfromPower Save mode toActivemode can be accomplishedby eithera softwaremethod ora hardwarewake-up event.The softwaremethod istowritea 0 tothePMMSTCTL.PSM bit.The valueof theregisterbitchanges onlyafterthetransitiontotheActivemode iscompleted. Ifthehigh-frequencyoscillatorisdisabledforPower Save operation,theoscillatormust be enabledand allowedtostabilizebeforethetransitiontoActivemode. To enablethehigh-frequencyoscillator,clearthe PMMSTCTL.DMC bit. Before clearing the PMMSTCTL.PSM bit, software must poll the PMMSR.MCLKSTB bittodeterminewhen theoscillatorhas stabilized.

16.6.6 Wake-Up TransitiontoActiveMode

A hardware wake-up eventswitchesthe devicedirectlyfrom Power Save, Idle,or Haltmode to Active mode. When a wake-up eventoccurs,theon-chiphardwareperformsthefollowingsteps: 1. ClearsthePMMSTCTL.DMC, PMMCSTCTL.DSC, and PMMPLLnCTL2.DPLLC bits,whichenablethe high-frequencyoscillator,low-frequencyoscillator,and PLL Clocks(ifany were disabled). 2. WaitsforthePMMSR.MCLKSTB and PMMSR.SCLKSTB bitstobecome set.IfeitherofthePLLs were enabledbeforeenteringthelow-powermode, waitsforthecorresponding PMMPLLnCTL2.PLLCLKSTB bitstobecome set. 3. SwitchesthedeviceintoActivemode.

16.6.7 Power Mode SwitchingProtection

The Power Management Module has severalmechanisms toprotectthedevicefrommalfunctionscaused by missingorunstableclocksignals.

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www.ti.com SNOSCW5 –MAY 2013 The PMMSR.MCLKSTB, PMMSR.SCLKSTB, and PMMPLLnCTL2.PLLCLKSTB bitsindicatethe current statusof the high-frequencyoscillator,low-frequencyoscillator,and PLLs, respectively.Softwarecan check the appropriatebitbeforeswitchingto a power mode thatrequiresa specificclock.A set bit indicatesan operating,stableclock.A clearbitindicatesa clockthatisdisabled,notavailable,ornotyet stable. Duringa power mode transition,ifthereisa requesttoswitchtoa mode whichuses a clockwitha clear stabilitybit,theswitchisdelayeduntilthebitissetby thehardware. When thesystem isbuiltwithoutan externalcrystalnetworkforthelow-frequencyclock,Main Clockora PLL Clockisdividedby a prescalertoproducethelow-frequencyclock.Inthissituation,Main Clockis disabledonlyintheHaltmode, and cannotbe disabledforthePower Save orIdlemode. Followingreset,Main ClockdrivesSlow Clockthrougha prescaler.The prescalervalueresultsina Slow Clockrateof32.786.885Hz. NOTE For correctoperationintheabsence ofa low-frequencycrystal,theX2CKI pinmust be tied low(notleftfloating)so thatthehardwarecan detecttheabsence ofthecrystal.

16.7 Power Management Register

Table16-3shows thepower management register. Table16-3.Power Management Register NAME ADDRESS DESCRIPTION PMMSTCTL FF A404h Power Management StateControlRegister

16.7.1 Power Management StateControlRegister(PMMSTCTL)

The PMMSTCTL registeris a byte-wide,read/writeregisterthatcontrolsthe operatingpower mode (Active,Power Save,Idle,orHalt)and enablesordisablesthehigh-frequencyoscillatorinthePower Save and Idlemodes. At reset,theregisterarecleared.The formatoftheregisterisshown below.At reset,the registeriscleared. 7 6 5 4 3 2 1 0 DSC WACK HCCM DMC WBPSM HALT IDLE PSM PSM When thePower Save Mode bitisclear,thesystemisinActivemode. IftheWBPSM bitis clear,writing1 tothePSM bitcausesthedevicetostarttheswitchtoPower Save mode. If theWBPSM bitissetwhen thePSM bitiswrittenwith1,entryintoPower Save mode is delayeduntilexecutionofa WAIT instruction.The PSM bitbecomes setaftertheswitchto Power Save mode iscomplete.The PSM bitcan be clearedby software,and itcan be cleared by hardwarewhen a hardwarewakeup eventisdetected. 0 – DeviceisnotinPower Save mode. 1 – DeviceisinPower Save mode. IDLE The IdleMode bitindicateswhetherthedevicehas enteredIdlemode. IftheWBPSM bitis clearand thedeviceisinPower Save mode, writing1 totheIDLE bitcausesthedeviceto starttheswitchtoIDLE mode. IftheWBPSM bitissetwhen theIDLE bitiswrittenwith1, entryintoIdlemode isdelayeduntilexecutionofa WAIT instruction.The IDLE bitcan be set and clearedby software.Itisalsoclearedby hardwarewhen a hardwarewake-up eventis detected.When set,theIDLE bitoverridesthePSM bit. 0 – DeviceisnotinIdlemode. 1 – DeviceisinIdlemode. Copyright© 2013,Texas InstrumentsIncorporated Power Management Module 101 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com HALT The HaltMode bitindicateswhetherthedeviceisinHaltmode. IftheWBPSM bitisclearand thedeviceisinPower Save mode, writing1 totheHALT bitcausesthedevicetostartthe switchtoHaltmode. IftheWBPSM bitissetwhen theHALT bitiswrittenwith1,entryinto Haltmode isdelayeduntilexecutionofa WAIT instruction.When inHaltmode, thePMM stopsHCLK Clockand thenturnsoffthehigh-frequencyoscillatorand PLLs.The low- frequencyoscillatoralsomay be stoppedinHaltmode by settingthePMMSTCTL.DSC bit. The HALT bitcan be setand clearedby software.Haltmode isexitedby a hardwarewake-up event.When thissignalissethigh,theoscillatorisstarted.Aftertheoscillatorhas stabilized, theHALT bitisclearedby hardware.When set,theHALT bitoverridestheIDLE and PSM bits. 0 – DeviceisnotinHaltmode. 1 – DeviceisinHaltmode. WBPSM When theWaitBeforePower Save Mode bitisclear,a switchfromActivemode toPower Save mode onlyrequiressettingthePSM bit.When theWBPSM bitisset,a switchfrom Activemode toPower Save,Idle,orHaltmode isperformedby settingthePSM, IDLE,or HALT bit,respectively,and thenexecutinga WAIT instruction.Also,iftheDMC orDPLLC bits areset,thehigh-frequencyoscillatororPLLs may be disabledonlyaftera WAIT instructionis executedand thePower Save,Idle,orHaltmode isentered. 0 – Mode transitionsmay occurimmediately. 1 – Mode transitionsaredelayeduntilthenextWAIT instructionisexecuted. DMC The DisableMain Clockbitmay be used todisableMain Clockand thehigh-frequency oscillatorinPower Save and Idlemodes. InActivemode, Main Clockisenabledwithout regardtotheDMC value.InHaltmode, Main ClockisdisabledwithoutregardtotheDMC value.DisablingMain ClockwillalsodisablethePLL Clocks.The DMC bitisclearedby hardwarewhen a hardwarewake-up eventisdetected. 0 – Main ClockisonlydisabledinHaltmode orwhen disabledby theHCC mechanism. 1 – Main ClockisalsodisabledinPower Save and Idlemodes, unlessSlow Clockis generatedfromMain ClockorPLL Clock. HCCM The Hardware ClockControlforMain Clockbitmay be used inPower Save and Idlemodes to disableMain Clockand thehigh-frequencyoscillatorconditionally,dependingon whetherthe BluetoothLLC isinSleepmode. DisablingMain Clockhas theside-effectofdisablingthePLL Clocks.The DMC bitmust be clearforthismechanism tooperate.The HCCM bitis automaticallyclearedwhen thedeviceentersActivemode. 0 – Main ClockisdisabledinPower Save orIdlemode onlyiftheDMC bitisset. 1 – Main ClockisalsodisablediftheBluetoothLLC isidle. WACK The Wake-Up on InterruptAcknowledgebitissettoenablea mode inwhichthesystemwill wake up when an interruptacknowledgeoccurs.Thiscouldbe used inPower Save mode withoutusingtheWAIT instruction,so thatan interruptcouldbe used topower up thesystem quickly,ratherthanneedingthesoftwaretodo it.IftheWACK bitisclear,thenan interrupt acknowledgewillnotcause a wake up froma lowpower mode. 0 – Interruptacknowledgedoes notwake up fromlow-powermode. 1 – Interruptacknowledgewakes up fromlow-powermode. DSC The DisableSlow Clockbitisused todisablethelow-frequencyoscillatorinHaltmode. This bitwouldtypicallybe setformaximum power savings,butthelow-frequencyoscillatoris optimizedforverylowpower so itmay notbe necessarytodisableit.Leavingtheoscillator runningavoidsa start-updelayforthelow-frequencyoscillator.The DSC bitisclearedwhen a hardwarewake-up eventoccurs. 0 – Low-frequencyoscillatorisnotdisabled. 1 – Low-frequencyoscillatorisdisabledwhen Haltmode isentered.

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17 Multi-InputWake-Up

The Multi-InputWake-Up (MIWU) module allowsmost general-purposeI/Oportpins,certainperipheral pins(thatdo notsharefunctionalitywitha GPIO port),and certainperipheraleventstobreakthesystem outofa low-powermode and returntoActivemode. Each MIWU inputcan be programmed toasserta wake-up signalforexitingfrom a low-powermode, and each inputcan be independentlyprogrammed to assertan interruptrequeston any ofeightmaskableinterruptsassignedtotheMIWU module. Eighttypesofregisterscontrolthegenerationofinterruptsand wake-up events,and one registerindicates thestatusofpendinginterruptrequests:

• WKRPNDx — two 32-bitregistersindicatewhichMIWU inputshave detectedrisingedges sincethey were lastcleared(eitherby resetorwritingtoWKCLRx).
• WKFPNDx — two 32-bitregistersindicatewhichMIWU inputshave detectedfallingedges sincethey were lastcleared(eitherby resetorwritingtoWKCLRx).
• WKCLRx — writing1 tobitsineitherofthesetwo 32-bitregistersclearsthecorrespondingbitsinthe WKRPNDx and WKFPNDx registers.The WKCLRx registersarewrite-only.
• WKRENx — two 32-bitregistersholdbitsforenablinga wake-up eventwhen a risingedge isdetected on thecorrespondingMIWU input.
• WKFENx — two 32-bitregistersholdbitsforenablinga wake-up eventwhen a fallingedge isdetected on thecorrespondingMIWU input.
• WKREINx — two 32-bitregistersholdbitsforenablingan interruptwhen a risingedge isdetectedon thecorrespondingMIWU input.
• WKFEINx — two 32-bitregistersholdbitsforenablingan interruptwhen a fallingedge isdetectedon thecorrespondingMIWU input.
• WKICTLx — four32-bitregistersprovidetwo-bitfieldstoselectone offourMIWU interruptchannels availablewhen an enabledinterruptoccurs.MIWU inputs31:0can onlyassertMIWU interrupts3:0, whileMIWU inputs63:32can onlyassertMIWU interrupts7:4.
• WKISTAT — indicatespendingMIWU interrupts. The MIWU module isalwaysactive,includinginHaltmode when alldeviceclocksarestopped.Therefore, detectingan externaltriggerconditionand settingbitsinWKRPNDx and WKFPNDx do not requirean activeHCLK ClockorPCLK Clock. Copyright© 2013,Texas InstrumentsIncorporated Multi-InputWake-Up 103 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

MIWU Interrupt 3:0 WKISTA T3:0 DS330 De- code De- code WKICTL1/WKICTL2 WUI32 WUI63 MIWU Interrupt 7:4 WKISTA T7:4 De- code De- code WKICTL3/WKICTL4 Rising Edge Falling Edge Interrupt WKREN1/WKREN2 WKFEN1/WKFEN2 Rising Edge Wake Up Falling Edge Wake Up CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure17-1.Multi-InputWake-Up Module Block Diagram Table17-1liststhesourcesconnectedtotheMIWU inputs.A sourcewhichisa GPIO portpincannotbe used unlessitisenabledforuse as an input,eitherby enablingan alternatefunctioninwhich thepinis used as an inputorby settingitscorrespondingbitina PxIEN register.Ifthisisnotdone,theinputlogic forthepinisdisabled. Table17-1.MIWU Sources MIWU CHANNEL SOURCE MIWU CHANNEL SOURCE WUI0 PE0 WUI32 PF0 WUI1 PE1 WUI33 PF1 WUI2 PE2 WUI34 PF2 WUI3 PE3 WUI35 PF3 WUI4 PE4 WUI36 PF4 WUI5 PE5 WUI37 PF5 WUI6 PE6 WUI38 PF6

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www.ti.com SNOSCW5 –MAY 2013 Table17-1.MIWU Sources (continued) MIWU CHANNEL SOURCE MIWU CHANNEL SOURCE WUI7 PE7 WUI39 PF7 WUI8 PE8 WUI40 PF8 WUI9 PE9 WUI41 PF9 WUI10 PE10 WUI42 PF10 WUI11 PE11 WUI43 PF11 WUI12 PE12 WUI44 PF12 WUI13 PE13 WUI45 PF13 WUI14 PE14 WUI46 PF14 WUI15 PE15 WUI47 PF15 WUI16 PG0 WUI48 PH0 WUI17 PG1 WUI49 PH1 WUI18 PG2 WUI50 PH2 WUI19 PG3 WUI51 DSP WUI20 PG4 WUI52 ACCESS.bus 0 WUI21 PG5 WUI53 A/D Converter WUI22 PG6 WUI54 BluetoothLLC WUI23 PG7 WUI55 Reserved WUI24 PG8 WUI56 USB WUI25 PG9 WUI57 Reserved WUI26 PG10 WUI58 ACCESS.bus 1 WUI27 PG11 WUI59 Reserved WUI28 PG12 WUI60 TWM T0OUT WUI29 PG12 WUI61 RTC RTCEVT3 WUI30 PG14 WUI62 RTC RTCEVT2 WUI31 PG15 WUI63 RTC RTCEVT1

17.1 Multi-InputWake-Up Registers

Table17-2liststheMIWU registers. Table17-2.Multi-InputWake-Up Registers NAME ADDRESS DESCRIPTION WKRPND1 FF C020h RisingEdge PendingRegister1 WKRPND2 FF C024h RisingEdge PendingRegister2 WKFPND1 FF C030h FallingEdge PendingRegister1 WKFPND2 FF C034h FallingEdge PendingRegister2 WKCLR1 FF C040h ClearPendingRegister1 WKCLR2 FF C044h ClearPendingRegister2 WKREN1 FF C000h RisingEdge EnableRegister1 WKREN2 FF C004h RisingEdge EnableRegister2 WKFEN1 FF C010h FallingEdge EnableRegister1 WKFEN2 FF C014h FallingEdge EnableRegister2 WKRIEN1 FF C050h RisingEdge InterruptEnableRegister1 WKRIEN2 FF C054h RisingEdge InterruptEnableRegister2 WKFIEN1 FF C060h FallingEdge InterruptEnableRegister1 WKFIEN2 FF C064h FallingEdge InterruptEnableRegister2 WKICTL1 FF C070h InterruptControlRegister1 Copyright© 2013,Texas InstrumentsIncorporated Multi-InputWake-Up 105 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table17-2.Multi-InputWake-Up Registers(continued) NAME ADDRESS DESCRIPTION WKICTL2 FF C074h InterruptControlRegister2 WKICTL3 FF C078h InterruptControlRegister3 WKICTL4 FF C07Ch InterruptControlRegister4 WKISTAT FF C090h InterruptStatusRegister

17.1.1 RisingEdge Pending Registern (WKRPNDn)

The WKRPNDn registersare 32-bit,read/writeregistersthatindicatewhethera risingedge has been detectedon thecorrespondingMIWU input.Bits31:0ofWKRPND1 correspondtoMIWU inputs31:0Bits 31:0ofWKRPND2 correspondtoMIWU inputs63:32.Writing1 tobitsintheWKCLRn registersclearsthe correspondingbitsintheWKRPNDn registers.The WKRPNDn registersareclearedatreset.The register formatisshown below. 31 0 WKRPD WKRPD The Wake-Up RisingEdge Pendingbitsindicatewhethera risingedge has occurredon the correspondingMIWU inputssincethebitswere lastcleared. 0 – No risingedge occurred. 1 – Risingedge occurred.

17.1.2 FallingEdge Pending Registern (WKFPNDn)

The WKFPNDn registersare 32-bit,read/writeregistersthatindicatewhethera fallingedge has been detectedon thecorrespondingMIWU input.Bits31:0ofWKFPND1 correspondtoMIWU inputs31:0Bits 31:0ofWKFPND2 correspondtoMIWU inputs63:32.Writing1 tobitsintheWKCLRn registersclearsthe correspondingbitsintheWKFPNDn registers.The WKFPNDn registersareclearedatreset.The register formatisshown below. 31 0 WKFPD WKFPD The Wake-Up FallingEdge Pendingbitsindicatewhethera fallingedge has occurredon the correspondingMIWU inputssincethebitswere lastcleared. 0 – No fallingedge occurred. 1 – Fallingedge occurred.

17.1.3 ClearPending Registern (WKCLRn)

The WKCLRn registersare 32-bit,write-onlyregistersthatclearbitsinthe WKRPNDn and WKFPNDn registers.Writing1 toa WKCLRn bitclearsthecorrespondingbitineach oftheotherregisters.WKCLR1 clearsbitsinWKRPND1 and WKFPND1, and WKCLR2 clearsbitsinWKRPND2 and WKFPND2. The registerformatisshown below. 31 0 WKCL

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www.ti.com SNOSCW5 –MAY 2013 WKCL The Wake-Up Clearbitsareused toselectivelyclearbitsinWKRPNDn and WKFPNDn. 0 – Writing0 has no effect. 1 – Writing1 clearsthecorrespondingbitpositioninWKRPNDn and WKFPNDn.

17.1.4 RisingEdge Enable Registern (WKRENn)

The WKRENn registersare32-bit,read/writeregistersthatenablea wake-up eventwhen a risingedge is detectedon thecorrespondingMIWU input.Bits31:0ofWKREN1 correspondtoMIWU inputs31:0Bits 31:0 of WKREN2 correspondto MIWU inputs63:32.The WKRENn registersare clearedat reset.The registerformatisshown below. 31 0 WKREN WKREN The Wake-Up RisingEdge Enablebitsenablea wake-up eventwhen a risingedge occurson thecorrespondingMIWU input. 0 – No wake-up eventenabled. 1 – Wake-up eventenabled.

17.1.5 FallingEdge Enable Registern (WKFENn)

The WKFENn registersare32-bit,read/writeregistersthatenablea wake-up eventwhen a fallingedge is detectedon thecorrespondingMIWU input.Bits31:0ofWKFEN1 correspondtoMIWU inputs31:0Bits 31:0 of WKFEN2 correspondto MIWU inputs63:32.The WKFENn registersare clearedat reset.The registerformatisshown below. 31 0 WKFEN WKFEN The Wake-Up FallingEdge Enablebitsenablea wake-up eventwhen a fallingedge occurs on thecorrespondingMIWU input. 0 – No wake-up eventenabled. 1 – Wake-up eventenabled.

17.1.6 RisingEdge InterruptEnable Registern (WKRIENn)

The WKRIENn registersare 32-bit,read/writeregistersthatenablean interruptwhen a risingedge is detectedon thecorrespondingMIWU input.Bits31:0ofWKRIEN1 correspondtoMIWU inputs31:0Bits 31:0ofWKRIEN2 correspondtoMIWU inputs63:32.The WKRIENn registersare clearedatreset.The registerformatisshown below. 31 0 WKRIEN WKRIEN The RisingEdge InterruptEnablebitsenablean interruptwhen a risingedge occurson the correspondingMIWU input. 0 – No interruptenabled. 1 – Interruptenabled.

17.1.7 FallingEdge InterruptEnable Registern (WKFIENn)

The WKFIENn registersare 32-bitregisters,read/writethatenablean interruptwhen a fallingedge is detectedon thecorrespondingMIWU input.Bits31:0ofWKFIEN1 correspondtoMIWU inputs31:0Bits 31:0 of WKFIEN2 correspondto MIWU inputs63:32.The WKFIENn registersare clearedat reset.The registerformatisshown below. Copyright© 2013,Texas InstrumentsIncorporated Multi-InputWake-Up 107 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 31 0 WKFIEN WKFIEN The FallingEdge InterruptEnablebitsenablean interruptwhen a fallingedge occurson thecorrespondingMIWU input. 0 – No interruptenabled. 1 – Interruptenabled.

17.1.8 InterruptControlRegistern (WKICTLn)

The WKICTLn registersare 32-bit,read/writeregistersthatprovide2-bitfieldswhich selectthe MIWU interruptchannelsused by theassociatedMIWU channels.Each MIWU inputcan onlyactivateone offour interruptchannels.MIWU inputs31:0 can onlyactivateMIWU interruptchannels3:0,and MIWU inputs 63:32can onlyactivateMIWU interruptchannels7:4. The WKICTL1 registerselectsinterruptsforMIWU inputs15:0,WKICTL2 selectsinterruptsforMIWU inputs31:16,WKICTL3 selectsinterruptsforinputs47:32,and WKICTL4 selectsinterruptsforinputs 63:48.At reset,theWKICTLn registersarecleared.The registerformatofWKICTL1 isshown below (the otherregistershave a similarformat). WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 WKINTR The InterruptRequestfieldsselectwhichoffouravailableMIWU interruptchannelsare activatedforthecorrespondingMIWU input. 00 – SelectsMIWU interruptchannel0 or4. 01 – SelectsMIWU interruptchannel1 or5. 10 – SelectsMIWU interruptchannel2 or6. 11 – SelectsMIWU interruptchannel3 or7.

17.1.9 InterruptStatusRegister(WKISTAT)

The WKISTAT registerisa 32-bitread-onlyregisterthatindicatesthe statusof the 8 MIWU interrupt channels.No interruptchannelsareactivefollowingreset.The registerformatisshown below. 31 8M M 7 0 Reserved WKIST WKIST The InterruptStatusbitsindicatewhichMIWU interruptchannelsarecurrentlyassertingan interruptrequest. 0 – No interruptrequestisbeingasserted. 1 – An interruptrequestisbeingasserted.

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18 Input/OutputPorts

The CP3SP33 has 64 software-configurablegeneral-purposeI/Opins(36 on the FBGA-144 package), organizedintofourports,named PortE, PortF,PortG, and PortH. All16 pinson PortsE, F,and G and threepins on 8-bitPort H have independentlyprogrammable MIWU channels,which give them the capabilitytointerrupttheCPU and wake up thesystemfromlow-powermodes. In additionto theirgeneral-purposeI/Ofunction,most of the pinson PortsE, F, and G have alternate functionsforuse withon-chipperipheralmodules such as the UARTs and timers.Architecturally,there may be two alternatefunctionsfora portpin,and softwaremust specifywhichfunctiontoselect(A orB), even when only one functionis implemented.The alternatefunctionsof allI/O pins are shown in Table18-2.To avoidglitches,softwareshouldfirstselectthealternatefunction,thenenablethealternate function,and finallyinitializethemodule whichuses thealternatefunction. The I/O pin characteristicsare fullyprogrammable.Each pin can be configuredto operateas a TRI- STATE output,push-pulloutput,inputwithweak pullup,inputwithweak pull-down,or high-impedance input.Differentpinswithinthesame portcan be individuallyconfiguredtooperateindifferentmodes. Figure18-1shows theI/Oportpinlogic.The registerbits,multiplexers,and buffersallowtheportpintobe configuredintothevariousoperatingmodes. To reduce power consumption,inputbuffersconfiguredforgeneral-purposeI/Oare onlyenabledwhen theyare read.When configuredforan alternatefunction,theinputbuffersare enabledcontinuously.To minimizepower consumption,inputsignalstoenabledbuffersmust be heldwithin0.2voltsoftheVCC or GND voltage. The electricalcharacteristicsand drivecapabilitiesof the inputand outputbuffersare describedin Section36. Copyright© 2013,Texas InstrumentsIncorporated Input/OutputPorts 109 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Alt. Source Alt. Function Pull Enable Pull Direction Direction Interrupt Enable Register Data Out Register Direction Register Pull Enable Register Alt. A Device Data Output Alt. B Device Direction Data In Read Strobe Alt. A Data Input Alternate Function Register Alternate Source Register Data Input Alt. B Data Input Alt. B Device Data Output Alt. A Device Direction MIWU Channel Pull Direction Register Data Out Flip-Flop Interrupt En DS400 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure18-1.I/OPortPin Logic

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18.1 Open-Drain Operation

A portpincan be configuredtooperateas an invertingopen-drainoutputbuffer.To do this,softwaremust clearthebitinthePxDOUT registerand use thePxDIR bittosetthevalueoftheportpin.Inopen-drain operation,theoutputbufferistoggledbetween drivinglogiclow and TRI-STATE (high-impedancemode). Thisisachievedby usingthePxDIR registertoswitchbetween drivinga low outputand configuringthe portpinas an input.Ifdesired,theinternalweak pulluporpulldowncan be enabledtopullthesignaltoa harmlessstatewhen theoutputbufferisinTRI-STATE mode.

18.2 PortRegisters

Each porthas a setofmemory-mapped registers:

• PxDIR— specifieswhether the portisan inputor output,exceptwhen usingan alternatefunction. When an alternatefunctionisused,peripheralcontrolsportdirection.
• PxDIN— indicatesthestateson theportpins.
• PxDOUT — holds data drivenon the portpins,when the portis configuredas an outputand no alternatefunctionisused.When an alternatefunctionisused,theperipheraldevicecontrolsthedata output.This registeralsospecifiesstateswhich cause assertionof interrupts,when interruptsare enabled(seePxIEN register).
• PxIEN— enablesan interruptwhen thestateon theportpinmatches thestateinPxDOUT register.
• PxALT — enablestheportalternatefunction.
• PxALTS — selectsbetween alternatefunctions(A and B)
• PxWPU — enablesa weak pulluporpulldown
• PxPDR — selectsthepullup/pulldowndirection. Table18-1.PortRegisters NAME ADDRESS DESCRIPTION PEDIR FF C404h PortE DirectionRegister PEDIN FF C408h PortE Data InputRegister PEDOUT FF C40Ch PortE Data OutputRegister PEIEN FF C41Ch PortE InterruptEnableRegister PEALT FF C400h PortE AlternateFunctionRegister PEALTS FF C418h PortE AlternateFunctionSourceRegister PEWPU FF C410h PortE Weak Pullup/PulldownEnableRegister PEPDR FF C420h PortE Weak Pullup/PulldownDirectionRegister PFDIR FF C804h PortF DirectionRegister PFDIN FF C808h PortF Data InputRegister PFDOUT FF C80Ch PortF Data OutputRegister PFIEN FF C81Ch PortF InterruptEnableRegister PFALT FF C800h PortF AlternateFunctionRegister PFALTS FF C818h PortF AlternateFunctionSourceRegister PFWPU FF C810h PortF Weak Pullup/PulldownEnableRegister PFPDR FF C820h PortF Weak Pullup/PulldownDirectionRegister PGDIR FF 6404h PortG DirectionRegister PGDIN FF 6408h PortG Data InputRegister PGDOUT FF 640Ch PortG Data OutputRegister PGIEN FF 641Ch PortG InterruptEnableRegister PGALT FF 6400h PortG AlternateFunctionRegister PGALTS FF 6418h PortG AlternateFunctionSourceRegister PGWPU FF 6410h PortG Weak Pullup/PulldownEnableRegister PGPDR FF 6420h PortG Weak Pullup/PulldownDirectionRegister Copyright© 2013,Texas InstrumentsIncorporated Input/OutputPorts 111 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table18-1.PortRegisters(continued) NAME ADDRESS DESCRIPTION PHDIR FF CC04h PortH DirectionRegister PHDIN FF CC08h PortH Data InputRegister PHDOUT FF CC0Ch PortH Data OutputRegister PHIEN FF CC1Ch PortH InterruptEnableRegister PHALT FF CC00h PortH AlternateFunctionRegister PHALTS FF CC18h PortH AlternateFunctionSourceRegister PHWPU FF CC10h PortH Weak Pullup/PulldownEnableRegister PHPDR FF CC20h PortH Weak Pullup/PulldownDirectionRegister Inthedescriptionsoftheportregisters,thelower-caseletter“x”representstheportdesignation,eitherE, F, G, or H. For example,“PxDIR register” means any one oftheportdirectionregisters:PEDIR, PFDIR, PGDIR, orPHDIR. Alloftheportregistersare 16-bitread/writeregisters,exceptfortheportdatainputregisters,which are read-onlyregisters.Each registerbitcontrolsthe functionof the correspondingportpin.For example, PGDIR.2 (bit2 ofthePGDIR register)controlsthedirectionofportpinPG2.

18.2.1 PortDirectionRegister(PxDIR)

The PxDIR registerselectswhether the correspondingportpin is used forinputor output.A reset operationclearstheportdirectionregisters,whichinitializesthepinsas inputs. 15 0M PxDIR PxDIR The PortDirectionbitsselectthedirectionofthecorrespondingportpin. 0 – Input. 1 – Output.

18.2.2 PortData InputRegister(PxDIN)

The PxDIN registerisa read-onlyregisterthatreturnsthecurrentstateon each portpin.The CPU can readthisregisteratany time,even when thepinisconfiguredas an output. 15 0M PxDIN PxDIN The PortData Inbitsindicatethestateon thecorrespondingportpin. 0 – Pinislow. 1 – Pinishigh.

18.2.3 PortData Output Register(PxDOUT)

The PxDOUT registerholdsthedatatobe drivenon outputportpins.When thepinsare configuredas outputsand no alternatefunctionisenabled,writingtothisregisterchanges theoutputvalue.Reading the registerreturnsthelastvaluewrittentotheregister. When an interruptisenabledthroughthePxIEN register,thePxDOUT registerspecifiesthesignallevel whichassertstheinterrupt. A warm reset(softwareresetorwatchdogreset)leavestheregistercontentsunchanged.Atpower-up,the PxDOUT registerscontainundefineddata.

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www.ti.com SNOSCW5 –MAY 2013 15 0M PxDOUT PxDOUT The PortData Out bitsholdthedatatobe drivenon pinsconfiguredas outputsingeneral- purposeI/Omode. When interruptsareenabledinthePxIEN register,thePxDOUT bits specifythesignallevelswhichassertinterrupts. 0 – Driveoutputpinlow. 1 – Driveoutputpinhigh.

18.2.4 PortInterruptEnable Register(PxIEN)

The PxIEN registersenabletheportinputlogicso thatthecorrespondingpinscan be used as wake-up inputstotheMIWU. All16 pinson PortsE, F, and G and threepinson 8-bitPortH have independently programmable MIWU channels,which givethem the capabilityto interruptthe CPU and wake up the system from low-powermodes. Ifan alternatefunctionisenabledwhich uses a pinas an input,theport inputlogicisalreadyenabled,so itisnotrequiredtosetthecorrespondingbitinitsPxIEN register.The PxDOUT registerspecifiesthesignallevelwhich assertsthewake-up signaltotheMIWU. At reset,the registerisclearedto0000h. 15 0M PxIEN PxIEN The PortInterruptEnablebitsenabletheportinputlogicso thatthecorrespondingportpins can be used as MIWU inputs. 0 – Interruptdisabled. 1 – Interruptenabled.

18.2.5 PortAlternateFunctionRegister(PxALT)

The PxALT registerscontrolwhethertheportpinsare used forgeneral-purposeI/Oor fortheiralternate function.Each portpincan be controlledindependently. A clearbitinthealternatefunctionregistercauses thecorrespondingpintobe used forgeneral-purpose I/O.Inthisconfiguration,theportpinoutputbufferiscontrolledby thedirectionregister(PxDIR)and the dataoutputregister(PxDOUT). The inputbufferisvisibletosoftwareas thedatainputregister(PxDIN). A set bitin the alternatefunctionregister(PxALT) causes the correspondingpin to be used forits peripheralI/Ofunction.When the alternatefunctionisselected,the portdirectionand outputdata are controlledby theperipheraldevice. A resetclearstheportalternatefunctionregisters,whichinitializesthepinsas general-purposeI/Oports. 15 0M PxALT PxALT The PortAlternateFunctionbitscontrolwhetherthecorrespondingportpinsaregeneral- purposeI/Oportsorareused intheiralternatefunctionby an on-chipperipheral. 0 – General-purposeI/Oselected. 1 – Alternatefunctionselected. Copyright© 2013,Texas InstrumentsIncorporated Input/OutputPorts 113 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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18.2.6 PortAlternateFunctionSelectRegister(PxALTS)

The PxALTS registerselectsbetween two peripheraldevicesavailableforthealternatefunctionofa port pin.These bitsareignoredunlessthecorrespondingPxALT bitsareset.Each portpincan be controlled independently. 15 0M PxALTS PxALTS The AlternateFunctionSelectbitsselectamong two alternatefunctions.Table18-2shows themapping ofthePxALTS bitstothealternatefunctions.Unused PxALTS bitsmust be clear. Table18-2.AlternateFunctionSelect PxALTS = 0 PxALTS = 1 PxALTS = 0 PxALTS = 1PORT PIN PORT PIN(DeviceA) (DeviceB) (DeviceA) (DeviceB) PE0 USART0 RXD0 TIO0_1 PG0 I2SCLK Reserved PE1 USART0 TXD0 Reserved PG1 I2SWS Reserved PE2 USART0 RTS0 TIO0_3 PG2 I2SSDI Reserved PE3 USART0 CTS0 Reserved PG3 I2SSDO Reserved PE4 USART0 CKX0 TIO0_2 PG4 MSK1 Reserved PE5 TA0 NMI PG5 MDIDO1 Reserved PE6 CAN1RX Reserved PG6 MDODI1 Reserved PE7 CAN1TX Reserved PG7 MWCS1 TA1 PE8 MSK Reserved PG8 SRFS UART3 RTS3 PE9 MDIDO0 Reserved PG9 SCK DIGMIC1 PE10 MDODI0 Reserved PG10 SFS TCIO1 PE11 MWCS0 TIO0_7 PG11 STD DIGMIC2 PE12 SCL0 TIO0_5 PG12 SRD Reserved PE13 IDPULLUP TIO1_1 PG13 SRCLK UART3 CTS3 PE14 DRVVBUS TIO1_3 PG14 UART3 RXD3 TB1 PE15 IDDIG TIO1_5 PG15 UART3 TXD3 Reserved PF0 RFSYNC Reserved PH0 TIO1_4 Reserved PF1 SCLK Reserved PH1 SDA0 TIO1_6 PF2 SDAT Reserved PH2 CAN0RX TIO1_7 PF3 SLE Reserved PH3 CAN0TX TIO1_8 PF4 BTSEQ1 Reserved PH4 Reserved Reserved PF5 BTSEQ2 Reserved PH5 Reserved Reserved PF6 BTSEQ3 Reserved PH6 Reserved Reserved PF7 ASYNC TB0 PH7 Reserved Reserved PF8 UART1 RXD1 TIO0_4 PH8 Reserved Reserved PF9 UART1 TXD1 Reserved PH9 Reserved Reserved PF10 UART1 RTS1 TIO0_6 PH10 Reserved Reserved PF11 UART1 CTS1 Reserved PH11 Reserved Reserved PF12 UART2 RXD2 TIO0_8 PH12 Reserved Reserved PF13 UART2 TXD2 Reserved PH13 Reserved Reserved PF14 UART2 RTS2 TIO1_2 PH14 Reserved Reserved PF15 UART2 CTS2 Reserved PH15 Reserved Reserved

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18.2.7 PortWeak Pullup/PulldownEnable Register(PxWPU)

The PxWPU registercontrolswhethera weak pullupor pulldowndeviceisenabledon theoutputbuffer. The pullupor pulldowndevice,ifenabledby theregisterbit,operateswhenever theportoutputbufferis disabled(TRI-STATE mode).Enablingthepulluporpulldowndeviceisunaffectedby whethertheportpin isinGPIO or alternatefunctionmode. A resetoperationclearsthePxWPU registers,which disablesall pullupsand pulldowns. 15 0M PxWPU PxWPU The Weak Pullup/PulldownEnablebitscontrolwhethertheweak pullup/pulldowndeviceis enabled. 0 – Weak pullup/pulldowndisabled. 1 – Weak pullup/pulldownenabled.

18.2.8 PortWeak Pullup/PulldownDirectionRegister(PxPDR)

The PxPDR registerselectswhethera weak pullupor pulldowndeviceisenabledon theoutputbuffer. The pulluporpulldowndevice,ifenabledinthePxWPU register,operateswhenever theportoutputbuffer isdisabled(TRI-STATE mode). The PxPDR bitsare ignoredunlessthe correspondingPxWPU bitsare set.Atreset,theregistersareinitializedtoFFFFh, whichselectspullups. 15 0M PxPDR PxPDR The Pullup/PulldownDirectionbitsselectbetween a pullupand a pulldowndevice. 0 – Pulldownselected. 1 – Pullupselected.

19 BluetoothController

The integratedhardware BluetoothLower LinkController(LLC) compliesto the BluetoothSpecification Version1.2and integratesthefollowingfunctions:

• 7K-bytededicatedBluetoothdataRAM
• 1K-bytededicatedBluetoothsequencerRAM
• SupportofallBluetooth1.2packettypes
• Supportforfastfrequencyhoppingof1600 hops/s
• Access code correlationand slottimingrecoverycircuit
• Power Management ControlLogic
• BlueRF-compatibleinterfacetoconnectwithNational’s LMX5252 and otherRF transceiverchips For a detaileddescriptionof the interfaceto the LMX5252, consultthe LMX5252 data sheetwhich is availablefrom the Texas Instrumentswirelessgroup.Nationalprovidessoftwarelibrariesforusingthe BluetoothLLC. DocumentationforthesoftwarelibrariesisalsoavailablefromNationalSemiconductor.

19.1 RF Interface

The CP3SP33 interfacestotheLMX5251 orLMX5252 radiochipsthoughtheRF interface. Figure19-1shows theinterfacebetween theCP3SP33 and theLMX5251 radiochip. Copyright© 2013,Texas InstrumentsIncorporated BluetoothController 115 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

RFDA TA BBDA TA_1 PG2/BTSEQ1 BPKTCTL PG3/SCLK BDCLK PG4/SDA T BDDA TA PG1/RFCE BXTLEN IOVCC VCC +2.8V PG5/SLE BDEN# DS332 CP3SP33 LMX5251 CLKIN BBP_CLOCK RFDA TA TX_RX_DA TA PG0/RFSYNC TX_RX_SYNC PG3/SCLK CCB_CLOCK PG4/SDA T CCB_DA TA PG1/RFCE CE IOVCC VDD_DIG_IN VCC PG5/SLE CCB_LA TCH DS331 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure19-1.LMX5251 Interface Figure19-2shows theinterfacebetween theCP3SP33 and theLMX5252 radiochip. Figure19-2.LMX5252 Interface The CP3SP33 implementsa BlueRF-compatibleinterface,which may be used withotherRF transceiver chips.

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19.1.1 RF InterfaceSignals

The RF interfacesignalsaregroupedas follows:

• Modem Signals(CLKIN,RFDATA, and RFSYNC)
• ControlSignal(RFCE)
• SerialInterfaceSignals(SCLK, SDAT, and SLE)
• BluetoothSequencerStatusSignals(BTSEQ1, BTSEQ2, and BTSEQ2) Softwaremust enablethealternatefunctionsoftheRF interfacesignalstoallowthem tobe controlledby theBluetoothmodule. 19.1.1.1CLKIN The CLKIN pinistheinputsignalforthe12-MHz clocksignal.The radiochipuses thissignalinternallyas the12× oversamplingclockand providesitexternallytotheCP3SP33 foruse as theMain Clock. 19.1.1.2RFDATA The RFDATA signalisthemultiplexedBluetoothdatareceiveand transmitsignal.The dataisprovidedat a bitrateof1 Mbit/swith12× oversampling,synchronizedtothe12 MHz CLKIN. The RFDATA signalisa dedicatedRF interfacepin.Thissignalisdriventoa logichighlevelafterreset. 19.1.1.3RFSYNC In receivemode (datadirectionfrom the radiochipto the CP3SP33), the RFSYNC signalactsas the frequencycorrection/DCcompensationcircuitcontroloutputto the radiochip.The RFSYNC signalis drivenlow throughoutthecorrelationphase and drivenhighwhen synchronizationtothereceivedaccess code isachieved. Intransmitmode (datadirectionfromtheCP3SP33 totheradiochip),theRFSYNC signalenablestheRF outputoftheradiochip.When theRFSYNC pinisdrivenhigh,theRF transmittercircuitoftheradiochip isenabled,correspondingtothesettingsofthepower controlregisterintheradiochip The RFSYNC signalisthealternatefunctionofthegeneral-purposeI/OpinPG0. At reset,thispinisin TRI-STATE mode. Softwaremust enablethe alternatefunctionof the PG0 pinto givecontrolover this signaltotheRF interface. 19.1.1.4RFCE The RFCE signalisthechipenableoutputtotheexternalRF chip.When theRFCE signalisdrivenhigh, theRF chippower iscontrolledby thesettingsofitspower controlregisters.When theRFCE signalis drivenlow,the RF chip is powered-down. However, the serialinterfaceis stilloperationaland the CP3SP33 can stillaccesstheRF chipinternalcontrolregisters. The RFCE signalisthealternatefunctionofthegeneral-purposeI/OpinPG1. At reset,thispinisinTRI- STATE mode. Softwaremust enablethealternatefunctionofthePG1 pintogivecontroloverthissignal totheRF interface. During Bluetoothpower-down phases, the CP3SP33 providesa mechanism to reduce the power consumptionofan externalRF chipby drivingtheRFCE signaloftheRF interfacetoa logiclow level. This featureis availablewhen the Power Management Module of the CP3SP33 has enabled the Hardware ClockControlmechanism. (However,thecurrentversionoftheradiochipdoes notimplementa power-reductionmode.) 19.1.1.5SCLK The SCLK signalistheserialinterfaceshiftclockoutput.The CP3SP33 alwaysactsas themasterofthe serialinterfaceand thereforealwaysprovidestheshiftclock.The SCLK signalisthealternatefunctionof the general-purposeI/OpinPG3. At reset,thispinisinTRI-STATE mode. Softwaremust enablethe alternatefunctionofthePG3 pintogivecontroloverthissignaltotheRF interface. Copyright© 2013,Texas InstrumentsIncorporated BluetoothController 117 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 19.1.1.6SDAT The SDAT signalisthemultiplexedserialdatareceiveand transmitpathbetween theradiochipand the CP3SP33. The SDAT signalisthealternatefunctionofthegeneral-purposeI/OpinPG4. At reset,thispinisinTRI- STATE mode. Softwaremust enablethealternatefunctionofthePG4 pintogivecontroloverthissignal totheRF interface. SLE The SLE pinistheserialloadenableoutputoftheserialinterfaceoftheCP3SP33. Duringwriteoperations(totheradiochipregisters),thedatareceivedby theshiftregisteroftheradiochip iscopiedintotheaddressregisteron thenextrisingedge ofSCLK aftertheSLE signalgoes high. Duringreadoperations(readfromtheregisters),theradiochipreleasestheSDAT lineon thenextrising edge ofSCLK aftertheSLE signalgoes high SLE isthealternatefunctionofthegeneral-purposeI/OpinPG5. At reset,thispinisinTRI-STATE mode. Softwaremust enablethe alternatefunctionof the PG5 pinto givecontrolover thissignalto the RF interface. 19.1.1.7BTSEQ[3:1] The BTSEQ[3:1]signalsindicateinternalstatesoftheBluetoothsequencer,whichareused forinterfacing tosome externaldevices.

19.2 SerialInterface

The radiochipregisterset can be accessed by the CP3SP33 throughthe serialinterface.The serial interfaceuses threepinsoftheRF interface:SDAT, SCLK, and SLE. The serialinterfaceoftheCP3SP33 alwaysoperatesas themaster,providingtheshiftclock(SCLK) and loadenable(SLE) signaltotheradiochip.The radiochipalwaysactsas theslave. A 25-bitshiftprotocolisused to performread/writeaccesses to the radiochipinternalregisters.The completeprotocoliscomprisedofthefollowingsections:

• 3-bitHeader Field
• Read/WriteBit
• 5-bitAddressField
• 16-bitData Field Header The 3-bitheadercontainsthefixeddata101b (exceptforFastWriteOperations). Read/WriteBit The headerisfollowedby theread/writecontrolbit(R/W).IftheRead/Writebitisclear,a writeoperation isperformedand the16-bitdataportioniscopiedintotheaddressedradiochipregister. Address The addressfieldisused toselectone oftheradiochipinternalregisters. Data The datafieldisused totransferdatatoorfroma radiochipregister.The timingismodifiedforreads,to transfercontroloverthedatasignalfromtheCP3SP33 totheradiochip. Figure19-3shows theserialinterfaceprotocolformat. 24 22 21 20 16 15 0 Header[2:0] R/W Address[4:0] Data[15:0] Figure19-3.SerialInterfaceProtocolFormat

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www.ti.com SNOSCW5 –MAY 2013 Data istransferredon theserialinterfacewiththemost significantbit(MSB) first. WriteOperation When theR/W bitisclear,the16 bitsofthedatafieldareshiftedoutoftheCP3SP33 on thefallingedge ofSCLK. Data issampled by theradiochipon therisingedge ofSCLK. When SLE ishigh,the16-bitdata are copied intothe radiochip registeron the next risingedge of SCLK. The data is loaded in the appropriateradiochipregisterdependingon thestateofthefouraddressbits,Address[4:0].Figure19-4 shows thetimingforthewriteoperation. Figure19-4.SerialInterfaceWriteTiming Copyright© 2013,Texas InstrumentsIncorporated BluetoothController 119 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

D0D1D6D7D8D9D10D11D12A0A1A2 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Read Operation When theR/W bitisset,dataisshiftedoutoftheradiochipon therisingedge ofSCLK. Data issampled by theCP3SP33 on thefallingedge ofSCLK. On receptionoftheread command (R/W = 1),theradio chiptakescontroloftheserialinterfacedataline.The received16-bitdataisloadedby theCP3SP33 after thefirstfallingedge ofSCLK when SLE ishigh.When SLE ishigh,theradiochipreleasestheSDAT line againon the nextrisingedge of SCLK. The CP3SP33 takescontrolof the SDAT lineagainafterthe followingrisingedge ofSCLK. Which radiochipregisterisread,depends on thestateofthefouraddress bits,Address[4:0].The transferis always 16 bits,withoutregardto the actualsizeof the register. Unimplementedbitscontainundefineddata.Figure19-5shows thetimingforthereadoperation. Figure19-5.SerialInterface16-bitFast-WriteTiming Figure19-6.SerialInterface8-bitFast-WriteTiming 32-BitWriteOperation On theLMX5252, a 32-bitregisterisloadedby writingtothesame registeraddresstwice.The firstwrite loadsthehighword (bits31:16),and thesecond writeloadsthelow word (bits15:0).The two writesmust be separatedby atleasttwo clockcycles.Fora 4-MHz clock,theminimum separationtimeis500 ns. The valuereadfroma 32-bitregisterisa countervalue,notthecontentsoftheregister.The countervalue indicateswhichwords have been written.Ifthehighword has been written,thecounterreadsas 0000h.If bothwords have been written,thecounterreadsas 0001h.The valuereturnedby readinga 32-bitregister isindependentofthecontentsoftheregister. Figure19-7and Figure19-8show thetimingfor32-bitregisterwritingand reading.

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500 ns D16D31A0A1A2A3A4RH0H1H2 D0D15A0A1A2A3A4RH0H1H2 SLE SCLK SDA T DS322 >500 ns D0D14D15A0A1A2A3A4WH0H1H2D16D30D31A0A1A2A3A4WH0H1H2 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure19-7.32-BitWriteTiming Figure19-8.32-BitRead Timing An example ofa 32-bitwriteisshown inTable40.Inthisexample,the32-bitvalueFFFF DC04h iswritten to registeraddress 0Ah. In cycle1, the high word (FFFFh) iswritten.In the firstpartof cycle2, the CP3SP33 drivestheheader,R/W bit,and registeraddressfora readcycle.Inthesecond partofcycle2, theLMX5252 drivesthecountervalue.The countervalueis0,whichindicatesone word has been written. Incycle3,thelow word (DC04h) iswritten.Inthefirstpartofcycle4,theCP3SP33 drivestheheader, R/W bit,and registeraddressfora read cycle.In the second partof cycle4, the LMX5252 drivesthe countervalue.The countervalueis1,whichindicatestwo words have been written. Table19-1.Example of32-BitWritewithInterleavedReads CYCLE SERIAL DATA ON SDAT DESCRIPTION 1 101 0 01010 1111111111111111 Writecycledrivenby CP3SP33. Data isFFFFh. Addressis0Ah. 2 101 1 01010 Firstpartofreadcycledrivenby CP3SP33. Addressis0Ah. 0000000000000000 Second partofreadcycledrivenby LMX5252. Countervalueis0. 3 101 0 01010 1101110000000100 Writecycledrivenby CP3SP33. Data isDC04h. Addressis0Ah. 4 101 1 01010 Firstpartofreadcycledrivenby CP3SP33. Addressis0Ah. 0000000000000001 Second partofreadcycledrivenby LMX5252. Countervalueis1. Copyright© 2013,Texas InstrumentsIncorporated BluetoothController 121 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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19.3 LMX5251 Power-Up Sequence

To power-upa Bluetoothsystem based on theCP3SP33 and LMX5251 devices,thefollowingsequence must be performed. 1. ApplyVDD totheLMX5251. 2. ApplyIOVCC and VCC totheCP3SP33. 3. The RESET_N pinoftheradiochipisdirectlyconnectedtotheVuc pinoftheradiochipand the RFVcc pinofthePulsar.As thevoltageon theRESET_N (alsoVuc and RFVcc) isappliedafter applyinga voltagetotheVdd pin,theLMX5251 isproperlyreset. 4. After(Power-On)resetofthePulsartheRFDATA pinofthePulsarisdrivenhigh.The RFCE, RFSYNC and SDAT pinsoftePulsararesetintohigh-impedancestate.However,therearepullup/pulldown resistorsbuiltintotheS_CLK, S_DATA, S_LE, and Rx/Tx_Synchpinsoftheradiochiptoassurethe correctinitialvoltagelevelsfora properpower-upsequence. 5. The RFDATA pindriventologichighlevelcausestheradiochiptoenableitsoscillatorand afteran oscillatorstart-updelay,theradiochipoutputsa stable12 MHz clock(BB_CLK/BRCLK) tothePulsar. 6. By receivinga stableclockfromtheradiochip,thePulsarisoperationaland theCR16 enablesthe alternatefunctionoftheGPIO pin,used by theRF interface. 7. Now theBluetoothLLC can directlycontroltheRF interfacepinsand setsthepinstothelogichigh levelsrequiredduringthepower-upphase.The RFCE pindrivenhighforcestheradiochiptoswitch from“power-up”to“normal”mode and todisableit’s internalpullup/pulldownresistorsoftheRF interface. 8. Inthe“normal”mode theoscillatoroftheRF chipiscontrolledviatheRFCE pin.DrivingtheRFCE pin tologichighlevelenablestheoscillatorand theRF chipoutputstheBBCLK. 9. DrivetheRESET# pinoftheLMX5251 higha minimum of2 ms aftertheLMX5251 and CP3000 supplyrailsarepowered up.ThisresetstheLMX5251 and CP3SP33. 10. AfterinternalPower-On Reset(POR) oftheCP3SP33, theRFDATA pinisdrivenhigh.The RFCE, RFSYNC, and SDAT pinsareinTRI-STATE mode. Internalpullup/pulldownresistorson the CCB_CLOCK (SCLK),CCB_DATA (SDAT),CCB_LATCH (SLE),and TX_RX_SYNC (RFSYNC) inputs oftheLMX5251 pullthesesignalstostatesrequiredduringthepower-upsequence. 11. When theRFDATA pinisdrivenhigh,theLMX5251 enablesitsoscillator.Afteran oscillatorstart-up delay,theLMX5251 drivesa stable12-MHz BBP_CLOCK (CLKIN)totheCP3SP33. 12. The Bluetoothbaseband processoron theCP3SP33 now directlycontrolstheRF interfacepinsand drivesthelogiclevelsrequiredduringthepower-upphase.When theRFCE pinisdrivenhigh,the LMX5251 switchesfrom“power-up”to“normal”mode and disablestheinternalpullup/pulldown resistorson itsRF interfaceinputs. 13. In“normal”mode, theoscillatoroftheLMX5251 iscontrolledby theRFCE signal.DrivingRFCE high enablestheoscillator,and theLMX5251 drivesitsBBP_CLOCK (CLKIN)output.

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LMX5251 in Normal ModeLMX5251 in Power-Up Mode LMX5251 Oscillator Start-Up LMX5251 Initialization CP3000 Initialization Active High DS333 RESET# LMX5251 RESET CP3000 tPTOR CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure19-9.LMX5251 Power-Up Sequence

19.4 LMX5252 Power-Up Sequence

A Bluetoothsystembased on theCP3SP33 and LMX5252 deviceshas thefollowingstates:

• Off— When the LMX5252 entersOffmode, allconfigurationdata islost.In thisstate,the LMX5252 drivesBPOR low.
• Power-Up — When the power supplyison and the LMX5252 RESET# inputishigh,the LMX5252 startsup itscrystaloscillatorand entersPower-Up mode. Afterthe crystaloscillatorissettled,the LMX5252 sends fourclockcycleson BRCLK (CLKIN)beforedrivingBPOR high.
• RF Init— The baseband controlleron the CP3SP33 now drivesRFCE highand takescontrolof the crystaloscillator.The baseband performsalltheneeded initialization(suchas writingtheregistersin theLMX5252 and crystaloscillatortrim).
• Idle— The baseband controlleron theCP3SP33 drivesRFDATA low when theinitializationisready. The LMX5252 isnow readytostarttransmitting,receiving,orenterSleepmode.
• Sleep— The LMX5252 can be forcedintoSleep mode at any time by drivingRFCE low. All configurationsettingsarekept,onlytheBluetoothlowpower clockisrunning(B3k2).
• Wait XTL — When RFCE goes high,thecrystaloscillatorbecomes operational.When itisstable,the LMX5252 entersIdlemode and drivesBRCLK (CLKIN). Copyright© 2013,Texas InstrumentsIncorporated BluetoothController 123 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Crystal Osc. Stable RF Init RFCE = High RFDA TA = Don't Care Write Registers RESET# = High and Power is On Power-Up Wait for Crystal Osc. To Stabilize RESET# = Low or Power is cycledOff RFCE = High Wait XTL Wait for Crystal Osc. To Stabilize RFCE = Low Sleep Any State Any State After RF Init Crystal Osc. Stable CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure19-10.LMX5252 Power States The power-upsequence fora Bluetoothsystem based on theCP3SP33 and LMX5252 devicesisshown inFigure19-11. Figure19-11.LMX5252 Power-Up Sequence

19.5 BluetoothSleep Mode

The Bluetoothcontrolleriscapableofputtingitselfintoa sleepmode fora specifiednumber ofSlow Clock cycles.Inthismode, thecontrollerclocksare stoppedinternally.The onlycircuitrywhich remainsactive aretwo counters(counterN and counterM) runningattheSlow Clockrate.These countersdeterminethe durationofthesleepmode. The sequence ofeventswhen enteringtheLLC sleepmode isas follows: 1. The currentBluetoothcountercontentsarereadby theCPU. 2. Software“estimates”theBluetoothcountervalueafterleavingthesleepmode 3. The new BluetoothcountervalueiswrittenintotheBluetoothcounterregister.

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1 MHz/12 MHz

www.ti.com SNOSCW5 –MAY 2013 4. The BluetoothsequencerRAM isupdatedwiththecode requiredby theBluetoothsequencerto enter/exitSleepmode. 5. The BluetoothsequencerRAM and theBluetoothLLC registersareswitchedfromtheHCLK Clock domain tothelocal12 MHz Bluetoothclockdomain.Atthispoint,theBluetoothsequencerRAM and BluetoothLLC registerscannotbe updatedby theCPU, because theCPU no longerhas accesstothe BluetoothLLC. 6. Hardware ClockControl(HCC) isenabled,and theCP3SP33 entersa low-powermode (PowerSave orIdlemode).WhileinPower Save mode, theSlow ClockdrivestheHCLK Clock.WhileinIdlemode, theHCLK Clockisturnedoff. 7. The BluetoothsequencerchecksifHCC isenabled.IfHCC isenabled,thesequencerassertsHCC to thePMM. On thenextrisingedge ofthelow-frequencyclock,the1MHz clockand the12 MHz clock arestoppedlocallywithintheBluetoothLLC. Atthispoint,theBluetoothsequencerisstopped. 8. The M-counterstartscounting.AfterM + 1 Slow Clockcycles,theHCC signaltothePMM is deasserted. 9. The PMM restartsthe12 MHz Main Clock(andthePLL,ifrequired).The N-counterstartscounting. AfterN + 1 Slow Clockcycles,theBluetoothclocks(1MHz and 12 MHz) areturnedon again.The Bluetoothsequencerstartsoperating. 10. The Bluetoothsequencerwaitsforthecompletionofthesleepmode. When completed,theBluetooth sequencerassertsa wake-up signaltotheMIWU (seeSection17.0Section17). 11. The PMM switchestheHCLK Clocktothehigh-frequencyclockand theCP3SP33 entersActivemode again.HCC isdisabled.The BluetoothsequencerRAM and BluetoothLLC registersareswitchedback fromthelocal12 MHz BluetoothclocktotheHCLK Clock.Atthispoint,theBluetoothsequencerRAM and BluetoothLLC registersareonce againaccessibleby theCPU. Ifenabled,an interruptisissuedto theCPU. Figure19-12.BluetoothSleep Mode Sequence

19.6 BluetoothGlobalRegisters

Table19-2shows thememory map oftheBluetoothLLC globalregisters. Copyright© 2013,Texas InstrumentsIncorporated BluetoothController 125 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table19-2.Memory Map ofBluetoothGlobalRegisters ADDRESS DESCRIPTION 0001 2080h–0001 20C8h GlobalLLC Configuration 0001 20C9h –0001 20FFh Unused

19.7 BluetoothSequencer RAM

The sequencerRAM isa 1K memory-mapped sectionofRAM thatcontainsthesequencerprogram.This RAM can be readand writtenby theCPU inthesame way as theStaticRAM space and can alsobe read by thesequencerintheBluetoothLLC. Arbitrationbetween thesedevicesisperformedinhardware.

19.8 BluetoothShared Data RAM

The shared data RAM isa 7K memory-mapped sectionof RAM thatcontainsthe linkcontroldata,RF programminglook-uptable,and thelinkpayload.ThisRAM can be readand writteninthesame way as theStaticRAM space and can alsobe read by thesequencerintheBluetoothLLC. Arbitrationbetween thesedevicesisperformedinhardware.Table19-3shows thememory map oftheBluetoothLLC shared Data RAM. Table19-3.Memory Map ofBluetoothShared RAM ADDRESS DESCRIPTION 0001 2500h–0001 26D9h RF Programming Look-upTable 0001 26DAh –0001 26FFh Unused 0001 2700h–0001 273Fh LinkControl0 0001 2740h–0001 277Fh LinkControl1 0001 2780h–0001 27BFh LinkControl2 0001 27C0h –0001 27FFh LinkControl3 0001 2800h–0001 283Fh LinkControl4 0001 2840h–0001 287Fh LinkControl5 0001 2880h–0001 28BFh LinkControl6 0001 28C0h –0001 28FFh LinkControl7 0001 2900h–0001 36FFh LinkPayload0–6

20 TelematicsCodec

The telematicscodec providesdualinputchannelsforvoicerecognition,telematics,voice-over-IP(VoIP), and Bluetoothapplications,and itprovideshigh-qualitystereooutputformusic playbackand voiceDAC functions. The ADC has thesefeatures:

• Two differentialorsingle-endedanalogmicrophoneinput
• Two digitalmicrophoneinterfaces
• Programmable microphonegainand muting
• SNR of70 dB forADC path
• Fixed125× oversamplingrate
• 8 kHz to24 kHz
• Selectablechoiceofhigh-passfilters The stereoDAC has thesefeatures:
• >85 dB SNR
• Selectablemono and stereomodes

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• Exactsample ratesof8,12,16,24,and 48 kHz derivedfrom12-MHz clock
• Exactsample ratesof22.05,24,32,44.1,48,88.2,96,176.4,and 192 kHz fromon-chipPLL
• 125× oversamplingratemode using2,3,4,6,or12 MHz clock
• 128× oversamplingratemode
• 64× and 32× oversamplingratemodes forhigh-quality96/192kHz audio
• On-chipfullydifferentialsignalingforanalogcircuitrytoensurehighPSRR and lowcrosstalk
• Mute and low-powermodes on outputs
• Programmable sidetonefromADC
• Clickand pop reductionand DC protectioncircuits
• Zero-crossingdetectionformode changing
• Power-management sequencertoprotectexternalcomponents (suchas speakers)frompower fluctuations
• Programmable 5-tapFIR filterfortonecontroland compensation Figure20-1.TelematicsCodec

20.1 CODEC ADC

The ADCs aredesignedforoperationat8 or16 kHz and meet alltypicalspecificationsatthislevel.They can be used atsample ratesup to24 kHz by increasingtheinputclockfrom 1 MHz up to3 MHz. The ADCs are 125×-oversampled,second-order,analogsigma-deltamodulator(ASDM) designedspecifically foraudioapplications.They use IIRfilterstoobtainlargestopbandattenuations.The frequencyresponse matches thatused forBluetoothand GSM at8 kHz,and itissuitableforG.722 applicationsat16 kHz. The ADCs have selectablehigh-passfiltersto supportpop/windrejectionat highersamplingrates.The clockshouldbe setas shown inTable20-1. Copyright© 2013,Texas InstrumentsIncorporated TelematicsCodec 127 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table20-1.Codec ADC Clock Frequency SAMPLING FREQUENCY CODEC ADC CLOCKOVERSAMPLING RATE (kHz) FREQUENCY (MHz) 125 8 1 125 12 1.5 125 16 2 125 24 3

20.2 CODEC DAC

The stereoDAC operatesinone offouroversamplingmodes (32×,64×,125×,or128×),as selectedinthe DACOSR fieldoftheTCDCBASIC register.Thisallowsa 12-MHz clockfor8,16,24,or48 kHz audioor an externalclockforany othersamplingrateup to192 kHz as shown inTable20-2. Table20-2.Codec DAC Clock Frequency SAMPLING CODEC DAC CLOCKOVERSAMPLINGDACOSR FIELD FREQUENCY FREQUENCYRATE (kHz) (MHz) 0 125 8 2 0 125 12 3 0 125 16 4 0 125 24 6 0 125 32 8 0 125 48 12 1 128 22.05 5.6448 1 128 32 8.192 1 128 44.1 11.2896 1 128 48 12.288 10 64 88.2 11.2896 10 64 96 12.288 11 32 176.4 22.5792 11 32 192 24.576 The codec stereoDAC is a CD-qualitythird-order“bit-stream” DAC similarto those found on most commercialCD players.The stopband attenuationisgreaterthan76 dB and systempass-bandripplecan be kepttowithin0.01dB.TypicalSNRs are85dB withouta weightingfilter. To meet the requirementsof typicalautomotivetelematicsapplications,the analogsignalpath isfully differential.Forbestaudioperformance,theDAC shouldoperatesynchronouslytotheCPU.

20.3 Compensation Filter

To allowcompensationof roll-offin the DAC and analog filtersections,an FIR compensationfilteris appliedtotheinputdataattheoriginalsample rate.The filtercan alsobe used forprecisedigitalgainand simpletonecontrols,althougha DSP or CPU shouldbe used ifmore powerfultonecontrolisrequired. Figure20-2shows thefilterstages.

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www.ti.com SNOSCW5 –MAY 2013 Figure20-2.Compensation FIR Filter By default,the filterappliesabout 2 dB of compensationat 20 kHz. Five taps is sufficientto allow passband equalizationand ripplecancellationtoaround±0.01dB. Because thefiltermust alwaysbe phase linear,thecoefficientsaresymmetrical.CoefficientsC0, C1, and C2 areprogrammable,C3 isequaltoC1, and C4 isequaltoC0. The maximum power ofthisfiltermust notexceed thatoftheexamplesgiveninTable20-3. Table20-3.DefaultFilterCoefficients SAMPLING FREQUENCY OVER-SAMPLING RATE C0 C1 C2 C3 C4(kHz) 48 125 343 –2291 26984 –2291 343 48 128 61 –371 25699 –371 61

20.4 ReconstructionFilter

The outputof the stereoDAC ispassed throughlow-passreconstructionfiltersto remove quantization noise(the“sigma-deltatail”).Because the DAC isoptimizedforhigh-qualityaudio(44.1kHz or higher sample rate),thecutofffrequencyofthefilterisplacedat24 kHz. At low sample rates(forexample,8 kHz),quantizationnoisewillappearbelow thiscutofffrequency.Ifthe applicationrequiresthisnoisetobe removed,severalsolutionsarepossible.For example,low-passfilters may be added totheDAC outputs.Even simpleRC filterswillprovidesubstantialnoisereduction.Audio devicesintendedforvoice(suchas headsets)oftenprovidean effectivefilterbecause of theirlimited bandwidth. Insoftware,digitalinterpolationmay be used toupsample thedatafora highersample rate.Thissolution requiresno additionalhardware,butitconsumes more CPU bandwidthand adds delaytotheaudiopath.

20.5 PeripheralBus Interface

The codec isa slavedeviceon thesharedaudioperipheralAPB bus.As shown inFigure20-1,thecodec interfacehas fourFIFOs,two read FIFOs forthetwo ADC channelsand two writeFIFOs forthestereo DAC channels.Four independentDMA requestsare availablecorrespondingto the fourchannels.One interruptrequest(IRQ28)isavailablefortriggeringby any channel.

20.5.1 FIFOs

The ADC and DAC triggerdepthsarecontrolledindependentlytosupportdifferingsamplingrates.The full depthoftheFIFOs does notneed notbe used,and a lesserdepthmay be used toreducelatency. Each ADC FIFO remainsinthesame statewhen itsADC isdisabledand isonlyclearedduringa resetor flushcondition.The ADC FIFOs should be flushedbeforethe ADCs are unmuted to clearany old samples,or thecodec can be placedinresetusingtheSoftReset bit(SFTRST bitintheTCDCDEBUG register).Thiscan be used tostartthecodec froma known state. Copyright© 2013,Texas InstrumentsIncorporated TelematicsCodec 129 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com The DAC FIFOs areautomaticallyflushedwhen theDAC isdisabled.When theDAC ismuted,theDAC FIFOs shouldbe flushedbeforetheDAC isunmuted.

20.5.2 Interrupts

Interruptrequestson IRQ28 can be generatedfrom severalsources,such as FIFO overrun/underrun, power-cycleevents,and audiosignalzero-crossingsand clippingevents(usefulforchanges totheDSP or audio stream).The interruptenable register(TCDCIRQEN) and FIFO triggercontrolregister (TCDCFIFO) are used to enable events which assertinterruptrequests.The pending/clearregister (TCDCIRQPNDCLR) indicateswhich eventshave occurred.Writing1 toa bitintheTCDCIRQPNDCLR registerclearstheevent. Because theinterruptrequestcan be handledby eithertheCPU orDSP interruptcontrollers,theinterrupt requestispassed throughtheAudioSubsystem Controller(ASC),whichisprogrammed torouteittothe interruptcontroller.To use thecodec interrupt,itmust be enabledatthreelevels:

• Codec module— theinterruptmust be enabledintheTCDCIRQEN register.
• ASC module— thecodec interruptisassignedtoASC interruptchannel8,so bit8 intheASCINTSEL registermust be cleartoselecttheCPU interruptcontrollerorsettoselecttheDSP interruptcontroller.
• Interruptcontroller— the interruptrequestmust be enabled in the interruptcontroller.For the CPU interruptcontroller,thisisinterruptrequestIRQ28.

20.5.3 DMA

A DMA requestor interruptrequestmay be enabledwhen a FIFO reachesitstriggerlevel.Low trigger levelsarerecommended fortriggeringDMA requests,toreduceunnecessarylatency.DMA requestsand IRQ28 interruptrequestsare mutuallyexclusive,however interruptrequestsIRQ49, IRQ48, IRQ47, and IRQ46 may be enabledforDMA requestson channels10,11,12,and 13,respectively. Because thecodec DMA requestscan be handledby eithertheCPU or DSP DMA controllers,theDMA requestsarepassed throughtheAudioSubsystem Controller(ASC),whichisprogrammed toroutethem totheDMA controller.To use thecodec DMA requests,theymust be enabledatthreelevels:

• Codec module— thecodec DMA requestsmust be enabledintheTCDCFIFO register.
• ASC module— thecodec DMA requestsare assignedtoASC DMA channels10 (ADC1),11 (ADC2), 12 (leftDAC), and 13 (rightDAC). These channelsare controlledby bits10, 11, 12, and 13 inthe ASCDMASEL0 register.The bitsmust be cleartoselecttheCPU DMA controlleror settoselectthe DSP DMA controller.IftheDSP DMA controllerisselected,theDSP DMA channelmust be enabledin theASCDDMASELn registers.
• DMA controller— the DMA requestsmust be enabled in the DMA controller.For the CPU DMA controller,theseareDMA requests10 (ADC1),11 (ADC1),12 (leftDAC), and 13 (rightDAC). Ifa DMA requestisdisabledwhileitisasserted,the requestwillremain asserted,which blockslower- priorityrequeststo the DMA controller.To avoidthissituation,softwarecan eithercheck thatthe DMA requestisnotassertedbeforedisablingtherequest,oritcan disabletherequestintheDMA controller.

20.6 FreezeMode

When Freezemode isentered,thecodec willexhibitthefollowingbehavior:

• The contentsoftheADC and DAC FIFOs and theFIFO outputdatado notchange.
• The DAC outputsaremuted.

20.7 Reset

The ADC, DACs, DSP, and analogmodules shouldnotbe resetasynchronouslyinnormalapplications, because thismay damage externalelectro-mechanicaldevicessuch as speakers.

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www.ti.com SNOSCW5 –MAY 2013 Ifa watchdog resetoccurs,the codec’s integralpower management willnot power down the analog circuitryina safemanner. When softwareneeds to resetthe codec,itshouldsetand then clearthe SFTRST bitintheTCDCDEBUG register.

20.8 DC ProtectionMonitor

Ifthe analogoutputsare used to drivea loudspeakerdifferentially,then DC offsetson the outputscan damage thedrivers.IftheDAC FIFO outputhas notchanged fora programmablenumber ofsamples,the DC protectionmonitortriggersa DAC FIFO flush.Ifthenumber ofDC protectionmonitoreventsexceeds a programmable limit,themonitorcan alsoshutdown thestereoDAC. IftheDAC isnotbeingused for audioapplicationsand a constantDC outputisrequired,themonitorcan be disabled.

20.9 SidetoneInjection

SidetoneinjectionfromtheADC1 channelcan be enabledindividuallyforeach DAC channel.The levelof sidetoneattenuationisprogrammable intheSIDETONEATTEN fieldoftheTCDCDSP registerfrom 0 to –36 dB inincrementsof3 dB. Ifthesidetonesignalforeitherchannelcauses clipping,a warningflagis set(STCLPL orSTCLPR intheTCDCDSP register). Ifthesidetoneisused,ADC1 and thestereoDAC must runfromthesame clockatthesame sample and oversamplingrate.Thiscan be enabledby settingthe CLKTIE bitinthe TCDCADC1CLK registerand selectinga DAC oversamplingrateof125.

20.10 TelematicsCodec RegisterSet

Table20-4liststhetelematicscodec registers. Table20-4.TelematicsCodec Registers NAME ADDRESS DESCRIPTION TCDCBASIC FF 4400h Codec BasicConfigurationRegister TCDCDACSTATUS FF 4404h Codec DAC StatusRegister TCDCADCSTATUS FF 4408h Codec ADC StatusRegister TCDCDSP FF 440Ch Codec DSP Set-UpRegister TCDCADCANA1 FF 4410h Codec ADC1 AnalogControlRegister TCDCADCANA2 FF 4414h Codec ADC2 AnalogControlRegister TCDCADC1CLK FF 4418h Codec ADC1 ClockRegister TCDCADC2CLK FF 441Ch Codec ADC2 ClockRegister TCDCDACCLK FF 4420h Codec DAC ClockRegister TCDCFIFO FF 4424h Codec FIFO TriggerControlRegister TCDCIRQEN FF 4428h Codec InterruptEnableRegister TCDCIRQPNDCLR FF 442Ch Codec InterruptPending/ClearRegister TCDCCOMPC0 FF 4430h Codec CompensationFilterC0/4 Tap Register TCDCCOMPC1 FF 4434h Codec CompensationFilterC1/3 Tap Register TCDCCOMPC2 FF 4438h Codec CompensationFilterC2 Tap Register TCDCADC1 FF 4448h Codec ADC1 Data Register TCDCADC2 FF 444Ch Codec ADC2 Data Register TCDCLEFT FF 4450h Codec Left-ChannelDAC Data Register TCDCRIGHT FF 4454h Codec Right-ChannelDAC Data Register TCDCDEBUG FF 443Ch Codec Debug Register TCDCMONITOR FF 4458h Codec MonitorControland StatusRegister Copyright© 2013,Texas InstrumentsIncorporated TelematicsCodec 131 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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20.10.1 Codec Basic ConfigurationRegister(TCBCBASIC)

The TCDCBASIC registerisa 16-bitread/writeregisterthatcontrolsthebasicoperationofthecodec.At reset,thisregisterisclearedto0000h. 7 6 5 4 2 1 0 MUTEL DACOSR DACSTMODE ADC2ON ADC1ON 15 14 13 12 11 10 9 8 DFS AFS FLSDAC FLSADC Reserved SEM MUTER ADC1ON The ADC1 On bitcontrolswhetherADC1 isenabledtorun.When writtenwith1,ADC1 beginsitspower-upsequence.Check theADC1UP bitintheTCDCIRQPNDCLR registertodeterminewhetherADC1 has completeditspower-upsequence. 0 – ADC1 disabled. 1 – ADC1 enabled. ADC2ON The ADC2 On bitcontrolswhetherADC2 isenabledtorun.When writtenwith1,ADC2 beginsitspower-upsequence.Check theADC2UP bitintheTCDCIRQPNDCLR registertodeterminewhetherADC2 has completeditspower-upsequence. 0 – ADC2 disabled. 1 – ADC2 enabled. DACSTMODE The DAC SidetoneMode fieldcontrolsthebasicfunctionoftheDAC, sidetoneinput, and outputstage.The sidetoneistakenfromADC1. DACSTMODE FIELD LEFT CHANNEL RIGHT CHANNEL

000 Off Off

001 Left Right

010 Left Off

011 Left+ Sidetone Off

100 Left+ Sidetone Left

101 Left+ Sidetone Right

110 Left Right+ Sidetone

111 Left+ Sidetone Right+ Sidetone

DOCOSR The DAC OversamplingRate fieldselects32×,64×,125×,or128× oversamplingrate forthestereoDAC. Note thattheADCs have a fixedoversamplingrateof125×. 00 – 125× 01 – 128× 10 – 64× 11 – 32× MUTEL The Mute Left-ChannelDAC bitcontrolswhethertheleft-channelDAC willbe muted afterthenextzero-crossingoccurs. 0 – Left-channelDAC mute off. 1 – Left-channelDAC mute enabled. MUTER The Mute Right-ChannelDAC bitcontrolswhethertheright-channelDAC willbe muted afterthenextzero-crossingoccurs. 0 – Right-channelDAC mute off. 1 – Right-channelDAC mute enabled. SEN The StatusEnablebitcontrolstheclockforthebus interface.When thebus interfaceis drivenwitha clock,thepower-upand power-down interruptsfortheADCs and DACs may be used. 0 – Bus interfaceclocksdisabled. 1 – Bus interfaceclocksenabled.

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www.ti.com SNOSCW5 –MAY 2013 FLSADC The FlushADC FIFO bitcan be used toflushtheADC FIFOs.Writing1 tothisbitclears theFIFOs. 0 – No effect. 1 – FlushtheADC FIFOs. FLSDAC The FlushDAC bitcan be used toflushthestereoDAC FIFOs.Writing1 tothisbit clearstheFIFOs.Thisshouldbe used when deliberatelypausingtheDAC datastream orany othertimewhen theDAC FIFOs willbe underrundeliberately.IftheDAC FIFOs areunderrunand thisbitisnotset,thentheDAC iscontinuouslydrivenwiththeoldest dataand thiswillresultina DC component on theDAC outputs. 0 – No effect. 1 – FlushtheDAC FIFOs. AFS The ADC FIFO StatusMode bitcontrolstheencodingoftheADC1FIFO and ADC2FIFO fieldsintheTCDCADCSTATUS register.See thedescriptionoftheTCDCADCSTATUS reisterformore information. DFS The DAC FIFO StatusMode bitcontrolstheencodingoftheLEFTFIFO and RIGHTFIFO fieldsintheTCDCDACSTATUS register.See thedescriptionofthe TCDCDACSTATUS registerformore information.

20.10.2 Codec DAC StatusRegister(TCDCDACSTATUS)

The TCDCDACSTATUS registerisa 16-bit,read-onlyregisterthatindicatesthestatusoftheDAC FIFOs and theDAC analogoutputstage.AfterDAC operationisenabledintheTCDCDACCLK and TCDCBASIC registers,theDACSTATUS bitwillbecome settoindicatethattheDAC isoperational.The leftand right DAC FIFOs areclearwhiletheDAC isdisabled.WhiletheDAC isenabled,theFIFOs can be flushedby usingthe FLSDAC bitin the TCDCBASIC registeror by resettingthe codec usingthe SoftReset bit (SFTRST bitin the TCDCDEBUG register).The DAC FIFOs shouldbe flushedbeforethe DACs are unmuted toclearany oldsamples.Afterreset,thisregisterisinitializedto1010h,whichindicatestheDAC FIFOs containno validwords and theanalogoutputstageispowered down. 15 14 13 12 8 7 5 4 0 DACSTATUS Reserved RIGHTFIFO Reserved LEFTFIFO LEFTFIFO The Left-ChannelDAC FIFO StatusfieldindicatesthecurrentstatusoftheFIFO forthe left-channelDAC. Afterreset,thedefaultmode forthisfieldistoreportthenumber of empty words availableintheFIFO,so itindicates10h (empty).By settingtheDFS bitin theTCDCBASIC register,thisindicationisreversedand thefieldreportsthenumber of validwords ofdata,as shown below: FIFO STATUS FIELD DFS BIT DESCRIPTION 00h 0 Full(16validwords) 01h to0Fh 0 15 to1 validwords 10h 0 Empty (novaliddata) 1Eh 0 Underrunerror(readwhileempty) 1Fh 0 Overrunerror(writtenwhilefull) 00h 1 Empty (novaliddata) 01h to0Fh 1 1 to15 validwords 10h 1 Full(16validwords) 1Eh 1 Underrunerror(readwhileempty) 1Fh 1 Overrunerror(writtenwhilefull) Copyright© 2013,Texas InstrumentsIncorporated TelematicsCodec 133 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com RIGHTFIFO The Right-ChannelDAC FIFO StatusfieldindicatesthecurrentstatusoftheFIFO forthe right-channelDAC. Afterreset,thedefaultmode forthisfieldistoreportthenumber of empty words availableintheFIFO,so itindicates10h (empty).By settingtheDFS bitin theTCDCBASIC register,thisindicationisreversedand thefieldreportsthenumber of validwords ofdata.The encodingofthefieldisthesame as thatshown forthe LEFTFIFO field. DACSTATUS The DAC StatusbitindicateswhethertheDAC outputstagesareenabled,whichmay occurdue toremainingchargeon thebypasscapacitor.Softwaremust checkthatthisbit has clearedbeforeenteringdisablingtheclocktothecodec (orenteringa low-power mode thatdisablestheclock). 0 – DAC off. 1 – DAC on.

20.10.3 Codec ADC StatusRegister(TCDCADCSTATUS)

The TCDCADCSTATUS registerisa 16-bit,read-onlyregisterthatindicatesthecurrentstatusoftheADC FIFOs,ADCs, and ADC analoginputstage.AfterADC operationisenabledintheTCDCADCCLKn and TCDCBASIC registers,thecorrespondingADCnSTATUS bitswillbecome settoindicatethattheADCs are operational.The ADC FIFOs are unchanged whilethe ADCs are disabled.While the ADCs are enabled,theFIFOs can be flushedby usingtheFLSADC bitintheTCDCBASIC registeror by resetting thecodec usingtheSoftReset bit(SFTRST bitintheTCDCDEBUG register).Afterreset,thisregisteris initializedto1010h,whichindicatestheADC FIFOs containno validwords and theanaloginputstageis powered down. 15 14 13 12 8 7 5 4 0 ADC2STATUS ADC1STATUS Reserved ADC2FIFO Reserved ADC1FIFO ADC1FIFO The ADC1 FIFO StatusfieldindicatesthecurrentstatusoftheADC1 FIFO.Afterreset, thedefaultmode forthisfieldistoreportthenumber ofempty words intheFIFO,so it indicates10h (empty).By settingtheAFS bitintheTCDCBASIC register,thisindication isreversedand thefieldreportsthenumber ofvalidwords ofdata,as shown below: ADC FIFO STATUS AFS BIT DESCRIPTION FIELD 00h 0 Full(16validwords) 01h to0Fh 0 15 to1 validwords 10h 0 Empty (novaliddata) 1Eh 0 Underrunerror(readwhileempty) 1Fh 0 Overrunerror(writtenwhilefull) 00h 1 Empty (novaliddata) 01h to0Fh 1 1 to15 validwords 10h 1 Full(16validwords) 1Eh 1 Underrunerror(readwhileempty) 1Fh 1 Overrunerror(writtenwhilefull) ADC2FIFO The ADC2 FIFO StatusfieldindicatesthecurrentstatusoftheADC2 FIFO.Afterreset, thedefaultmode forthisfieldistoreportthenumber ofvalidwords intheFIFO,so it indicates10h (empty).By settingtheAFS bitintheTCDCBASIC register,this indicationisreversedand thefieldreportsthenumber ofvalidwords ofdata.The encodingofthefieldisthesame as thatshown fortheADC1FIFO field. ADC1STATUS The ADC1 StatusbitindicateswhetherADC1 isenabled.IfADC1 isenabled,itsclock must notbe disabled. 0 – ADC1 disabled. 1 – ADC1 enabled.

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www.ti.com SNOSCW5 –MAY 2013 ADC2STATUS The ADC2 StatusbitindicateswhetherADC2 isenabled.IfADC2 isenabled,itsclock must notbe disabled. 0 – ADC2 disabled. 1 – ADC2 enabled.

20.10.4 Codec DSP Set-Up Register(TCDCDSP)

The TCDCDSP registerisa 16-bit,read/writeregisterthatconfiguressome of the DSP portionsof the module.Afterreset,thisregisterisclearedto0000h. 15 14 13 12 9 8 7 5 4 3 2 1 0 CUST ADC2 ADC1 DAC DACReserved STCLPR STCLPL SIDETONEATTEN CLKPH DIGMICGAIN COMP DITOFF DITOFF DITOFF DITON DACDITON The DAC DitherOn bitenablesditheringtheoutput,withoutregardtotheaudio content. 0 – Ditheringmay be on oroff. 1 – Ditheringalwayson. DACDITOFF The DAC DitherOffbitdisablesditheringtheoutput,withoutregardtotheaudio content.Ifset,thisbitoverridestheDACDITON bit. 0 – Ditheringmay be on oroff. 1 – Ditheringalwaysoff. ADC1DITON The ADC1 DitherOffbitdisablesditheringtheADC1 ASDM input. 0 – Ditheringmay be on oroff. 1 – Ditheringalwaysoff. ADC2DITON The ADC2 DitherOffbitdisablesditheringtheADC2 ASDM input. 0 – Ditheringmay be on oroff. 1 – Ditheringalwaysoff. CUSTCOMP The CUSTCOMP bitselectsbetween defaultcompensationfiltercoefficientsand custom valuesintheTCDCCOMP0, TCDCCOMP1, and TCDCCOMP2 registers. Defaultvaluesvarywiththeover-samplingratetokeep thereconstructionfilteroutput flatup to20kHz. 0 – Defaultcoefficientsareused. 1 – Custom coefficientsareused. DIGMICGAIN The DIGMICGAIN fieldselectsa scalingfactorfortheDIGMIC1 inputdata.Itcan be used toprovideextragainforsmallanalogsignalswhen themicrophonepre-amplifier gainisnotsufficient.Itiscontrollablein2 dB stepsbetween 0 dB and 14 dB. DIGMICGAIN FIELD GAIN (db) 000 0 001 2 010 4 011 6 100 8 101 10 110 12 111 14 Copyright© 2013,Texas InstrumentsIncorporated TelematicsCodec 135 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com CLKPH The ClockPhase bitcan be used toinvertthephase oftheoutputclockforuse with non-standarddigitalmicrophones. 0 – Normal clock. 1 – Invertedclock. SIDETONEATTEN The SidetoneAttenuationfieldspecifiesthegainused inthesidetonefeedback.This shouldonlybe used iftheDAC and ADC areoperatingatthesame sample rates. SIDETONEATTEN FIELD GAIN (db)

0000 Off(Mute)

0001 –36 0010 –33 0011 –30 0100 –28 0101 –26 0110 –24 0111 –22 1000 –20 1001 –18 1010 –15 1011 –12 1100 –9 1101 –66 1110 –3 1111 0 STCLPL The SidetoneClippingLeftChannelbitindicatesthatthesidetoneappliedtotheleftDAC channelistoolarge,and thesignalhas clipped.More headroom shouldbe providedinthe DAC dataorthelevelofsidetoneshouldbe reduced.Write1 tothebittoclearit. 0 – No clippinghas occurred. 1 – Clippinghas occurred. STCLPR The SidetoneClippingRightChannelbitindicatesthatthesidetoneappliedtotherightDAC channelistoolarge,and thesignalhas clipped.More headroom shouldbe providedinthe DAC dataorthelevelofsidetoneshouldbe reduced.Write1 tothebittoclearit. 0 – No clippinghas occurred. 1 – Clippinghas occurred.

20.10.5 Codec ADC Analog ControlRegistern (TCDCADCANAn)

The TCDCADCANAn registersare 16-bit,read/writeregisterthatconfigurethe analog portionsof the ADCs. Afterreset,theseregistersareclearedto0000h. 15 14 13 12 11 10 8 7 6 5 4 3 0 Reserved HPF MUTE MICSEL Reserved Reserved MICMODE Reserved MICGAIN MICGAIN The MicrophoneGain fieldselectsthegainofthemicrophonepre-amp.Fora MICGAIN of0 dB,theinputshouldnotexceed 500 mVpp (thirdharmonicdistortion~ –70 dB).Forlower distortion,reducethemaximum inputsignalby 3 dB,a 350 mVpp inputgivesa third harmonicat~ –80 dB.Thisappliestobothdifferentialand single-endedconfigurations. Fora differentialinput,thepeak-to-peakvoltageisthedifferencebetween themaximum negativevoltageon TCMICnN and themaximum positivevoltageon TCMICnP. Fora single- ended input,thepeak-to-peakvoltageisthedifferencebetween theminimum and maximum voltageon TCMICnP.

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www.ti.com SNOSCW5 –MAY 2013 GAIN MAX. INPUT RECOMMENDED INPUTMICGAIN FIELD (db) (mVpp) (mVpp) 0 0 500 354 1 1.8 406 287 10 4.1 312 220 11 6 251 177 100 7.8 204 144 101 10.1 156 111 110 12 126 88.8 111 14.5 94.2 66.6 1000 16.1 78.3 55.4 1001 18.1 62.2 44 1010 20.6 46.7 33 1011 22.1 39.3 27.8 1100 24.1 31.2 22 1101 26.6 23.4 16.5 1110 28.2 19.5 13.8 1111 30.1 15.6 11.1 MICMODE The MicrophoneMode fieldconfigurestheanalogmicrophoneinput. 0 – Differential(TCMICnP and TCMICnN inputs). 1 – Single-ended(TCMICnP inputonly). MICSEL The MicrophoneSelectbitselectsbetween theanalogand digitalmicrophoneinputs.When a digitalmicrophoneisselected,theTCIO1 pinisconfiguredas an outputclockat125× oversamplingrate,withoutregardtotheGPIO registers.The digitalmicrophoneisa four-pin devicewhichwilltaketheADC clockand producea sigma-deltastreamsuitableforthe decimator. 0 – Analoginput. 1 – Digitalinput. MUTE The Mute bitenablesmutingthemicrophoneinput.ForADC1, mutingisappliedtoboth analogand digitalinputs.ForADC2, onlytheanaloginputismuted. 0 – Mutingdisabled. 1 – Mutingenabled. HPF The HighPass Filterfieldcontrolsthehigh-passfilterappliedtotheoutputoftheADC, typicallyused foreliminatingwind/road/popnoise.The HPF has two options,toenablethe ADC tobe used at8 kHz and 16 kHz sample rateswithoutalteringtheHPF response. HPF FIELD DESCRIPTION 8 kHz 16 kHz

00 Bypass Bypass

01 –0.5dBPointat300 Hz –0.5dBPointat600 Hz Notchat55 Hz (recommended) Notchat110 Hz 10 –0.5dBPointat150 Hz –0.5dBPointat300 Hz Notchat27 Hz Notchat55 Hz (recommended)

11 Reserved Reserved

From 16 kHz to24 kHz theHPF roll-offoptionswillbe toohighfrequencyformost applications,so itisrecommended thatthefilterisbypassedabove 16 kHz.Simplevoiceapplicationsrarely requiresample ratesabove 16 kHz.Itisrecommended thatforhigherqualityapplicationsinwhich 24 kHz recordingisrequired,a signalconditioningalgorithmtoremove unwanted LF shouldbe used. Copyright© 2013,Texas InstrumentsIncorporated TelematicsCodec 137 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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20.10.6 Codec ADC Clock ControlRegistern (TCDCADCnCLK)

The TCDCADCnCLK registersare 16-bit,read/writeregistersthatconfigurethe ADC clocksources. These registersmust onlybe programmed when the correspondingADC isdisabled.At reset,these registersareclearedto0000h. 15 12 11 10 8 7 0 Reserved CLKTIE ADCCLKSRC ADCCLKDIV ADCCLKDIV The ADC ClockDivisorfieldspecifiestheADC clockperiodintermsofhalf-cyclesof theinputclock.The fieldisbiasedby 1,so togeta periodof4 half-cycles,loadthis fieldwith3.A valueofzerodisablestheclock. ADCCLKSRC The ADC ClockSourcefieldselectstheclocksourcefortheADC clockdivisor. Independentclocksourcescan be programmed foreach ADC and theDAC, toallow each sectionofthecodec torunfromdifferentclocks.Ifthesidetoneisused,ADC1 and theDAC must runfromthesame clocksourceatthesame sample and oversamplingrate.AlthoughPLL1 and PLL2 clocksareavailableas ADC clock sources,itisrecommended touse AuxiliaryClock4 when a timebasederivedfroma PLL isdesired. ADCCLKSRC FIELD SOURCE

000 PCLK Clock

001 TCIO1 Input

010 PLL2 Clock

011 I2SCLK Input

100 AAI SCK Input

101 AuxiliaryClock4

110 PLL1 Clock

111 ClockDisabled

CLKTIE The ClockTiebitisused todrivetheADC clockfromtheDAC clock,whichcausesthe ADCCLKDIV and ADCCLKSRC fieldstobe ignored.Onlytheinputclocksourceand clockdivisorareaffectedby theCLKTIE bit. 0 – ADC clockindependentofDAC clock. 1 – ADC clockdrivenby DAC clock.

20.10.7 Codec DAC Clock ControlRegister(TCDCDACCLK)

The TCDCDACCLK registerisa 16-bit,read/writeregisterthatconfiguresthe DAC clocksource.This registermust onlybe programmed when theDAC isdisabled.Atreset,thisregisterisclearedto0000h. 15 14 13 12 11 10 8 7 0 Reserved SEL6_144 DACRNG DACCLKSRC DACCLKDIV DACCLKDIV The DAC ClockDivisorfieldspecifiestheDAC clockperiodintermsofhalf-cyclesof theinputclock.The fieldisbiasedby 1,so togeta periodof4 half-cycles,loadthisfield with3.A valueofzerodisablestheclock. DACCLKSRC The DAC ClockSourcefieldselectstheclocksourcefortheDAC clockdivisor. Independentclocksourcescan be programmed foreach ADC and theDAC, toallow each sectionofthecodec torunfromdifferentclocks.Ifthesidetoneisused,ADC1 and theDAC must runfromthesame clocksourceatthesame sample and oversampling rate.AlthoughPLL1 and PLL2 clocksareavailableas ADC clocksources,itis recommended touse AuxiliaryClock4 when a timebasederivedfroma PLL isdesired.

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www.ti.com SNOSCW5 –MAY 2013 DACCLKSRC FIELD SOURCE DACRNG The DACRNG fieldspecifiestheexpectedinputclockrangeoftheDAC. Thisisused by thepower management unittoensurecorrecttimingduringpower up and power down. Iftheexactclockrangeisnotavailable,use thenextfastest. TYPICAL SAMPLE RATEDACRNG FIELD RANGE (MHz) (kHz) 00 2 8 01 6 24 10 12 48 11 24 96 SEL6_144 The Select6 MHz bitisused toselectthe6 MHz synctoclockthereconstructionfilter, ratherthanthe12 MHz clock. 0 – 12 MHz clock. 1 – 6 MHz sync.

20.10.8 Codec FIFO TriggerControlRegister(TCDCFIFO)

The TCDCFIFO registerisa 16-bit,read/writeregisterthatconfigurestheeventswhich assertDMA and interruptrequests.Atreset,thisregisterisclearedto0000h. 15 14 13 12 11 8 7 4 3 0 DMAR DMAL DMAADC2 CMAADC1 DACFIFOTRIG ADC2FIFOTRIG ADC1FIFOTRIG ADC1FIFOTRIG The ADC FIFO TriggerLevelfieldspecifieshow many empty words areintheADC1 FIFO when an eventistriggered. ADC2FIFOTRIG The ADC FIFO TriggerLevelfieldspecifieshow many empty words areintheADC2 FIFO when an eventistriggered. DACFIFOTRIG The DAC FIFO TriggerLevelfieldspecifieshow many validwords areremainingin eitheroftheDAC FIFOs when an eventistriggered. DMAADC1 The DMA ADC1 bitenablesa DMA requestinresponsetotheADC1 triggerevent.If theADC1FIFO bitintheTCDCIRQEN registerisset,theDMAADC1 bitisignored. (Interruptand DMA requestsaremutuallyexclusive.) 0 – ADC1 DMA requestdisabled. 1 – ADC1 DMA requestenabled. DMAADC2 The DMA ADC2 bitenablesa DMA requestinresponsetotheADC2 triggerevent.If theADC2FIFO bitintheTCDCIRQEN registerisset,theDMAADC2 bitisignored. (Interruptand DMA requestsaremutuallyexclusive.) 0 – ADC2 DMA requestdisabled. 1 – ADC2 DMA requestenabled. Copyright© 2013,Texas InstrumentsIncorporated TelematicsCodec 139 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com DMAL The DMA LeftChannelbitenablesa DMA requestinresponsetotheleftchannel DAC FIFO assertingtheDAC triggerevent.IftheLFTFIFO bitintheTCDCIRQEN registerisset,theDMAL bitisignored.(Interruptand DMA requestsaremutually exclusive.) 0 – LeftchannelDAC DMA requestdisabled. 1 – LeftchannelDAC DMA requestenabled. DMAR The DMA RightChannelbitenablesa DMA requestinresponsetotherightchannel DAC FIFO assertingtheDAC triggerevent.IftheRGTFIFO bitintheTCDCIRQEN registerisset,theDMAR bitisignored.(Interruptand DMA requestsaremutually exclusive.) 0 – RightchannelDAC DMA requestdisabled. 1 – RightchannelDAC DMA requestenabled.

20.10.9 Codec InterruptRequest Enable Register(TCDCIRQEN)

The TCDCIRQEN registerisa 16-bit,read/writeregisterthatenablesinterruptrequestsfrom thecodec. The clocktotheTCDCIRQPNDCLR registerisenabledwhen any ofthefieldsinthisregisterareset.After reset,thisregisterisclearedto0000h. 7 6 5 4 3 2 1 0 ADCDOWN DACUP ADC2U ADC1UP RGTFIFO LFTFIFO ADC2FIFO ADC1FIFO 15 14 13 12 11 10 9 8 Reserved STCLP MICCLP ZXDR ZXDL DACDOWN ADC2DOWN ADC1FIFO The ADC1 FIFO bitenablesan interruptwhen theADC1 FIFO isfilledtothetrigger levelspecifiedintheTCDCFIFO register,when theFIFO isfull,orwhen theFIFO is empty.SettingtheADC1FIFO bitcausestheDMAADC1 bittobe ignored.(Interruptand DMA requestsaremutuallyexclusive.) 0 – ADC1 FIFO interruptdisabled. 1 – ADC1 FIFO interruptenabled. ADC2FIFO The ADC2 FIFO bitisused totriggeran interruptwhen theADC2 FIFO isfilledtothe triggerlevelspecifiedintheTCDCFIFO register,when theFIFO isfull,orwhen the FIFO isempty.SettingtheADC2FIFO bitcausestheDMAADC2 bittobe ignored. (Interruptand DMA requestsaremutuallyexclusive.) 0 – ADC2 FIFO interruptdisabled. 1 – ADC2 FIFO interruptenabled. LFTFIFO The LeftDAC FIFO bitenablesan interruptwhen theleft-channelDAC FIFO isemptied tothetriggerlevelspecifiedintheTCDCFIFO register,when theFIFO isfull,orwhen theFIFO isempty.SettingtheLFTFIFO bitcausestheDMAL bittobe ignored. (Interruptand DMA requestsaremutuallyexclusive.) 0 – Left-channelFIFO interruptdisabled. 1 – Left-channelFIFO interruptenabled. RGTFIFO The RightDAC FIFO bitenablesan interruptwhen theright-channelDAC FIFO is emptiedtothetriggerlevelspecifiedintheTCDCFIFO register,when theFIFO isfull,or when theFIFO isempty.SettingtheRGTFIFO bitcausestheDMAR bittobe ignored. (Interruptand DMA requestsaremutuallyexclusive.) 0 – Right-channelFIFO interruptdisabled. 1 – Right-channelFIFO interruptenabled. ADC1UP The ADC1 Power-Up bitenablesan interruptwhen ADC1 has powered up. 0 – ADC1 power-upinterruptdisabled. 1 – ADC1 power-upinterruptenabled.

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www.ti.com SNOSCW5 –MAY 2013 ADC2UP The ADC2 Power-Up bitenablesan interruptwhen ADC2 has powered up. 0 – ADC2 power-upinterruptdisabled. 1 – ADC2 power-upinterruptenabled. DACUP The DAC Power-Up bitenablesan interruptwhen thestereoDAC has powered up. 0 – DAC power-upinterruptdisabled. 1 – DAC power-upinterruptenabled. ADC1DOWN The ADC1 Power-Down bitenablesan interruptwhen ADC1 has powered down. 0 – ADC1 power-down interruptdisabled. 1 – ADC1 power-down interruptenabled. ADC2DOWN The ADC2 Power-Down bitenablesan interruptwhen ADC2 has powered down. 0 – ADC2 power-down interruptdisabled. 1 – ADC2 power-down interruptenabled. DACDOWN The DAC Power-Down bitenablesan interruptwhen theDAC has powered down. 0 – DAC power-down interruptdisabled. 1 – DAC power-down interruptenabled. ZXDL The Zero-CrossingDetectorLeftChannelbitenablesan interruptwhen theleft-channel reconstructionfilteroutputcrosseszero.Thisisusefulifthegainofan externalaudio deviceistobe changed.Internalgainsarecontrolledautomaticallyon theseevents. 0 – Zero-crossinginterruptdisabled. 1 – Zero-crossinginterruptenabled. ZXDR The Zero-CrossingDetectorRightChannelbitenablesan interruptwhen theright- channelreconstructionfilteroutputcrosseszero. 0 – Zero-crossinginterruptdisabled. 1 – Zero-crossinginterruptenabled. MICCLP The MicrophoneClippingbitenablesan interruptwhen theDIGMIC1 inputgainstage clips. 0 – Microphoneclippinginterruptdisabled. 1 – Microphoneclippinginterruptenabled. STCLP The SidetoneClippingbitenablesan interruptwhen eithersidetonefeedtotheDACs clip. 0 – Sidetoneclippinginterruptdisabled. 1 – Sidetoneclippinginterruptenabled.

20.10.10 Codec InterruptPending/ClearRegister(TCDCIRQPNDCLR)

The TCDCIRQPNDCLR registerisa 16-bit,read/writeregisterthatindicatesthestateofpendinginterrupt requests.The bitsinthisregistercorrespondtotheinterruptenablebitsintheTCDCIRQEN register.A set bit in the TCDCIRQPNDCLR registerindicatesthat the request is enabled and asserted.The TCDCIRQPNDCLR registerisalsoused by theinterruptserviceroutinetocleartheserequests.Writing1 toa bitinthisregisterclearstherequest.Writing0 has no effect.Afterreset,thisregisterisclearedto 0000h. 7 6 5 4 3 2 1 0 ADC1DOWN DACUP ADC2UP ADC1UP RGTFIFO LFTFIFO ADC2FIFO ADC1FIFO 15 14 13 12 11 10 9 8 Reserved STCLP MICCLP ZXDR ZXDL DACDOWN ADC2DOWN

20.10.11 Codec Compensation FilterC0/4 Tap Register(TCDCCOMP0)

The TCDCCOMP0 registerisa 16-bit,read/writeregisterthatspecifiestheC0 and C4 coefficientsofthe compensationfilter,when theCUSTCOMP bitoftheTCDCDSP registerisset.When theCUSTCOMP bit isclear,theTCDCCOMP0 registerisignored.Afterreset,thisregisterisclearedto0000h Copyright© 2013,Texas InstrumentsIncorporated TelematicsCodec 141 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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20.10.12 Codec Compensation FilterC1/3 Tap Register(TCDCCOMP1)

The TCDCCOMP1 registerisa 16-bit,read/writeregisterthatspecifiestheC1 and C3 coefficientsofthe compensationfilter,when theCUSTCOMP bitoftheTCDCDSP registerisset.When theCUSTCOMP bit isclear,theTCDCCOMP1 registerisignored.Afterreset,thisregisterisclearedto0000h 15 1 COMPC1

20.10.13 Codec Compensation FilterC2 Tap Register(TCDCCOMP2)

The TCDCCOMP2 registeris a 16-bit,read/writeregisterthatspecifiesthe C2 coefficientof the compensationfilter,when theCUSTCOMP bitoftheTCDCDSP registerisset.When theCUSTCOMP bit isclear,theTCDCCOMP2 registerisignored.Afterreset,thisregisterisclearedto0000h 15 1 COMPC2

20.10.14 Codec ADC Data Registern (TCDCADCn)

The TCDCADCn registersare 16-bit,read-onlyregistersused tounloada word from thecorresponding ADC FIFOs.Afterreset,theseregistersareclearedto0000h 15 1 ADCDATA

20.10.15 Codec LeftChannel DAC Data Register(TCDCLEFT)

The TCDCLEFT registerisa 16-bit,read/writeregisterused to loada word intothe left-channelDAC FIFO.Afterreset,thisregisterisclearedto0000h 15 1 LEFTDATA

20.10.16 Codec RightChannel DAC Data Register(TCDCRIGHT)

The TCDCRIGHT registerisa 16-bit,read/writeregisterused toloada word intotheright-channelDAC FIFO.Afterreset,thisregisterisclearedto0000h 15 1 RIGHTDATA

20.10.17 Codec Debug Register(TCDCDEBUG)

The TCDCDEBUG registerisa 16-bit,read/writeregisterused toconfiguretheTCIO1 pinand safelyreset thecodec.Afterreset,thisregisterisclearedto0000h. 15 8 7 6 4 3 0 Reserved SFTRST Reserved GPIO GPIO The GPIO fieldconfigurestheTCIO1 pin(alternatefunctionofPG10).

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0000 Input Audioinputclockat256× or512× oversamplingrate

0001 Output ADC1 Clock

0010 Output ADC2 Clock

0011 Output DIGMIC1 Clock

0100 Output DAC Clock

0101 Output ADC1 SerialData Stream

0110 Output ADC2 SerialData Stream

0111 Output LeftChannelDAC SerialData Stream

1000 Output RightChannelDAC SerialData Stream

1001 Output SidetoneLeftOverflow

1010 Output SidetoneRightOverflow

1011 Output DIGMIC Overflow

1100 Output 1

1101 Output 0

1101 N/A Reserved SFTRST The SoftResetbitisused toresetthecodec independentlyofa systemreset.The codec is safelyresetby settingand thenclearingthisbit.Afterthebitiscleared,configuration registersremainunchanged.The ADC and DAC FIFOs areflushed.Pendinginterruptsand DMA requestsarecleared.The ADCs and DAC, ifenabled,entertheirstart-uproutinesto ensureno noise(clickand pop)isheard. 0 – Normal operation. 1 – Softreset.

20.10.18 Codec MonitorControl/StatusRegister(TCDCMONITOR)

The TCDCMONITOR registerisa 16-bit,read/writeregisterthatconfigurestheDC protectionmonitor.The monitorensuresthat,ifthesystem hangs,harmfulDC outputsarenotdriventoexternaldevicessuch as speakers.The monitorisenabledby default.When triggered,itwillflushtheDAC FIFOs.IftheSDE bitis setand thenumber ofDC protectioneventsexceedsa programmablelimit,theprotectionmonitorwillalso shutdown thestereoDAC. Afterreset,thisregisterisclearedto0000h. 15 14 13 11 10 9 0 Reserved SDE SDLIMIT MD DCLIMIT DCLIMIT The DC Limitfieldspecifiesthenumber oftimesa sample can have thesame valuebefore theDC protectionmonitoristriggeredtoprotecttheexternaldevice.Ifthenumber isless than16,a defaultvalueof1023 isused. MD The MonitorDisablebitallowssoftwaretodisablethemonitor.By default,themonitoris enableduntilsoftwaresetsthisbit. 0 – Monitorenabled. 1 – Monitordisabled. SDLIMIT The Shutdown Limitfieldisused tospecifythenumber ofDC protectioneventswhichmay occurbeforethestereoDAC isshutdown. To cleartheshutdowncondition,softwaremust respondtotheDACDOWN interrupt. SDE The Shutdown EnablebitenablesstereoDAC shutdownwhen themonitoristriggered.Ifa shutdowneventoccurs,thestereoDAC remainsshutdown untilthisbitiscleared. 0 – DAC shutdowndisabled. 1 – DAC shutdownenabled. Copyright© 2013,Texas InstrumentsIncorporated TelematicsCodec 143 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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20.11 Usage Notes

The telematicscodec isdesignedformaximum flexibility,thissectiongivesan overviewofrecommended systemsetupsfordifferentapplications.

20.11.1 In-CarBluetoothTelephony

Inthismode, thecodec actsas a bridgebetween a Bluetooth-equippedmobiletelephoneand thecar’s head unit.A GSM phone establishesa linkand transmitsvoice-bandaudiodata inthe CVSD format, whichiswell-suitedtoa noisyenvironment.The dataisreceivedby theBluetoothLLC and passed tothe CVSD decoder.The CVSD convertsthedataintolinear16-bitsamples whicharetransferredtoand from thecodec (possiblythroughtheon-chipDSP). The codec thenperformsthedigital-to-analogand analog- to-digitalconversionand theanaloginterfaceswiththecarradio. Any differencesinsample rateshouldbe acrosstheCVSD linkwhere theypose theleastthreattoaudio quality.The DAC should be used in 8-kHz mode ratherthan implementingan SRC (Sample Rate Conversion)scheme. The codec shouldsharea clocksourcewiththeBluetoothLLC. Data:bidirectionalmono 8-kHz16-bitlinearformat. AudioclockforDAC: 2.000MHz. DACOSR = 00 AudioclockforADC: 1.000MHz.

20.11.2 I2S Music Playback

Inthisexample,theADC isnotused and thedataisprovidedfrom theI2S interface.The I2S interface shouldbe configuredas a slavetoallowthesample ratetobe derivedfromtheexternalsourcedevice.If thesourcesample rateisnot48 kHz,thenSRC isperformedintheDSP coprocessor.The sample rateof theaudiostreammust be known orconveyed by othermeans. Data ismost likelypassed usinginterrupt requests.The SRC must cope withtherateconversionand allowfora toleranceintheinputraterelative to the outputrate,varyingthe algorithmto match the requiredoutputrateby knowing how oftendata arrivesand applyingskew on theinterpolation/decimationwhen required.Thiscan be avoidedby usinga clocksynchronoustotheaudiosourceand usingan oversamplingrateotherthan125. Data:Stereo44.1-kHz16-bitlinearformat. AudioclockforDAC: 12.288MHz. DACOSR = 01.

20.11.3 WirelessMusic Headphones

Inthisexample,theADC isnotused and compressed dataisprovidedfromtheBluetoothlink.The DSP must thenconvertthisdatainto48-kHz,16-bitstereoaudioforuse by theDAC. Data:Stereo48-kHz16-bitlinearformat. AudioclockforDAC: 12.000MHz. DACOSR = 00.

20.11.4 WirelessVoice Headset

In thisexample,the deviceisconfiguredinthe same way as forIn-CarBluetoothTelephony,but the outputmust drivea headphone amplifierratherthanthedifferentiallineoutputs.

20.11.5 MP3 Playback

Thisapplicationuses thestereoDAC toplaybackaudiofrommemory, so a PLL can be used tocreatean approximate11.025MHz clockfor44.1-kHzsampleswith12.000MHz for48-kHzdata. In thisexample, the ADC can be used forthe typicalvoicenotes feature,8-kHz recordingdata in companded formatusingtheCVSD ’s G.711 circuitstocompress thedata,ratherthanusinga DSP for compression.

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20.11.6 VoIP and 3G Telephony

Thisapplicationcan requireG.722 supportwithsample ratesup to16 kHz in16-bitmode. The ADC and DAC must be used attheserateswiththecompressionbeinghandledby a DSP. The delaycaused by the G.722 algorithmand FIFO depthsshouldbe minimizedtoensurethegroupdelayspecificationsaremet.

20.12 Tuning theCompensation Filter

For unusual sample ratesor where the circuitis used to drivea non-linearaudio system, itis straightforwardtocalculatetherequiredcompensationfiltercoefficients.First,replaceallcoefficientswith zero exceptC2, which shouldbe replacedwitha valueof 20000 (toensure thatthe outputfrequency responseisnotlimitedby headroom).Thiseliminatestheeffectofthecompensationfilterand a frequency sweep on theinputtotheDAC willproducetheuncompensated responseofthesystem.The inverseof thisresponsecan then be used to calculatethe requiredcoefficientsusingthe inversediscretefourier transform: (5) In which H D isthe desiredresponse(fromω up to ωcutoff),and n isthe tap number. In practice,this requiresminormanual optimizationofthecoefficientLSBs toobtainacceptablerippleacrossthenewly optimizedpassband.

20.13 ObtainingMaximum DAC SNR

The noiseflooroftheDAC increasesatfrequenciesabove Fs/2and careshouldbe takenatsample rates below 44.1kHz, because thisreducesSNR. For maximum SNR when theDAC isoperatedat8 kHz, a low-passfiltercan be used to limitthe bandwidthof the analogaudiooutputto 4 kHz beforedrivinga systemwithwiderbandwidth. Ifthesame DAC channelisused forboth8 kHz and 44.1/48kHz sample rates,the8-kHz signalcan be interpolatedin softwareto a higherrate.This saves the component costof the externalfilterat the expense ofgroupdelay. These modificationsarenotrequiredintypicalBluetoothapplications,because thesignalnoisefloorisfar higherthan the DAC noiseto 20 kHz, and speaker bandwidthsare not much widerthan 4–6 kHz. It becomes an issuewhen usingdigitalattenuationon voiceband signalsbeforethe DAC. Thisreduces SNR linearlyand therelativenoisecan become audible.Itisrecommended thattheDAC isoperatedat fulldynamicrangeand attenuationisperformedatthelaststageintheanalogsignalpath.

21 USB Controller

The dual-roleUSB controllermay be used as eitherthe host or the peripheralin point-to-point communicationswithanotherUSB device.The USB controllerisa peripheralon theCPU coreAHB bus. An on-chipUSB transceiversupportsfull-speed(12Mbps) operation. The USB controllercomplieswithboththeUSB 2.0specification(full-speedmode) and withtheOn-The- Go supplement to the specification.USB On-The-Go has been introducedto providea low-cost connectivitysolutionforconsumer devicessuch as mobilephones, PDAs, digitalcameras, and MP3 players.Devicesthatare solelyperipheralsinitiatetransfersthrougha SessionRequest Protocol(SRP), whiledual-roledevicessupportbothSRP and HostNegotiationProtocol(HNP). The USB controllerisconfiguredforup toseven endpointpipes,one bidirectionalpipeforEndpoint0 and unidirectionaltransmitand receivepipesforEndpoints1, 2, and 3. The endpointscan be individually programmed forBulk/Interruptor Isochronoustransfers.(Whether these endpointsare used forIN transactionsorforOUT transactionsatany timewilldepend on whetherthedeviceiscurrentlybeingused as a USB peripheraloras thehostforpoint-to-pointcommunicationswithanotherUSB peripheral.) Copyright© 2013,Texas InstrumentsIncorporated USB Controller 145 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

• Host USB TransceiverUSB RAM Combine Endpoints EP0 Control - Function EP1-3 Control Transmit Packet Encode Rx Buff Tx Buff Rx Buff Tx Buff Packet Decode Cycle Control CRC Gen/Check UTM Synchronization Data Sync AHB Bus HS Negotiation Timers HNP/SRP Receive Host Transaction Scheduler Interrupt Control EP Reg. Decoder Common Regs Cycle Control FIFO Decoder CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Each endpointpipe has itsown FIFO buffer.Table 21-1 shows the sizeof each FIFO, which isthe maximum packetsizewhich can be used withthe correspondingendpointpipe.In double-buffermode, themaximum packetsizeisreducedby a factoroftwo. Table21-1.Endpoint FIFO BufferSize ENDPOINT DIRECTION FIFO SIZE (bytes) TRANSFER TYPE

0 Bidirectional 64 Control

1 Transmit 256 Isochronous

1 Receive 256 Isochronous

2 Transmit 64 Bulk/Interrupt

2 Receive 64 Bulk/Interrupt

3 Transmit 64 Bulk/Interrupt

3 Receive 64 Bulk/Interrupt

The USB controllerprovidesallencoding,decoding,and checkingneeded forsendingand receivingUSB packets.ItinterruptstheCPU onlywhen endpointdatahas been successfullytransferred. When actingas thehostforpoint-to-pointcommunications,theUSB controllermaintainsa framecounter and automaticallyschedulesSOF, Isochronous,Interrupt,and Bulktransfers.Italsoincludessupportfor the SRP and HRP protocolsfor point-to-pointcommunications,definedin the USB On-The-Go specification. Figure21-1.USB ControllerBlock Diagram

21.1 Modes ofOperation

The USB controllerhas two main modes ofoperation:

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• PeripheralMode — theUSB controllerencodes,decodes,checks,and directsallUSB packetssentand received.IN transactionsare handled throughthe device’s Tx FIFOs, and OUT transactionsare handledthroughitsRx FIFOs.Ifa FIFO becomes fullduringan OUT transactionorempty duringan IN transaction,a NAK handshake packetisautomaticallyreturnedto the host.A NAK packetisalso returnedforany endpointthathas interruptsdisabled.Peripheralmode isused when the deviceis actingas a peripheralto a standardUSB hostor as a peripheralinpoint-to-pointcommunications. Control,Bulk,Isochronous,and Interrupttransactionsaresupported.
• Host Mode — the USB controlleractsas the hostinpoint-to-pointcommunicationwithanotherUSB device.Inthismode, itcan communicate withanotherdevice(butnota hub),thatsupportsControl, Bulk,Isochronous,or Interrupttransactions.IN transactionsare handledthroughthe Rx FIFOs, and OUT transactionsarehandledthroughtheTx FIFOs.As wellas encoding,decoding,and checkingthe USB packets being sent and received,the USB controllerautomaticallyschedulesIsochronous endpointsand Interruptendpointstoperformone transactioneveryn frames,inwhichn representsthe pollingintervalthathas been programmed forthe endpoint.The remainingbus bandwidthisshared equallyamong theControland Bulkendpoints.Only one downstream devicecan be supportedinHost mode.

21.2 USB Connector Interface

21.2.1 USB 2.0 A full-speedUSB 2.0interfacerequires22Ω seriesresistorson theD+ and D – datasignals,tomeet the impedance specificationforthesesignals,as shown inFigure21-2. Figure21-2.USB 2.0Connector Interface

21.2.2 USB On-The-Go

Additionalsignalsareused toimplementUSB On-The-Go features,as shown inFigure21-3. Copyright© 2013,Texas InstrumentsIncorporated USB Controller 147 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

+3.3V USB OTG Connector UGND DS341 CP3SP33 1 2 3 4 5 VBUS IDPULLUP IDDIG DRVVBUS +3.3V +5V CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure21-3.USB On-The-Go Connector Interface For point-to-pointcommunications,thedevicemay alsobe requiredtopower theVBUS to5V as theA deviceoftheconnection(sourceofpower and defaulthost)or,as theB device(defaultperipheral),tobe abletowake theA deviceby chargingVBUS to2V.A 100kΩ pulldownresistoron theDRVVBUS outputis recommended toensurethatVBUS isnotpulledhighduringreset. Whether theUSB controllerinitiallyoperatesinHost mode orinPeripheralmode depends on whetheritis beingused inan A deviceora B device,whichinturndepends on whethertheIDDIG inputislow orhigh. When the USB controllerisoperatingas an A device,itisinitiallyconfiguredto operateinHost mode. When operatingas a B device,the USB controllerisinitiallyconfiguredto operateinPeripheralmode. However,theHOSTREQ bitintheDEVCTL registercan be used torequestthata B devicebecomes the Hostthenexttimethereisno activityon theUSB bus. The IDDIG inputreflectsthestateoftheID pinofthedevice’s mini-ABreceptacle,withIDDIG beinglow indicatingan A plugand operationas an A device,and IDDIG beinghighindicatinga B plugand operation as a B device. Informationon whethertheUSB controllerisactingas an A deviceor as a B deviceisindicatedinthe DEVCTL register,alongwithinformationabout the levelof VBUS relativeto the highand low voltage thresholdsused tosignalSessionStartand SessionEnd.

21.3 USB ControllerRegisterSet

The USB controllercommon registersaffectallendpoints.In addition,foreach endpointthereisan endpoint-specificregisterbank.There isan indexedaddressingmechanism foraccessingtheendpoint- specificregisterbanks,and therearealsonon-indexedimages ofeach registerbank.Eithertheindexed or the non-indexedimages may be used to access these registers.The INDEX registerselectsthe registerbank accessibleintheimage atFF 0810h. Table21-2liststheUSB controllercommon registers,Table21-3liststheendpoint-specificregistersina bank,and Table21-4liststheregisterbanks. Table21-2.USB Common InterfaceRegisters NAME ADDRESS DESCRIPTION FADDR FF 0800h FunctionAddressRegister POWER FF 0801h Power Management Register INTRTX FF 0802h InterruptRegisterforEndpoint0 and Tx Endpoints1-3 INTRRX FF 0804h InterruptRegisterforRx Endpoints1-3

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www.ti.com SNOSCW5 –MAY 2013 Table21-2.USB Common InterfaceRegisters(continued) NAME ADDRESS DESCRIPTION INTRTXE FF 0806h InterruptEnableRegisterforINTRTX INTRRXE FF 0808h InterruptEnableRegisterforINTRRX INTRUSB FF 080Ah InterruptRegisterforUSB Common Interrupts INTRUSBE FF 080Bh InterruptEnableRegisterforINTRUSB FRAME FF 080Ch Frame Number Register INDEX FF 080Eh IndexRegister EP0FIFO FF 0820h Endpoint0 FIFO EP1FIFO FF 0824h Endpoint1 FIFO EP2FIFO FF 0828h Endpoint2 FIFO EP3FIFO FF 082Ch Endpoint3 FIFO DEVCTL FF 0860h USB OTG DeviceControlRegister VCTRL FF 0C00h USB TransceiverControlRegister VSTATUS FF 0C02h USB TransceiverStatusRegister Table21-3.USB Endpoint-SpecificInterfaceRegisters NAME ADDRESS DESCRIPTION TXMAXP base + 00h TransmitMaximum PacketSizeRegister CSR0 base + 02h Controland StatusRegister(Endpoint0) TXCSR base + 02h TransmitControland StatusRegister(Endpoints1-3) RXMAXP base + 04h ReceiveMaximum PacketSizeRegister RXCSR base + 06h ReceiveControland StatusRegister COUNT0 base + 08h ReceiveCount Register(Endpoint0) RXCOUNT base + 08h ReceiveCount Register(Endpoints1-3) TXTYPE base + 0Ah TransmitTransferType Register NAKLIMIT0 base + 0Bh NAK LimitRegister(Endpoint0) TXINTERVAL base + 0Bh TransmitPollingIntervalRegister(Endpoints1-3) RXTYPE base + 0Ch ReceiveTransferType Register RXINTERVAL base + 0Dh ReceivePollingIntervalRegister(Endpoints1-3) Table21-4.USB Endpoint RegisterBanks NAME BASE DESCRIPTION ADDRESS INDEXED FF 0810h IndexedRegisterBank EP0NIND FF 0900h Endpoint0 RegisterBank EP1NIND FF 0910h Endpoint1 RegisterBank EP2NIND FF 0920h Endpoint2 RegisterBank EP3NIND FF 0930h Endpoint3 RegisterBank Copyright© 2013,Texas InstrumentsIncorporated USB Controller 149 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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21.3.1 FunctionAddress Register(FADDR)

The FADDR registeris an 8-bit,read/writeregisterthatholds the functionaddress.When the USB controlleris in Host mode, thisregistershould be loaded withthe value sent in a SET_ADDRESS command duringdeviceenumerationas theaddressfortheperipheraldevice.When theUSB controlleris being used in Peripheralmode, thisregistershould be loaded withthe address receivedthrougha SET_ADDRESS command, which willthen be used fordecodingthe functionaddress in subsequent tokenpackets.The new addresswillnottakeeffectimmediately,because thehostwillstillbe usingthe oldaddressforthe Statusstageof the devicerequest.The USB controllerwillcontinueto use the old addressfordecodingpacketsuntilthedevicerequesthas completed.At reset,thisregisterisclearedto 00h. 7 6 0 Reserved FUNCADDR FUNCADDR The FunctionAddressfieldholdsthe7-bitaddressoftheperipheralpartofthe transaction.

21.3.2 Power Register(POWER)

The POWER registerisan 8-bit,read/writeregisterthatisused forcontrollingSuspend and Resume signaling,and some basicoperationalaspectsoftheUSB controller.At reset,thisregisterisinitializedto 20h. 7 6 5 4 3 2 1 0 Reserved ReservedISOUPDATE SOFTCONN RESET RESUME SUSPENDMODE ENABLESUSPENDM(Mustbe 0) (Mustbe 0) ENABLESUSPENDM The EnableSuspend Mode bitisused toshutdown theUSB transceiverin Suspend mode tosave power. 0 – USB transceiveralwaysenabled. 1 – USB transceiverdisabledinSuspend mode. SUSPENDMODE The Suspend Mode bitissetby softwaretoenterSuspend mode (Hostmode) orby hardwarewhen Suspend mode isentered(Peripheralmode).Itwillbe clearedwhen theINTRUSB registerisread(asa resultofreceivinga Suspend interrupt).Itwillalsobe clearedifSuspend mode isexitedby settingthe Resume bittoinitiatea remotewake-up. 0 – Suspend mode has notbeen entered. 1 – Suspend mode has been entered(Peripheralmode),orsoftwarehas requestedentryintoSuspend mode (Hostmode). RESUME The Resume bitissetby softwaretogenerateResume signalingon theUSB to performremotewake-up fromSuspend mode. Once set,itshouldbe leftsetfor approximately10 ms (atleast1 ms and no more than15 ms),thencleared.In Hostmode, thisbitissetby hardwarewhen Resume signalingfromthe peripheralisdetectedwhiletheHostisinSuspend mode. 0 – No Resume signaling. 1 – GenerateResume signalingorResume signalingdetected. RESET The Resetbitcan be used todeterminewhen Resetsignalingispresenton the USB. Itissetwhen Resetsignalingisdetectedand remainssetuntilthebus revertstoan idlestate.Thisbitisread/writeinHostmode, and readonlyin Peripheralmode. 0 – No Resetsignalingdetected. 1 – Resetsignalingdetected.

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www.ti.com SNOSCW5 –MAY 2013 SOFTCONN The SoftConnect/Disconnectbitcan be used when theUSB controllerisacting as a peripheraltoswitchtheUSB transceiverbetween normalmode and non- drivingmode. As a result,itcan be used toconnect/disconnectthedevicefrom itshostwithouthavingthechange thephysicalconnections,when thedeviceis actingas a peripheral.Aftera hardwarereset,theSOFTCONN bitisclear.The USB controllerwillthereforeappeardisconnecteduntilthesoftwarehas setthe SOFTCONN bit.Softwarecan thenchoose when tosetthetransceiverintoits normalmode. Systems witha lengthyinitializationproceduremay use thisto ensurethatinitializationiscompleteand thesystemisreadytoperform enumerationbeforeconnectingtotheUSB. AftertheSOFTCONN bithas been set,clearingthisbitwillputthetransceiverintonon-drivingmode. The USB controllerwillthenappeartohave been disconnectedtootherdeviceson the USB bus.ThisbitisonlyvalidinPeripheralmode. 0 – USB transceiverisinnon-drivingmode. 1 – USB transceiverisenabledtodriveD+ and D-. ISOUPDATE The IsochronousUpdate bitonlyaffectsIN Isochronousendpoints(Endpoint1). Itisnormallyused as a method ofensuringa “clean”start-upofan IN Isochronouspipe.When set,theUSB controllerwillwaitforan SOF tokenfrom thetimeTXPKTRDY issetbeforesendingthepacket.Ifan IN tokenisreceived beforean SOF token,thena zero-lengthdatapacketwillbe sent.Thisbitisonly validinPeripheralmode. 0 – Normal mode. 1 – Isochronousupdatemode.

21.3.3 InterruptRegisterforEndpoint 0 and TransmitEndpoints (INTRTX)

The INTRTX registerisa 16-bit,read-onlyregisterthatindicateswhichinterruptsarecurrentlyassertedfor Endpoint0 and theTransmitEndpoints1,2,and 3.Bitsforendpointsthathave notbeen configuredwill alwaysreturn0.Allassertedinterruptsare clearedwhen thisregisterisread.Afterreset,thisregisteris clearedto0000h. 15 4 3 2 1 0 Reserved EP3TX EP2TX EP1TX EP0 EP0 The Endpoint0 bitindicatesthatan interruptwas assertedforEndpoint0. 0 – No interruptasserted. 1 – Interruptasserted. EPnTX The Endpointn Transmitbitindicatesthatan interruptwas assertedforTransmitEndpointn (n= 1 to3). 0 – No interruptasserted. 1 – Interruptasserted.

21.3.4 InterruptRegisterforReceive Endpoints (INTRRX)

The INTRRX registerisa 16-bit,read-onlyregisterthatindicateswhich interruptsare currentlyasserted forReceiveEndpoints1,2,and 3.Bitsforendpointsthathave notbeen configuredwillalwaysreturn0.All assertedinterruptsareclearedwhen thisregisterisread.Afterreset,thisregisterisclearedto0000h. 15 4 3 2 1 0 Reserved EP3RX EP2RX EP1RX Reserved Copyright© 2013,Texas InstrumentsIncorporated USB Controller 151 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com EPnRX The Endpointn Receivebitindicatesthatan interruptwas assertedforReceiveEndpointn (n = 1 to3). 0 – No interruptasserted. 1 – Interruptasserted.

21.3.5 InterruptEnable RegisterforEndpoint 0 and TransmitEndpoints (INTRTXE)

The INTRTXE registerisa 16-bit,read/writeregisterthatcontrolswhether interruptsare enabled for Endpoint0 and theTransmitEndpoints1,2,and 3.Bitsforendpointsthathave notbeen configuredwill alwaysreturn0.Afterreset,thisregisterisinitializedto000Fh. 15 4 3 2 1 0 Reserved EP3TX EP2TX EP1TX EP0 EP0 The Endpoint0 bitcontrolswhetheran interruptisenabledforEndpoint0. 0 – No interruptenabled. 1 – Interruptenabled. EPnTX The Endpointn Transmitbitcontrolswhetheran interruptisenabledforTransmitEndpointn (n= 1 to3). 0 – No interruptenabled. 1 – Interruptenabled.

21.3.6 InterruptEnable RegisterforReceive Endpoints (INTRRXE)

The INTRRXE registerisa 16-bit,read/writeregisterthatcontrolswhether interruptsare enabled for ReceiveEnd-points1,2,and 3.Afterreset,thisregisterisinitializedto000Eh. 15 4 3 2 1 0 Reserved EP3RX EP2RX EP1RX Reserved EPnRX The Endpointn Receivebitcontrolswhetheran interruptisenabledforReceiveEndpointn (n= 1 to3). 0 – No interruptenabled. 1 – Interruptenabled.

21.3.7 InterruptRegisterforUSB Controller(INTRUSB)

The INTRUSB registerisan 8-bit,read-onlyregisterthatindicateswhichinterruptsarecurrentlyasserted forthe USB controller.Allassertedinterruptsare clearedwhen thisregisterisread.Afterreset,this registerisclearedto00h. 7 6 5 4 3 2 1 0 VBUSERROR SESSREQ DISCON CONN SOF RESETBABBLE RESUME SUSPEND SUSPEND The Suspend bitindicatesthatan interruptwas assertedbecause Suspend signaling was detectedon thebus.ThisbitisonlyvalidinPeripheralmode. 0 – No interruptasserted. 1 – Interruptasserted. RESUME The Resume bitindicatesthatan interruptwas assertedbecause Resume signaling was detectedwhiletheUSB Controllerwas inSuspend mode. 0 – No interruptasserted. 1 – Interruptasserted. RESETBABBLE The Reset/Babblebitindicatesthatan interruptwas assertedbecause babblewas detected(unexpectedbus activity)inHostmode orresetsignalingwas detectedin Peripheralmode. 0 – No interruptasserted. 1 – Interruptasserted.

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www.ti.com SNOSCW5 –MAY 2013 SOF The StartofFrame bitindicatesthatan interruptwas assertedbecause a new frame started. 0 – No interruptasserted. 1 – Interruptasserted. CONN The Connectionbitindicatesthatan interruptwas assertedbecause a device connectionwas detected.ThisbitisonlyvalidinHostmode. 0 – No interruptasserted. 1 – Interruptasserted. DISCON The Disconnectbitindicatesthatan interruptwas assertedbecause a device disconnectwas detectedinHostmode ora sessionended inPeripheralmode. 0 – No interruptasserted. 1 – Interruptasserted. SESSREQ The SessionRequestbitindicatesthatan interruptwas assertedbecause a Session Requestsignalwas detectedon thebus.Thisbitisonlyvalidwhen theUSB controllerisan A device. 0 – No interruptasserted. 1 – Interruptasserted. VBUSERROR The VBUS Errorbitindicatesthatan interruptwas assertedbecause VBUS dropped belowtheVBUS Validthresholdduringa session.Thisbitisonlyvalidwhen theUSB controllerisan A device. 0 – No interruptasserted. 1 – Interruptasserted.

21.3.8 InterruptEnable RegisterforUSB Controller(INTRUSBE)

The INTRUSBE registerisan 8-bit,read/writeregisterthatcontrolswhich USB controllerinterruptsare enabled.Afterreset,thisregisterisinitializedto06h. 7 6 5 4 3 2 1 0 VBUSERROR SESSREQ DISCON CONN SOF RESETBABBLE RESUME SUSPEND SUSPEND The Suspend bitenablesan interruptwhen Suspend signalingisdetectedon thebus. ThisbitisonlyvalidinPeripheralmode. 0 – No interruptenabled. 1 – Interruptenabled. RESUME The Resume bitenablesan interruptwhen Resume signalingisdetectedwhilethe USB ControllerisinSuspend mode. 0 – No interruptenabled. 1 – Interruptenabled. RESETBABBLE The Reset/Babblebitenablesan interruptwhen babbleisdetected(unexpectedbus activity)inHostmode orresetsignalingisdetectedinPeripheralmode. 0 – No interruptenabled. 1 – Interruptenabled. SOF The StartofFrame bitenablesan interruptwhen a new framestarts. 0 – No interruptenabled. 1 – Interruptenabled. CONN The Connectionbitenablesan interruptwhen a deviceconnectionisdetected.Thisbit isonlyvalidinHostmode. 0 – No interruptenabled. 1 – Interruptenabled. Copyright© 2013,Texas InstrumentsIncorporated USB Controller 153 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com DISCON The Disconnectbitenablesan interruptwhen a devicedisconnectisdetectedinHost mode ora sessionisended inPeripheralmode. 0 – No interruptenabled. 1 – Interruptenabled. SESSREQ The SessionRequestbitenablesan interruptwhen a SessionRequestsignalis detectedon thebus.Thisbitisonlyvalidwhen theUSB controllerisan A device. 0 – No interruptenabled. 1 – Interruptenabled. VBUSERROR The VBUS Errorbitenablesan interruptwhen VBUS dropsbelowtheVBUS Valid thresholdduringa session.Thisbitisonlyvalidwhen theUSB controllerisan A device. 0 – No interruptenabled. 1 – Interruptenabled.

21.3.9 Frame Register(FRAME)

The Frame registerisa 16-bit,read-onlyregisterthatholdsthelastreceivedframenumber.At reset,this registerisclearedto0000h. 15 11M M 10 0 Reserved FRAMENUMBER FRAMENUMBER The Frame Number fieldholdsthe11-bitframenumber.

21.3.10 IndexRegister(INDEX)

The Indexregisterisan 8-bit,read/writeregisterthatselectstheendpoint-specificregisterbank which is accessibleintheregionFF 0810h toFF 081Fh.Atreset,thisregisterisclearedto00h. 7 4M M 3 0 Reserved INDEX INDEX The Indexfieldholdsthe4-bitendpointindex.Only0000b,0001b,0010b,and 0011b arevalid values.

21.3.11 Endpoint n FIFO Register(EPnFIFO)

The Endpointn FIFO registersare32-bit,read/writeregistersthataccessthetransmitFIFOs when written and thereceiveFIFOs when read(n= 0 to3). 31 0 FIFODATA

21.3.12 Device ControlRegister(DEVCTL)

The DEVCTL registerisan 8-bit,read/writeregisterthatisused toselectwhethertheUSB Controlleris operatinginPeripheralmode orinHost mode, and forcontrollingand monitoringtheUSB VBus line.After reset,thisregisterisclearedto00h. 7 6 5 4 3 2 1 0 BDEVICE FSDEV LSDEV VBUS HOSTMODE HOSTREQ SESSION

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www.ti.com SNOSCW5 –MAY 2013 SESSION The Sessionbitissetorclearedby softwaretostartorend a session,when operating as an A device.As a B device,thisbitiscontrolledby hardwaretoindicatewhen a sessionstartsand ends.Itisalsosetby softwaretoinitiatetheSessionRequest Protocol,orclearedby softwarewhen inSuspend mode toperforma software disconnect. 0 – Sessiondisabled. 1 – Sessionenabled. HOSTREQ The HostRequestbitissettoinitiatetheHostNegotiationProtocolwhen Suspend mode isentered.Itisclearedwhen HostNegotiationiscompleted.Thisbitisonlyvalid as a B device. 0 – No hostnegotiation. 1 – Initiatehostnegotiation. HOSTMODE The HostMode bitindicateswhethertheUSB controllerisinHostorPeripheralmode. Thisisa read-onlybit. 0 – Peripheralmode. 1 – Hostmode. VBUS The VBUS fieldindicatesthecurrentVBUS level.Thisisa read-onlyfield. 00 – Below SessionEnd. 01 – Above SessionEnd,belowAValid. 10 – Above AValid,belowVBusValid. 11 – Above VBusValid. LSDEV The Low-Speed Devicebitindicateswhen a low-speeddeviceisdetected.Low-speed mode isnotsupported.Thisisa read-onlybit. 0 – Low-speed devicenotdetected.1 – Low-speed devicedetected. FSDEV The Full-SpeedDevicebitindicateswhen a full-speeddeviceisdetected.Thisbitis onlyvalidinHostmode. Thisisa read-onlybit. 0 – Full-speeddevicenotdetected. 1 – Full-speeddevicedetected. BDEVICE The B DevicebitindicateswhethertheUSB controllerisoperatingas an A deviceora B device.Thisbitisonlyvalidwhilea sessionisinprogress.Thisisa read-onlybit. 0 – A device. 1 – B device.

21.3.13 Endpoint 0 Controland StatusRegister(CSR0)

The CSR0 registerisa 16-bit,read/writeregisterthatprovidescontroland statusbitsforEndpoint0.Ithas differentformatsinPeripheraland Hostmodes. Afterreset,thisregisterisclearedto0000h. PeripheralMode Format 15 9 8 7 6 5 4 3 2 1 0 Reserve SERVICED SERVICE SEND SETUP DATA SENTFLUSHFIFO TXPKTRDY RXPKTRDYd SETUPEND DRXPKTRDY STALL END END STALL RXPKTRDY The ReceivePacketReady bitissetwhen a datapackethas been received. An interruptisasserted(ifenabled)when thisbitisset.Softwareclearsthe RXPKTRDY bitby writing1 totheSERVICEDRXPKTRDY bit. 0 – No datapacketreceived. 1 – Data packetreceived. TXPKTRDY The TransmitPacketReady bitissetby softwareafterloadinga datapacket intotheFIFO.The bitisclearedautomaticallywhen thedatapackethas been transmitted.An interruptisasserted(ifenabled)when thisbitiscleared. 0 – No packetintransmitFIFO. 1 – Data packetinFIFO,readytotransmit. Copyright© 2013,Texas InstrumentsIncorporated USB Controller 155 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com SENTSTALL The SentSTALL Handshake bitissetwhen a STALL handshake is transmitted.SoftwareclearsthisbittodetectthenextSTALL handshake. 0 – No STALL handshake sincethebitwas lastcleared. 1 – STALL handshake transmitted. DATAEND The Data End bitissetby softwareunderthreecircumstances:when setting theTXPKTRDY bitforthelastdatapacket,when clearingtheRXPKTRDY bit afterunloadingthelastdatapacket,orwhen settingtheTXPKTRDY bitfora zero-lengthdatapacket.The bitisclearedautomatically. 0 – Not theend ofthedata. 1 – Lastorzero-lengthdatapacket. SETUPEND The SetupEnd bitissetwhen a controltransactionends beforetheDATAEND bithas been set.An interruptwillbe assertedand theFIFO flushedatthistime. The bitisclearedby writinga 1 totheSERVICEDSETUPEND bit. 0 – No unexpectedend ofcontroltransaction. 1 – Unexpectedend ofcontroltransaction. SENDSTALL The Send STALL Handshake bitiswrittenwith1 toterminatethecurrent transaction.The STALL handshake willbe transmitted,and thenthisbitwillbe clearedautomatically. 0 – Normal operation. 1 – Write1 tosend theSTALL handshake. SERVICEDRXPKTRDY The ServicedReceivePacketReady bitiswrittenwith1 toclearthe RXPKTRDY bit.The SERVICEDRXPKTRDY bitisclearedautomatically. 0 – Normal state. 1 – Write1 tocleartheRXPKTRDY bit. SERVICEDSETUPEND The ServicedSetupEnd bitiswrittenwith1 tocleartheSETUPEND bit.The SERVICEDSETUPEND bitisclearedautomatically. 0 – Normal state. 1 – Write1 tocleartheSETUPEND bit. FLUSHFIFO The FlushFIFO bitiswrittenwith1 toflushtheEndpoint0 FIFO.The FIFO pointerisresetand theTXPKTRDY/RXPKTRDY bitiscleared.The FLUSHFIFO bithas no effectunlessTXPKTRDY/RXPKTRDY bitisset.The FLUSHFIFO bitisclearedautomatically. 0 – Normal operation. 1 – FlushtheEndpoint0 FIFO and cleartheTXPKTRDY/RXPKTRDY bit. Host Mode Format 15 9 8 7 6 5 4 3 2 1 0 NAKTIME STATUS SETUPReserved FLUSHFIFO REQPKT ERROR RXSTALL TXPKTRDY RXPKTRDYOUT PKT PKT RXPKTRDY The ReceivePacketReady bitissetwhen a datapackethas been received.An interruptisasserted(ifenabled)when thisbitisset.Softwareclearsthisbitafter unloadingthepacketfromtheFIFO todetectthenextpacket. 0 – No datapacketreceived. 1 – Data packetreceived. TXPKTRDY The TransmitPacketReady bitissetby softwareafterloadinga datapacketintothe FIFO.The bitisclearedautomaticallywhen thedatapackethas been transmitted.An interruptisasserted(ifenabled)when thisbitiscleared. 0 – No packetintransmitFIFO. 1 – Data packetinFIFO,readytotransmit.

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www.ti.com SNOSCW5 –MAY 2013 RXSTALL The ReceiveSTALL handshake bitissetwhen a STALL handshake isreceived. SoftwareclearsthisbittodetectthenextSTALL handshake. 0 – No STALL handshake sincethebitwas lastcleared. 1 – STALL handshake received. SETUPPKT The SetupPacketbitissetby softwareatthesame timetheTXPKTRDY bitisset,to selecta SETUP tokeninsteadofan OUT tokenforthetransaction. 0 – OUT tokenselected. 1 – SETUP tokenselected ERROR The Errorbitissetwhen threeattemptshave been made toperforma transaction withno responsefromtheperipheral.An interruptisassertedwhen thisbitisset. Softwareclearsthisbittodetectthenexterrorevent. 0 – No erroreventdetectedsincethebitwas lastcleared. 1 – Erroreventdetected. REQPKT The RequestPacketbitiswrittenwith1 torequestan IN transaction.The REQPKT bitisclearedwhen theRXPKTRDY bitisset. 0 – No requestasserted. 1 – Requestforan IN transactionasserted. STATUSPKT The StatusPacketbitissetby softwareatthesame timeas theTXPKTRDY or REQPKT bitisset,toperforma StatusStagetransaction.Settingthisbitensuresthat thedatatoggleissetto1 so thata DATA1 packetisused fortheStatusStage transaction. 0 – Normal operation. 1 – StatusStagetransactionselected. NAKTIMEOUT The NAK Timeoutbitissetwhen Endpoint0 ishaltedfollowingthereceiptofNAK responsesforlongerthanthetimesetby theNAKLIMIT0 register.Softwaremust clearthisbittoallowtheendpointtocontinue. 0 – Normal operation. 1 – Endpoint0 halted. FLUSHFIFO The FLUSHFIFO bitiswrittenwith1 toflushtheEndpoint0 FIFO.The FIFO pointer isresetand theTXPKTRDY/RXPKTRDY bitiscleared.The FLUSHFIFO bithas no effectunlessTXPKTRDY/RXPKTRDY bitisset. 0 – Normal operation. 1 – FlushtheEndpoint0 FIFO and cleartheTXPKTRDY/RXPKTRDY bit.

21.3.14 Endpoint 0 Count Register(COUNT0)

The COUNT0 registerisan 8-bit,read-onlyregisterthatindicatesthe currentnumber of receiveddata bytesintheEndpoint0 FIFO.The valuechanges as thecontentsoftheFIFO change,and itisonlyvalid whiletheCSR0.RXPKTRDY bitisset.Atreset,thisregisterisclearedto00h. 7 6 0 Reserved COUNT COUNT The Count fieldindicateshow many validbytesareintheEndpoint0 receiveFIFO.

21.3.15 Endpoint 0 NAK LimitRegister(NAKLIMIT0)

The NAKLIMIT0 registerisan 8-bit,read/writeregisterthatspecifiesthenumber offramesafterwhichan Endpoint0 timeoutoccursinHost mode when receivinga streamofNAK responses.(Equivalentsettings forotherendpointscan be made throughtheirTXINTERVAL and RXINTERVAL registers.) The number offramesis2m-1,inwhich m isthevaluespecifiedintheregister.IfthehostreceivesNAK responsesfrom thetargetformore framesthanthenumber representedby thelimitsetinthisregister, theendpointwillbe halted.Atreset,thisregisterisclearedto00h. Copyright© 2013,Texas InstrumentsIncorporated USB Controller 157 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 7 5M M 4 0 Reserved LIMIT LIMIT The LimitfieldspecifiestheEndpoint0 timeout.A valueof0 or1 disablesthetimeoutfunction. Valuesfrom2 to16 (decimal)enablethetimeoutfunction.Valuesabove 16 arereserved.

21.3.16 TransmitMaximum Packet SizeRegister(TXMAXP)

The TXMAXP registerisa 16-bit,read/writeregisterthatspecifiesthemaximum amount ofdatathatcan be transferredthroughtheselectedtransmitendpointina singleframe.Thisvaluemust comply withthe constraintsplaced by the USB Specificationon packet sizes for Bulk,Interruptand Isochronous transactionsinfull-speedoperations.The valueshouldmatch thewMaxPacketSize fieldoftheStandard EndpointDescriptorforthe associatedendpoint(see UniversalSerialBus SpecificationRevision2.0, Chapter 9).A mismatch couldcause unexpectedresults.The valuewrittento thisregistermust not exceed thetransmitFIFO size.Ifthevaluewrittentothisregisterislessthan,orequalto,halfthetransmit FIFO size,two packetscan be buffered.Ifthisregisterischanged afterpacketshave been sentfromthe endpoint,thentheendpointFIFO shouldbe completelyflushed(usingtheFLUSHFIFO bitintheTXCSR register)afterwritingthe new value to the TXMAXP register.There is a TXMAXP registerforeach transmitendpoint(exceptEndpoint0).Atreset,thisregisterisclearedto0000h. 15 11M M 10 0 Reserved MAXSIZE MAXSIZE The Maximum PacketSizefieldspecifies(inbytes)themaximum payloadtransmittedina singletransaction.Validvaluesforthisfieldare8,16,32,and 64 (decimal).

21.3.17 TransmitControland StatusRegister(TXCSR)

The TXCSR registerisa 16-bit,read/writeregisterthatprovidescontroland statusbitsfortheassociated endpoint(exceptEndpoint0).Ithas differentformatsin Peripheraland Host modes. Afterreset,this registerisinitializedto2000h. PeripheralMode Format 7 6 5 4 3 2 1 0 Reserved CLRDATATOG SENTSTALL SENDSTALL FLUSHFIFO UNDERRUN FIFONOTEMPTY TXPKTRDY 15 14 13 12 11 10 9 8 AUTOSET ISO Reserved FRCDATATOG Reserved TXPKTRDY The TransmitPacketReady bitissetby softwareafterloadinga datapacketintothe FIFO.The bitisclearedautomaticallywhen thedatapackethas been transmitted.An interruptisasserted(ifenabled)when thisbitiscleared. 0 – No packetintransmitFIFO. 1 – Data packetinFIFO,readytotransmit. FIFONOTEMPTY The FIFO Not Empty bitindicatesthatthereisatleastone packetinthetransmit FIFO. 0 – TransmitFIFO isempty. 1 – TransmitFIFO isnotempty. UNDERRUN The TransmitUnderrunbitissetwhen an IN tokenisreceivediftheTXPKTRDY bitis clear.SoftwareclearstheUNDERRUN bittodetectthenextunderrunevent. 0 – No underruneventdetectedsincethebitwas lastcleared. 1 – Underruneventdetected.

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www.ti.com SNOSCW5 –MAY 2013 FLUSHFIFO The FLUSHFIFO bitiswrittenwith1 toflushthetransmitFIFO.The FIFO pointeris resetand theTXPKTRDY bitiscleared.The FLUSHFIFO bithas no effectunless TXPKTRDY bitisset.Ifdouble-bufferingisenabled,theFLUSHFIFO bitmay need to be writtentwicetocompletelycleartheFIFO.The FLUSHFIFO bitiscleared automatically. 0 – Normal operation. 1 – FlushthetransmitFIFO and cleartheTXPKTRDY bit. SENDSTALL The Send STALL Handshake bitissettosend a STALL handshake inresponsetoan IN token.Softwaremust clearthisbittoterminatetheSTALL condition.Thisbitis ignoredwhen theendpointisused forisochronoustransfers. 0 – Normal operation. 1 – STALL condition. SENTSTALL The SentSTALL Handshake bitissetwhen a STALL handshake istransmitted.Also, thetransmitFIFO isflushed,and theTXPKTRDY bitiscleared.Softwareclearsthis bittodetectthenextSTALL handshake. 0 – No STALL handshake sincethebitwas lastcleared. 1 – STALL handshake transmitted. CLRDATATOG The ClearData Togglebitiswrittenwith1 toresettheendpointdatatoggleto0. 0 – Normal operation. 1 – Write1 toresetendpointdatatoggleto0. FRCDATATOG The ForceData Togglebitiswrittenwith1 toforcetheendpointdatatoggletoswitch and thedatapackettobe clearedfromtheFIFO,withoutregardtowhetheran ACK was received.Thiscan be used by Interrupttransmitendpointsthatareused to communicateratefeedbackforIsochronousendpoints. 0 – Normal operation. 1 – Write1 toforceendpointdatatotoggle. ISO The IsochronousTransferbitspecifieswhethertheBulk/InterruptorIsochronous transfertypeisused. 0 – Bulk/Interrupttransfertype. 1 – Isochronoustransfertype. AUTOSET The AutomaticSetbitissetby softwaretoenablea mode inwhichtheTXPKTRDY bitisautomaticallysetwhen dataofthemaximum packetsize(valueinTXMAXP register)isloadedinthetransmitFIFO.Ifa packetoflessthanthemaximum packet sizeisloaded,thentheTXPKTRDY bitmust be setexplicitlyby software.The TXPKTRDY bitisalsoautomaticallysetwhen thefirstoftwo packetsinthetransmit FIFO has been sentand thesecond packetisthemaximum packetsize. 0 – Normal mode. 1 – AutomaticallysetTXPKTRDY when maximum packetsizepacketisloadedinto thetransmitFIFO. Host Mode Format 7 6 5 4 3 2 1 0 NAKTIMEOUT CLRDATATOG RXSTALL Reserved FLUSHFIFO ERROR FIFONOTEMPTY TXPKTRDY 15 14 13 12 11 10 9 8 AUTOSET Reserved FRCDATATOG Reserved TXPKTRDY The TransmitPacketReady bitissetby softwareafterloadinga datapacketintothe FIFO.The bitisclearedautomaticallywhen thedatapackethas been transmitted.An interruptisasserted(ifenabled)when thisbitiscleared. 0 – No packetintransmitFIFO. 1 – Data packetinFIFO,readytotransmit. Copyright© 2013,Texas InstrumentsIncorporated USB Controller 159 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com FIFONOTEMPTY The FIFO Not Empty bitindicatesthatthereisatleastone packetinthetransmit FIFO. 0 – TransmitFIFO isempty. 1 – TransmitFIFO isnotempty. ERROR The Errorbitissetwhen threeattemptshave been made tosend a packetand no handshake packethas been received.An interruptisassertedwhen thisbitisset. SoftwareclearstheERROR bittodetectthenexterrorevent.Thisbitisonlyvalidfor Bulkand Interruptendpoints. 0 – No erroreventdetectedsincethebitwas lastcleared. 1 – Erroreventdetected. FLUSHFIFO The FLUSHFIFO bitiswrittenwith1 toflushthetransmitFIFO.The FIFO pointeris resetand theTXPKTRDY bitiscleared.The FLUSHFIFO bithas no effectunless TXPKTRDY bitisset.Ifdouble-bufferingisenabled,theFLUSHFIFO bitmay need to be writtentwicetocompletelycleartheFIFO.The FLUSHFIFO bitiscleared automatically. 0 – Normal operation. 1 – FlushthetransmitFIFO and resettheTXPKTRDY bit. RXSTALL The ReceiveSTALL Handshake bitissetwhen a STALL handshake isreceived.The FIFO pointerisresetand theTXPKTRDY bitiscleared.Softwareclearsthe RXSTALL bittodetectthenextSTALL handshake. 0 – No STALL eventdetectedsincethebitwas lastcleared. 1 – STALL eventdetected. CLRDATATOG The ClearData Togglebitiswrittenwith1 toresettheendpointdatatoggleto0. 0 – Normal operation. 1 – Write1 toresetendpointdatatoggleto0. NAKTIMEOUT The NAK Timeoutbitissetwhen thetransmitendpointishaltedfollowingthereceipt ofNAK responsesforlongerthanthetimesetas theNAK LimitintheTXINTERVAL register.SoftwareclearstheNAKTIMEOUT bittoallowtheendpointtocontinue.This bitisonlyvalidforBulkendpoints. 0 – No NAK timeouteventdetectedsincethebitwas lastcleared. 1 – NAK timeouteventdetected. FRCDATATOG The ForceData Togglebitiswrittenwith1 toforcetheendpointdatatoggletoswitch and thedatapackettobe clearedfromtheFIFO,withoutregardtowhetheran ACK was received.Thiscan be used by Interrupttransmitendpointsthatareused to communicateratefeedbackforIsochronousendpoints. 0 – Normal operation. 1 – Write1 toforceendpointdatatotoggle. AUTOSET The AutomaticSetbitissetby softwaretoenablea mode inwhichtheTXPKTRDY bitisautomaticallysetwhen dataofthemaximum packetsize(valueinTXMAXP register)isloadedinthetransmitFIFO.Ifa packetoflessthanthemaximum packet sizeisloaded,thentheTXPKTRDY bitmust be setexplicitlyby software.The TXPKTRDY bitisalsoautomaticallysetwhen thefirstoftwo packetsinthetransmit FIFO have been sentand thesecond packetisthemaximum packetsize. 0 – Normal mode. 1 – AutomaticallysetTXPKTRDY when maximum packetsizepacketisloadedinto thetransmitFIFO.

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21.3.18 Receive Maximum Packet SizeRegister(RXMAXP)

The RXMAXP registerisa 16-bit,read/writeregisterthatspecifiesthemaximum amount ofdatathatcan be transferredthroughthe selectedreceiveendpointin a singleframe.The value is subjectto the constraintsplacedby theUSB Specificationon packetsizesforBulk,Interrupt,and Isochronoustransfers. The valueshouldmatch thewMaxPacketSize fieldoftheStandardEndpointDescriptorfortheassociated endpoint(see UniversalSerialBus SpecificationRevision2.0, Chapter 9).A mismatch could cause unexpectedresults.The valuewrittentothisregistermust notexceed thereceiveFIFO size.Ifthevalue writtentothisregisterislessthan,or equalto,halfthereceiveFIFO size,two packetscan be buffered. There isa RXMAP registerforeach receiveendpoint(exceptEndpoint0).At reset,thisregisteriscleared to0000h. 15 11M M 10 0 Reserved MAXSIZE MAXSIZE The Maximum PacketSizefieldspecifies(inbytes)themaximum payloadreceivedina singletransaction.

21.3.19 Receive Controland StatusRegister(RXCSR)

The RXCSR registerisa 16-bit,read/writeregisterthatprovidescontroland statusbitsfortheassociated endpoint(exceptEndpoint0).Ithas differentformatsin Peripheraland Host modes. Afterreset,this registerisclearedto0000h. PeripheralMode Format 7 6 5 4 3 2 1 0 CLRDATATOG SENTSTALL SENDSTALL FLUSHFIFO DATAERROR OVERRUN FIFOFULL RXPKTRDY 15 14 13 12 11 10 8 AUTOCLEAR ISO Reserved RXPKTRDY The ReceivePacketReady bitissetwhen a datapacketisreceived.Software shouldclearthisbitwhen thepacketisunloadedfromthereceiveFIFO todetectthe nextpacket.An interruptisasserted(ifenabled)when thisbitisset. 0 – No packetinreceiveFIFO. 1 – Data packetinFIFO,readytounload. FIFOFULL The FIFO Fullbitindicatesthatno more packetscan be loadedintothereceive FIFO. 0 – ReceiveFIFO isnotfull. 1 – ReceiveFIFO isfull. OVERRUN The Overrunbitissetwhen an OUT packetcannotbe loadedintothereceiveFIFO. SoftwareclearstheOVERRUN bittodetectthenextoverrunevent.Thisbitisonly validforIsochronousendpoints. 0 – No overruneventdetectedsincethebitwas lastcleared. 1 – Overruneventdetected. DATAERROR The Data Errorbitissetwhen theRXPKTRDY bitissetand thedatapackethas a CRC orbit-stuffingerror.Softwareclearsthisbittodetectthenextdataerror.This bitisonlyvalidforIsochronousendpoints. 0 – No dataerrorsincethebitwas lastcleared. 1 – Data errordetected. Copyright© 2013,Texas InstrumentsIncorporated USB Controller 161 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com FLUSHFIFO The FLUSHFIFO bitiswrittenwith1 toflushthereceiveFIFO.The FIFO pointeris resetand theRXPKTRDY bitiscleared.The FLUSHFIFO bithas no effectunless RXPKTRDY bitisset.Ifdouble-bufferingisenabled,theFLUSHFIFO bitmay need tobe writtentwicetocompletelycleartheFIFO.The FLUSHFIFO bitiscleared automatically. 0 – Normal operation. 1 – FlushthetransmitFIFO and resettheRXPKTRDY bit. SENDSTALL The Send STALL Handshake bitissetby softwaretoissuea STALL handshake. Softwaremust clearthisbittoterminatetheSTALL condition.Thisbitisignoredfor Isochronousend-points. 0 – Normal operation. 1 – STALL condition. SENTSTALL The SentSTALL Handshake bitissetwhen a STALL handshake istransmitted. SoftwareclearsthisbittodetectthenextSTALL handshake. 0 – No STALL handshake sincethebitwas lastcleared. 1 – STALL handshake transmitted. CLRDATATOG The ClearData Togglebitiswrittenwith1 toresettheendpointdatatoggleto0. 0 – Normal operation. 1 – Write1 toresetendpointdatatoggleto0. ISO The IsochronousTransferbitspecifieswhethertheBulk/InterruptorIsochronous transfertypeisused. 0 – Bulk/Interrupttransfertype. 1 – Isochronoustransfertype. AUTOCLEAR The AutomaticClearbitissetby softwaretoenablea mode inwhichthe RXPKTRDY bitisautomaticallyclearedwhen dataofthemaximum packetsize (valueinRXMAXP register)has been unloadedfromthereceiveFIFO.Ifa packetof lessthanthemaximum packetsizeisunloaded,thentheRXPKTRDY bitmust be setexplicitlyby software. 0 – Normal mode. 1 – AutomaticallyclearRXPKTRDY when maximum packetsizepacketisunloaded fromthereceiveFIFO. Host Mode Format 7 6 5 4 3 2 1 0 DATAERRORCLRDATATOG RXSTALL REQPKT FLUSHFIFO ERROR FIFOFULL RXPKTRDYNAKTIMEOUT 15 14 13 12 11 10 8 AUTOCLEAR AUTOREQ Reserved RXPKTRDY The ReceivePacketReady bitissetwhen a datapackethas been receivedinthe FIFO.Softwareshouldclearthisbitwhen theFIFO isunloadedtodetectthenext packet.An interruptisasserted(ifenabled)when thisbitisset. 0 – No packetinreceiveFIFO. 1 – Data packetinFIFO,readytounload. FIFOFULL The FIFO Fullbitissetwhen no more packetscan be loadedintothereceiveFIFO. 0 – ReceiveFIFO isempty. 1 – ReceiveFIFO isfull.

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www.ti.com SNOSCW5 –MAY 2013 ERROR The Errorbitissetwhen threeattemptshave been made toreceivea packetand no packethas been received.SoftwareclearstheERROR bittodetectthenexterror event.An interruptisassertedwhen thebitisset.ThisbitisonlyvalidforBulkand Interruptendpoints. 0 – No erroreventdetectedsincethebitwas lastcleared. 1 – Erroreventdetected. DATAERROR The DATAERROR bit(Isochronousendpointonly)issetwhen theRXPKTRDY bitis setand thedatapackethas a CRC orbit-stuffingerror.Itisclearwhen the RXPKTRDY bitisclear. 0 – No dataerrorsincethebitwas lastcleared. 1 – Data errordetected. NAKTIMEOUT The NAKTIMEOUT bit(Bulkendpointonly)issetwhen thereceiveendpointis haltedfollowingreceiptofNAK responsesforlongerthanthetimesetas theNAK limitintheRXINTERVAL register.Softwareshouldclearthisbittoallowtheendpoint tocontinue. 0 – No timeout. 1 – NAK timeoutoccurred. FLUSHFIFO The FLUSHFIFO bitiswrittenwith1 toflushthereceiveFIFO.The FIFO pointeris resetand theRXPKTRDY bitiscleared.The FLUSHFIFO bithas no effectunless RXPKTRDY bitisset.Ifdouble-bufferingisenabled,theFLUSHFIFO bitmay need tobe writtentwicetocompletelycleartheFIFO. 0 – Normal operation. 1 – FlushthereceiveFIFO and cleartheRXPKTRDY bit. REQPKT The RequestPacketbitiswrittenwith1 torequestan IN transaction.The REQPKT bitisclearedwhen theRXPKTRDY bitisset. 0 – No requestasserted. 1 – Requestforan IN transactionasserted. RXSTALL The ReceiveSTALL Handshake bitissetwhen a STALL handshake isreceived. SoftwareclearstheRXSTALL bittodetectthenextSTALL handshake.An interrupt isasserted(ifenabled)when thisbitisset. 0 – No STALL handshake detectedsincethebitwas lastcleared. 1 – STALL handshake detected. CLRDATATOG The ClearData Togglebitiswrittenwith1 toresettheendpointdatatoggleto0. 0 – Normal operation. 1 – Write1 toresetendpointdatatoggleto0. AUTOREQ The AutomaticRequestbitspecifieswhethertheREQPKT bitisautomaticallyset when theRXPKTRDY bitiscleared. 0 – Automaticrequestisdisabled. 1 – Automaticrequestisenabled. AUTOCLEAR The AutomaticClearbitissetby softwaretoenablea mode inwhichthe RXPKTRDY bitisautomaticallyclearedwhen dataofthemaximum packetsize (valueinRXMAXP register)isunloadedfromthereceiveFIFO.Ifa packetofless thanthemaximum packetsizeisunloaded,thentheRXPKTRDY bitmust be set explicitlyby software. 0 – Normal mode. 1 – AutomaticallyclearRXPKTRDY when maximum packetsizepacketisunloaded fromthereceiveFIFO. Copyright© 2013,Texas InstrumentsIncorporated USB Controller 163 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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21.3.20 Receive Count Register(RXCOUNT)

The RXCOUNT registerisa 16-bit,read-onlyregisterthatindicatesthecurrentnumber ofreceiveddata bytesinthe receiveFIFO. The valuechanges as the contentsof the FIFO change,and itisonlyvalid whiletheRXPKTRDY bitisset.Atreset,thisregisterisclearedto0000h. 15 13M M 12 0 Reserved COUNT COUNT The Count fieldindicateshow many validbytesareinthereceiveFIFO.

21.3.21 TransmitTransferType Register(TXTYPE)

The TXTYPE registerisan 8-bit,read/writeregisterthatmust be writtenwiththeendpointnumber tobe targetedby theendpointand thetransactionprotocoltouse forthecurrentlyselectedtransmitendpoint. There isa TXTYPE registerforeach endpoint(exceptEndpoint0).Thisregisterisonlyused inHost mode. Atreset,thisregisterisclearedto00h. 7 6 5 4 3 0 Reserved PROTOCOL ENDPOINT ENDPOINT The Endpointfieldspecifiesthetargetendpoint.Softwaremust setthisvaluetothe endpointnumber containedinthetransmitendpointdescriptorreturnedduringdevice enumeration. PROTOCOL The Protocolfieldspecifiestheprotocolforthetransmitendpoint. 00 – Reserved. 01 – Isochronous. 10 – Bulk. 11 – Interrupt.

21.3.22 TransmitIntervalRegister(TXINTERVAL)

The TXINTERVAL registerisan 8-bit,read/writeregisterthatspecifiesthepollingintervalforthecurrently selectedtransmitendpoint,forInterruptand Isochronousendpoints.For Bulk endpoints,thisregister specifiesthe number of frames afterwhich the endpointshouldtimeouton receivinga stream of NAK responses.There isa TXINTERVAL registerforeach endpoint(exceptEndpoint0).Thisregisterisonly used inHostmode. Atreset,thisregisterisclearedto00h. 7 0 INTERVAL/TIMEOUT INTERVAL/TIMEOUT The INTERVAL/TIMEOUT fieldspecifiesa number offrames.The valueis interpreteddifferentlydependingon thetransfertype. TRANSFER TYPE VALID VALUES (n) NUMBER OF FRAMES Interrupt 1-255 n Iso. 1-16 2n-1 Bulk 2-16(0or1 disablesNAK function) 2n-1

21.3.23 Receive TransferType Register(RXTYPE)

The RXTYPE registerisan 8-bit,read/writeregisterthatmust be writtenwiththeendpointnumber tobe targetedby theendpointand thetransactionprotocoltouse forthecurrentlyselectedreceiveendpoint. There isa RXTYPE registerforeach endpoint(exceptEndpoint0).ThisregisterisonlyvalidinHost mode. Atreset,thisregisterisclearedto00h.

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www.ti.com SNOSCW5 –MAY 2013 15 6 5 4 3 0 Reserved PROTOCOL ENDPOINT ENDPOINT The Endpointfieldspecifiesthetargetendpoint.Softwaremust setthisvaluetothe endpointnumber containedinthereceiveendpointdescriptorreturnedduringdevice enumeration. PROTOCOL The Protocolfieldspecifiestheprotocolforthereceiveendpoint. 00 – Reserved. 01 – Isochronous. 10 – Bulk. 11 – Interrupt.

21.3.24 Receive IntervalRegister(RXINTERVAL)

The RXINTERVAL registerisan 8-bit,read/writeregisterthatspecifiesthepollingintervalforthecurrently selectedreceiveendpoint,forInterruptand Isochronousendpoints.For Bulk endpoints,thisregister specifiesthe number of frames afterwhich the endpointshouldtimeouton receivinga stream of NAK responses.There isa RXINTERVAL registerforeach endpoint(exceptEndpoint0).Thisregisterisonly validinHostmode. Atreset,thisregisterisclearedto00h. 7 0 INTERVAL/TIMEOUT INTERVAL/TIMEOUT INTERVAL/TIMEOUT fieldspecifiesa number offrames.The valueis interpreteddifferentlydependingon thetransfertype. TRANSFER TYPE VALID VALUES (n) NUMBER OF FRAMES Interrupt 1-255 n Iso. 1-16 2n-1 Bulk 2-16(0or1 disablesNAK function) 2n-1

21.3.25 USB TransceiverControlRegister(VCTRL)

The VCTRL registerisa 16-bit,read/writeregisterused to providethe addressforaccessingthe USB transceivercontrolregisters.These registersareonlyaccessiblethroughthisregister-basedinterface.The VCTRL registeralsoprovidesdataforwritestothoseregisters.Atreset,thisregisterisclearedto0000h. 15 14 8 7 0 DWEN ADDRESS DATA DATA The Data fieldspecifiesthedataloadedintotheaddressedregisterwhen writesare performed. ADDRESS The Addressfieldspecifiestheregisteraddress.The onlyvalidaddressis: 01h – PTCI_SUSPCTRL. DWEN The Data WriteEnablebitcontrolswhethertheaddressedregisteriswrittenwiththedata. 0 – Writedisabled. 1 – Writeenabled.

21.3.26 USB TransceiverStatusRegister(VSTATUS)

The VSTATUS registeris an 8-bit,read-onlyregisterthatreturnsthe data in the addressed USB transceivercontrolregister.Atreset,thisregisterisclearedto00h. Copyright© 2013,Texas InstrumentsIncorporated USB Controller 165 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 7 0 VSTATUS VSTATUS The VSTATUS fieldreturnsthedataintheregisteraddressedby theVCTRL register.

21.3.27 USB Suspend ControlRegister(PTCI_SUSPCTRL)

The PTCI_SUSPCTRL registerisan 8-bit,write-onlyregisterwhich providesan interfaceforforcingthe USB transceiverand OTG signalsintoSuspend mode. Atreset,thisregisterisclearedto00h. 7 4 3 2 1 0 Reserved SUSPOTG_CTRL SUSP_CTRL FORCE_SUSP FORCE_SUSPOTG FORCE_SUSPOTG The ForceSuspend OTG bitforcestheUSB OTG signalsintoSuspend mode, when selectedby theSUSPOTG_CTRL bit. 0 – Normal operation. 1 – Suspend mode. FORCE_SUSP The ForceSuspend bitforcestheUSB transceiverintoSuspend mode, when selectedby theSUSP_CTRL bit. 0 – Normal operation. 1 – Suspend mode SUSP_CTRL The Suspend ControlbitselectswhethertheUSB logicortheFORCE_SUSP bit controlsSuspend mode fortheUSB transceiver. 0 – USB logic. 1 – FORCE_SUSP bit. SUSPOTG_CTRL The Suspend OTG bitselectswhethertheUSB logicortheFORCE_SUSPOTG bitcontrolsSuspend mode fortheUSB OTG signals. 0 – USB logic. 1 – FORCE_SUSPOTG bit.

22 Dual CAN Interfaces

Each CAN interfacecontainsa FullCAN class,CAN (ControllerArea Network)serialbus interfacefor low/highspeed applications.Itsupportsreceptionand transmissionof extended frames witha 29-bit identifier,standardframeswithan 11-bitidentifier,applicationsthatrequirehighspeed (up to1 MBit/s), and a low-speedCAN interfacewithCAN mastercapability.Data transferbetween theCAN bus and the CPU ishandledby 15 message buffersper interface,which can be individuallyconfiguredas receiveor transmitbuffers.Everymessage bufferincludesa status/controlregisterwhichprovidesinformationabout itscurrentstatusand capabilitiesto configurethe buffer.Allmessage buffersare able to assertan interrupton the receptionof a validframe or the successfultransmissionof a frame.In addition,an interruptcan be generatedon bus errors. An incomingmessage isonlyacceptedifthemessage identifierpasses one oftwo acceptancefiltering masks. The filteringmask can be configuredtoreceivea singlemessage ID foreach bufferora groupof IDs foreach receivebuffer.One ofthebuffersuses a separatemessage filteringprocedure.Thisprovides the capabilityto establisha BASIC-CAN path. Remote transmissionrequestscan be processed automaticallyby automaticreconfigurationto a receiveraftertransmissionor by automated transmit schedulingupon reception.A prioritydecoder allowsany bufferto have one of 16 transmitpriorities includingthehighestorlowestabsolutepriority,fora totalof240 differenttransmitpriorities. A decidedbittimecounter(16-bitwide)isprovidedtosupportrealtimeapplications.The contentsofthis counterare capturedintothe message bufferRAM on receptionor transmission.The countercan be synchronizedthroughtheCAN network.Thissynchronizationfeatureallowsa resetofthecounterafter thereceptionortransmissionofa message inbuffer0.

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www.ti.com SNOSCW5 –MAY 2013 The CAN modules are fastAPB bus peripheralswhich allowsingle-cycleread/writeaccess.The CPU controlsthe CAN modules by programming the registersin the CAN registerblocks.This includes initializationoftheCAN baud rate,logicleveloftheCAN pins,and enable/disableoftheCAN modules.A setofdiagnosticfeatures,such as loopback,listenonly,and erroridentification,supportdevelopmentwith theCAN modules and providea sophisticatederrormanagement tool. The CAN modules implementthefollowingfeatures:

• CAN specification2.0B – Standarddataand remoteframes – Extendeddataand remoteframes – 0 to8 bytesdatalength – Programmable bitrateup to1 Mbit/s
• 15 message buffers,each configurableas receiveortransmitbuffers – Message buffersare16-bitwideRAM mapped tothelowerwords ofa 32-bitwidememory space – One buffermay be used as a BASIC-CAN path
• Remote Frame support – Automatictransmissionafterreceptionofa Remote TransmissionRequest(RTR) – Autoreceiveaftertransmissionofa RTR
• Acceptancefiltering – Two filteringcapabilities:globalacceptancemask and individualbufferidentifiers – One ofthebuffersuses an independentacceptancefilteringprocedure
• Programmable transmitpriority
• Interruptcapability – One interruptvectorforallmessage buffersineach module (receive/transmit/error) – Each interruptsourcecan be enabled/disabled
• 16-bitcounterwithtimestamp capabilityon successfulreceptionortransmissionofa message
• Power Save capabilitieswithprogrammableWake-Up overtheCAN bus (alternatesourceforthe Multi-InputWake-Up module)
• Push-pullcapabilityoftheinput/outputpins
• Diagnosticfunctions – Erroridentification – Loopback and listen-onlyfeaturesfortestand initializationpurposes

22.1 FunctionalDescription

As shown in Figure 22-1, the CAN modules consistsof three blocks:the CAN core, interface management, and a RAM containingthemessage buffers. There are two dedicateddevicepins foreach CAN interface,CANnTX forthe transmitoutputand CANnRX forthereceiveinput(n= 0 or1). The CAN coreimplementsthebasicCAN protocolfeaturessuch as bit-stuffing,CRC calculation/checking, and errormanagement. Itcontrolsthe transceiverlogicand createserrorsignalsaccordingto the bus rules.Inaddition,itconvertsthedatastreamfromtheCPU (paralleldata)totheserialCAN bus data. The interfacemanagement block is dividedintothe registerblock and the interfacemanagement processor.The registerblockprovidesthe CAN interfacewithcontrolinformationfrom the CPU and providestheCPU withstatusinformationfromtheCAN module.Additionally,itgeneratestheinterruptto theCPU. The interfacemanagement processorisa statemachine executingtheCPU ’s transmissionand reception commands and controllingthe data transferbetween severalmessage buffersand the RX/TX shift registers. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 167 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

BTL, RX shift, TX shift, CRC CAN CORE INTERFACE MANAGEMENT RAM Bit Stream Processor Error Management Logic Interface Management Processor Acceptance Filtering Interface Management Processor ACCEPTANCE MASKS CONTROL CAN PRESCALER BTL CONFIG TX/RX Message Buffer 0 TX/RX Message Buffer 1 TX/RX Message Buffer 14 CANnRX Wake-Up CRX Control Status Control Data CANnTX CTX 10 DS343 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Fifteen(15)message buffersarememory mapped intoRAM totransmitand receivedatathroughtheCAN bus. Eight16-bitregistersbelong to each buffer.One of the registerscontainscontroland status informationaboutthemessage bufferconfigurationand thecurrentstateofthebuffer.The otherregisters areused forthemessage identifier,a maximum ofup toeightdatabytes,and thetimestamp information. Duringthe receiveprocess,the incomingmessage willbe storedin a hidden receivebufferuntilthe message isvalid.Then,thebuffercontentswillbe copiedintothefirstmessage bufferwhichacceptsthe ID ofthereceivedmessage. Figure22-1.CAN Block Diagram

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22.2 Basic CAN Concepts

Thissectionprovidesa genericoverviewofthebasicconceptsoftheControllerArea Network(CAN). The CAN protocolisa message-based protocolthatallowsa totalof2032 (211 –16)differentmessages in thestandardformatand 512 million(229 – 16)differentmessages intheextendedframeformat. EveryCAN Frame isbroadcaston thecommon bus.Each module receiveseveryframeand filtersoutthe frames which are not requiredforthe module'stask.For example,ifa dashboard sends a requestto switchon headlights,theCAN module responsibleforbrakelightsmust notprocessthismessage. A CAN mastermodule has theabilitytoseta specificbitcalledthe“remote datarequestbit” (RTR) ina frame.Such a message isalsocalleda “Remote Frame”.Itcauses anothermodule,eitheranothermaster or a slavewhich acceptsthisremote frame,to transmita data frame afterthe remote frame has been completed. Additionalmodules can be added toan existingnetworkwithouta configurationchange.These modules can eitherperformcompletelynew functionsrequiringnew data,orprocessexistingdatatoperforma new functionality. As theCAN networkismessage oriented,a message can be used as a variablewhich isautomatically updatedby thecontrollingprocessor.Ifany module cannotprocessinformation,itcan send an overload frame. The CAN protocolallowsseveraltransmittingmodules tostarta transmissionatthesame timeas soon as theydetectthe bus isidle.Duringthe startof transmission,everynode monitorsthe bus lineto detect whetheritsmessage isover-writtenby a message witha higherpriority.As soon as a transmittingmodule detectsanothermodule witha higherpriorityaccessingthebus,itstopstransmittingitsown frame and switchestoreceivemode, as shown inFigure22-2. Figure22-2.CAN Message Arbitration Ifa dataorremoteframelosesarbitrationon thebus due toa higher-prioritizeddataorremoteframe,orif itis destroyedby an errorframe,the transmittingmodule willautomaticallyretransmitituntilthe transmissionissuccessfulorsoftwarehas canceledthetransmitrequest. Ifa transmittedmessage losesarbitration,theCAN module willrestarttransmissionatthenextpossible timewiththemessage whichhas thehighestinternaltransmitpriority. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 169 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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22.2.1 CAN Frame Types

CommunicationviatheCAN bus isbasicallyestablishedby means offourdifferentframetypes:

• Data Frame
• Remote Frame
• ErrorFrame
• OverloadFrame Data and remoteframescan be used inbothstandardand extendedframeformat.Ifno message isbeing transmitted,i.e.,thebus isidle,thebus iskeptatthe“recessive”level. Remote and dataframesarenon-returntozero(NRZ) coded withbit-stuffingineverybitfield,whichholds computableinformationforthe interface,i.e.,startof frame,arbitrationfield,controlfield,data field(if present),and CRC field. Errorand overloadframesarealsoNRZ coded,butwithoutbit-stuffing. Afterfiveconsecutivebitsofthesame value(includinginsertedstuffbits),a stuffbitoftheinvertedvalue isinsertedintothe bitstream by the transmitterand deletedby the receiver.The followingshows the stuffedand destuffedbitstreamforconsecutiveones and zeros.

22.2.2 CAN Frame Fields

Data and remoteframesconsistofthefollowingbitfields:

• StartofFrame (SOF)
• ArbitrationField
• ControlField
• Data Field
• CRC Field
• ACK Field
• EOF Field 22.2.2.1StartofFrame (SOF) The Startof Frame (SOF) indicatesthe beginningof data and remote frames.Itconsistsof a single “dominant” bit.A node isonlyallowedto starttransmissionwhen the bus isidle.Allnodes have to synchronizetotheleadingedge (firstedge afterthebus was idle)caused by theSOF ofthenode which startstransmissionfirst. 22.2.2.2ArbitrationField The Arbitrationfieldconsistsoftheidentifierfieldand theRTR (Remote TransmissionRequest)bit.For extendedframesthereisalsoa SRR (SubstituteRemote Request)and a IDE (IDExtension)bitinserted between ID18 and ID17 oftheidentifierfield.The valueoftheRTR bitis“dominant”ina dataframeand “recessive”ina remoteframe. 22.2.2.3ControlField The Controlfieldconsistsofsixbits.For standardframesitstartswiththeID Extensionbit(IDE)and a reservedbit(RB0).For extendedframes,thecontrolfieldstartswithtwo reservedbits(RB1,RB0).These bitsarefollowedby the4 bitData LengthCode (DLC). The CAN receiveracceptsallpossiblecombinationsofthereservedbits(RB1,RB0).The transmittermust be configuredtosend onlyzeros.

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STANDARD DA TA FRAME (number of bits = 44 + 8N) Control Field Data Field END OF FRAME CRC Field CRC Arbitration Field IDENTIFIER 10 ... 0 11 4 DA TA LENGTH CODE START OF FRA ME ID 10 ID0 RTR IDE RB0 DLC3 DLC d d d d r r r r r r r r r CRC DEL ACK DEL ACKNOWLEDGEMENT Bit Stuffing 8 8 15 168N (0 < N < 8) Note: d = dominant r = recessive DS020 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 22.2.2.4Data Length Code (DLC) The DLC fieldindicatesthenumber ofbytesinthedatafield.Itconsistsoffourbits.The datafieldcan be oflengthzero.The admissiblenumber ofdatabytesfora dataframerangesfrom0 to8. 22.2.2.5Data Field The Data fieldconsistsofthedatatobe transferredwithina dataframe.Itcan contain0 to8 bytes.A remoteframehas no datafield. 22.2.2.6CyclicRedundancy Check (CRC) The CRC fieldconsistsof the CRC sequence followedby the CRC delimiter.The CRC sequence is derivedby thetransmitterfromthemodulo 2 divisionoftheprecedingbitfields,startingwiththeSOF up totheend ofthedatafield,excludingstuff-bits,by thegeneratorpolynomial: x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1 The remainderofthisdivisionistheCRC sequence transmittedoverthebus.On thereceiverside,the module dividesallbitfieldsup totheCRC delimiterexcludingstuffbits,and checks iftheresultiszero. This willthen be interpretedas a validCRC. Afterthe CRC sequence a single“recessive” bitis transmittedas theCRC delimiter. 22.2.2.7ACK Field The ACK fieldistwo bitslongand containstheACK slotand theACK delimiter.The ACK slotisfilledwith a “recessive”bitby thetransmitter.Thisbitisoverwrittenwitha “dominant”bitby everyreceiverthathas receiveda correctCRC sequence. The second bitof the ACK fieldis a “recessive” bitcalledthe acknowledgedelimiter. The End ofFrame fieldclosesa dataand a remoteframe.Itconsistsofseven “recessive”bits.

22.2.3 CAN Frame Formats

22.2.3.1Data Frame The structureofa standarddataframeisshown inFigure22-3.The structureofan extendeddataframe isshown inFigure22-4. Figure22-3.Standard Data Frame Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 171 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

EXTENDED DA TA FRAME (number of bits = 64 + 8N) Control Field Data Field END OF FRAME CRC Field CRC Arbitration Field IDENTIFIER 28 ... 18 11 4 DA TA LENGTH CODE START OF FRAME ID 28 ID18 ID17 ID0 SRR IDE RTR RB1 RB0 DLC3 DLC d r r d d d r r r r r r r r r CRC DEL ACK DEL SCK Bit Stuffing 18 8 1 5 168N (0 < N < 0) IDENTIFIER 17 ... 0 Note: d = dominant r = recessive DS021 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure22-4.Extended Data Frame A CAN dataframeconsistsofthefollowingfields:

• StartofFrame (SOF)
• ArbitrationField+ ExtendedArbitration
• ControlField
• Data Field
• CyclicRedundancy Check Field(CRC)
• AcknowledgmentField(ACK)
• End ofFrame (EOF) 22.2.3.2Remote Frame Figure22-5 shows the structureof a standardremote frame.Figure22-6 shows the structureof an extendedremoteframe.

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EXTENDED REMOTE FRAME (number of bits = 64) Control Field END OF FRAME CRC Field CRC Arbitration Field IDENTIFIER 28 ... 18 Note: d = dominant r = recessive 11 4 DA TA LENGTH CODE START OF FRAME ID 28 ID18 ID17 ID0 SRR IDE RTR RB1 RB0 DLC3 DLC0 d r r r d d r r r r r r r r r CRC DEL ACK DEL SCK 18 15 IDENTIFIER 17 ... 0 DS023 STANDARD REMOTE FRAME (number of bits = 44) Control Field END OF FRAME CRC Field CRC Arbitration Field IDENTIFIER 10 ... 0 START OF FRAME ID 10 ID0 ID3 RTR IDE RB0 d d d d r r r r r r r r r CRC DEL ACK DEL ACKNOWLEDGEMENT 154 DA TA LENGTH CODE DLC3 DLC0 Note: d = dominant r = recessive DS022 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure22-5.Standard Remote Frame Figure22-6.Extended Remote Frame A remote frame is comprised of the followingfields,which is the same as a data frame (see Section22.2.2)exceptforthedatafield,whichisnotpresent.

• StartofFrame (SOF
• ArbitrationField+ ExtendedArbitration
• ControlField
• CyclicRedundancy Check Field(CRC)
• Acknowledgmentfield(ACK)
• End ofFrame (EOF) Note thattheDLC must have thesame valueas thecorrespondingdataframe topreventcontentionon thebus.The RTR bitis“recessive”. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 173 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

< 6 ECHO ERROR FLAG ERROR DELIMITER DA TA FRAME OR REMOVE FRAME An error frame can start anywhere within a frame INTER-FRAME OR OVERLOAD FRAME Note: d = dominant r = recessive dd d d d d d d rr r d r r r r DS024 d r CP3SP33 SNOSCW5 –MAY 2013 www.ti.com 22.2.3.3ErrorFrame As shown inFigure22-7,theErrorFrame consistsoftheerrorflagand theerrordelimiterbitfields.The errorflagfieldisbuiltup fromthevariouserrorflagsofthedifferentnodes.Therefore,itslengthmay vary froma minimum ofsixbitsup toa maximum oftwelvebitsdependingon when a module has detectedthe error.Whenever a biterror,stufferror,form error,or acknowledgment errorisdetectedby a node, the node startstransmissionofan errorflagatthenextbit.Ifa CRC errorisdetected,transmissionofthe errorflagstartsat the bitfollowingthe acknowledge delimiter,unlessan errorflagfora previouserror conditionhas alreadybeen started. Ifa deviceisintheerroractivestate,itcan send a “dominant” errorflag,whilea errorpassivedeviceis onlyallowedtotransmit“recessive” errorflags.Thisisdone topreventtheCAN bus from gettingstuck due toa localdefect.ForthevariousCAN devicestates,refertoSection22.2.4. Figure22-7.ErrorFrame 22.2.3.4Overload Frame As shown inFigure22-8,an overloadframe consistsoftheoverloadflagand theoverloaddelimiterbit fields.The bitfieldshave thesame lengthas theerrorframefield:sixbitsfortheoverloadflagand eight bitsforthedelimiter.The overloadframe can onlybe sentaftertheend offrame (EOF) fieldand inthis way destroysthefixedform oftheintermissionfield.As a result,allothernodes alsodetectan overload conditionand startthetransmissionofan overloadflag.Afteran overloadflaghas been transmitted,the overloadframeisclosedby theoverloaddelimiter. NOTE A CAN module neverinitiatesan overloadframe due toitsinabilitytoprocessan incoming message. However,itisabletorecognizeand respondtooverloadframesinitiatedby other devices.

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INT = Intermission Suspend Transmission is only for error passive nodes. DA TA FRAME OR REMOTE FRAMENote: d = dominant r = recessive r r r DS026 dr r r r r r r r r r r r r r r r r r r OVERLOAD FRAME OVERLOAD FLAG OVERLOAD DELIMITEREND OF FRAME OR ERROR DELIMITER OR OVERLOAD DELIMITER An overload frame can only start at the end of a frame INTER-FRAME SP ACE OR ERROR FRAME Note: d = dominant r = recessive d r r r r DS025 rr r rdddddd CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure22-8.Overload Frame 22.2.3.5InterframeSpace Data and remote frames are separatedfrom everyprecedingframe (data,remote,errorand overload frames)by the interframespace (see Figure22-9).Errorand overloadframes are not preceded by an interframespace;theycan be transmittedas soon as theconditionoccurs.The interframespace consists ofa minimum ofthreebitfieldsdependingon theerrorstateofthenode. Figure22-9.InterframeSpace

22.2.4 ErrorTypes

22.2.4.1BitError A CAN devicewhich iscurrentlytransmittingalsomonitorsthebus.Ifthemonitoredbitvalueisdifferent fromthetransmittedbitvalue,a biterrorisdetected.However,thereceptionofa “dominant”bitinsteadof a “recessive” bitduringthe transmissionof a passiveerrorflag,duringthe stuffedbitstream of the arbitrationfield,orduringtheacknowledgeslotisnotinterpretedas a biterror. 22.2.4.2StuffError A stufferrorisdetectedif6 consecutivebitsoccurwithouta statechange ina message fieldencoded with bitstuffing. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 175 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

11 consecutive 'recessive" bits received (TEC OR REC) > 95 128 occurrences of 11 consecutive 'recessive" bits TEC > 255 ERROR ACTIVE ERROR WARNING ERROR P ASSIVE (TEC AND REC) < 96 (TEC OR REC) > 127 (TEC AND REC) < 128 BUS OFF DS027 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com 22.2.4.3Form Error A form errorisdetected,ifa fixedframe bit(e.g.,CRC delimiter,ACK delimiter)does not have the specifiedvalue.For a receiver,a “dominant”bitduringthelastbitofEnd ofFrame does notconstitutea frameerror. 22.2.4.4BitCRC Error A CRC errorisdetectediftheremainderfromtheCRC calculationofa receivedCRC polynomialisnon- zero. 22.2.4.5Acknowledgment Error An acknowledgment errorisdetectedwhenever a transmittingnode does not get an acknowledgment fromany othernode (i.e.,when thetransmitterdoes notreceivea “dominant”bitduringtheACK frame). 22.2.4.6ErrorStates The devicecan be inone offivestateswithrespecttoerrorhandling(seeFigure22-10). Figure22-10.Bus States 22.2.4.7Synchronize Once a CAN module isenabled,itwaitsfor11 consecutiverecessivebitsto synchronizewiththe bus. Afterthat,a CAN module becomes erroractiveand can participateinthebus communication.Thisstate must also be entered afterwaking-up the device using the Multi-InputWake-Up feature.See Section22.11. 22.2.4.8ErrorActive An erroractiveunitcan participateinbus communicationand may send an active(“dominant”)errorflag. 22.2.4.9ErrorWarning The ErrorWarning stateisa sub-stateofErrorActivetoindicatea heavilydisturbedbus.A CAN module behaves as inErrorActivemode. The deviceisresetintothe ErrorActivemode ifthe valueof both countersislessthan96.

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www.ti.com SNOSCW5 –MAY 2013 22.2.4.10ErrorPassive An errorpassiveunitcan participateinbus communication.However, iftheunitdetectsan erroritisnot allowedto send an activeerrorflag.The unitsends onlya passive(“recessive”) errorflag.A deviceis errorpassivewhen thetransmiterrorcounteror thereceiveerrorcounterisgreaterthan127.A device becoming errorpassivewillsend an activeerrorflag.An errorpassivedevicebecomes erroractiveagain when bothtransmitand receiveerrorcounterarelessthan128. 22.2.4.11Bus Off A unitthatisbus offhas the outputdriversdisabled,i.e.,itdoes not participateinany bus activity.A deviceisbus offwhen thetransmiterrorcounterisgreaterthan255.A bus offdevicewillbecome error activeagainaftermonitoring128 × 11 “recessive” bits(includingbus idle)on thebus.When thedevice goes from“bus off“to“erroractive“,botherrorcounterswillhave a valueof0.

22.2.5 ErrorCounters

There are multiplemechanisms intheCAN protocoltodetecterrorsand inhibiterroneousmodules from disablingallbus activities.Each CAN module includestwo errorcounterstoperformerrormanagement. The receiveerrorcounter(REC) and thetransmiterrorcounter(TEC) are8-bitswide,locatedinthe16-bit wide CANEC register.The countersare modifiedby the CAN module accordingto the ruleslistedin Table 22-1. Thistableprovidesan overviewof the CAN errorconditionsand the behaviorof the CAN module;fora detaileddescriptionoftheerrormanagement and faultconfinementrules,refertotheCAN Specification2.0B. IftheMSB (bit7)oftheREC isset,thenode iserrorpassiveand theREC willnotincrementany further. The Errorcounterscan be readby applicationsoftwareas describedunderSection22.10.15. Table22-1.ErrorCounter Handling CONDITION ACTION Receive ErrorCounter Conditions A receiverdetectsa biterrorduringsendingan activeerrorflag. Incrementby 8 A receiverdetectsa “dominant“bitas thefirstbitaftersendingan errorflag Incrementby 8 Afterdetectingthe14thconsecutive“dominant“bitfollowingan activeerrorflagor Incrementby 8 overloadflag,orafterdetectingthe8thconsecutive“dominant“bitfollowinga passive errorflag.Aftereach sequence ofadditional8 consecutive“dominant”bits. Any othererrorcondition(stuff,frame,CRC, ACK) Incrementby 1 A validreceptionortransmission Decrement by 1 unlesscounterisalready0 TransmitErrorCounter Conditions A transmitterdetectsa biterrorwhilesendingan activeerrorflag Incrementby 8 Afterdetectingthe14thconsecutive“dominant“bitfollowingan activeerrorflagor Incrementby 8 overloadflagorafterdetectingthe8thconsecutive“dominant“bitfollowinga passive errorflag.Aftereach sequence ofadditional8 consecutive‘dominant’bits. Any othererrorcondition(stuff,frame,CRC, ACK) Incrementby 8 A validreceptionortransmission Decrement by 1 unlesscounterisalready0 SpecialerrorhandlingfortheTEC counterisperformedinthefollowingsituations:

• A stufferroroccurs duringarbitration,when a transmitted“recessive” stuffbitis receivedas a “dominant”bit.Thisdoes notleadtoan incrementoftheTEC.
• An ACK-erroroccursinan errorpassivedeviceand no “dominant”bitsaredetectedwhilesendingthe passiveerrorflag.Thisdoes notleadtoan incrementoftheTEC.
• Ifonlyone deviceison thebus and thisdevicetransmitsa message, itwillgetno acknowledgment. Thiswillbe detectedas an errorand the message willbe repeated.When the devicegoes “error passive”and detectsan acknowledgeerror,theTEC counterisnotincremented.Thereforethedevice willnotgo from”errorpassive”tothe“bus off”statedue tosuch a condition. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 177 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

1 to 8 Time Quanta2 to 16 Time Quanta 4 to 25 TIme Quanta SAMPLE POINT TRANSMISSION POINT INTERNAL TIME QUANTA CLOCK ONE TIME QUANTUM

1 TIme

A TIME SEGMENT 1 (TSEG1) TIME SEGMENT 2 (TSEG2) A = synchronization segment (Sync) DS028 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

22.2.6 BitTime Logic

IntheBitTime Logic(BTL),theCAN bus speed and theSynchronizationJump Widthcan be configured by software.The CAN module dividesa nominal bittime intothreetime segments: synchronization segment, time segment 1 (TSEG1), and time segment 2 (TSEG2). Figure22-11 shows the various elementsofa CAN bittime. 22.2.6.1CAN BitTime The number oftimequantaina CAN bit(CAN BitTime) rangesbetween 4 and 25.The sample pointis positionedbetween TSEG1 and TSEG2 and thetransmissionpointispositionedattheend ofTSEG2. Figure22-11.BitTiming TSEG1 includesthepropagationsegment and thephase segment 1 as specifiedintheCAN specification 2.0B.The lengthofthetimesegment 1 intimequanta(tq)isdefinedby theTSEG1[3:0]bits. TSEG2 representsthephase segment 2 as specifiedintheCAN specification2.0B.The lengthoftime segment 2 intimequanta(tq)isdefinedby theTSEG2[3:0]bits. The SynchronizationJump Width (SJW) definesthe maximum number of timequanta (tq)by which a receivedCAN bitcan be shortenedorlengthenedinordertoachieveresynchronizationon “recessive”to “dominant” datatransitionson thebus.IntheCAN implementation,theSJW must be configuredlessor equaltoTSEG1 orTSEG2, whicheverissmaller. 22.2.6.2Synchronization The SynchronizationJump Width (SJW) definesthe maximum number of timequanta (tq)by which a receivedCAN bitcan be shortenedorlengthenedinordertoachievere-synchronizationon “recessive”to “dominant” datatranstionson thebus.IntheCAN implementation,theSJW must be configuredlessor equaltoTSEG1 orTSEG2, whicheverissmaller. However, two CAN nodes neveroperateatexactlythesame clockrate,and thebus signalmay deviate from the idealwaveform due to the physicalconditionsof the network (bus lengthand load).To compensate forthevariousdelayswithina network,thesample pointcan be positionedby programming thelengthofTSEG1 and TSEG2 (seeFigure22-11). Inaddition,two typesofsynchronizationaresupported.The BTL logiccompares theincomingedge ofa CAN bitwith the internalbittiming.The internalbittimingcan be adapted by eitherhard or soft synchronization(re-synchronization). Hard synchronizationisperformedatthebeginningofa new framewiththefallingedge on thebus while thebus isidle.Thisisinterpretedas theSOF. Itrestartstheinternallogic.

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www.ti.com SNOSCW5 –MAY 2013 Softsynchronizationisperformedduringthereceptionofa bitstreamtolengthenor shortentheinternal bittime.Depending on thephase error(e),TSEG1 may be increasedorTSEG2 may be decreasedby a specificvalue,there-synchronizationjump width(SJW). Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 179 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

"NORMAL" BIT TIME NEXT BITTSEG2TSEG1A e PREVIOUS BIT NEXT BITTSEG2SJWTSEG1A BIT TIME LENGTHENED BY SJW CAN Clock DS029 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com The phase errorisgivenby thedeviationoftheedge totheSYNC segment,measured inCAN clocks. The valueofthephase errorisdefinedas: e = 0,iftheedge occurswithintheSYNC segment e > 0,iftheedge occurswithinTSEG1 e < 0,iftheedge occurswithinTSEG2 ofpreviousbit Re-synchronizationisperformedaccordingtothefollowingrules:

• Ifthe magnitudeof e islessthen or equalto the programmed valueof SJW, resynchronizationwill have thesame effectas hardsynchronization.
• Ife > SJW, TSEG1 willbe lengthenedby thevalueoftheSJW (seeFigure22-12).
• Ife < –SJW, TSEG2 willbe shortenedby thevalueSJW (seeFigure22-13). Figure22-12.Resynchronization(e> SJW)

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Quanta Clock (1/tq) ÷ (1+TSEG1+TSEG2)÷ DS031 CKIbusclock (PSC) (1 TSEG1 TSEG2) u PREVIOUS BIT "NORMAL" BIT TIME TSEG2TSEG1A e PREVIOUS BIT BIT TIME SHORTENED BY SJW NEXT BITTSEG2TSEG1A Bus Signal CAN Clock DS030 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure22-13.Resynchronization(e< –SJW)

22.2.7 Clock Generator

The CAN prescaler(PSC) isshown isFigure22-14.ItdividestheCKI inputclockby thevaluedefinedin the CTIM register.The resultingclockiscalledtime quanta clockand definesthe lengthof one time quantum (tq). RefertoSection22.10.7fora detaileddescriptionoftheCTIM register. NOTE PSC isthevalueoftheclockprescaler.TSEG1 and TSEG2 arethelengthoftimesegment 1 and 2 intimequanta. The resultingbus clockcan be calculatedby Equation6: (6) The valuesofPSC, TSEG1, and TSEG2 arespecifiedby thecontentsoftheregistersPSC, TSEG1, and TSEG2 as follows: PSC = PSC[5:0]+ 2 TSEG1 = TSEG1[3:0]+ 1 TSEG2 = TSEG2[2:0]+ 1 Figure22-14.CAN Prescaler Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 181 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

BUFFER_ID Buffer 13 BUFFER_ID GMASK1 GMASK2 Buffer 14 BUFFER_IDBMASK1 BMASK2 DS032 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

22.3 Message Transfer

Each CAN module has access to15 independentmessage buffers,which are memory mapped inRAM. Each message bufferconsistsof8 different16-bitRAM locationsand can be individuallyconfiguredas a receivemessage bufferoras a transmitmessage buffer. A dedicatedacceptancefilteringprocedureenablessoftwareto configureeach bufferto receiveonlya singlemessage ID or a group of messages. One bufferuses an independentfilteringprocedure,which providesthepossibilitytoestablisha BASIC-CAN path. For receptionofdataframeorremoteframes,a CAN module followsa “receiveon firstmatch”rulewhich means thata givenmessage isonlyreceivedby one buffer:the firstone which matches the received message ID. The transmissionofa framecan be initiatedby softwarewritingtothetransmitstatusand priorityregister. An alternateway toschedulea transmissionistheautomaticanswer toremoteframes.Inthelattercase, the CAN module willscheduleeverybufferfortransmissionto respond to remote frames witha given identifieriftheacceptancemask matches.Thisimpliesthata singleremoteframeisabletopollmultiple matchingbuffersconfiguredtorespondtothetriggeringremotetransmissionrequest.

22.4 Acceptance Filtering

Two 32-bitmasks are used to filterunwanted messages from the CAN bus: GMASK and BMASK. Figure22-15shows themask and thebufferscontrolledby themasks. Figure22-15.Acceptance Filtering Acceptancefilteringoftheincomingmessages forthebuffers0...13isperformedby means ofa global filteringmask (GMASK) and by thebufferID ofeach buffer.Acceptancefilteringofincomingmessages for buffer14 isperformedby a separatefilteringmask (BMASK) and by thebufferID ofthatbuffer. Once a receivedobjectiswaitinginthehiddenbuffertobe copiedintoa buffer,theCAN module scansall buffersconfiguredas receivebuffersfora matchingfilteringmask. The buffers0 to 13 are checked in ascendingorderbeginningwithbuffer0.The contentsofthehiddenbufferarecopiedintothefirstbuffer witha matchingfilteringmask. Bitsholdinga 1 in the globalfilteringmask (GMASK) can be representedas a “don’t care” of the associatedbitofeach bufferidentifier,regardlessofwhetherthebufferidentifierbitis1 or0.

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BUFFER_ID1 1010101010101010 BUFFER_ID2 1010110101010 XXXXXXXX10101010 Accepted ID Group 1010110101010 DS034 GMASK1 0000000000000000 GMASK2 0000000000000 BUFFER_ID1 1010101010101010 BUFFER_ID2 1010110101010 1010101010101010 Accepted ID 1010110101010 DS033 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Thisprovidesthecapabilitytoacceptonlya singleID foreach bufferor toaccepta group ofIDs.The followingtwo examplesillustratethedifference.

22.4.1 Example 1:Acceptance ofa SingleIdentifier

Iftheglobalmask isloadedwith00h,theacceptancefilteringofan incomingmessage isonlydetermined by theindividualbufferID.Thismeans thatonlyone message ID isacceptedforeach buffer. Figure22-16.Acceptance ofa SingleIdentifier

22.4.2 Example 2:Receptionofan IdentifierGroup

Set bitsintheglobalmask registerchange thecorrespondingbitstatuswithinthebufferID to“don’tcare” (X).Messages which match the non-“don’t care” bits(thebitscorrespondingto clearbitsinthe global mask register)areaccepted. Figure22-17.Acceptance ofa Group ofIdentifiers A separatefilteringpath isused forbuffer14. For thisbuffer,acceptancefilteringisestablishedby the bufferID inconjunctionwiththebasicfilteringmask. Thisbasicmask uses thesame method as theglobal mask (setbitscorrespondto“don’tcare”bitsinthebufferID). Therefore,thebasicmask allowsa largenumber ofinfrequentmessages tobe receivedby thisbuffer. NOTE IftheBMASK registerisequaltotheGMASK register,thebuffer14 can be used thesame way as thebuffers0 to13. The buffers0 to13 arescanned priortobuffer14.Subsequently,thebuffer14 willnotbe checked fora matchingID when one ofthebuffers0 to13 has alreadyreceivedan object. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 183 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

1111111100000 0000000000000000 1111111100000BMASK BUFFER14_ID Saved when buffer is empty Saved when buffer is empty Saved when buffer is empty Saved when buffer is empty 0000000000000000 XXXXXXXX01010 1010101010101010 XXXXXXXX01010BUFFER1_ID BUFFER13_ID 1010101010101010 XXXXXXXX01010 1010101010101010 BUFFER0_ID XXXXXXXX01010 1010101010101010 DS035 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com By settingtheBUFFLOCK bitintheconfigurationregister,thereceivingbufferisautomaticallylockedafter receptionofone validframe.The bufferwillbe unlockedagainaftertheCPU has readthedataand has writtenRX_READY inthebufferstatusfield.With thislockfunction,softwarehas thecapabilitytosave severalmessages withthe same identifieror same identifiergroup intomore than one buffer.For example,a bufferwiththe second highestprioritywillreceivea message ifthe bufferwiththe highest priorityhas alreadyreceiveda message and isnow locked(providedthatboth buffersuse the same acceptancefilteringmask). As shown inFigure22-18,severalmessages withthesame ID arereceivedwhileBUFFLOCK isenabled. The filteringmask ofthebuffers0,1,13,and 14 issettoacceptthismessage. The firstincomingframe willbe receivedby buffer0.Because buffer0 isnow locked,thenextframewillbe receivedby buffer1, and so on. Ifallmatchingreceivebuffersare fulland locked,a furtherincomingmessage willnot be receivedby any buffer. Figure22-18.Message StoragewithBUFFLOCK Enabled

22.5 Receive Structure

Allreceivedframesareinitiallybufferedina hiddenreceivebufferuntiltheframeisvalid.(The validation pointfora receivedmessage isthenext-to-lastbitoftheEOF.) The receivedidentifieristhencompared to every bufferID togetherwiththe respectivemask and the status.As soon as the validationpointis reached,thewholecontentsofthehiddenbufferarecopiedintothematchingmessage bufferas shown in Figure22-19. NOTE The hiddenreceivebuffermust notbe accessedby theCPU.

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BUFFER_ID Buffer 13 BUFFER_ID Buffer 14 BUFFER_ID DS036 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure22-19.Receive Buffer The followingsectiongivesan overviewofthereceptionofthedifferenttypesofframes. The receiveddataframeisstoredinthefirstmatchingreceivebufferbeginningwithbuffer0.Forexample, ifthemessage isacceptedby buffer5,thenatthetimethemessage willbe copied,theRX requestis clearedand theCAN module willnottrytomatch theframetoany subsequentbuffer. Allcontentsofthehiddenreceivebufferarealwayscopiedintotherespectivereceivebuffer.Thisincludes thereceivedmessage ID as wellas thereceivedData LengthCode (DLC);thereforewhen some mask bitsare settodon’tcare,theID fieldwillgetthereceivedmessage ID which couldbe differentfrom the previousID.The DLC ofthereceivingbufferwillbe updatedby theDLC ofthereceivedframe.The DLC of the receivedmessage isnot compared withthe DLC alreadypresentinthe CNSTAT registerof the message buffer.ThisimpliesthattheDLC code oftheCNSTAT registerindicateshow may data bytes actuallybelongtothelatestreceivedmessage. The remote framesare handledby theCAN interfaceintwo differentways. Inthefirstmethod,remote framescan be receivedlikedataframesby configuringthebuffertobe RX_READY and settingtheID bits includingthe RTR bit.In thatcase,the same procedureappliesas describedforData Frames. In the second method,a remote frame can triggerone or more message buffertotransmita dataframe upon reception.ThisprocedureisdescribedundersectionSection22.6.

22.5.1 Receive Timing

As soon as a CAN module receivesa “dominant”biton theCAN bus,thereceiveprocessisstarted.The receivedID and datawillbe storedinthehiddenreceivebufferiftheglobalor basicacceptancefiltering datawillbe copiedintothebufferafterthereceptionofthe6th EOF bitas a message isvalidatthistime. The copy process of every frame,regardlessof the length,takes at least17 CKI cycles(see also Section22.9.1).Figure22-20shows thereceivetiming. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 185 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

1 BIT

3 BIT

7 BIT

rx_start BUS ACK FIELD

2 BIT

16 BIT

(IF PRESENT) n × 8 BIT ARBITRATION FIELD CONTROL+ 12/29 BIT 6 BIT+ BUS IDLE DS037 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure22-20.Receive Timing To indicatethata frameiswaitinginthehiddenbuffer,theBUSY bit(ST[0])oftheselectedbufferisset duringthecopy procedure.The BUSY bitwillbe clearedby theCAN module immediatelyafterthedata bytesare copiedintothebuffer.Afterthecopy processisfinished,theCAN module changes thestatus fieldto RX_FULL. In turn,the CPU shouldchange the statusfieldto RX_READY when the data is processed.When a new objecthas been receivedby thesame buffer,beforetheCPU changed thestatus to RX_READY, the CAN module willchange the statusto RX_OVERRUN to indicatethatat leastone frame has been overwrittenby a new one. Table 22-2 summarizes the currentstatusand the resulting updatefromtheCAN module. Table22-2.WritingtoBufferStatusCode During RX_BUSY CURRENT STATUS RESULTING STATUS RX_READY RX_FULL RX_NOT_ACTIVE RX_NOT_ACTIVE RX_FULL RX_OVERRUN DuringtheassertionoftheBUSY bit,allwritestothereceivingbufferare disabledwiththeexceptionof thestatusfield.Ifthestatusischanged whiletheBUSY bitisasserted,thestatusisupdatedby theCAN module as shown inTable22-2. The bufferstatesare indicatedand controlledby the ST[3:0]bitsin the CNSTAT register(see

22.5.2 Receive Procedure

Softwareexecutesthe followingprocedureto initializea message bufferforthe receptionof a CAN message. 1. Configurethereceivemasks (GMASK orBMASK). 2. ConfigurethebufferID. 3. Configurethemessage bufferstatusas RX_READY. To readtheoutofa receivedmessage, theCPU must executethefollowingsteps(seeFigure22-21):

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Write RX_READY Read CNSTA T Clear RX_PND Read buffer (id/data/control) RX_READY? RX_BUSYx? RX_BUSYx? RX_FULL or RX_OVERRUN? RX_OVERRUN? (optional, for information) Y es No DS038 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure22-21.BufferRead Routine(BUFFLOCK Disabled) The firststepisonlyapplicableifpollingisused togetthestatusofthereceivebuffer.Itcan be deleted foran interruptdrivenreceiveroutine. 1. Read thestatus(CNSTAT) ofthereceivebuffer.IfthestatusisRX_READY, no was themessage received,so exit.IfthestatusisRX_BUSY, thecopy processfromhiddenreceivebufferisnot completedyet,so readCNSTAT again. Ifa bufferisconfiguredtoRX_READY and itsinterruptisenabled,itwillassertan interruptas soon as thebufferhas receiveda message and enteredtheRX_FULLstate (seealsoSection22.7).Inthat case theproceduredescribedbelowmust be followed. 2. Read thestatustodetermineifa new message has overwrittentheone originallyreceivedwhich triggeredtheinterrupt. 3. WriteRX_READY intoCNSTAT. 4. Read theID/dataand objectcontrol(DLC/RTR) fromthemessage buffer. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 187 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Clear RX_PND Write RX_READY Read buffer (id/data/control) DS039 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com 5. Read thebufferstatusagainand checkitisnotRX_BUSYx. Ifitis,repeatthisstepuntilRX_BUSYx has gone away. 6. IfthebufferstatusisRX_FULL orRX_OVERRUN, one ormore messages were copied.Inthatcase, startoverwithstep2. 7. IfstatusisstillRX_READY (assetby theCPU atstep2),clearinterruptpendingbitand exit. When theBUFFLOCK functionisenabled(seeBUFFLOCK insectionSection22.4),itisnotnecessaryto check fornew messages receivedduringtheread processfrom thebuffer,as thisbufferislockedafter thereceptionofthefirstvalidframe.A read from a lockedreceivebuffercan be performedas shown in Figure22-22. Figure22-22.BufferRead Routine(BUFFLOCK Enabled) Forsimplicityonlytheapplicableinterruptroutineisshown: 1. Read theID/dataand objectcontrol(DLC/RTR) fromthemessage buffer. 2. WriteRX_READY intoCNSTAT. 3. Clearinterruptpendingbitand exit.

22.5.3 Rx BufferStates

As shown inFigure22-22, a receiveprocedurestartsas soon as softwarehas setthe bufferfrom the RX_NOT_ACTIVE stateintothe RX_READY state.The statussectionof CNSTAT registerissetfrom 0000b to0010b.When a message isreceived,thebufferwillbe RX_BUSYx duringthecopy processfrom thehiddenreceivebufferintothemessage buffer.AfterwardsthisbufferisRX_FULL. The CPU can then read thebufferdataand eitherresetthebufferstatustoRX_READY or receivea new frame beforethe CPU readsthebuffer.Inthesecond case,thebufferstatewillautomaticallychange toRX_OVERRUN to indicatethatatleastone message was lost.Duringthecopy processthebufferwillagainbe RX_BUSYx fora shorttime,butinthiscase theCNSTAT statussectionwillbe 0101b,as thebufferwas RX_FULL (0100b) before.Afterfinallyreadingthe lastreceivedmessage, the CPU can resetthe bufferto RX_READY.

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TX_BUSY current buffer CPU write TX_ONCE in buffer status Begin selection of next buffer if new tx_request TX_BUSY next buffer BUS IDLE ACK FIELD (IF PRESENT) n × 8 BIT ARBITRATION FIELD + CONTROL 12/29 BIT + 6 BIT BUS DS040 CP3SP33 www.ti.com SNOSCW5 –MAY 2013

22.6 TransmitStructure

To transmita CAN message, softwaremust configurethemessage bufferby changingthebufferstatusto TX_NOT_ACTIVE. The bufferisconfiguredfortransmissionifthe ST[3]bitof the bufferstatuscode (CNSTAT) isset.In TX_NOT_ACTIVE status,the bufferisready to receivedata from the CPU. After receivingalltransmissiondata (ID,data bytes,DLC, and PRI),the CPU can startthe transmissionby writingTX_ONCE intothe bufferstatusregister.During the transmission,the statusof the bufferis TX_BUSYx. After successfultransmission,the CAN module willreset the buffer status to TX_NOT_ACTIVE. Ifthe transmissionprocess fails,the bufferconditionwillremain TX_BUSYx for retransmissionuntilthe frame was successfullytransmittedor the CPU has canceledthe transmission request. To Send a Remote Frame (Remote TransmissionRequest)tootherCAN nodes,softwaresetstheRTR bitof the message identifier(see Section22.10.5) and changes the statusof the message bufferto TX_ONCE. Afterthisremote frame has been transmittedsuccessfully,thismessage bufferwill automaticallyentertheRX_READY stateand isreadytoreceivetheappropriateanswer.Note thatthe mask bitsRTR/XRTR need tobe settoreceivea dataframe(RTR = 0)ina bufferwhichwas configured totransmita remoteframe(RTR = 1). To answer Remote Frames,theCPU writesTX_RTR inthebufferstatusregister,whichcauses thebuffer towaitfora remote frame.When a remote frame passes theacceptancefilteringmask ofone or more buffers,thebufferstatuswillchange toTX_ONCE_RTR, thecontentsofthebufferwillbe transmitted,and afterwardstheCAN module willwriteTX_RTR inthestatuscode registeragain. IftheCPU writesTX_ONCE_RTR intothebufferstatus,thecontentsofthebufferwillbe transmitted,and thesuccessfultransmissionthebuffergoes intothe“waitforRemote Frame”conditionTX_RTR.

22.6.1 TransmitScheduling

AfterwritingTX_ONCE intothebufferstatus,thetransmissionprocessbeginsand theBUSY bitisset.As soon as a buffergetstheTX_BUSY status,thebufferisno longeraccessibleby theCPU exceptforthe ST[3:1]bitsoftheCNSTAT register.StartingwiththebeginningoftheCRC fieldofthecurrentframe,the CAN module looksforanotherbuffertransmitrequestand selectsthebufferwiththehighestpriorityfor the nexttransmissionby changingthe bufferstatefrom TX_ONCE to TX_BUSY. Thistransmitrequest can be canceledby theCPU or can be overwrittenby anothertransmitrequestofa bufferwitha higher priorityas longas thetransmissionofthenextframe has notyetstarted.Thismeans thatbetween the beginningoftheCRC fieldofthecurrentframeand thetransmissionstartofthenextframe,two buffers, thecurrentbufferand thebufferscheduledforthenexttransmission,are intheBUSY status.To cancel thetransmitrequestofthenextframe,theCPU must change thebufferstatetoTX_NOT_ACTIVE. When thetransmitrequesthas been overwrittenby anotherrequestofa higherprioritybuffer,theCAN module changes thebufferstatefrom TX_BUSY toTX_ONCE. Therefore,thetransmitrequestremainspending. Figure22-23furtherillustratesthetransmittiming. Figure22-23.Data Transmission Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 189 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Ifthe transmitprocessfailsor the arbitrationislost,the transmissionprocesswillbe stoppedand will continueaftertheinterruptingreceptionortheerrorsignalinghas finished(seeFigure22-23).Inthatcase, a new bufferselectfollowsand theTX processisexecutedagain. NOTE The canceledmessage can be delayedby a TX requestof a bufferwitha higherpriority. WhileTX_BUSY ishigh,softwarecannotchange thecontentsofthemessage bufferobject. Inallcases,writingtotheBUSY bitwillbe ignored.

22.6.2 TransmitPriority

The CAN module isabletogeneratea streamofscheduledmessages withoutreleasingthebus between two messages so thatan optimizedperformancecan be achieved.Itwillarbitrateforthebus immediately aftersendingthepreviousmessage and willonlyreleasethebus due toa lostarbitration. Ifmore thanone bufferisscheduledfortransmission,thepriorityisbuiltby themessage buffernumber and theprioritycode intheCNSTAT register.The 8-bitvalueofthepriorityiscombined by the4-bitTXPRI valueand the 4-bitbuffernumber (0...14)as shown below.The lowestresultingnumber resultsinthe highesttransmitpriority. 7 4M M 3 0 TXPRI BUFFER # Table22-3shows thetransmitpriorityconfigurationifthepriorityisTXPRI = 0 foralltransmitbuffers. Table22-3.TransmitPriority(TXPRI = 0) TXPRI BUFFER NUMBER PRI TX PRIORITY 0 0 0 Highest 0 1 1 : : : : : : : : 0 14 14 Lowest Table22-4shows thetransmitpriorityconfigurationifTXPRI isdifferentfromthebuffernumber. Table22-4.TransmitPriority(TXPRI not 0) TXPRI BUFFER NUMBER PRI(1) TX PRIORITY 14 0 224 Lowest 13 1 209 12 2 194 11 3 179 10 4 164 9 5 149 8 6 134 7 7 119 6 8 104 5 9 89 4 10 74 3 11 59 (1) Iftwo buffershave thesame priority(PRI),thebufferwiththelower buffernumber willhave thehigherpriority.

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Write_buffer Write TX_ONCE or TX_ONCE_RTR or TX_RTR Write TX_NOT_ACTIVE Write ID/data TX_BUSYx? Y es No DS041 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Table22-4.TransmitPriority(TXPRI not 0)(continued) TXPRI BUFFER NUMBER PRI(1) TX PRIORITY 2 12 44 1 13 29 0 14 14 Highest

22.6.3 TransmitProcedure

The transmissionofa CAN message must be executedas follows(seeFigure22-24) 1. ConfiguretheCNSTAT statusfieldas TX_NOT_ACTIVE. IfthestatusisTX_BUSY, a previous transmitrequestisstillpendingand softwarehas no accesstothedatacontentsofthebuffer.Inthat case,softwaremay choose towaituntilthebufferbecomes availableagainas shown.Otheroptions aretoexitfromtheupdateroutineuntilthebufferhas been transmittedwithan interruptgenerated,or thetransmissionisabortedby an error. 2. Load bufferidentifierand dataregisters.(ForremoteframestheRTR bitoftheidentifierneeds tobe setand loadingdatabytescan be omitted.) 3. ConfiguretheCNSTAT statusfieldtothedesiredvalue: – TX_ONCE totriggerthetransmissionprocessofa singleframe. – TX_ONCE_RTR totriggerthetransmissionofa singledataframeand thenwaitfora received remoteframetotriggerconsecutivedataframes. – TX_RTR waitsfora remoteframetotriggerthetransmissionofa dataframe. WritingTX_ONCE orTX_ONCE_RTR intheCNSTAT statusfieldwillsettheinternaltransmitrequestfor theCAN module. Ifa bufferisconfiguredas TX_RTR and a remote frame isreceived,thedatacontentsoftheaddressed bufferwillbe transmittedautomaticallywithoutfurtherCPU activity. Figure22-24.BufferWriteRoutine Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 191 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

TX_ONCE_RTR 1110 CAN schedules TX RTR received TX done Transmit request cancelled CPU writes 1000 Remote transmission request sent - now wait to receive a data frame TX request delayed by a TX request of higher priority message Transmit request cancelled CPU writes 1000 CAN schedules TX TX request CPU writes 1100 TX request CPU writes 1110 CPU writes 1010 TX_BUSY2 1111 TX done transmit failed TX_RTR 1010 TX_NOT_ACTIVE 1000 TX_BUSY0 1101 RX_READY 0010 TX_ONCE 1100 transmit failed DS042 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

22.6.4 TX BufferStates

The transmissionprocesscan be startedaftersoftwarehas loadedthe bufferregisters(data,ID,DLC, PRI)and setthebufferstatusfromTX_NOT_ACTIVE toTX_ONCE, TX_RTR, orTX_ONCE_RTR. When theCPU writesTX_ONCE, thebufferwillbe TX_BUSY as soon as theCAN module has scheduled thisbufferforthenexttransmission.Aftertheframe couldbe successfullytransmitted,thebufferstatus willbe automaticallyresetto TX_NOT_ACTIVE when a data frame was transmittedor to RX_READY when a remoteframewas transmitted. IftheCPU configuresthemessage buffertoTX_ONCE_RTR, itwilltransmititsdatacontents.Duringthe transmission,thebufferstateis1111b as theCPU wrote1110b intothestatussectionoftheCNSTAT register.Afterthe successfultransmission,the bufferentersthe TX_RTR stateand waitsfora remote frame.When itreceivesa remote frame,itwillgo back intotheTX_ONCE_RTR state,transmititsdata bytes,and returntoTX_RTR. IftheCPU writes1010b intothebufferstatussection,itwillonlyenterthe TX_RTR state,butitwillnotsend itsdatabytesbeforeitwaitsfora remoteframe.Figure22-25illustrates thepossibletransmitbufferstates. Figure22-25.TransmitBufferStates

22.7 Interrupts

Each CAN module has one dedicatedICU interruptvectorforallinterruptconditions.Inaddition,thedata framereceiveeventisan inputtotheMIWU (seeSection17).The interruptprocesscan be initiatedfrom thefollowingsources.

• CAN datatransfer – Receptionofa validdataframeinthebuffer.(Bufferstatechanges fromRX_READY toRX_FULL orRX_OVERRUN.) – Successful transmissionof a data frame. (Bufferstate changes from TX_ONCE to TX_NOT_ACTIVE orRX_READY.) – Successfulresponsetoa remoteframe.(Bufferstatechanges fromTX_ONCE_RTR toTX_RTR.) – Transmitscheduling.(Bufferstatechanges fromTX_RTR toTX_ONCE_RTR.)

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Clear interrupt flags of every message buffer individually ICODE CIEN CICEN IRQ IST3 IST2 IST1 IST0 DS043 CP3SP33 www.ti.com SNOSCW5 –MAY 2013

• CAN errorconditions – Detectionof an CAN error.(The CEIPND bitin the CIPND registerwillbe set as wellas the correspondingbitsintheerrordiagnosticregisterCEDIAG.) The receive/transmitinterruptaccesstoeverymessage buffercan be individuallyenabled/disabledinthe CIEN register.The pendingflagsofthemessage bufferarelocatedintheCIPND register(readonly)and can be clearedby resettingtheflagsintheCICLR registers.

22.7.1 HighestPriorityInterruptCode

To reducethedecodingtimefortheCIPND register,thebufferinterruptrequestwiththehighestpriorityis placedas interruptstatuscode intotheIST[3:0]sectionoftheCSTPND register. Each ofthebufferinterruptsas wellas theerrorinterruptcan be individuallyenabledor disabledinthe CAN InterruptEnableregister(CIEN).As soon as an interruptconditionoccurs,everyinterruptrequestis indicatedby a flagintheCAN InterruptPending register(CIPND).When theinterruptcode logicforthe presenthighestpriorityinterruptrequestisenabled,thisinterruptwillbe translatedintotheIST3:0bitsof the CAN Status Pending register(CSTPND). An interruptrequestcan be clearedby settingthe correspondingbitintheCAN InterruptClearregister(CICLR). Figure22-26shows theCAN interruptmanagement. Figure22-26.InterruptManagement The highestpriorityinterruptsourceistranslatedintothebitsIRQ and IST3:0as shown inTable22-5. Table22-5.HighestPriorityInterruptCode (ICEN=FFFF) CAN INTERRUPT REQUEST IRQ IST3 IST2 IST1 IST0 No Request 0 0 0 0 0 ErrorInterrupt 1 0 0 0 0 Buffer0 1 0 0 0 1 Buffer1 1 0 0 1 0 Buffer2 1 0 0 1 1 Buffer3 1 0 1 0 0 Buffer4 1 0 1 0 1 Buffer5 1 0 1 1 0 Buffer6 1 0 1 1 1 Buffer7 1 1 0 0 0 Buffer8 1 1 0 0 1 Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 193 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

ACK slot and buffer 0 active CAN bits on the bus DS044 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Table22-5.HighestPriorityInterruptCode (ICEN=FFFF) (continued) CAN INTERRUPT REQUEST IRQ IST3 IST2 IST1 IST0 Buffer9 1 1 0 1 0 Buffer10 1 1 0 1 1 Buffer11 1 1 1 0 0 Buffer12 1 1 1 0 1 Buffer13 1 1 1 1 0 Buffer14 1 1 1 1 1

22.7.2 Usage Notes

The interruptcode IST3:0can be used withinthe interrupthandleras a displacementto jump to the relevantsubroutine. The CAN InterruptCode Enable (CICEN) registerisused in the CAN interrupthandlerifsoftwareis servicingallreceivebufferinterruptsfirst,followedby alltransmitbufferinterrupts.Inthiscase,software can firstenableonlyreceivebufferinterruptsto be coded,then scan and serviceallpendinginterrupt requestsinthe orderof theirpriority.Afterprocessingallthe receiveinterrupts,softwarechanges the CICEN registerto disableallreceivebuffersand enablealltransmitbuffers,then servicesallpending transmitbufferinterruptrequestsaccordingtotheirpriorities.

22.8 Time Stamp Counter

Each CAN module featuresa freerunning16-bittimer(CTMR) incrementingeverybittimerecognizedon theCAN bus.The valueofthistimerduringtheACK slotiscapturedintotheTSTP registerofa message bufferaftera successfultransmissionor receptionofa message. Figure22-27 shows a simplifiedblock diagramoftheTime Stamp counter. Figure22-27.Time Stamp Counter The timercan be synchronizedovertheCAN networkby receivingor transmittinga message toor from buffer0.Inthiscase,theTSTP registerofbuffer0 capturesthecurrentCTMR valueduringtheACK slot of a message (as above),and then the CTMR isresetto 0000b. Synchronizationcan be enabled or disabledusingtheCGCR.TSTPEN bit.

22.9 Memory Organization

Each CAN module occupies288 words inthe memory addressspace.Thisspace isorganizedas 15 banks of 16 words per bank (plusone 16-word reservedbank) forthe message buffersand 28 words (plus4 reservedwords)forcontroland status.

22.9.1 CPU Access toCAN Registers/Memory

Allmemory locationsoccupiedby themessage buffersare sharedby theCPU and CAN modules,with CPU accesshavingpriorityoverCAN access.The CAN modules and theCPU normallyhave single-cycle access to thismemory. However, ifan access contentionoccurs,the access to the memory isblocked everycycleuntilthecontentionisresolved.Thisaccessarbitrationistransparenttosoftware.

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www.ti.com SNOSCW5 –MAY 2013 Ifa bufferisbusy duringthereceptionofan object(copyprocessfrom thehiddenreceivebuffer)or is scheduledfortransmission,theCPU has no writeaccess tothedatacontentsofthebuffer.Writetothe status/controlbyteand readaccesstothewholebufferisalwaysenabled. Allconfigurationand statusregisterscan eitherbe accessed by the CAN module or the CPU. These registersprovidesingle-cycleaccesswithoutany potentialwaitstate. Allregisterdescriptionswithinthenextsectionshave thefollowinglayout: 15 0 Bit/FieldNames ResetValue CPU Access (R = readonly,W = writeonly,R/W = read/write) The CAN peripheralregistersand shared memory are implementedas 16-bitwords which occupy the lowerhalfof32-bitdoublewordlocationsintheaddressspace.The upperhalfisreserved.

22.9.2 Message BufferOrganization

The message buffersare thecommunicationinterfacesbetween CAN and theCPU forthetransmission and thereceptionofCAN frames.There are 15 message bufferslocatedatfixedaddressesinRAM. As shown inTable22-6,each bufferconsistsoftwo words reservedfortheidentifiers,4 words reservedfor up toeightCAN databytes,one word reservedforthetimestamp,and one word fordatalengthcode, transmitprioritycode,and thebufferstatuscodes. Table22-6.Message BufferMap BufferAddress 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Register BASE + 00h CNSTAT DLC Reserved PRI ST BASE + 04h TSTP TSTP[15:0] BASE + 08h DATA3 Data7[7:0] Data8[7:0] BASE + 0Ch DATA2 Data5[7:0] Data6[7:0] BASE + 10h DATA1 Data3[7:0] Data4[7:0] BASE + 14h DATA0 Data1[7:0] Data2[7:0] BASE + 18h ID0 XI[14:0] RTR BASE + 1Ch ID1 XI[28:18]/ID[10:0] SRR/RTR IDE XI[17:15]

22.10 CAN ControllerRegisters

Table22-7liststheregistersforthetwo CAN modules (CAN0 and CAN1). Table22-7.CAN ControllerRegisters NAME ADDRESS DESCRIPTION CNSTAT See Table22-6 Message BufferStatus/ControlRegister CGCR0 FF BA00h CAN0 GlobalConfigurationRegister CGCR1 FF BE00h CAN1 GlobalConfigurationRegister CTIM0 FF BA04h CAN0 TimingRegister CTIM1 FF BE04h CAN1 TimingRegister GMSKX0 FF BA08h CAN0 GlobalMask Register GMSKX1 FF BE08h CAN1 GlobalMask Register GMSKB0 FF BA0Ch CAN0 GlobalMask Register GMSKB1 FF BE0Ch CAN1 GlobalMask Register BMSKX0 FF BA10h CAN0 BasicMask Register Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 195 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table22-7.CAN ControllerRegisters(continued) NAME ADDRESS DESCRIPTION BMSKX1 FF BE10h CAN1 BasicMask Register BMSKB0 FF BA14h CAN0 BasicMask Register BMSKB1 FF BE14h CAN1 BasicMask Register CIEN0 FF BA18h CAN0 InterruptEnableRegister CIEN1 FF BE18h CAN1 InterruptEnableRegister CIPND0 FF BA1Ch CAN0 InterruptPendingRegister CIPND1 FF BE1Ch CAN1 InterruptPendingRegister CICLR0 FF BA20h CAN0 InterruptClearRegister CICLR1 FF BE20h CAN1 InterruptClearRegister CICEN0 FF BA24h CAN0 InterruptCode EnableRegister CICEN1 FF BE24h CAN1 InterruptCode EnableRegister CSTPND0 FF BA28h CAN0 StatusPendingRegister CSTPND1 FF BE28h CAN1 StatusPendingRegister CANEC0 FF BA2Ch CAN0 ErrorCounterRegister CANEC1 FF BE2Ch CAN1 ErrorCounterRegister CEDIAG0 FF BA30h CAN0 ErrorDiagnosticRegister CEDIAG1 FF BE30h CAN1 ErrorDiagnosticRegister CTMR0 FF BA34h CAN0 TimerRegister CTMR1 FF BE34h CAN1 TimerRegister

22.10.1 Message BufferStatus/ControlRegister(CNSTAT)

The bufferstatus(ST),the bufferpriority(PRI),and the data lengthcode (DLC) are controlledby manipulatingthe contentsof the BufferStatus/ControlRegister(CNSTAT). The CPU and CAN module have accesstothisregister. 15 12 11 8 7 4 3 0 DLC Reserved PRI ST R/W ST The BufferStatusfieldcontainsthestatusinformationofthebufferas shown inTable22-8.This fieldcan be modifiedby theCAN module.The ST0 bitsactsas a bufferbusy indication.When theBUSY bitisset,any writeaccesstothebufferisdisabledwiththeexceptionofthelowerbyte oftheCNSTAT register.The CAN module setsthisbitifthebufferdataiscurrentlycopiedfrom thehiddenbufferorifa message isscheduledfortransmissionoriscurrentlytransmitting.The CAN module alwaysclearsthisbiton a statusupdate. Table22-8.BufferStatusSectionoftheCNSTAT Register ST3 ST0ST2 ST1 BUFFER STATUS(DIR) (BUSY) 0 0 0 0 RX_NOT_ACTIVE 0 0 0 1 ReservedforRX_BUSY. (ThisconditionindicatesthatsoftwarewroteRX_NOT_ACTIVE toa buffer when thedatacopy processisstillactive.) 0 0 1 0 RX_READY 0 0 1 1 RX_BUSY0 (IndicatesdataisbeingcopiedforthefirsttimeRX_READY → RX_BUSY0.) 0 1 0 0 RX_FULL 0 1 0 1 RX_BUSY1 (Indicatesdataisbeingcopiedforthesecond timeRX_FULL → RX_BUSY1.) 0 1 1 0 RX_OVERRUN 0 1 1 1 RX_BUSY2 (IndicatesdataisbeingcopiedforthethirdorsubsequenttimesRX_OVERRUN → RX_BUSY2.)

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www.ti.com SNOSCW5 –MAY 2013 Table22-8.BufferStatusSectionoftheCNSTAT Register(continued) ST3 ST0ST2 ST1 BUFFER STATUS(DIR) (BUSY) 1 0 0 0 TX_NOT_ACTIVE 1 0 0 1 ReservedforTX_BUSY. (ThisstateindicatesthatsoftwarewroteTX_NOT_ACTIVE toa transmit bufferwhichisscheduledfortransmissionoriscurrentlytransmitting.) 1 1 0 0 TX_ONCE 1 1 0 1 TX_BUSY0 (Indicatesthata bufferisscheduledfortransmissionorisactivelytransmitting;itcan be due toone oftwo cases:a message ispendingfortransmissionoriscurrentlytransmitting,oran automatedanswer ispendingfortransmissionoriscurrentlytransmitting.) 1 0 1 0 TX_RTR (Automaticresponsetoa remoteframe.) 1 0 1 1 ReservedforTX_BUSY1. (Thisconditiondoes notoccur.) 1 1 1 0 TX_ONCE_RTR (Changes toTX_RTR aftertransmission.) 1 1 1 1 TX_BUSY2 (Indicatesthata bufferisscheduledfortransmissionorisactivelytransmitting;itcan be due toone oftwo cases:a message ispendingfortransmissionoriscurrentlytransmitting,oran automatedanswer ispendingfortransmissionoriscurrentlytransmitting.) PRI The TransmitPriorityCode fieldholdsthesoftware-definedtransmitprioritycode forthemessage buffer. DLC The Data LengthCode fielddeterminesthenumber ofdatabyteswithina received/transmitted frame.Fortransmission,thesebitsneed tobe setaccordingtothenumber ofdatabytestobe transmitted.Forreception,thesebitsindicatethenumber ofvalidreceiveddatabytesavailablein themessage buffer.Table22-9shows thepossiblebitcombinationsforDLC3:0 fordatalengths from0 to8 bytes. Table22-9.Data Length Coding DLC Number ofData Bytes(1) 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 (1) The maximum number ofdatabytesreceived/transmittedis8,even iftheDLC fieldissettoa valuegreaterthan8.Therefore,ifthedata lengthcode isgreaterorequaltoeightbytes,theDLC fieldis ignored.

22.10.2 StorageofStandard Messages

Duringthe processingof standardframes,the Extended-Identifier(IDE)bitisclear.The ID1[3:0]and ID0[15:0]bitsare“don’tcare”bits.A standardframewitheightdatabytesisshown inTable22-10. IDE The IdentifierExtensionbitdetermineswhetherthemessage isa standardframeoran extendedframe. 0 – Message isa standardframeusing11 identifierbits. 1 – Message isan extendedframe. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 197 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com RTR The Remote TransmissionRequestbitindicateswhetherthemessage isa dataframeora remoteframe. 0 – Message isa dataframe. 1 – Message isa remoteframe. ID The ID fieldisused forthe11 standardframeidentifierbits. Table22-10.Standard Frame with8 Data Bytes BufferAddress 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Register BASE + 00h CNSTAT DLC Reserved PRI ST BASE + 04h TSTP TSTP[15:0] BASE + 08h DATA3 Data7[7:0] Data8[7:0] BASE + 0Ch DATA2 Data5[7:0] Data6[7:0] BASE + 10h DATA1 Data3[7:0] Data4[7:0] BASE + 14h DATA0 Data1[7:0] Data2[7:0] BASE + 18h ID0 Don'tCare BASE + 1Ch ID1 ID[10:0] RTR IDE Don'tCare

22.10.3 StorageofMessages withLess Than 8 Data Bytes

The databytesthatare notused fordatatransferare “don’tcares”.Iftheobjectistransmitted,thedata withinthesebyteswillbe ignored.Iftheobjectisreceived,thedatawithinthesebyteswillbe overwritten withinvaliddata.

22.10.4 StorageofExtended Messages

Ifthe IDE bitisset,the bufferhandlesextended frames.The storageof the extended ID followsthe descriptionsinTable22-11.The SRR bitisatthebitpositionoftheRTR bitforstandardframeand needs tobe transmittedas 1. Table22-11.Extended Messages with8 Data Bytes BufferAddress 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Register BASE + 00h CNSTAT DLC Reserved PRI ST BASE + 04h TSTP TSTP BASE + 08h DATA3 Don'tCare BASE + 0Ch DATA2 BASE + 10h DATA1 BASE + 14h DATA0 BASE + 18h ID0 ID[14:0] RTR BASE + 1Ch ID1 ID[28:18] SRR IDE ID17:15] SRR The SubstituteRemote RequestbitreplacestheRTR bitused instandardframesatthisbit position.The SRR bitneeds tobe setby software. IDE The IdentifierExtensionbitdetermineswhetherthemessage isa standardframeoran extended frame. 0 – Message isa standardframeusing11 identifierbits. 1 – Message isan extendedframe. RTR The Remote TransmissionRequestbitindicateswhetherthemessage isa dataframeora remoteframe. 0 – Message isa dataframe. 1 – Message isa remoteframe.

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www.ti.com SNOSCW5 –MAY 2013 ID The ID fieldisused tobuildthe29-bitidentifierofan extendedframe.The ID[28:18]fieldisused forthe11 standardframeidentifierbits.

22.10.5 StorageofRemote Messages

Duringremote frame transfer,thebufferregistersDATA0 –DATA3 are “don’tcares”.Ifa remote frame is transmitted,the contentsof theseregistersare ignored.Ifa remote frame isreceived,the contentsof theseregisterswillbe overwrittenwithinvaliddata.The structureofa message buffersetup fora remote framewithextendedidentifierisshown inTable22-12. Table22-12.Extended Remote Frame BufferAddress 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Register BASE + 00h CNSTAT DLC Reserved PRI ST BASE + 04h TSTP TSTP[15:0] BASE + 08h DATA3 Data7[7:0] Data8[7:0] BASE + 0Ch DATA2 Data5[7:0] Data6[7:0] BASE + 10h DATA1 Data3[7:0] Data4[7:0] BASE + 14h DATA0 Data1[7:0] Data2[7:0] BASE + 18h ID0 ID[14:0] RTR BASE + 1Ch ID1 ID[28:18] SRR IDE ID17:15] SRR The SubstituteRemote RequestbitreplacestheRTR bitused instandardframesatthisbit position.The SRR bitneeds tobe setby softwareifthebufferisconfiguredtotransmita message withan extendedidentifier.Itwillbe receivedas monitoredon theCAN bus. IDE The IdentifierExtensionbitdetermineswhetherthemessage isa standardframeoran extended frame. 0 – Message isa standardframeusing11 identifierbits. 1 – Message isan extendedframe. RTR The Remote TransmissionRequestbitindicateswhetherthemessage isa dataframeora remote frame. 0 – Message isa dataframe. 1 – Message isa remoteframe. ID The ID fieldisused tobuildthe29-bitidentifierofan extendedframe.

22.10.6 CAN GlobalConfigurationRegistern (CGCRn)

The CGCRn registerisa 16-bit,read/writeregisterused to:

• Enable/disabletheCAN module.
• ConfiguretheBUFFLOCK functionforthemessage buffer0..14.
• Enable/disablethetimestamp synchronization.
• SetthelogiclevelsoftheCAN Input/Outputpins,CANnRX and CANnTX.
• Choose thedatastoragedirection(DDIR).
• Selecttheerrorinterrupttype(EIT).
• Enable/disablediagnosticfunctions. 15 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EIT DIAGEN INTERNAL LOOPBACK IGNACK LO DDIR TSTPE BUFFLOCK CRX CT CANEN N X 0 0 R/W R/W Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 199 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Sequence of Data Bytes on the Bus CRCData8 t Data7Data6Data5Data4Data3Data2Data1ID Data2Data10A Data4 Data308 Data6 Data506 Data8 Data704 Data Bytes ADDR Offset DS045 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com CANEN The CAN Enablebitenables/disablestheCAN module.When theCAN module isdisabled, allinternalstatesand theTEC and REC counterregistersarecleared.InadditiontheCAN module clockisdisabled.AllCAN module controlregistersand thecontentsoftheobject memory areleftunchanged.Softwaremust make surethatno message ispendingfor transmissionbeforetheCAN module isdisabled. 0 – CAN module isdisabled. 1 – CAN module isenabled. CTX The ControlTransmitbitconfiguresthelogicleveloftheCAN transmitpinCANnTX. 0 – Dominantstateis0;recessivestateis1. 1 – Dominantstateis1;recessivestateis0. CRX The ControlReceivebitconfiguresthelogicleveloftheCAN receivepinCANnRX. 0 – Dominantstateis0;recessivestateis1. 1 – Dominantstateis1;recessivestateis0. BUFFLOCK The BufferLock bitconfiguresthebufferlockfunction.Ifthisfeatureisenabled,a buffer willbe lockedupon a successfulframereception.The bufferwillbe unlockedagainby writingRX_READY inthebufferstatusregister,i.e.,afterreadingdata. 0 – Lock functionisdisabledforallbuffers. 1 – Lock functionisenabledforallbuffers. TSTPEN The Time Stamp Enablebitenablesordisablesthetimestamp synchronizationfunctionof theCAN module. 0 – Time synchronizationdisabled.The Time Stamp countervalueisnotresetupon receptionortransmissionofa message to/frombuffer0. 1 – Time synchronizationenabled.The Time Stamp countervalueisresetupon reception ortransmissionofa message to/frombuffer0. DDIR The Data Directionbitselectsthedirectionthedatabytesaretransmittedand received. The CAN module transmitsand receivestheCAN Data1 bytefirstand theData8 bytelast (Data1,Data2,...,Data7,Data8).IftheDDIR bitisclear,thedatacontentsofa received message isstoredwiththefirstbyteatthehighestdataaddressand thelastdataatthe lowestdataaddress(seeFigure69).The same appliesfortransmitteddata. 0 – Firstbyteatthehighestaddress,subsequentbytesatloweraddresses. 1 – Firstbyteatthelowestaddress,subsequentbytesathigheraddresses. Figure22-28.Data DirectionBitClear SettingtheDDIR bitwillcause thedirectionofthedatastoragetobe reversed— thelastbytereceivedis storedatthehighestaddressand thefirstbyteisstoredatthelowestaddress,as shown in Figure22-29.

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Sequence of Data Bytes on the Bus CRCData8 t Data7Data6Data5Data4Data3Data2Data1ID Data7Data80A Data5 Data608 Data3 Data406 Data1 Data204 Data Bytes ADDR Offset DS046 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure22-29.Data DirectionBitSet LO The ListenOnlybitcan be used toconfiguretheCAN interfacetobehave onlyas a receiver.Thismeans:

• Cannot transmitany message.
• Cannot send a dominantACK bit
• When errorsaredetectedon thebus,theCAN module willbehave as intheerror passivemode. Usingthislistenonlyfunction,theCAN interfacecan be adjustedforconnectingtoan operatingnetworkwithunknown bus speed. 0 – Transmit/receivemode. 1 – Listen-onlymode. When theIgnoreAcknowledgebitisset,theCAN module does notexpecttoreceivea dominantACK bittoindicatethevalidityofa transmittedmessage. Itwillnotsend an error framewhen thetransmittedframeisnotacknowledgedby any otherCAN node.This featurecan be used inconjunctionwiththeLOOPBACK bitforstand-alonetestsoutside ofa CAN network. 0 – Normal mode. 1 – The CAN module does notexpecttoreceivea dominantACK bittoindicatethe validityofa transmittedmessage. LOOPBACK When theLoopback bitisset,allmessages sentby theCAN module can alsobe received by a CAN module bufferwitha matchingbufferID.However,theCAN module does not acknowledgea message sentby itself.Therefore,theCAN module willsend an error framewhen no otherdeviceconnectedtothebus has acknowledgedthemessage. 0 – No loopback. 1 – Loopback enabled. INTERNAL IftheInternalfunctionisenabled,theCANnTX and CANnRX pinsoftheCAN module are internallyconnectedtoeach other.Thisfeaturecan be used inconjunctionwiththe LOOPBACK mode. Thismeans thattheCAN module can receiveitsown sentmessages withoutconnectingan externaltransceiverchiptotheCANnTX and CANnRX pins;it allowssoftwaretorunrealstand-alonetestswithoutany peripheraldevices. 0 – Normal mode. 1 – Internalmode. DIAGEN The DiagnosticEnablebitgloballyenablesordisablesthespecialdiagnosticfeaturesof theCAN module.Thisincludesthefollowingfunctions:
• LO (ListenOnly) Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 201 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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• IGNACK (IgnoreAcknowledge).
• LOOPBACK (Loopback)
• INTERNAL (InternalLoopback).
• Writeaccesstohiddenreceivebuffer. 0 – Normal mode. 1 – Diagnosticfeaturesenabled. EIT The ErrorInterruptType bitcontrolsthebehavioroftheErrorInterruptPendingbit (CIPNDn.EIPND) when an errorInterruptisasserted,ifenabledby theErrorInterrupt Enablebit(CIENn.EIEN). 0 – The EIPND bitisseton everyerroron theCAN bus. 1 – The EIPND bitissetonlyiftheerrorstate(CSTPNDn.NS) changes as a resultof incrementingeitherthereceiveortransmiterrorcounter.

22.10.7 CAN Timing Registern (CTIMn)

The CTIMn registerdefinestheconfigurationoftheBitTime Logic(BTL). 15 9 8 7 6 3 2 0 PSC SJW TSEG1 TSEG2 R/W PSC The PrescalerConfigurationfieldspecifiestheCAN prescaler.The settingsareshown in Table22-13. Table22-13.CAN PrescalerSettings PSC6:0 Prescaler 000000 2 000001 3 000010 4 000011 5 000100 6 : : 1111101 127 1111110 128 1111111 128 SJW The SynchronizationJump WidthfieldspecifiestheSynchronizationJump Width,whichcan be programmed between 1 and 4 timequanta(seeTable22-14). Table22-14.SJW Setting SJW (1) SynchronizationJump Width (SJW) 00 1 timequantum 01 2 timequanta 10 3 timequanta 11 4 timequanta (1) The settingsofSJW must be configuredtobe smallerorequalto TSEG1 and TSEG2

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www.ti.com SNOSCW5 –MAY 2013 TSEG The Time Segment 1 fieldconfiguresthelengthoftheTime 1 Segment 1 (TSEG1).Itisnotrecommended toconfigurethe timesegment 1 tobe smallerthan2 timequanta.(seeTable22- 15). Table22-15.Time Segment 1 Settings TSEG1[3:0] Length ofTime (TSEG1)

0000 Not recommended

TSE The Time Segment 2 fieldspecifiesthenumber oftimequanta G2 (tq)forphase segment 2 (seeTable22-16). Table22-16.Time Segment 2 Settings TSEG2 Length ofTSEG2 000 1 timequantum 001 2 timequanta 010 3 timequanta 011 4 timequanta 100 5 timequanta 101 6 timequanta 110 7 timequanta 111 8 timequanta

22.10.8 CAN GlobalMask Registern (GMSKBn/GMSKXn)

The GMSKBn and GMSKXn registersallowsoftwareto globallymask, or “don’t care” the incoming extended/standardidentifierbits,RTR/XRTR and IDE. Throughoutthisdocument, the GMSKBn and GMSKXn 16-bitregistersarereferencedas a 32-bitregisterGMSK. The followingarethebitsfortheGMSKBn register. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 203 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 15 5 4 3 2 0 GM[28:18] RTR IDE GM[17:15] R/W The followingarethebitsfortheGMSKXn register. 15 1M 0 GM[14:0] XRTR R/W ForallGMSKBn and GMSKXn registerbits,thefollowingapplies: 0 – The incomingidentifierbitmust match thecorrespondingbitinthemessage bufferidentifier register. 1 – Accept1 or0 (“don’tcare”)intheincomingID bitindependentfromthecorrespondingbitinthe message bufferID registers.The correspondingID bitinthemessage bufferwillbe overwrittenby theincomingidentifierbits. When an extendedframeisreceivedfromtheCAN bus,allGMSKn bitsGM28:0, IDE,RTR, and XRTR areused tomask theincomingmessage. Inthiscase,theRTR bitintheGMSKn registercorrespondsto theSRR bitinthemessage. The XRTR bitintheGMSKn registercorrespondstotheRTR bitinthe message. DuringthereceptionofstandardframesonlytheGMSKn bitsGM28:18, RTR, and IDE areused.Inthis case,theGM28:18 bitsintheGMSKn registercorrespondtotheID10:0bitsinthemessage. GlobalMask GM28:18 RTR IDE GM17:0 XRTR StandardFrame ID10:0 RTR IDE Unused ExtendedFrame ID28:18 SRR IDE ID17:0 RTR

22.10.9 CAN Basic Mask Registern (BMSKBn/BMSKXn)

The BMSKBn and BMSKXn registersallow masking the buffer14, or “don’t care” the incoming extended/standardidentifierbits,RTR/XRTR, and IDE.Throughoutthisdocument,thetwo 16-bitregisters BMSKBn and BMSKXn arereferencedas a 32-bitregisterBMSKn. The followingarethebitsfortheBMSKXn register. 15 5 4 3 2 0 bM[28:18] RTR IDE BM[17:15] R/W The followingarethebitsfortheBMSKXn register. 15 1M 0 BM[14:0] XRTR R/W ForallBMSKBn and BMSKXn registerbitsthefollowingapplies: 0 – The incomingidentifierbitmust match thecorrespondingbitinthemessage bufferidentifier register. 1 – Accept1 or0 (“don’tcare”)intheincomingID bitindependentfromthecorrespondingbitinthe message bufferID registers.The correspondingID bitinthemessage bufferwillbe overwrittenby theincomingidentifierbits.

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www.ti.com SNOSCW5 –MAY 2013 When an extendedframeisreceivedfromtheCAN bus,allBMSKn bitsBM28:0,IDE,RTR, and XRTR areused tomask theincomingmessage. Inthiscase,theRTR bitintheBMSKn registercorrespondsto theSRR bitinthemessage. The XRTR bitintheBMSKn registercorrespondstotheRTR bitinthe message. Duringthereceptionofstandardframes,onlytheBMSKn bitsBM28:18,RTR, and IDE areused.Inthis case,theBM28:18 bitsintheBMSKn registercorrespondtotheID10:0bitsinthemessage. Basic Mask BM28:18 RTR IDE BM17:0 XRTR StandardFrame ID10:0 RTR IDE Unused ExtendedFrame ID28:18 SRR IDE ID17:0 RTR

22.10.10 CAN InterruptEnable Registern (CIENn)

The CIENn registerenablesthetransmit/receiveinterruptsofthemessage buffers0 through14 as wellas theCAN ErrorInterrupt. 15 14 0 EIEN IEN R/W EIEN The ErrorInterruptEnablebitallowstheCAN module tointerrupttheCPU ifany kindofCAN receive/transmiterrorsaredetected.Thiscausesany errorstatuschange intheerrorcounter registersREC/TEC isabletogeneratean errorinterrupt. 0 – The errorinterruptisdisabledand no errorinterruptwillbe generated. 1 – The errorinterruptisenabledand a change inREC/TEC willcause an interrupttobe generated. IEN The BufferInterruptEnablebitsallowsoftwaretoenable/disabletheinterruptsourceforthe correspondingmessage buffer.Forexample,IEN14 controlsinterruptsfrombuffer14,and IEN0 controlsinterruptsfrombuffer0. 0 – Bufferas interruptsourcedisabled. 1 – Bufferas interruptsourceenabled.

22.10.11 CAN InterruptPending Registern (CIPNDn)

The CIPNDn registerindicatesany CAN Receive/TransmitInterruptRequests caused by the message buffers0..14and CAN erroroccurrences. 15 14 0 EIPND IPND R EIPND The ErrorInterruptPendingfieldindicatesthestatuschange ofTEC/REC and willexecutean errorinterruptiftheEIEN bitisset.Softwarehas theresponsibilitytocleartheEIPND bit usingtheCICLRn register. 0 – CAN statusisnotchanged. 1 – CAN statusischanged. IPND The BufferInterruptPendingbitsaresetby theCAN module followinga successful transmissionorreceptionofa message toorfromthecorrespondingmessage buffer.For example,IPND14 correspondstobuffer14,and IPND0 correspondstobuffer0. 0 – No interruptpendingforthecorrespondingmessage buffer. 1 – Message bufferhas generatedan interrupt. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 205 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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22.10.12 CAN InterruptClearRegistern (CICLRn)

The CICLRn registerbitsindividuallyclearCAN interruptpendingflagscaused by the message buffers and from the ErrorManagement Logic.Do not modify thisregisterwithinstructionsthataccess the registeras a read-modify-writeoperand,such as thebitmanipulationinstructions. 15 14 0 EICLR ICLR W EICLR The ErrorInterruptClearbitisused tocleartheEIPND bit. 0 – The EIPND bitisunaffectedby writing0. 1 – The EIPND bitisclearedby writing1. ICLR The BufferInterruptClearbitsareused tocleartheIPND bits. 0 – The correspondingIPND bitisunaffectedby writing0. 0 – The correspondingIPND bitisclearedby writing1.

22.10.13 CAN InterruptCode Enable Registern (CICENn)

The CICENn registercontrolswhethertheinterruptpendingflagintheCIPND registeristranslatedinto the InterruptCode fieldof the CSTPND register.Allinterruptrequests,CAN error,and message buffer interruptscan be enabled/disabledseparatelyfortheinterruptcode indicationfield. 15 14 0 EICEN ICEN R/W EICEN The ErrorInterruptCode Enablebitcontrolsencodingforerrorinterrupts. 0 – Errorinterruptpendingisnotindicatedintheinterruptcode. 1 – Errorinterruptpendingisindicatedintheinterruptcode. ICEN The BufferInterruptCode Enablebitscontrolencodingformessage bufferinterrupts. 0 – Message bufferinterruptpendingisnotindicatedintheinterruptcode. 1 – Message bufferinterruptpendingisindicatedintheinterruptcode.

22.10.14 CAN StatusPending Registern (CSTPNDn)

The CSTPNDn registerholdsthestatusoftheCAN Node and theInterruptCode. 15 8 7 5 4 3 0 Reserved NS IRQ IST R NS The CAN Node StatusfieldindicatesthestatusoftheCAN node as shown inTable22-17. Table22-17.CAN Node Status NS Node Status

000 Not Active

010 ErrorActive

011 ErrorWarningLevel

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www.ti.com SNOSCW5 –MAY 2013 IRQ/IST The IRQ bitand IST fieldindicatetheinterruptsourceofthehighestpriorityinterrupt currentlypendingand enabledintheCICENn register.Table22-18shows theseveral interruptcodes when theencodingforallinterruptsourcesisenabled(CICEN = FFFFh). Table22-18.HighestPriorityInterruptCode IRQ IST3:0 CAN InterruptRequest 0 0000 No interruptrequest 1 0000 Errorinterrupt 1 0001 Buffer0 1 0010 Buffer1 1 0011 Buffer2 1 0100 Buffer3 1 0101 Buffer4 1 0110 Buffer5 1 0111 Buffer6 1 1000 Buffer7 1 1001 Buffer8 1 1010 Buffer9 1 1011 Buffer10 1 1100 Buffer11 1 1101 Buffer12 1 1110 Buffer13 1 1111 Buffer14

22.10.15 CAN ErrorCounter Registern (CANECn)

The CANECn registerreportsthevaluesoftheCAN ReceiveErrorCounterand theCAN TransmitError Counter. 15 8M M 7 0 REC TEC R REC The CAN ReceiveErrorCounterfieldreportsthevalueofthereceiveerrorcounter. TEC The CAN TransmitErrorCounterfieldreportsthevalueofthetransmiterrorcounter.

22.10.16 CAN ErrorDiagnosticRegistern (CEDIAGn)

The CEDIAGn registerreportsinformationaboutthelastdetectederror.The CAN module identifiesthe fieldwithinthe CAN frame formatin which the erroroccurred,and itidentifiesthe bitnumber of the erroneousbitwithintheframefield.The APB bus masterhas read-onlyaccesstothisregister,and allbits areclearedon reset. 15 14 13 12 11 10 9 4 3 0 Reserved DRIVE MON CRC STUFF TXE EBID EFID R Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 207 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com EFID The ErrorFieldIdentifierfieldidentifiestheframefieldinwhichthelasterroroccurred.The encodingoftheframefieldsisshown inTable22-19. Table22-19.ErrorFieldIdentifier EFID3:0 Field

0000 ERROR

0001 ERROR DEL

0010 ERROR ECHO

0011 BUS IDLE

0100 ACK

0101 EOF

0110 INTERMISSION

0111 SUSPEND TRANSMISSION

1000 SOF

1001 ARBITRATION

1010 IDE

1011 EXTENDED ARBITRATION

1100 R1/R0

1101 DLC

1110 DATA

1111 CRC

EBID The ErrorBitIdentifierfieldreportsthebitpositionoftheincorrectbitwithintheerroneous framefield.The bitnumber startswiththevalueequaltotherespectiveframefieldlength minus one atthebeginningofeach fieldand isdecrementedwitheach CAN bit.Figure22-30 shows an example on how theEBID iscalculated. Figure22-30.EBID Example Forexample,assume theEFID fieldshows 1110b and theEBID fieldshows 111001b.This means thefaultyfieldwas thedatafield.To calculatethebitpositionoftheerror,theDLC of themessage needs tobe known.Forexample,fora DLC of8 databytes,thebitcounterstarts withthevalue:(8× 8)– 1 = 63;so when EBID5:0= 111001b = 57,thenthebitnumber was 63 – 57 = 6. TXE The TransmitErrorbitindicateswhethertheCAN module was an activetransmitteratthetime theerroroccurred. 0 – The CAN module was a receiveratthetimetheerroroccurred. 1 – The CAN module was an activetransmitteratthetimetheerroroccurred.

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www.ti.com SNOSCW5 –MAY 2013 STUFF The StuffErrorbitindicateswhetherthebitstuffingrulewas violatedatthetimetheerror occurred.Note thatcertainbitfieldsdo notuse bitstuffingand thereforethisbitmay be ignored forthosefields. 0 – No bitstuffingerror. 1 – The bitstuffingrulewas violatedatthetimetheerroroccurred. CRC The CRC ErrorbitindicateswhethertheCRC isinvalid.Thisbitshouldonlybe checkedifthe EFID fieldshows thecode oftheACK field. 0 – No CRC erroroccurred. 1 – CRC erroroccurred. MON The Monitorbitshows thebus valueon theCANnRX pinas sampled by theCAN module atthe timeoftheerror. DRIVE The Drivebitshows theoutputvalueon theCANnTX pinatthetimeoftheerror.Note thata receiverwillnotdrivethebus exceptduringACK and duringan activeerrorflag.

22.10.17 CAN Timer Registern (CTMRn)

The CTMR registerreportsthecurrentvalueoftheTime Stamp Counteras describedinSection22.8. 15 0 CTMR15:0 R The CTMRn registerisa freerunning16-bitcounter.Itcontainsthenumber ofCAN bitsrecognizedby the CAN module sincetheregisterhas been cleared.The counterstartstoincrementfrom thevalue0000h aftera hardwarereset.IftheTimer Stamp Enable bit(TSTPEN) intheCAN globalconfigurationregister (CGCRn) isset,thecounterwillalsobe clearedon a message transferofthemessage buffer0 The contentsof CTMRn are capturedintothe Time Stamp registerof the message bufferafter successfullysendingorreceivinga frame,as describedinSection22.8.

22.11 System Start-Upand Multi-InputWake-Up

Aftersystem start-up,allCAN-relatedregistersareintheirresetstate.The CAN module can be enabled afterallconfigurationregistersaresettotheirdesiredvalue.The followinginitialsettingsmust be made:

• ConfiguretheCAN Timingregister(CTIMn).See Section22.2.6.
• Configureeverybuffertoitsfunctionas receive/transmit.See Section22.10.1.
• Settheacceptancefilteringmasks.See Section22.4.
• EnabletheCAN interface.See Section22.10.6. BeforedisablingtheCAN module,softwaremust make surethatno transmissionisstillpending. NOTE Activityon theCAN bus can wake up thedevicefrom a low-powermode by selectingthe CANnRX pinas an inputtotheMulti-InputWake-Up module.Inthiscase,theCAN module must notbe disabledbeforeenteringthelow-powermode. DisablingtheCAN module also disablestheCANnRX pin.As an alternative,theCANnRX pincan be connectedtoany other inputpinoftheMulti-InputWake-Up module.Thisinputchannelmust thenbe configuredto triggera wake-up eventon a fallingedge (ifa dominantbitisrepresentedby a low level).In thiscase, the CAN module can be disabledbeforeenteringthe low-powermode. After waking up, softwaremust enable the CAN module again.Allconfigurationand buffer registersstillcontainthesame datatheyheldbeforethelow-powermode was entered. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 209 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

BUS_H BUS_L RS APB Bus GND Transceiver Chip 120 120 DS344 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

22.11.1 ExternalConnection

The CAN module uses the CANnTX and CANnRX pinsto connectto the physicallayerof the CAN interface.They providethefunctionalitydescribedinTable22-20. Table22-20.ExternalCAN Pins SignalName Type Description CANnTX Output TransmitdatatotheCAN bus CANnRX Input ReceivedatafromtheCAN bus The logiclevelsare configurableby theCTX and CRX bitsoftheGlobalConfigurationRegisterCGCRn (seeSection22.10.6).

22.11.2 TransceiverConnection

An externaltransceiverchipmust be connectedbetween theCAN blockand thebus.Itestablishesa bus connectionindifferentialmode and providesthedriverand protectionrequirements.Figure22-31shows a possibleISO-High-Speedconfiguration. Figure22-31.ExternalTransceiver

22.11.3 Timing Requirements

Processingmessages and updatingmessage buffersrequirea certainnumber ofclockcycles,as shown inTable22-21.These requirementsmay leadtosome restrictionsregardingtheBitTime Logicsettings and theoverallCAN performancewhicharedescribedbelow inmore detail.Waitcyclesneed tobe added tothecyclecountforCPU access totheobjectmemory as describedinSection22.9.1.The number of occurrencesperframeisdependenton thenumber ofmatchingidentifiers. Table22-21.CAN Module InternalTiming Task Cycle Count Occurrence/Frame Copy hiddenbuffertoreceivemessage buffer 17 0–1 Update statusfromTX_RTR toTX_ONCE_RTR 3 0–15

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www.ti.com SNOSCW5 –MAY 2013 Table22-21.CAN Module InternalTiming (continued) Task Cycle Count Occurrence/Frame Schedulea message fortransmission 2 0–1 The criticalpathderivesfrom receivinga remote frame,which triggersthetransmissionofone or more dataframes.There are a minimum offourbittimesin-betweentwo consecutiveframes.These bittimes startatthevalidationpointofreceivedframe (receptionof6thEOF bit)and end attheearliestpossible transmissionstartofthenextframe,whichisafterthethirdintermissionbitat100% burstbus load. These fourbittimeshave tobe setinperspectivewiththetimingrequirementsoftheCAN module. Copyright© 2013,Texas InstrumentsIncorporated DualCAN Interfaces 211 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com The minimum durationofthefourCAN bittimesisdeterminedby thefollowingBitTime Logicsettings: PSC = PSCmin = 2 TSEG1 = TSEG1min = 2 TSEG2 = TSEG2min = 1 Bittime= Sync + Time Segment 1 + Time Segment 2 Bittime= (1+ 2 + 1)tq= 4 tq Bittime= (4tq× PSC) clockcycles Bittime= (4tq× 2)clockcycles= 8 clockcycles Fortheseminimum BTL settings,fourCAN bittimestake32 clockcycles. The followingisan example thatassumes typicalcase:

• Minimum BTL settings
• Receptionand copy ofa remoteframe
• Update ofone bufferfromTX_RTR
• Scheduleofone bufferfromtransmit As outlinedinTable22-21,thecopy process,update,and schedulingthenexttransmissiongivesa total of17 + 3 + 2 = 22 clockcycles.Thereforeundertheseconditionsthereisno timingrestriction. The followingexample assumes theworstcase:
• Minimum BTL settings
• Receptionand copy ofa remotefram
• Update ofthe14 remainingbuffersfromTX_RTR
• Scheduleofone bufferfortransmit Alltheseactionsintotalrequire17 + (14× 3)+ 2 = 61 clockcyclestobe executedby theCAN module. ThisleadstothelimitationoftheBitTime Logicof61 /4 = 15.25clockcyclesperCAN bitas a minimum, resultingintheminimum clockfrequencieslistedbelow.(The frequencydepends on thedesiredbaud rate and assumes theworstcase scenariocan occurintheapplication.) Table 22-22 givesexamples forthe minimum clockfrequencyinorderto ensure properfunctionalityat variousCAN bus speeds. Table22-22.Minimum Clock Frequency Requirements Baud Rate Minimum Clock Frequency 1 Mbit/sec 15.25MHz 500 kbit/sec 7.625MHz 250 kbit/sec 3.81MHz

22.11.4 BitTime Logic CalculationExamples

The calculationof the CAN bus clocksusingCKI = 16 MHz isshown inthe followingexamples.The desiredbaud rateforbothexamplesis1 Mbit/s. Example 1 TSEG1 = TSEG1[3:0]+ 1 = 3 + 1 = 4 TSEG2 = TSEG2[2:0]+ 1 = 2 + 1 = 3 SJW = TSEG2 = 3

• Sample pointpositionedat62.5% ofbittime
• Bus Clock= 16 MHz /(2× (1+ 4 + 3))= 1 Mbit/s(nominal)

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www.ti.com SNOSCW5 –MAY 2013 Example 2 TSEG1 = TSEG1[3:0]+ 1 = 1 + 1 = 2 TSEG2 = TSEG2[2:0]+ 1 = 0 + 1 = 1 SJW = TSEG2 = 1

• Sample pointpositionedat75% ofbittime
• Bus Clock= 16 MHz /(2× (1+ 4 + 3))= 1Mbit/s(nominal)

22.11.5 Acceptance FilterConsiderations

The CAN module providestwo acceptance filtermasks GMSKn and BMSKn, as describedin message object,whichincludesthestandardidentifier,theextendedidentifier,and theframecontrolbits RTR, SRR, and IDE.

22.11.6 Remote Frames

Remote framescan be automaticallyprocessedby theCAN module.However,tofullyenablethisfeature, theRTR/ XRTR bits(forbothstandardand extendedframes)withintheBMSKn and/orGMSKn register need to be setto “don’t care”. Thisisbecause a remote frame withthe RTR bitsetshouldtriggerthe transmissionof a data frame withthe RTR bitclearand thereforethe ID bitsof the receivedmessage need topass throughtheacceptancefilter.The same appliestotransmittingremoteframesand switching toreceivethecorrespondingdataframes.

22.12 Usage Notes

Under certainconditions,the CAN module receivesa frame sent by itself,even though the loopback featureisdisabled.Two conditionsmust be truetocause thismalfunction:

• A transmitbufferand atleastone receivebufferare configuredwiththesame identifier.Assume this identifieriscalledID_RX_TX. Withregardtothereceivebuffer,thismeans thatthebufferidentifierand thecorrespondingfitermasks are setup ina way thatthebufferisabletoreceiveframeswiththe identifierID_RX_TX.
• The followingsequence ofeventsoccurs: 1. A message withtheidentifierID_RX_TX fromanotherCAN node isreceivedintothereceivebuffer. 2. A message withtheidentifierID_RX_TX issentby theCAN module immediatelyafterthereception tookplace. When theseconditionsoccur,the frame sentby the CAN module willbe copiedintothe nextreceive bufferavailablefortheidentifierID_RX_TX. Ifa frame withan identifierdifferentto ID_RX_TX issentor receivedinbetween events1 and 2, the problemdoes notoccur.

23 Analog-to-DigitalConverter

The ADC providesthefollowingfeatures:

• 10-inputanalogmultiplexer
• 10 single-endedchannelsor5 differentialchannels
• Externalfilteringcapability
• 12-bitresolutionwith10-bitaccuracy
• Signbit
• 10-microsecondconversiontime
• Internalorexternalstarttrigger Copyright© 2013,Texas InstrumentsIncorporated Analog-to-DigitalConverter 213 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

ADC_DELAY1 Start Interrupt (IRQ9) Wake-Up (WUI53) Done PCLK Clock ADC SEQUENCER VREFNVREFP TRIGGER DELAY1 Auxiliary Clock 1 MUXOUT1 ADCIN CLKDIVASYNC ADC9 MUX_CFG ADC3 ADC1 ADC0 ADC_DELAY2 DELAY2 ADC2 ADC4 ADC2ADC0ADVCC ADC1VREF ADC3ADGND Control Input Multi- plexer Int/Ext Multi- plexer ADC Clock ADC_CONTROL Result ADCRESLT 4-Word FIFO APB Bus CLKSEL Clock ADC_DIV ADCIN PREF_CFG NREF_CFG CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

• Programmable startdelayafterstarttrigger
• Pollorinterrupton conversioncomplete Figure23-1.Analog-to-DigitalConverterBlock Diagram

23.1 FuncationalDescription

The ADC module consistsof an analog/digitalconverterand associatedstatemachine,togetherwith analogmultiplexerstosetup signalpathsforsamplingand voltagereferences,logictocontroltriggering oftheconverter,and a bus interface.

23.1.1 Data Path

Up to 10 pinson the FBGA-224 package may be configuredas 10 single-endedanalog inputsor 5 differentialpairs.(Two pinsareavailableas single-endedinputsorone differentialpairon theFBGA-144 package).Analog/digitaldatapasses throughfourmain blocksintheADC module between theinputpins and theAPB bus:

• InputMultiplexer— an analogmultiplexerthatselectsamong theinputchannels.
• Internal/ExternalMultiplexer— an analog multiplexerthatselectsbetween the outputof the Input Multiplexerand theADCIN externalanaloginput.
• Analog/DigitalConverter— receivesthe outputof the Internal/ExternalMultiplexerand performsthe analogtodigitalconversion.

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• ADCRESLT Register— makes conversionresultsfrom the ADC availableto the on-chipbus. The ADCRESLT registerincludesthe software-visibleend of a 4-word FIFO used to queue conversion results. The configurationof the analogsignalpathsiscontrolledby fieldsinthe ADCGCR register.The Input Multiplexeriscontrolledby the MUX_CFG field.The Internal/ExternalMultiplexeriscontrolledby the ADCIN bit.The analogmultiplexersforselectingthevoltagereferencesused by theADC arecontrolledby thePREF_CFG and NREF_CFG fields. The outputof the InputMultiplexerisavailableexternallyas the MUXOUT0 and MUXOUT1 signals.In single-endedmode, onlyMUXOUT0 isused. In differentialmode, MUXOUT0 isthe positivesideand MUXOUT1 isthenegativeside.The MUXOUT0 and MUXOUT1 outputsand theADCIN externalanalog inputare providedso thatexternalsignalconditioningcircuits(such as filters)may be appliedto the analogsignalsbeforeconversion.The MUXOUT0, MUXOUT1, and ADCIN signalsarealternatefunctions oftheADC inputs,so thenumber ofavailableADC inputsisreducedwhen thesesignalsareused.

23.1.2 Operation

The TRIGGER blockmay be configuredtoinitiatea conversionfromeitherofthesesources:

• ExternalASYNC Input— an edge on the ASYNC inputtriggersa conversion.This inputmay be configuredto be sensitiveto risingor fallingedges,as controlledby the POL bitinthe ADCCNTRL register.
• ADCSTART Register— writingany valuetotheADCSTART registertriggersa conversion. The TRIGGER blockincorporatesa glitchfilterto suppresstransientspikeson the ASYNC input.The TRIGGER blockwillrecognizeASYNC pulsewidthsof10 ns or greater.Once a triggereventhas been recognized,no furthertriggeringisrecognizeduntiltheconversioniscompleted. When the ASYNC inputisselectedas the triggersource,itmay be configuredforautomaticor non- automaticmode, as controlledby theAUTO bitintheADCCNTRL register:
• Automatic Mode — a conversionistriggeredby any qualifiededge on the ASYNC input(unlessa conversionisalreadyinprogress).
• Non-Automatic Mode — beforea conversionmay be triggeredfrom theASYNC input,softwaremust “prime”theTRIGGER blockby writingtheADCSTART register.Once theTRIGGER blockisprimed,a conversionistriggeredby any qualifiededge on theASYNC input.Aftertheconversioniscompleted, no additionaltriggereventswillbe recognizeduntilsoftwareonce againprimestheTRIGGER blockby writingtheADCSTART register. Once a triggereventisrecognized,the DELAY1 blockwaitsfora programmable delayspecifiedinthe ADC_DELAY1 fieldoftheADCSCDLY register.Then,itassertstheStartsignaltotheADC SEQUENCER block. When theStartsignalisreceived,theADC SEQUENCER blockinitiatestheconversionintheADC. After theconversioniscomplete,theresultisloadedintotheFIFO,and theDone signalisasserted. The ADCRESLT registerincludesthe software-visibleend of a 4-word FIFO, which allowsup to 4 conversionresultsto be queued forreading.Reading the ADCRESLT registerunloadsthe FIFO. Ifthe FIFO overflows,a bitissetintheADCRESLT register,and thelastconversionresultislost. The Done signalisvisibletosoftwareas theADC_DONE bitintheADCRESLT register.The Done signal isalsoan inputtotheinterruptcontroller(IRQ9).The interruptwillbe assertedwhenever theFIFO isnot empty (butwilldeassertforone PCLK Clock periodafterthe ADCRESLT registeris read).Total conversiontimeis10 microseconds. The Done signalisalsoan inputtotheMulti-InputWake-Up unit(WUI53).The MIWU inputisasserted whenever theFIFO isnotempty (butwilldeassertforone clockperiodaftertheADCRESLT registeris read).The wake-up outputisprovidedso thattheADC module can bringthesystem outofa low-power mode when a conversionoperationiscompleted.Itassertsearlierthantheinterruptoutput. Copyright© 2013,Texas InstrumentsIncorporated Analog-to-DigitalConverter 215 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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23.1.3 ADC Clock Generation

The DELAY2 blockgeneratesADC Clock,which isthe clockused internallyby the ADC module.ADC Clockisderivedfromeither:

• PCLK Clock— a programmabledividerisavailabletogeneratethe12 MHz clockrequiredby theADC fromthePCLK Clock.
• AuxiliaryClock 1— may be used to performconversionswhen the PCLK Clock isslowed down or suspended inlow-powermodes. The DELAY2 blockreceivestheclocksourceselectedby theCLKSEL bitoftheADCACR registerand adds a number of asynchronousincrementaldelay unitsspecifiedin the ADC_DELAY2 fieldof the ADCSCDLY register.This delayed clock(ADC Clock)then drivesthe TRIGGER, ADC, and ADC SEQUENCER blocks.ADC ClockalsodrivestheADC_DIV clockdivider,whichgeneratestheclockwhich drivestheDELAY1 block. Because the ADCRESLT FIFO isdrivenby PCLK Clock (notADC Clock),a conversionresultwillnot propagatetotheoutputoftheFIFO when PCLK Clockissuspended.

23.1.4 ADC VoltageReferences

The ADC blockhas positiveand negativevoltagereferenceinputs,VREFP and VREFN. Insingle-ended mode, onlyVREFP isused.An analogmultiplexerallowsselectingan externalVREF pin,the analog supplyvoltageADVCC, or the analog inputsADC0 or ADC1 as the positivevoltagereference,as controlledby thePREF_CFG fieldoftheADCGCR register.Anotheranalogmultiplexerallowsselecting the analogground ADGND or the analoginputsADC2 or ADC3 as the negativevoltagereference,as controlledby theNREF_CFG fieldoftheADCGCR register.

23.2 OperationinLow-Power Modes

To reduce the levelof switchingnoise in the environmentof the ADC, itis possibleto operatethe CP3SP33 in low-power modes, in which the PCLK Clock is slowed or switchedoff.Under these conditions,AuxiliaryClock 1 can be selectedas the clocksource forthe ADC module, however conversionresultscannotbe readby thesystemwhilethePCLK Clockissuspended.To operateina low- power mode: 1. ADC isconfiguredand a conversionisprimedortriggered. 2. A low-powermode isentered. 3. ADC conversioncompletesand a wake-up signalisassertedtotheMIWU unit. 4. Devicewakes up and processestheconversionresult. To conservepower,theADC shouldbe disabledbeforeenteringa low-powermode ifitsfunctionisnot required.

23.3 FreezeMode

When Freezemode isentered,theADC willexhibitthefollowingspecificbehavior:

• The automaticclear-on-readfunctionoftheresultregister(ADCRESLT) isdisabled.
• The FIFO isupdatedas usual,and an interruptfora completedconversioncan be asserted.

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23.4 ADC RegisterSet

Table23-1liststheADC registers. Table23-1.ADC Registers Name Address Description ADCGCR FF AC00h ADC GlobalConfigurationRegister ADCACR FF AC04h ADC AuxiliaryConfigurationRegister ADCCNTRL FF AC08h ADC ConversionControlRegister ADCSTART FF AC0Ch ADC StartConversionRegister ADCSCDLY FF AC10h ADC StartConversionDelayRegister ADCRESLT FF AC14h ADC ResultRegister

23.4.1 ADC GlobalConfigurationRegister(ADCGCR)

The ADCGCR registerisa 16-bit,read/writeregisterthatcontrolsthebasicoperationoftheinterface.The APB bus masterhas read/writeaccesstotheADCGCR register.Afterresetthisregisteriscleared. 15 14 13 12 11 10 9 7 6 3 2 1 0 MUXOUTEN INTEN NREF_CFG PREF_CFG Reserved MUX_CFG DIFF ADCIN CLKEN CLKEN The ClockEnablebitcontrolswhethertheADC module isrunning.When thisbitisclear,all ADC clocksaredisabled,theADC analogcircuitsareina low-powerstate,and ADC registers(otherthantheADCGCR and AGCACR registers)arenotwriteable.Clearingthis bitreinitializestheADC statemachine and cancelsany pendingtriggerevent.Settingthis bitenablestheADC clocksand powers up theADC analogcircuits.The converteris operationalwithin0.25µs ofbeingenabled. 0 – ADC disabled. 1 – ADC enabled. ADCIN The ADCIN bitselectsthesourceoftheADC input.When thebitisclear,thesourceisthe 10-channelInputMultiplexer.When thebitisset,thesourceistheADCIN pin. 0 – ADC inputisfrom10-channelmultiplexer. 1 – ADC inputisfromADCIN pin. DIFF The DifferentialOperationMode bitand theMUX_CFG fieldconfiguretheanalogcircuitsof theADC module.When thisbitisclear,theADC module operatesinsingle-endedmode. When thisbitisset,theADC operatesindifferentialmode. 0 – Single-endedmode. 1 – Differentialmode. MUX_CFG The MultiplexerConfigurationfieldand theDIFF bitconfiguretheanalogcircuitsoftheADC module,as shown below. Channel Channel (DIFF= 1)MUX_CFG (DIFF= 0) + - 0000 0 0 1 0001 1 1 0 0010 2 2 3 0011 3 3 2 0100 4 4 5 0101 5 5 4 0110 6 6 7 0111 7 7 6 Copyright© 2013,Texas InstrumentsIncorporated Analog-to-DigitalConverter 217 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Channel Channel (DIFF= 1)MUX_CFG (DIFF= 0) + - 1000 8 8 9 1001 9 9 8 1010 to1111 Reserved PREF_CFG The PositiveVoltageReferenceConfigurationfieldspecifiesthesourceoftheADC positivevoltagereference,as shown below: PREF_CFG PREF Source

00 Internal(ADVCC)

01 VREF

10 ADC0

11 ADC1

NREF_CFG The NegativeVoltageReferenceConfigurationfieldspecifiesthesourceoftheADC negativevoltagereference,as shown below: NREF_CFG NREF source

00 Internal(ADGND)

01 Reserved

10 ADC2

11 ADC3

MUXOUTEN The MUXOUT EnablebitcontrolswhethertheoutputoftheInputMultiplexerisavailable externally.Insingle-endedmode, theMUXOUT0 pinisactiveand theMUXOUT1 pinis disabled(TRI-STATE).Indifferentialmode, bothMUXOUT0 and MUXOUT1 areactive. 0 – MUXOUT0 and MUXOUT1 disabled. 1 – MUXOUT0 and MUXOUT1 enabled. INTEN The InterruptEnablebitcontrolswhethertheADC interrupt(IRQ9)isenabled.When enabled,theinterruptrequestisassertedwhen validdataisavailableintheADCRESLT register.Thisbithas no effecton thewake-up signaltotheMIWU unit(WUI53). 0 – IRQ9 disabled. 1 – IRQ9 enabled.

23.4.2 ADC AuxiliaryConfigurationRegister(ADCACR)

The ADCACR registerisa 16-bit,read/writeregisterused tocontroltheclockconfigurationand reportthe statusof the ADC module.The APB bus master has read/writeaccess to the ADCACR register.After reset,thisregisterisclear. 15 14 13 12 3 2 1 0 CNVT TRG PRM Reserved CLKDIV CLKSEL CLKSET The ClockSelectbitselectstheclocksourceused by theDELAY2 blocktogeneratethe ADC clock. 0 – ADC clockderivedfromPCLK Clock. 1 – ADC clockderivedfromAuxiliaryClock1. CLKDIV The ClockDivisorfieldspecifiesthedivisorappliedtoPCLK Clocktogeneratethe12 MHz clockrequiredby theADC module.OnlythePCLK Clockisaffectedby thisdivisor.The divisorisnotused when AuxiliaryClock1 isselectedas theclocksource.

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11 Reserved

PRM The ADC Primedbitisa read-onlybitthatindicatestheADC has been primedtoperforma conversionby writingtotheADCSTART register.The bitisclearedaftertheconversionis completed. 0 – ADC has notbeen primed. 1 – ADC has been primed. TRG The ADC Triggeredbitisa read-onlybitthatindicatestheADC has been triggered.The bitis setduringany pre-conversiondelay.The bitisclearedaftertheconversioniscompleted. Once triggered,no new triggereventswillbe recognizeduntilaftertheconversionhas completed,as indicatedby theADC_DONE bitintheADCRESLT register. 0 – ADC has notbeen triggered. 1 – ADC has been triggered. CNVT The ADC Conversionbitisa read-onlybitthatindicatestheADC has been primedtoperform a conversion,a validinternalorexternaltriggereventhas occurred,any preconversiondelay has expired,and theADC conversionisinprogress.The bitisclearedaftertheconversionis completed. 0 – ADC isnotperforminga conversion. 1 – ADC conversionisinprogress.

23.4.3 ADC Conversion ControlRegister(ADCCNTRL)

The ADCCNTRL registerisa 16-bit,read/writeregisterthatspecifiesthe triggerconditionsforan ADC conversion.Afterreset,theregisteriscleared. 15 3 2 1 0 Reserved AUTO EXT POL POL The ASYNC Polaritybitspecifiesthepolarityofedges whichtriggerADC conversions. 0 – ASYNC inputissensitivetorisingedges. 1 – ASYNC inputissensitivetofallingedges. EXT The ExternalTriggerbitselectswhetherconversionsaretriggeredby writingtheADCSTART registeroractivityon theASYNC input. 0 – ADC conversionstriggeredby writingtotheADCSTART register. 1 – ADC conversionstriggeredby qualifiededges on ASYNC input. AUTO The Automaticbitcontrolswhetherautomaticmode isenabled,inwhichany qualifiededge on theASYNC inputisrecognizedas a triggerevent.When automaticmode isdisabled,theADC module must be “primed”beforea qualifiededge on theASYNC inputcan triggera conversion. To primetheADC module,softwaremust writetheADCSTART registerwithany valuebefore an edge on theASYNC inputisrecognizedas a triggerevent.Aftertheconversionis completed,theASYNC inputwillbe ignoreduntilsoftwareagainwritestheADCSTART register.The AUTO bitisignoredwhen theEXT bitis0. 0 – Automaticmode disabled. 1 – Automaticmode enabled.

23.4.4 ADC StartConversion Register(ADCSTART)

The ADCSTART registerisa write-onlyregisterused by softwaretoinitiatean ADC conversion.Writing any valueto thisregisterwillcause the ADC to initiatea conversionor prime the ADC to initiatea conversion,as controlledby theADCCNTRL register. Copyright© 2013,Texas InstrumentsIncorporated Analog-to-DigitalConverter 219 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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23.4.5 ADC StartConversion Delay Register(ADCSCDLY)

The ADCSCDLY registerisa 16-bit,read/writeregisterthatcontrolscriticaltimingparametersforthe operationoftheADC module.Afterreset,theregisteriscleared. 15 14 13 5 4 0 ADC_DIV ADC_DELAY1 ADC_DELAY2 ADC_DELAY2 The ADC Delay2 fieldspecifiesthedelaybetween theADC module clocksource (eitherPCLK Clockaftera programmabledividerorAuxiliaryClock1)and theADC clock.The rangeofeffectivevaluesforthisfieldis0 to20.Valuesabove 20 produce thesame delayas 20,whichisabout42 ns. ADC_DELAY1 The ADC Delay1 fieldspecifiesthenumber ofclockperiodsby whichthetriggerevent willbe delayedbeforeinitiatinga conversion.The timebaseforthisdelayistheADC clock(12MHz) dividedby theADC_DIV divisor.The ADC_DELAY1 fieldhas 9 bits, whichcorrespondstoa maximum delayof511 clockperiods. ADC_DIV The ADC ClockDivisorfieldspecifiesthedivisorappliedtotheADC clock(12MHz) to generatetheclockused todrivetheDELAY1 block.The fieldisbiasedby 1,so the divisorselectedby theADC_DIV fieldmay be 1,2,3,or4.Witha module clockof12 MHz, themaximum delaywhichcan be providedby ADC_DIV and ADC_DELAY settingsis:

23.4.6 ADC ResultRegister(ADCRESLT)

The ADCRESLT registerisa 16-bit,read-onlyregisterthatincludesthesoftware-visibleend ofa 4-word FIFO.ConversionresultsareloadedintotheFIFO fromtheADC and unloadedwhen softwarereadsthe ADCRESLT register.The ADCRESLT registerisread-only.The definedfieldsinthisregisterarecleared when theregisterisread.Afterreset,thisregisterisclear. 15 14 13 12 11 0 ADC_DONE ADC_OFLW Reserved SIGN ADC_RESULT ADC_RESULT The ADC Resultfieldholdsa 12-bitvaluefortheconversionresult.IftheADC_DONE bitisclear,thereisno validresultinthisfield,and thefieldwillhave a valueof0.The ADC_RESULT fieldand theSIGN bittogetherformthesoftware-visibleend ofthe ADC FIFO. SIGN The Signbitindicateswhetherthe(minus)– inputhas a voltagegreaterthanthe(plus) + input(differentialmode only).Forexample ifADCGCR.MUX_CFG is000b,ADC0 is the+ inputand ADC1 isthe– input.Ifthevoltageon ADC0 isgreaterthanthevoltage on ADC1, theSIGN bitwillbe 0;ifthevoltageon ADC0 islessthanthevoltageon ADC1, theSIGN bitwillbe 1.Insingle-endedmode, thisbitalwaysreadsas 0. 0 – Indifferentialmode, + inputhas a voltagegreaterthanthe– input.Insingle-ended mode, thisbitisalways0. 1 – Indifferentialmode, – inputhas a voltagegreaterthanthe+ input. ADC_OFLW The ADC FIFO Overflowbitindicateswhetherthe4-wordFIFO behindtheADCRESLT registerhas overflowed.When thisoccurs,themost recentconversionresultislost. Thisbitisclearedwhen theADCRESLT registerisread. 0 – FIFO overflowhas notoccurred. 1 – FIFO overflowhas occurred.

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www.ti.com SNOSCW5 –MAY 2013 ADC_DONE The ADC Done bitindicateswhen an ADC conversionhas completed.When thisbitis set,thedataintheADC_RESULT fieldisvalid.When thisbitisclear,thereisno valid dataintheADC_RESULT field.The Done bitisclearedwhen theADCRESLT register isread,butiftherearequeued conversionresultsintheFIFO,theDone bitwill become setagainafterone PCLK Clockperiod. 0 – No ADC conversionhas completedsincetheADCRESLT registerwas lastread. 1 – An ADC conversionhas completedsincetheADCRESLT registerwas lastread.

24 Advanced Audio Interface

The Advanced Audio Interface(AAI)providesa serialsynchronous,fullduplexinterfaceto codecs and similarserialdevices.The transmitand receivepathsmay operateasynchronouslywithrespecttoeach other.Each pathuses a 3-wireinterfaceconsistingofa bitclock,a frame synchronizationsignal,and a datasignal. The CPU interfacecan be eitherinterrupt-drivenorDMA. Iftheinterfaceisconfiguredforinterrupt-driven I/O,dataisbufferedinthereceiveand transmitFIFOs.IftheinterfaceisconfiguredforDMA, thedatais bufferedinregisters. The AAI is functionallysimilarto a Motorola™ Synchronous SerialInterface(SSI).Compared to a standardSSI implementation,theAAI interfacedoes notsupporttheso called“On-demand Mode ”.Italso does notallowgatingoftheshiftclocks,so thereceiveand transmitshiftclocksare alwaysactivewhile theAAI isenabled.The AAI alsodoes notsupport12-bitand 24-bitdataword lengthormore than4 slots (words)perframe.The reductionofsupportedmodes isacceptable,because themain purposeoftheAAI istoconnecttoaudiocodecs,ratherthantootherprocessors(DSPs). The implementationof a FIFO as a 16-word receiveand transmitbufferisan additionalfeature,which simplifiescommunicationand reducesinterruptload.IndependentDMA isprovidedforeach of the four supportedaudiochannels(slots).The AAI alsoprovidesspecialfeaturesand operatingmodes tosimplify gain controlin an externalcodec and to connectto an ISDN controllerthroughan IOM-2 compatible interface.

24.1 Audio InterfaceSignals

24.1.1 SerialTransmitData (STD)

The STD pinisused to transmitdata from the serialtransmitshiftregister(ATSR). The STD pinisan outputwhen dataisbeingtransmittedand isinhigh-impedancemode when no dataisbeingtransmitted. The data on the STD pinchanges on the positiveedge of the transmitshiftclock(SCK).The STD pin goes intohigh-impedancemode on the negativeedge of SCK of the lastbitof the data word to be transmitted,assuming no otherdataword followsimmediately.Ifanotherdataword followsimmediately, theSTD pinremainsactiveratherthangoingtothehigh-impedancemode.

24.1.2 SerialTransmitClock (SCK)

The SCK pinisa bidirectionalsignalthatprovidestheserialshiftclock.Inasynchronousmode, thisclock isused onlyby the transmitterto shiftout data on the positiveedge. The serialshiftclockmay be generatedinternallyoritmay be providedby an externalclocksource.Insynchronousmode, theSCK pin isused by boththetransmitterand thereceiver.Data isshiftedoutfromtheSTD pinon thepositiveedge, and dataissampled on theSRD pinon thenegativeedge.

24.1.3 SerialTransmitFrame Sync (SFS)

The SFS pinisa bidirectionalsignalwhich providesframe synchronization.Inasynchronousmode, this signalisused as frame sync onlyby thetransmitter.Insynchronousmode, thissignalisused as frame sync by boththetransmitterand receiver.The framesync signalmay be generatedinternally,oritmay be providedby an externalsource. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 221 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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24.1.4 SerialReceive Data (SRD)

The SRD pinisused as an inputwhen dataisshiftedintotheAudio ReceiveShiftRegister(ARSR). In asynchronousmode, dataon theSRD pinissampled on thenegativeedge oftheserialreceiveshiftclock (SRCLK). Insynchronousmode, dataon theSRD pinissampled on thenegativeedge oftheserialshift clock(SCK).The dataisshiftedintoARSR withthemost significantbit(MSB) first.

24.1.5 SerialReceive Clock (SRCLK)

The SRCLK pinisa bidirectionalsignalthatprovidesthereceiveserialshiftclockinasynchronousmode. In thismode, data issampled on the negativeedge of SRCLK. The SRCLK signalmay be generated internallyoritmay be providedby an externalclocksource.Insynchronousmode, theSCK pinisused as shiftclockforboth the receiverand transmitter,so the SRCLK pin isavailableforuse as a general- purposeportpinoran auxiliaryframesync signaltoaccessmultipleslavedevices(e.g.codecs)withina network(seeNetworkmode).

24.1.6 SerialReceive Frame Sync (SRFS)

The SRFS pin is a bidirectionalsignalthat providesframe synchronizationfor the receiverin asynchronousmode. The frame sync signalmay be generatedinternally,or itmay be providedby an externalsource.In synchronousmode, the SFS signalisused as the frame sync signalforboth the transmitterand receiver,so theSRFS pinisavailableforuse as a general-purposeportpinoran auxiliary framesyncsignaltoaccessmultipleslavedevices(e.g.codecs)withina network(seeNetworkmode).

24.2 Audio InterfaceModes

There are two clockingmodes: asynchronousmode and synchronousmode. These modes differinthe sourceand timingoftheclocksignalsused totransferdata.When theAAI isgeneratingthebitshiftclock and framesyncsignalsinternally,synchronousmode must be used. There aretwo framingmodes: normalmode and networkmode. Innormalmode, one word istransferred perframe.Innetworkmode, up tofourwords aretransferredperframe.A word may be 8 or16 bits.The partoftheframe which carriesa word iscalleda slot.Network mode supportsmultipleexternaldevices sharingthe interface,inwhich each deviceisassigneditsown slot.Separateframe sync signalsare provided,so thateach deviceistriggeredtosend orreceiveitsdataduringitsassignedslot.

24.2.1 Asynchronous Mode

Inasynchronousmode, thereceiveand transmitpathsoftheaudiointerfaceoperateindependently,with each path using itsown bitclockand frame sync signal.The frame sync signalsmust be supplied externally.

24.2.2 Synchronous Mode

Insynchronousmode, thereceiveand transmitpathsoftheaudiointerfaceuse thesame shiftclockand framesync signal.The bitshiftclockand framesync signalforbothpathsarederivedfromthesame set ofclockprescalers.

24.2.3 Normal Mode

Innormalmode, each risingedge on theframesync signalmarks thebeginningofa new frameand also thebeginningofa new slot.A slotdoes notnecessarilyoccupy theentireframe.(A framecan be longer thanthedataword transmittedaftertheframe sync pulse.)Typically,a codec startstransmittinga fixed lengthdata word (e.g.8-bitlog PCM data)withthe frame sync signal,then the codec’s transmitpin returnstothehigh-impedancestatefortheremainderoftheframe. The AudioReceiveShiftRegister(ARSR) deserializesdatareceivedon theSRD pin(serialreceiverdata). Only thedatasampled aftertheframesync signalaretreatedas valid.Iftheinterfaceisinterrupt-driven, validdatabitsaretransferredfromtheARSR tothereceiveFIFO.IftheinterfaceisconfiguredforDMA, thedataistransferredtothereceiveDMA register0 (ARDR0).

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(SFS/SRFS) Shift Data (STD/SRD) Data High-impedance Frame Data DS053 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 The serialtransmitdata (STD) pinisonlyan activeoutputwhiledata isshiftedout.Afterthe defined number ofdatabitshave been shiftedout,theSTD pinreturnstothehigh-impedancestate. For operationinnormal mode, the SlotCount Selectfieldinthe GlobalConfigurationregister(AGCR) must be loaded with00b (one slotper frame).In addition,the SlotAssignment fieldforreceiveand transmitmust selectslot0. IftheinterfaceisconfiguredforDMA, theDMA slotassignmentbitsmust selectslot0.Inthiscase,the audiodataistransferredtoorfromthereceiveortransmitDMA register0 (ARDR0/ATDR0). Figure24-1shows theframetimingwhileoperatinginnormalmode witha longframesyncinterval. Figure24-1.Normal Mode Frame 24.2.3.1IRQ Support Ifthereceiverinterfaceisconfiguredforinterrupt-drivenI/O(RXDSA0 = 0),allreceiveddataare loaded intothereceiveFIFO. An IRQ isassertedas soon as thenumber ofdatabytesor words inthereceive FIFO isgreaterthana programmablewarninglimit. Ifthetransmitterinterfaceisconfiguredforinterrupt-drivenI/O(TXDSA0 = 0),alldatatobe transmittedis readfromthetransmitFIFO.An IRQ isassertedas soon as thenumber databytesorwords availablein thetransmitFIFO isequalorlessthana programmablewarninglimit. 24.2.3.2DMA Support IfthereceiverinterfaceisconfiguredforDMA (RXDSA0 = 1),receiveddataistransferredfromtheARSR intotheDMA receivebuffer0 (ARDR0). A DMA requestisassertedwhen theARDR0 registerisfull.Ifthe transmitterinterfaceisconfiguredforDMA (TXDSA0 = 1),datatobe transmittedarereadfromtheDMA transmitbuffer0 (ATDR0).A DMA requestisassertedtotheDMA controllerwhen theATDR0 registeris empty. Figure24-2shows thedataflowforIRQ and DMA mode innormalMode. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 223 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

TXDSA = 1 TXDSA = 0 ARSR SRD RX FIFO ARDR 0 DMA Request 1 IRQ DMA Slot Assignment RXDSA = 1 R XDSA = 0 A TSR STD TX FIFO A TDR 0 DMA Request 0 IRQ DS054 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure24-2.IRQ/DMA Support inNormal Mode 24.2.3.3Network Mode Innetworkmode, each frameiscomposed ofmultipleslots.Each slotmay transfer8 or16 bits.Allofthe slotsina frame must have thesame length.Innetworkmode, thesync signalmarks thebeginningofa new frame. More than two devicescan communicate withina networkusingthe same clockand data lines.The devicesconnectedtothesame bus use a time-multiplexedapproachtoshareaccess tothebus.Each devicehas certainslotsassignedtoit,inwhich onlythatdeviceisallowedtotransferdata.One master deviceprovidesthebitclockand theframesync signal(s).On allother(slave)devices,thebitclockand framesyncpinsareinputs. Up tofourslotscan be assignedtotheAAI,as itsupportsup tofourslotsperframe.Any otherslotswithin theframearereservedforotherdevices. The transmitteronlydrivesdataon theSTD pinduringslotswhichhave been assignedtotheAAI.During allotherslots,theSTD outputisinhigh-impedancemode, and datacan be drivenby otherdevices.The assignmentof slotsto the transmitterisspecifiedby the TransmitSlotAssignmentbits(TXSA) inthe ATCR register.Itcan alsobe specifiedwhetherthedatatobe transmittedistransferredfromthetransmit FIFO orthecorrespondingDMA transmitregister.Thereisone DMA transmitregister(ATDRn) foreach of themaximum fourdataslots.Each slotcan be configuredindependently. On the receiverside,only the validdata bitswhich were receivedduringthe slotsassignedto this interfaceare copiedintothe receiveFIFO or DMA registers.The assignmentof slotsto the receiveris specifiedby the Receive SlotAssignment bits(RXSA) in the ATCR register.Itcan alsobe specified whetherthereceiveddataiscopiedintothereceiveFIFO orintothecorrespondingDMA receiveregister. There isone DMA receiveregister(ARDRn) foreach ofthemaximum fourdataslots.Each slotmay be configuredindividually. Figure24-3 shows the frame timingwhileoperatinginnetworkmode withfourslotsper frame,slot1 assignedtotheinterface,and a longframesyncinterval.

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(STD/SRD) High-impedance Unused SlotsSlot1 Frame Slot0 Long Frame Sync (SFS/SRFS) Data (ignored) Data (ignored) Data (valid) DS055 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure24-3.Network Mode Frame 24.2.3.4InterruptSupport IfDMA isnotenabledfora receiveslotn (RXDSAn = 0),alldatareceivedinthisslotisloadedintothe receiveFIFO. The interruptrequestisassertedas soon as the number of data bytesor words inthe receiveFIFO isgreaterthana programmablewarninglimit. IfDMA isnotenabledfora transmitslotn (TXDSAn = 0),alldatatobe transmittedinthisslotare read from the transmitFIFO. The interruptrequestisassertedas soon as the number data bytesor words availableinthetransmitFIFO isequalorlessthana programmablewarninglimit. Because theinterruptrequestcan be handledby eithertheCPU orDSP interruptcontrollers,theinterrupt requestispassed throughtheAudioSubsystem Controller(ASC),whichisprogrammed torouteittothe interruptcontroller.To use thecodec interrupt,itmust be enabledatthreelevels:

• AAI module— theinterruptmust be enabledintheAISCR register.
• ASC module— the AAI interruptisassignedto ASC interruptchannel7, so bit7 inthe ASCINTSEL registermust be cleartoselectCPU interruptcontrollerorsettoselecttheDSP interruptcontroller
• Interruptcontroller— the interruptrequestmust be enabled in the interruptcontroller.For the CPU interruptcontroller,thisisinterruptrequestIRQ27 24.2.3.5DMA Support IfDMA supportis enabled fora receiveslotn (RXDSA0 = 1),alldata receivedin thisslotis only transferredfrom the ARSR intothe correspondingDMA receiveregister(ARDRn). A DMA requestis assertedwhen theARDRn registerisfull. IfDMA isenabledfora transmitslotn (TXDSAn = 1),alldatatobe transmittedinslotn arereadfromthe correspondingDMA transmitregister(ATDRn).A DMA requestisassertedtotheDMA controllerwhen the ATDRn registerisempty Figure24-4illustratesthedataflowforIRQ and DMA supportinnetworkmode, usingfourslotsperframe and DMA supportenabledforslots0 and 1 inreceiveand transmitdirection. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 225 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

(auxiliary frame sync) SRFS (auxiliary frame sync) STD/SRD Data from/to Codec 1 Data from/to Codec 3 Data from/to Codec 2 Slot 2 Slot 3 DS057 DMA Slot Assignment Slot 1 dataSlot 0 data Slot 2 and 3 data ARSR SRD ARDR 0 DMA Request 1ARDR 1 DMA Request 3ARDR 2 ARDR 3 RX FIFO IRQ DMA Slot Assignment Slot 1 dataSlot 0 dataA TSR STD A TDR 0 DMA Request 0A TDR 1 DMA Request 2 A TDR 2 A TDR 3 TX FIFO IRQ Slot 2 and 3 data DS056 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure24-4.IRQ/DMA Support inNetwork Mode Iftheinterfaceoperatesinsynchronousmode, thereceiveruses thetransmitbitclock(SCK) and transmit frame sync signal(SFS).Thisallowsthepinsused forthereceivebitclock(SRCLK) and receiveframe sync (SRFS) tobe used as additionalframesync signalsinnetworkmode. The extraframesync signals areusefulwhen theaudiointerfacecommunicatestomore thanone codec,because codecs typicallystart transmissionimmediatelyaftertheframesync pulse.The SRCLK pinisdrivenwitha framesync pulseat the beginningof the second slot(slot1),and the SRFS pinisdrivenwitha frame sync pulseat the beginningofslot2.Figure24-5 shows a frame timingdiagramforthisconfiguration,usingtheadditional framesyncsignalson SRCLK and SRFS toaddressup tothreedevices. Figure24-5.Accessing Three Devices inNetwork Mode

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www.ti.com SNOSCW5 –MAY 2013 Because fourofthesixAAI DMA requestscan be handledby eithertheCPU or DSP DMA controllers, theseDMA requestsarepassed throughtheAudioSubsystem Controller(ASC),whichisprogrammed to routethem totheDMA controller.To use theseAAI DMA requests,theymust be enabledatthreelevels:

• AAI module— theDMA requestsmust be enabledintheADMACR register.
• ASC module— theAAI DMA requestsare assignedtoASC DMA channels6 (ARDR0), 7 (ATDR0), 8 (ARDR1), and 9 (ATDR1). These channelsare controlledby bits6,7,8,and 9 intheASCDMASEL0 register,respectively.The bitsmust be cleartoselecttheCPU DMA controllerorsettoselecttheDSP DMA controller.IftheDSP DMA controllerisselected,theDSP DMA channelmust be enabledinthe ASCDDMASELn registers.
• DMA controller— the DMA requestmust be enabled in the DMA controller.For the CPU DMA controller,theseareDMA requests6 (ARDR0), 7 (ATDR0),8 (ARDR1), and 9 (ATDR1).

24.3 BitClock Generation

An 8-bitprescalerisprovidedtodividetheaudiointerfaceinputclockdown totherequiredbitclockrate. Softwarecan choose between two inputclocksources,AuxiliaryClock1 and AuxiliaryClock8. The inputclockisdividedby thevalueoftheprescalerBCPRS7:0 + 1 togeneratethebitclock. The bitclockratefbitcan be calculatedby thefollowingequation: fbit= n × fSample × Data Length n = Number ofSlotsperFrame fSample = Sample FrequencyinHz Data Length= Lengthofdataword inmultiplesof8 bits The idealrequiredprescalervaluePidealcan be calculatedas follows: Pideal= fAudio In/fbit fAudio In = SourceClockFrequencyinHz The realprescalermust be setto an integervalue,which shouldbe as closeas possibleto the ideal prescalervalue,tominimizethebitclockerror,fbit_error. fbit_error[%]= (fbit– fAudio In/Preal)/fbit× 100 Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 227 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Example: The audiointerfaceisused totransfer13-bitlinearPCM dataforone audiochannelata sample rateof8k samples persecond.The inputclockoftheaudiointerfaceis12MHz. Furthermore,thecodec requiresa minimum bitclockof256 kHz tooperateproperly.Therefore,thenumber ofslotsperframemust be setto 2 (networkmode) althoughactuallyonlyone slot(slot0) isused.The codec and theaudiointerfacewill put theirdata transmitpinsin TRI-STATE mode afterthe PCM data word has been transferred.The requiredbitclockratefbitcan be calculatedby thefollowingequation: fbit= n × fSample × Data Length= 2 × 8 kHz × 16 = 256 kHz The idealrequiredprescalervaluePidealcan be calculatedas follows: Pideal= fAudio In/fbit= 12 MHz /256 kHz = 46.875 Therefore,therealprescalervalueis47.Thisresultsina bitclockerrorequalto: fbit_error= (fbit– fAudio In/Preal)/fbit× 100 = (256kHz – 12 MHz/47) /256 kHz × 100 = 0.27%

24.4 Frame Clock Generation

The clockfortheframesynchronizationsignalsisderivedfromthebitclockoftheaudiointerface.A 7-bit prescalerisused to dividethe bitclockto generatethe frame sync clockforthe receiveand transmit operations.The bitclockisdividedby FCPRS + 1.Inotherwords,thevaluesoftwaremust writeintothe ACCR.FCPRS fieldisequaltothebitnumber per frame minus one.The frame may be longerthanthe validdataword butitmust be equaltoor largerthanthe8-bitor 16-bitword.Even if13-,14-,or 15-bit dataisbeingused,theframewidthmust alwaysbe atleast16 bitswide. Inaddition,softwarecan specifythelengthofa longframesync signal.A longframesync signalcan be either6,13,14,15,or16 bitslong,dependingon theexternalcodec beingused.The framesync length can be configuredby theFrame Sync Lengthfield(FSL)intheAGCR register.

24.5 Audio InterfaceOperation

24.5.1 Clock Configuration

An auxiliaryclock(generatedby the Clock module describedin Section14.7) must be configuredto providea 12 MHz inputclockas a timebase forthe AAI module.The CSS bitinthe ACCR register selectswhethertheinputclockisAuxiliaryClock1 orAuxiliaryClock8.

24.5.2 Interrupts

The interruptlogicoftheAAI combines up tofourinterruptsourcesand generatesone interruptrequest signaltotheInterruptControlUnit(ICU). The fourinterruptsourcesare:

• RX FIFO Overrun– AISCR.RXEIP = 1
• RX FIFO AlmostFull(WarningLevel)– AISCR.RXIP = 1
• TX FIFO Under run– AISCR.TXEIP = 1
• TX FIFO AlmostEmpty (WarningLevel)– AISCR.TXIP=1 InadditiontothededicatedinputtotheICU forhandlingtheseinterruptsources,theSerialFrame Sync (SFS) signalistheWUI26 inputtotheMIWU (seeSection17),whichcan be programmed toassertedge- triggeredinterrupts. Figure24-6shows theinterruptstructureoftheAAI.

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RXEIP = 1 RXEIE TXIP = 1 TXIE TXEIP = 1 TXEIE DS155 RXIP = 1 RXIE CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure24-6.AAI InterruptStructure

24.5.3 Normal Mode

Innormalmode, each framesync signalmarks thebeginningofa new frameand alsothebeginningofa new slot,sinceeach frameonlyconsistsofone slot.All16 receiveand transmitFIFO locationsholddata forthesame (andonly)slotofa frame.If8-bitdataaretransferred,onlythelow byteofeach 16-bitFIFO locationholdsvaliddata.

24.5.4 Transmit

Once the interfacehas been enabled,transmittransfersare initiatedautomaticallyat the beginningof everyframe.The beginningofa new frameisidentifiedby a framesync pulse.Followingtheframesync pulse,thedataisshiftedoutfromtheATSR totheSTD pinon thepositiveedge ofthetransmitdatashift clock(SCK). DMA Operation When a completedataword has been transmittedthroughtheSTD pin,a new dataword isreloadedfrom thetransmitDMA register0 (ATDR0).A DMA requestisassertedwhen theATDR0 registerisempty.Ifa new dataword must be transmittedwhiletheATDR0 registerisstillempty,thepreviousdatawillbe re- transmitted. FIFO Operation When a completedataword has been transmittedthroughtheSTD pin,a new dataword isloadedfrom thetransmitFIFO fromthecurrentlocationoftheTransmitFIFO Read Pointer(TRP).Afterthat,theTRP isautomaticallyincrementedby 1. A writetotheAudioTransmitFIFO Register(ATFR) resultsina writetothetransmitFIFO atthecurrent locationoftheTransmitFIFO WritePointer(TWP). AftereverywriteoperationtothetransmitFIFO,TWP isautomaticallyincrementedby 1. When theTRP isequaltotheTWP and thelastaccess totheFIFO was a read operation(a transferto the ATSR), the transmitFIFO isempty.When an additionalread operationfrom the FIFO to ATSR is performed(whilethe FIFO isalreadyempty),a transmitFIFO underrunoccurs.In thisevent,the read pointer(TRP) willbe decremented by 1 (incrementedby 15) and the previousdata word willbe transmittedagain.A transmitFIFO underrunisindicatedby theTXU bitintheAudio InterfaceTransmit Statusand ControlRegister(ATSCR). Also,no transmitinterruptwillbe generated. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 229 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com When theTRP isequaltotheTWP and thelastaccesstotheFIFO was a writeoperation(totheATFR), theFIFO isfull.Ifan additionalwritetoATFR isperformed,a transmitFIFO overrunoccurs.Thiserror conditionisnotpreventedby hardware.Softwaremust ensurethatno transmitoverrunoccurs. The transmitframesynchronizationpulseon theSFS pinand thetransmitshiftclockon theSCK pinmay be generatedinternally,ortheycan be suppliedby an externalsource.

24.5.5 Receive

At thereceiver,thereceiveddataon theSRD pinisshiftedintoARSR on thenegativeedge ofSRCLK (or SCK insynchronousmode),followingthereceiveframesyncpulse,SRFS (orSFS insynchronousmode). DMA Operation When a completedataword has been receivedthroughtheSRD pin,thenew dataword iscopiedtothe receiveDMA register0 (ARDR0). A DMA requestisassertedwhen theARDR0 registerisfull.Ifa new dataword isreceivedwhiletheARDR0 registerisstillfull,theARDR0 registerwillbe overwrittenwiththe new data. FIFO Operation When a completeword has been received,itistransferredtothereceiveFIFO atthecurrentlocationof theReceiveFIFO WritePointer(RWP). Then,theRWP isautomaticallyincrementedby 1. A read from the Audio Receive FIFO Register(ARFR) resultsina read from the receiveFIFO at the currentlocationof the Receive FIFO Read Pointer(RRP). Aftereveryread operationfrom the receive FIFO,theRRP isautomaticallyincrementedby 1. When theRRP isequaltotheRWP and thelastaccesstotheFIFO was a copy operationfromtheARFR, thereceiveFIFO isfull.When a new completedataword has been shiftedintoARSR whilethereceive FIFO was alreadyfull,theshiftregisteroverruns.Inthiscase,thenew dataintheARSR willnotbe copied intotheFIFO and theRWP willnotbe incremented.A receiveFIFO overrunisindicatedby theRXO bitin theAudioInterfaceReceiveStatusand ControlRegister(ARSCR). No receiveinterruptwillbe generated. When theRWP isequaltotheRRP and thelastaccesstothereceiveFIFO was a readfromtheARFR, a receiveFIFO underrunhas occurred.Thiserrorconditionisnot preventedby hardware.Softwaremust ensurethatno receiveunderrunoccurs. The receiveframesynchronizationpulseon theSRFS pin(orSFS insynchronousmode) and thereceive shiftclockon the SRCLK (orSCK insynchronousmode) may be generatedinternally,or theycan be suppliedby an externalsource.

24.5.6 Network Mode

Innetworkmode, each framesyncsignalmarks thebeginningofnew frame.Each framecan consistofup tofourslots.The audiointerfaceoperatesina similarway tonormalmode, however,innetworkmode the transmitterand receivercan be assignedtospecificslotswithineach frameas describedbelow.

24.5.7 Transmit

The transmitteronlyshiftsoutdataduringtheassignedslot.DuringallotherslotstheSTD outputisin TRI-STATE mode. 24.5.7.1DMA Operation When a completedataword has been transmittedthroughtheSTD pin,a new dataword isreloadedfrom thecorrespondingtransmitDMA registern (ATDRn).A DMA requestisassertedwhen ATDRn isempty.If a new dataword must be transmittedina slotn whileATDRn isstillempty,thepreviousslotn datawillbe retransmitted.

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www.ti.com SNOSCW5 –MAY 2013 24.5.7.2FIFO Operation When a completedataword has been transmittedthroughtheSTD pin,a new dataword isreloadedfrom thetransmitFIFO fromthecurrentlocationoftheTransmitFIFO Read Pointer(TRP).Afterthat,theTRP isautomaticallyincrementedby 1.Therefore,theaudiodatatobe transmittedinthenextslotoftheframe isreadfromthenextFIFO location. A writetotheAudioTransmitFIFO Register(ATFR) resultsina writetothetransmitFIFO atthecurrent locationoftheTransmitFIFO WritePointer(TWP). AftereverywriteoperationtothetransmitFIFO, the TWP isautomaticallyincrementedby 1. When theTRP isequaltotheTWP and thelastaccesstotheFIFO was a readoperation(transfertothe ATSR), the transmitFIFO isempty.When an additionalread operationfrom the FIFO to the ATSR is performed(whilethe FIFO isalreadyempty),a transmitFIFO underrunoccurs.In thiscase,the read pointer(TRP) willbe decremented by 1 (incrementedby 15) and the previousdata word willbe transmittedagain.A transmitFIFO underrunisindicatedby theTXU bitintheAudio InterfaceTransmit Statusand ControlRegister(ATSCR). No transmitinterruptwillbe generated(evenifenabled). Ifthe currentTRP isequalto the TWP and the lastaccess to the FIFO was a writeoperation(tothe ATFR), theFIFO isfull.Ifan additionalwritetotheATFR isperformed,a transmitFIFO overrunoccurs. Thiserrorconditionisnotpreventedby hardware.Softwaremust ensurethatno transmitoverrunoccurs. The transmitframesynchronizationpulseon theSFS pinand thetransmitshiftclockon theSCK pinmay be generatedinternally,ortheycan be suppliedby an externalsource.

24.5.8 Receive

The receiveshiftregister(ARSR) receivesdata words of allslotsin the frame,regardlessof the slot assignmentoftheinterface.However, onlythoseARSR contentsare transferredtothereceiveFIFO or DMA receiveregisterwhich were receivedduringthe assignedtimeslots.A receiveinterruptor DMA requestisinitiatedwhen thisoccurs. 24.5.8.1DMA Operation When a completedata word has been receivedthroughthe SRD pinina slotn, the new data word is transferredtothecorrespondingreceiveDMA registern (ARDRn). A DMA requestisassertedwhen the ARDRn registerisfull.Ifa new slotn data word isreceivedwhilethe ARDRn registerisstillfull,the ARDRn registerwillbe overwrittenwiththenew data. 24.5.8.2FIFO Operation When a completeword has been received,itistransferredtothereceiveFIFO atthecurrentlocationof theReceiveFIFO WritePointer(RWP). Afterthat,theRWP isautomaticallyincrementedby 1.Therefore, datareceivedinthenextslotiscopiedtothenexthigherFIFO location. A read from the Audio Receive FIFO Register(ARFR) resultsina read from the receiveFIFO at the currentlocationof the Receive FIFO Read Pointer(RRP). Aftereveryread operationfrom the receive FIFO,theRRP isautomaticallyincrementedby 1. When the RRP isequalto the RWP and the lastaccess to the FIFO was a transferto the ARFR, the receiveFIFO isfull.When a new completedataword has been shiftedintotheARSR whilethereceive FIFO was alreadyfull,the shiftregisteroverruns.In thiscase,the new data inthe ARSR willnot be transferredtotheFIFO and theRWP willnotbe incremented.A receiveFIFO overrunisindicatedby the RXO bitintheAudioInterfaceReceiveStatusand ControlRegister(ARSCR). No receiveinterruptwillbe generated(evenifenabled). When the currentRWP isequalto the TWP and the lastaccess to the receiveFIFO was a read from ARFR, a receiveFIFO underrunhas occurred.Thiserrorconditionisnotpreventedby hardware.Software must ensurethatno receiveunderrunoccurs. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 231 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

(SCK/SRCLK) Shift Data (STD/SRD) DS156 Short Frame Sync Pulse D6D5D4D3D2D1D0 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com The receiveframesynchronizationpulseon theSRFS pin(orSFS insynchronousmode) and thereceive shiftclockon the SRCLK (orSCK insynchronousmode) may be generatedinternally,or theycan be suppliedby an externalsource.

24.6 Communication Options

24.6.1 Data Word Length

The word lengthoftheaudiodatacan be selectedtobe either8 or16 bits.In16-bitmode, all16 bitsof thetransmitand receiveshiftregisters(ATSR and ARSR) areused.In8-bitmode, onlythelower8 bitsof thetransmitand receiveshiftregisters(ATSR and ARSR) areused.

24.6.2 Frame Sync Signal

The audiointerfacecan be configuredtouse eitherlongorshortframesyncsignalstomark thebeginning ofa new dataframe.IfthecorrespondingFrame Sync Select(FSS) bitintheAudio Controland Status registerisclear,thereceiveand/ortransmitpathgeneratesorrecognizesshortframesync pulseswitha lengthofone bitshiftclockperiod.When theseshortframesync pulsesareused,thetransferofthefirst databitor thefirstslotbeginsatthefirstpositiveedge oftheshiftclockafterthenegativeedge on the framesyncpulse. Ifthe correspondingFrame Sync Select(FSS) bitinthe Audio Controland Statusregisterisset,the receiveand/ortransmitpath generatesor recognizeslongframe sync pulses.For 8-bitdata,the frame sync pulsegeneratedwillbe 6 bitshiftclockperiodslong,and for16-bitdatatheframesync pulsecan be configuredtobe 13,14,15,or 16 bitshiftclockperiodslong.When receivingframe sync,itshouldbe activeon thefirstbitofdataand stayactivefora leasttwo bitclockperiods.Itmust go lowforatleastone bitclockperiodbeforestartinga new frame.When longframe sync pulsesare used,thetransferofthe firstword (firstslot)beginsat the firstpositiveedge of the bitshiftclockafterthe positiveedge of the framesyncpulse.Figure24-7shows examplesofshortand longframesyncpulses. Figure24-7.Shortand Long Frame Sync Pulses Some codecs requirean invertedframesync signal.Thisisavailableby settingtheInvertedFrame Sync bitintheAGCR register.

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A CD1A CD2D1D0 D2 D3 D4 D5 D6 D7 D8 D9 D10 D1 1 D12 CP3SP33 www.ti.com SNOSCW5 –MAY 2013

24.6.3 Audio ControlData

The audiointerfaceprovidestheoptiontofilla 16-bitslotwithup tothreedatabitsifonly13,14,or 15 PCM databitsaretransmitted.These additionalbitsarecalledaudiocontroldataand areappended tothe PCM datastream.The AAI can be configuredtoappend either1,2,or 3 audiocontrolbitstothePCM datastream.The number ofaudiodatabitstobe used isspecifiedby the2-bitAudio ControlOn (ACO) field.IftheACO fieldisnotequalto0,thespecifiednumber ofbitsaretakenfromtheAudioControlData field(ACD) and appended tothedatastreamduringeverytransmitoperation.The ADC0 bitisthefirstbit added to the transmitdata stream afterthe lastPCM data bit.Typically,thesebitsare used forgain control,ifthisfeatureissupportedby theexternalPCM codec.Figure24-8shows a 16-bitslotcomprising a 13-bitPCM dataword plusthreeaudiocontrolbits. Figure24-8.Audio SlotwithAudio ControlData

24.6.4 IOM-2 Mode

The AAI can operatein a specialIOM-2 compatiblemode to allowto connect to an externalISDN controllerdevice.InthisIOM-2 mode, theAAI can onlyoperateas a slave,i.e.,thebitclockand frame sync signalisprovidedby theISDN controller.The AAI onlysupportstheB1 and B2 dataoftheIOM-2 channel0,butignorestheothertwo IOM-2 channels.The AAI handlestheB1 and B2 dataas one 16-bit dataword. The IOM-2 interfacehas thefollowingproperties:

• Bitclockof1536 kHz (outputfromtheISDN controller)
• Frame repetitionrateof8 ksps(outputfromtheISDN controller)
• Double-speedbitclock(onedatabitistwo bitclockswide)
• B1 and B2 datause 8-bitlogPCM format
• Long framesyncpulse Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 233 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

A[7:0] Address D[7:0] Data XCSn Chip Select XOE Output Enable STD/SRD DS162 SFS C IOM-2 Channel 0 IOM-2 Frame (125 µs) IOM-2 Channel 1 IOM-2 Channel 2 C M IC2 IC1 C M B2 B1 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure24-9.IOM-2 Frame Structure Figure24-10shows theconnectionsbetween an ISDN controllerand a CP3SP33 usinga standardIOM-2 interfacefortheB1/B2 datacommunicationand theexternalbus interface(IOExpansion)forcontrolling theISDN controller. Figure24-10.CP3SP33/ISDN ControllerConnections To connectthe AAI to an ISDN controllerthroughan IOM-2 compatibleinterface,the AAI needs to be configuredinthisway:

• The AAI must be inIOM-2 Mode (AGCR.IOM2 = 1).
• The AAI operatesinsynchronousmode (AGCR.ASS = 0).
• The AAI operatesas a slave,thereforethebitclockand frame sync sourceselectionmust be setto external(ACGR.IEFS = 1,ACGR.IEBC = 1).
• The framesynclengthmust be settolongframesync(ACGR.FSS = 1).
• The dataword lengthmust be setto16-bit(AGCR.DWL = 1).
• The AAI must be settonormalmode (AGCR.SCS[1:0]= 0).

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24.6.5 Loopback Mode

Inloopbackmode, theSTD and SRD pinsare internallyconnectedtogether,so datashiftedoutthrough theATSR registerwillbe shiftedintotheARSR register.Thismode may be used fordevelopment,butit alsoallowstestingthetransmitand receivepathwithoutexternalcircuitry,forexample duringBuilt-In-Self- Test(BIST).

24.6.6 FreezeMode

When theFreezemode isentered,theaudiointerfaceexhibitsthefollowingbehavior:

• The receiveFIFO orreceiveDMA registersarenotupdatedwithnew data.
• The receivestatusbits(RXO, RXE, RXF, and RXAF) arenotchanged,even thoughthereceiveFIFO orreceiveDMA registersareread
• The transmitshiftregister(ATSR) isnot updated withnew data from the transmitFIFO or transmit DMA registers.
• The transmitstatusbits(TXU, TXF, TXE, and TXAE) arenotchanged,even thoughthetransmitFIFO ortransmitDMA registersarewritten.

24.7 Audio InterfaceRegisters

Table24-1.Audio InterfaceRegisters NAME ADDRESS DESCRIPTION ARFR FF 5000h AudioReceiveFIFO Register ARDR0 FF 5004h AudioReceiveDMA Register0 ARDR1 FF 5008h AudioReceiveDMA Register1 ARDR2 FF 500Ch AudioReceiveDMA Register2 ARDR3 FF 5010h AudioReceiveDMA Register3 ATFR FF 5014h AudioTransmitFIFO Register ATDR0 FF 5018h AudioTransmitDMA Register0 ATDR1 FF 501Ch AudioTransmitDMA Register1 ATDR2 FF 5020h AudioTransmitDMA Register2 ATDR3 FF 5024h AudioTransmitDMA Register3 AGCR FF 5028h AudioGlobalConfigurationRegister AISCR FF 502Ch AudioInterruptStatusand ControlRegister ARSCR FF 5030h AudioReceiveStatusand ControlRegister ATSCR FF 5034h AudioTransmitStatusand ControlRegister ACCR FF 5038h AudioClockControlRegister ADMACR FF 503Ch AudioDMA ControlRegister

24.7.1 Audio Receive FIFO Register(ARFR)

The Audio Receive FIFO registershows the receiveFIFO locationcurrentlyaddressedby the Receive FIFO Read Pointer(RRP). The receiveFIFO receives8-bitor 16-bitdata from the Audio Receive Shift Register(ARSR),when theARSR isfull. In8-bitmode, onlythelowerbyteoftheARFR isused,and theupperbytecontainsundefineddata.In16- bitmode, a 16-bitword iscopiedfrom ARSR intothereceiveFIFO. The APB bus masterhas read-only access to the receiveFIFO, representedby the ARFR register.Afterreset,the receiveFIFO (ARFR) containsundefineddata. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 235 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 15 8M M 7 0 ARFH ARFL ARFL The AudioReceiveFIFO Low Byteshows thelowerbyteofthereceiveFIFO locationcurrently addressedby theReceiveFIFO Read Pointer(RRP). ARFH The AudioReceiveFIFO HighByteshows theupperbyteofthereceiveFIFO location currentlyaddressedby theReceiveFIFO Read Pointer(RRP).In8-bitmode, ARFH contains undefineddata.

24.7.2 Audio Receive DMA Registern (ARDRn)

The ARDRn registercontainsthedatareceivedwithinslotn,assignedforDMA support.In8-bitmode, onlythelower8-bitportionoftheARDRn registerisused,and theupperbytecontainsundefineddata.In 16-bitmode, a 16-bitword istransferredfrom theAudio ReceiveShiftRegister(ARSR) intotheARDRn register.The APB bus master,typicallya DMA controller,has read-onlyaccess to the receiveDMA registers.Afterreset,theseregistersareclear. 15 8M M 7 0 ARDH ARDL ARDL The AudioReceiveDMA Low Bytefieldreceivesthelowerbyteoftheaudiodatacopiedfrom theARSR. ARDH In16-bitmode, theAudioReceiveDMA HighBytefieldreceivestheupperbyteoftheaudio dataword copiedfromARSR. In8-bitmode, theARDH registerholdsundefineddata.

24.7.3 Audio TransmitFIFO Register(ATFR)

The ATFR registershows the transmitFIFO locationcurrentlyaddressed by the TransmitFIFO Write Pointer(TWP). The Audio TransmitShiftRegister(ATSR) receives8-bitor 16-bitdatafrom thetransmit FIFO,when theATSR isempty.In8-bitmode, onlythelower8-bitportionoftheATSR isused,and the upper byteisignored(nottransferredintothe ATSR). In 16-bitmode, a 16-bitword iscopiedfrom the transmitFIFO intothe ATSR. The APB bus master has write-onlyaccess to the transmitFIFO, representedby theATFR register.Afterreset,thetransmitFIFO (ATFR) containsundefineddata. 15 8M M 7 0 ATFH ATFL ATFL The AudioTransmitLow BytefieldrepresentsthelowerbyteofthetransmitFIFO location currentlyaddressedby theTransmitFIFO WritePointer(TWP). ATFH In16-bitmode, theAudioTransmitFIFO HighBytefieldrepresentstheupperbyteofthe transmitFIFO locationcurrentlyaddressedby theTransmitFIFO WritePointer(TWP).In8-bit mode, theATFH fieldisnotused.

24.7.4 Audio TransmitDMA Registern (ATDRn)

The ATDRn registercontainsthe data to be transmittedin slotn, assignedforDMA support.In 8-bit mode, onlythe lower8-bitportionof the ATDRn registerisused, and the upper byte isignored(not transferredintotheATSR). In16-bitmode, thewhole 16-bitword istransferredintotheATSR. The APB bus master,typicallya DMA controller,has write-onlyaccess tothetransmitDMA registers.Afterreset, theseregistersareclear. 15 8M M 7 0 ATDH ATDL

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www.ti.com SNOSCW5 –MAY 2013 ATDL The AudioTransmitDMA Low Bytefieldholdsthelowerbyteoftheaudiodata. ATDH In16-bitmode, theAudioTransmitDMA HighBytefieldholdstheupperbyteoftheaudio dataword.In8-bitmode, theATDH fieldisignored.

24.7.5 Audio GlobalConfigurationRegister(AGCR)

The AGCR registercontrolsthe basicoperationof the interface.The APB bus master has read/write accesstotheAGCR register.Afterreset,thisregisterisclear. 7 6 5 4 3 2 1 0 IEBC FSS IEFS SCS LPB DWL ASS 15 14 13 12 11 10 9 8 CLKEN AAIEN IOM2 IFS FSL CTF CRF ASS The Asynchronous/SynchronousMode Selectbitcontrolswhethertheaudiointerfaceoperates inAsynchronousorinSynchronousmode. 0 – Synchronousmode. 1 – Asynchronousmode. DWL The Data Word Lengthbitcontrolswhetherthedataword has a lengthof8 or16 bits. 0 – 8-bitlength. 1 – 16-bitlength. LPB The Loop Back bitenablestheloopback mode. Inthismode, theSRD and STD pinsare internallyconnected.AfterresettheLPB bitisclear,so by defaulttheloopback mode is disabled. 0 – Loop back mode disabled. 1 – Loop back mode enabled. SCS The SlotCount Selectfieldspecifiesthenumber ofslotswithineach frame.Ifthenumber of slotsperframeisequalto1,theaudiointerfaceoperatesinnormalmode. Ifthenumber ofslots perframeisgreaterthan1,theinterfaceoperatesinnetworkmode. SCS NUMBER OF SLOTS PER MODE FRAME 0 1 Normal mode 1 2 Networkmode 10 3 Networkmode 11 4 Networkmode IEFS The Internal/ExternalFrame Sync bitcontrols,whethertheframesyncsignalforthereceiver and transmitteraregeneratedinternallyorprovidedfroman externalsource. 0 – Internalframesynchronizationsignal. 1 – Externalframesynchronizationsignal. FSS The Frame Sync Selectbitcontrolswhethertheinterface(receiverand transmitter)uses longor shortframesynchronizationsignals. 0 – Short(bitlength)framesynchronizationsignal. 1 – Long (wordlength)framesynchronizationsignal. IEBC The Internal/ExternalBitClockbitcontrolswhetherthebitclocksforreceiverand transmitterare generatedinternallyorprovidedfroman externalsource. 0 – Internalbitclock. 1 – Externalbitclock. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 237 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com CRF The ClearReceiveFIFO bitisused toclearthereceiveFIFO.When thisbitiswrittenwitha 1, allpointersofthereceiveFIFO aresettotheirresetstate.Afterupdatingthepointers,theCRF bitwillautomaticallybe clearedagain. 0 – Writing0 has no effect. 1 – Writing1 clearsthereceiveFIFO. CTF The ClearTransmitFIFO bitisused toclearthetransmitFIFO.When thisbitiswrittenwitha 1, allpointersofthetransmitFIFO aresettotheirresetstate.Afterupdatingthepointers,theCTF bitwillautomaticallybe clearedagain. 0 – Writing0 has no effect. 1 – Writing1 clearsthetransmitFIFO. FSL The Frame Sync Lengthfieldspecifiesthelengthoftheframesynchronizationsignal,when a longframesyncsignal(FSS = 1)and a 16-bitdataword length (DWL = 1)areused.Ifan 8-bitdataword lengthisused,longframesyncsarealways6 bit clocksinlength. FSL FRAME SYNC LENGTH 00 13 bitclocks 01 14 bitclocks 10 15 bitclocks 11 16 bitclocks IFS The InvertedFrame Sync bitcontrolsthepolarityoftheframesyncsignal. 0 – Active-highframesyncsignal. 1 – Active-lowframesyncsignal. IOME The IOM-2 Mode bitselectsthenormalPCM interfacemode ora specialIOM-2 mode used to connecttoexternalISDN controllerdevices.The AAI can onlyoperateas a slaveintheIOM-2 mode, i.e.thebitclockand framesyncsignalsareprovidedby theISDN controller.IftheIOM2 bitisclear,theAAI operatesinthenormalPCM interfacemode used toconnecttoexternal PCM codecsand otherPCM audiodevices. 0 – IOM-2 mode disabled. 1 – IOM-2 mode enabled. AAIEN The AAI EnablebitcontrolswhethertheAdvanced AudioInterfaceisenabled.When theAAI is disabled,allAAI registersremainaccessible. 0 – AAI module disabled. 1 – AAI module enabled. CLKEN The ClockEnablebitcontrolswhethertheAdvanced AudioInterfaceclockisenabled.The CLKEN bitmust be settoallowaccesstoany AAI register.Itmust alsobe setbeforeany other bitoftheAGCR can be set.The CLKEN bitisclearafterreset. 0 – AAI module clockdisabled. 1 – AAI module clockenabled.

24.7.6 Audio InterruptStatusand ControlRegister(AISCR)

The AISCR registerisused tospecifythesourceand theconditions,when theaudiointerfaceinterruptis assertedto the InterruptControlUnit.Italso holds the interruptpending bitsand the corresponding interruptclearbitsforeach audiointerfaceinterruptsource.The APB bus masterhas read/writeaccessto theAISCR register.Afterreset,thisregisterisclear. 7 6 5 4 3 2 1 0 TXEIP TXIP RXEIP RXIP TXEIE TXIE RXEIE RXIE 15 12 11 10 9 8 Reserved TXEIC TXIC RXEIC RXIC

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www.ti.com SNOSCW5 –MAY 2013 RXIC The ReceiveInterruptEnablebitcontrolswhetherreceiveinterruptsaregenerated.Ifthe RXIE bitisclear,no receiveinterruptwillbe generated. 0 – Receiveinterruptdisabled. 1 – Receiveinterruptenabled. RXEIE The ReceiveErrorInterruptEnablebitcontrolswhetherreceiveerrorinterruptsaregenerated. Settingthisbitenablesa receiveerrorinterrupt,when theReceiveBufferOverrun(RXOR) bit isset.IftheRXEIE bitisclear,no receiveerrorinterruptwillbe generated. 0 – Receiveerrorinterruptdisabled. 1 – Receiveerrorinterruptenabled. TXIE The TransmitInterruptEnablebitcontrolswhethertransmitinterruptsaregenerated.Setting thisbitenablesa transmitinterrupt,when theTransmitBufferAlmostEmpty (TXAE) bitisset. IftheTXIE bitisclear,no interruptwillbe generated. 0 – Transmitinterruptdisabled. 1 – Transmitinterruptenabled. TXEIE The TransmitErrorInterruptEnablebitcontrolswhethertransmiterrorinterruptsare generated.Settingthisbitto1 enablesa transmiterrorinterrupt,when theTransmitBuffer Underrun(TXUR) bitisset.IftheTXEIE bitisclear,no transmiterrorinterruptwillbe generated. 0 – Transmiterrorinterruptdisabled. 1 – Transmiterrorinterruptenabled. RSIP The ReceiveInterruptPendingbitindicatesthata receiveinterruptiscurrentlypending.The RXIP bitisclearedby writinga 1 totheRXIC bit.The RXIP bitprovidesread-onlyaccess. 0 – No receiveinterruptpending. 1 – Receiveinterruptpending. RXEIP The ReceiveErrorInterruptPendingbitindicatesthata receiveerrorinterruptiscurrently pending.The RXEIP bitisclearedby writinga 1 totheRXEIC bit.The RXEIP bitprovides read-onlyaccess. 0 – No receiveerrorinterruptpending. 1 – Receiveerrorinterruptpending. TXIP The TransmitInterruptPendingbitindicatesthata transmitinterruptiscurrentlypending.The TXIP bitisclearedby writinga 1 totheTXIC bit.The TXIP bitprovidesread-onlyaccess. – No transmitinterruptpending. 1 – Transmitinterruptpending. TXEIP TransmitErrorInterruptPending.Thisbitindicatesthata transmiterrorinterruptiscurrently pending.The TXEIP bitisclearedby softwareby writinga 1 totheTXEIC bit.The TXEIP bit providesread-onlyaccess. 0 – No transmiterrorinterruptpending. 1 – Transmiterrorinterruptpending. RXIC The ReceiveInterruptClearbitisused tocleartheRXIP bit. 0 – Writinga 0 totheRXIC bitisignored. 1 – Writinga 1 clearstheRXIP bit. RXEIC The ReceiveErrorInterruptClearbitisused tocleartheRXEIP bit. 0 – Writinga 0 totheRXEIC bitisignored. 1 – Writinga 1 clearstheRXEIP bit. TXIC The TransmitInterruptClearbitisused tocleartheTXIP bit. 0 – Writinga 0 totheTXIC bitisignored. 1 – Writinga 1 clearstheTXIP bit. TXEIC The TransmitErrorInterruptClearbitisused tocleartheTXEIP bit. 0 – Writinga 0 totheTXEIC bitisignored. 1 – Writinga 1 clearstheTXEIP bit. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 239 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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24.7.7 Audio Receive Statusand ControlRegister(ARSCR)

The ARSCR registerisused to controlthe operationof the receiverpath of the audiointerface.Italso holdsbitswhichreportthecurrentstatusofthereceiveFIFO.The APB bus masterhas read/writeaccess to the ARSCR register.At reset,thisregisterisclearedto 0000h, but afterenablingthe AAI clockit becomes 0004h. 15 12 11 8 7 4 3 2 1 0 RXFWL RXDSA RXSA RXO RXE RXF RXAF RXAF The ReceiveBufferAlmostFullbitissetwhen thenumber ofdatabytes/wordsinthereceive bufferisequaltothespecifiedwarninglimit. 0 – ReceiveFIFO belowwarninglimit. 1 – ReceiveFIFO isalmostfull. RXF The ReceiveBufferFullbitissetwhen thereceivebufferisfull.The RXF bitissetwhen the RWP isequaltotheRRP and thelastaccesswas a writetotheFIFO. 0 – ReceiveFIFO isnotfull. 1 – ReceiveFIFO full. RXE The ReceiveBufferEmpty bitissetwhen theRRP isequaltotheRWP and thelastaccessto theFIFO was a readoperation(readfromARDR). 0 – ReceiveFIFO isnotempty. 1 – ReceiveFIFO isempty. RXO The ReceiveOverflowbitindicatesthata receiveshiftregisterhas overrun.Thisoccurs,when a completeddataword has been shiftedintoARSR, whilethereceiveFIFO was alreadyfull (theRXF bitwas set).Inthiscase,thenew datainARSR willnotbe copiedintotheFIFO and theRWP willnotbe incremented.Also,no receiveinterruptand DMA requestwillgenerated. 0 – No overflowhas occurred. 1 – Overflowhas occurred. RXSA The ReceiveSlotAssignmentfieldspecifieswhichslotsarerecognizedby thereceiverofthe audiointerface.Multipleslotsmay be enabled.Iftheframeconsistsoflessthan4 slots,the RXSA bitsforunused slotsareignored.Forexample,ifa frameonlyconsistsof2 slots,RXSA bits2 and 3 areignored.The followingtableshows theslotassignmentscheme. RXSA BIT SLOTS ENABLED RXSA0 0 RXSA1 1 RXSA2 2 RXSA3 3 AfterresettheRXSA fieldisclear,so softwaremust loadthecorrectslotassignment. RXDSA The ReceiveDMA SlotAssignmentfieldspecifieswhichslots(audiochannels)aresupported by DMA. IftheRXDSA bitissetforan assignedslot(RXSAn = 1),thedatareceivedwithinthis slotwillnotbe transferredintothereceiveFIFO,butwillinsteadbe writtenintothe correspondingReceiveDMA dataregister(ARDRn). IftheARDRn registerisfulland theRMA bitisset,a DMA requestisasserted.IftheRXSA bitfora slotisclear,theRXDSA bitis ignored.The followingtableshows theDMA slotassignmentscheme. RXDSA3 must be 0. RXDSA BIT SLOTS ENABLED FOR DMA RXDSA0 0 RXDSA1 1 RXDSA2 2

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www.ti.com SNOSCW5 –MAY 2013 RXFWL The ReceiveFIFO WarningLevelfieldspecifieswhen a receiveinterruptisasserted.A receive interruptisasserted,when thenumber ofbytes/wordsinthereceiveFIFO isgreaterthanthe warninglevelvalue.An RXFWL valueof0 means thata receiveinterruptisassertedifone or more bytes/wordsareintheRX FIFO.Afterreset,theRXFWL bitisclear.

24.7.8 Audio TransmitStatusand ControlRegister(ATSCR)

The ATSCR registercontrolsthebasicoperationoftheinterface.Italsoholdsbitswhichreportthecurrent statusoftheaudiocommunication.The APB bus masterhas read/writeaccesstotheATSCR register.At reset,thisregisterisloadedwithF000h,butafterenablingtheAAI clockitbecomes F003h. 15 12 11 8 7 4 3 2 1 0 TXFWL TXDSA TXSA TXU TXF TXF TXAF TXAE The TransmitFIFO AlmostEmpty bitissetwhen thenumber ofdatabytes/wordsintransmit bufferisequaltothespecifiedwarninglimit. 0 – TransmitFIFO above warninglimit. 1 – TransmitFIFO atorbelowwarninglimit. TXE The TransmitFIFO Empty bitissetwhen thetransmitbufferisempty.The TXE bitissetto one everytimetheTRP isequaltotheTWP and thelastaccesstotheFIFO was read operation(intoATSR). 0 – TransmitFIFO notempty. 1 – TransmitFIFO empty. TXF The TransmitFIFO Fullbitissetwhen theTWP isequaltotheTRP and thelastaccesstothe FIFO was writeoperation. 0 – TransmitFIFO notfull. 1 – TransmitFIFO full. TXU The TransmitUnderflowbitindicatesthatthetransmitshiftregister(ATSR) has underrun.This occurswhen thetransmitFIFO was alreadyempty and a completedataword has been transferred.Inthiscase,theTRP willbe decrementedby 1 and thepreviousdatawillbe retransmitted.No transmitinterruptand no DMA requestwillbe generated. 0 – Transmitunderrunoccurred. 1 – Transmitunderrundidnotoccur. TXSA The TransmitSlotAssignmentfieldspecifiesduringwhichslotsthetransmitterisactiveand drivesdatathroughtheSTD pin.The STD pinisinhighimpedance stateduringallotherslots. Iftheframeconsistsoflessthan4 slots,theTXSA bitsforunused slotsareignored.For example,ifa frameonlyconsistsof2 slots,TXSA bits2 and 3 areignored.The followingtable shows theslotassignmentscheme. TXSA BIT SLOTS ENABLED TXSA0 0 TXSA1 1 TXSA2 2 TXSA3 3 AfterresettheTXSA fieldisclear,so softwaremust loadthecorrectslotassignment. TXDSA The TransmitDMA SlotAssignmentfieldspecifieswhichslots(audiochannels)aresupported by DMA. IftheTXDSA bitissetforan assignedslot(TXSAn = 1),thedatatobe transmitted withinthisslotwillnotbe readfromthetransmitFIFO,butwillinsteadbe readfromthe correspondingTransmitDMA dataregister(ATDRn).A DMA requestisassertedwhen the ATDRn registerisempty.IftheTXSA bitfora slotisclear,theTXDSA bitisignored.The followingtableshows theDMA slotassignmentscheme. TXDSA3 must be 0. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 241 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com TXDSA BIT SLOTS ENABLED FOR DMA TXDSA0 0 TXDSA1 1 TXDSA2 2 TXFWL The TransmitFIFO WarningLevelfieldspecifieswhen a transmitinterruptisasserted.A transmitinterruptisassertedwhen thenumber ofbytesorwords inthetransmitFIFO isequal orlessthanthewarninglevelvalue.A TXFWL valueofFh means thata transmitinterruptis assertedifone ormore bytesorwords areavailableinthetransmitFIFO.Atreset,theTXFWL fieldisloadedwithFh.

24.7.9 Audio Clock ControlRegister(ACCR)

The ACCR registerisused tocontrolthebittimingoftheaudiointerface.Afterreset,thisregisterisclear. 15 8 7 1 0 BCPRS FCPRS CSS CSS The ClockSourceSelectbitselectsone outoftwo possibleclocksourcesfortheaudio interface. 0 – AuxiliaryClock1. 1 – AuxiliaryClock8. FCPRS The Frame ClockPrescalerisused todividethebitclocktogeneratetheframeclockforthe receiveand transmitoperations.The bitclockisdividedby (FCPRS + 1).Afterreset,the FCPRS fieldisclear.The maximum allowedbitclockratetoachievean 8 kHz frameclockis 1024 kHz.Thisvaluemust be setcorrectlyeven iftheframesyncisgeneratedexternally. BCPRS The BitClockPrescalerisused todividetheaudiointerfaceclock(selectedby theCSS bit)to generatethebitclockforthereceiveand transmitoperations.The audiointerfaceinputclockis dividedby (BCPRS + 1).Afterreset,theBCPRS7:0 bitsareclear.

24.7.10 Audio DMA ControlRegister(ADMACR)

The ADMACR registerisused tocontroltheDMA supportoftheaudiointerface.Inaddition,itisused to configuretheautomatictransmissionoftheaudiocontrolbits.Afterreset,thisregisterisclear. 15 13 12 11 10 8 7 4 3 0 Reserved ACO ACD TMD RMD RMD The ReceiveMasterDMA fieldspecifywhichslots(audiochannels)aresupportedby DMA, i.e., when a DMA requestisassertedtotheDMA controller.IftheRMDn bitissetforan assigned slot(RXDSAn = 1),a DMA requestisassertedwhen theARDRn registerisfull.IftheRXDSAn bitfora slotisclear,theRMDn bitisignored.The followingtableshows thereceiveDMA requestscheme. RMD DMA REQUEST CONDITION

0000 None

0001 ARDR0 full

0010 ARDR1 full

0011 ARDR0 fullorARDR1 full

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www.ti.com SNOSCW5 –MAY 2013 TMD The TransmitMasterDMA fieldspecifieswhichslots(audiochannels)aresupportedby DMA, i.e.,when a DMA requestisassertedtotheDMA controller.IftheTMD fieldissetforan assignedslot(TXDSAn = 1),a DMA requestisassertedwhen theATDRn registerisempty.If theTXDSA bitfora slotisclear,theTMD fieldisignored.The followingtableshows thetransmit DMA requestscheme. TMD FIELD DMA REQUEST CONDITION

0001 ATDR0 empty

0010 ATDR1 empty

0011 ATDR0 empty orATDR1 empty

ACD The AudioControlData fieldisused tofilltheremainingbitsofa 16-bitslotifonly13,14,or15 bitsofPCM audiodataaretransmitted. ACO The AudioControlOutputfieldcontrolsthenumber ofcontrolbitsappended tothePCM data word. 00 – No AudioControlbitsareappended. 01 – Append ACD0. 10 – Append ACD1:0. 11 – Append ACD2:0.

24.8 Usage Example

The followingexample shows theAAI beingused tointerfacetotwo single-channelcodecs.The interface has thefollowingcharacteristics:

• Synchronousmode
• 8-bitdataword
• Networkmode with4 slotsperframe
• Slot0 isassignedforAudiointerface-Codec 1 communication(receiveand transmit)
• Slot1 assignedforAudiointerface-Codec 2 communication(receiveand transmit)
• Slots2 and 3 unused
• Internallongframesynchpulse
• Internalshiftclock,adjustedtoachievea 64 kb/slogPCM audioquality
• Frame ratesetto8 kHz (seebelow)
• Bitclocksetto256 kHz (seebelow) ItisnotcurrentlypossiblefortheAAI toproducean exact8 kHz frame ratetogetherwithan exact256 kHz bitratefrom a 12-MHz clockinput.Ifthisisused ina system containinga component thatrequires dataata framerateofprecisely8 kHz (includingtheCVSD/PCM converter),thenan audioartifactmay be produced.Ifa PLL clockgeneratorisavailable,itcan be used toprovidean inputclockofthefrequency requiredtoprovidesuitablederivativefrequencies. Figure24-11 shows theconnectionsbetween theAAI and theexternalcodecs.Figure24-12 shows the timingoftheinterface. Copyright© 2013,Texas InstrumentsIncorporated Advanced AudioInterface 243 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

1/(8 kHz) = 125 us Frame Slot 0 SFS SRCLK (SFS1) STD/SRD Data from/to Codec 1 Data from/to Codec 2 Slot 2 Slot 3 DS372 High Impedance Frame Sync for Codec 2 Frame Sync for Codec 1 CP3SP33 MSM7717 SFS XSYNC SCK BCLK DS371 STD PCMIN SRCLK/SFS1 RSYNC SRD PCMOUT MSM7717 XSYNC BCLK PCMIN RSYNC PCMOUT CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure24-11.InterfacetoTwo ExternalCodecs Figure24-12.Codec Data on Two Slots

25 I2S Interface

The Inter-ICSound (I2S) bus isa popular3-wireserialbus forinterfacetoaudiochips,such as codecs. Thisisa simpledatainterface,withoutany form ofaddressor deviceselection.On an I2S bus,thereis onlyone bus masterand one transmitter,butthemasterisnotnecessarilya transmitterora receiver.The mastermay be a transmitter,a receiver,ora controllerfordatatransfersbetween otherdevicesactingas transmitterand receiver.In high-qualityaudioapplicationsinvolvinga codec,the codec istypicallythe masterso thatithas precisecontrolovertheI2S bus clock. The I2S bus carriestwo channels,leftand right,which are typicallyused to carrystereoaudio data streams.The dataalternatesbetween leftand rightchannels,as controlledby a word selectsignaldriven by thebus master.

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I2SSDI, I2SSDO N N Right Channel N-1 N-2 N-3 MSB MSB N-1 N-2 N-3 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Four 8-levelFIFOs are providedto bufferthe receiveand transmitdirectionsof the two channels. Programmable thresholdsare providedto triggerinterruptor DMA requestswhen the FIFOs require loadingorunloading. The I2S module providesa three-pinunidirectionalorfour-pinbidirectionalserialinterfaceconsistingof:

• SerialClock(I2SCLK)— bitclockforserialdatatransfer.The transmitterdrivesthedataon thefalling edge.The receiverlatchesthedataon therisingedge.The bus masterdrivesthissignal.
• Word Select(I2SSWS)— alternatelyselectsbetween leftand rightchannels,and definesthebeginning and end ofa word.The highand lowphases must be equallength.The bus masterdrivesthissignal.
• SerialData (I2SSDIand I2SSDO)— bitstreambetween thetransmitterand receiver.The MSB is alwayssentfirst.IntheCP3SP33 implementation,separatepinsareprovidedforserialdatainput (I2SSDI)and serialdataoutput(I2SSDO). The I2S module supportsthreecommon audiointerfaceformats:
• I2S Format— MSB transmittedone clockperiodafterI2SSWS toggles.I2SSWS islowfortheleft channeland highfortherightchannel.
• Left-JustifiedFormat— MSB transmittedfollowingtheclockedge when I2SSWS toggles.I2SSWS is highfortheleftchanneland lowfortherightchannel.
• Right-JustifiedFormat— LSB transmittedduringtheclockperiodbeforeI2SSWS toggles.I2SSWS is highfortheleftchanneland lowfortherightchannel. The number ofdatabitsisprogrammablefrom8 to24 bitsperword,and theword lengthisprogrammable from 8 to32 bits.The dataispositionedintheword accordingtotheformat.Intheleft-justifiedand I2S formats,thedatastartswiththeMSB inthefirstorsecond clockperiods,respectively.Iftheword lengthis lessthanthenumber ofdatabits,thetrailingLSBs aretruncated.Intheright-justifiedformat,thenumber ofdatabitsand theword lengthareused todeterminewhen tostartsendingorreceivingthedatabits,so itiscriticalto program thesevaluescorrectly.In thisformat,the word lengthmust be longerthan the number ofdatabits,otherwisethetransceiverwilldefaulttoleft-justifiedmode. Figure25-1shows thetimingofan I2S formatdatatransfer. Figure25-1.I2S Format Figure25-2shows thetimingofa left-justifieddatatransfer. Copyright© 2013,Texas InstrumentsIncorporated 245I2S Interface SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

I2SSDI, I2SSDO 5 3 4 2 1 0 5 Right Channel 4 3 2 0 1 LSB LSB I2SSCK Left Channel DS439 I2SSWS I2SSDI, I2SSDO N-1 N N-1N Right Channel N-2 N-3 N-4 MSB MSB N-2 N-3 N-4 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure25-2.Left-JustifiedFormat Figure25-3shows thetimingofa right-justifieddatatransfer. Figure25-3.Right-JustifiedFormat

25.1 Interruptsand DMA

Programmable thresholdsare providedforthe transmitand receiveFIFOs to assertinterruptor DMA requestswhen the transmitFIFO can accept new data or the receiveFIFO needs to be unloaded. Because the requestscan be handled by eitherthe CPU or DSP interruptand DMA controllers,the requestsare passed throughthe Audio Subsystem Controller(ASC). To use the interruptor DMA requests,theymust be enabledatthreelevels:

• I2S Module— the RXLI and RXRI bitsinthe I2SRXCTL registermust be setto enablethe receiver interruptrequestsfortheleftand rightchannels,respectively.The RXLD and RXRD bitsenablethe receiverDMA requests.The TXLI and TXRI bitsin the I2STXCTL registerenable the transmitter interruptrequests.The TXLD and TXRD bitsenablethetransmitterDMA requests.
• ASC Module— theI2S interruptisassignedtoASC interruptchannel.Bit6 intheASCINTSEL register must be cleartoselectCPU interruptcontrolleror settoselecttheDSP interruptcontroller.The I2S DMA requestsareassignedtoASC DMA channels14,15,16,and 17.For thereceiverDMA requests, ASCDMASEL0 registerbits14 and 15 forthe leftand rightchannels,respectively,must be clearto selectCPU DMA controllerorsettoselecttheDSP DMA controller.For thetransmitterDMA requests, ASCDMASEL1 registerbits0 and 1 fortheleftand rightchannels,respectively,must be cleartoselect CPU DMA controllerorsettoselecttheDSP DMA controller.
• Interruptor DMA Controller— therequestmust be enabledintheinterruptor DMA controller.For the CPU interruptcontroller,thisisinterruptrequestIRQ26.FortheCPU DMA controller,DMA requests14 and 15 areused by thereceiverleftand rightchannels,respectively,and DMA requests16 and 17 are used by thetransmitterleftand rightchannels.

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Mode Bits 31:24 Bits 23:16 Bits 15:8 Bits 7:0

00 Data

01 Data

10 Data

11 Data

www.ti.com SNOSCW5 –MAY 2013 Errorinterruptsmay be enabledforreceiveFIFO overrunand transmitFIFO underrun.A receiveFIFO overrunoccurson writingto a fullreceiveFIFO. A transmitFIFO underrunoccurson readingfrom an empty transmitFIFO. The RXER bitinthe I2SRXCTL registerenablesreceiveerrorinterrupts,and the TXER bitenablestransmiterrorinterrupts. To avoida transmitFIFO underrun,the TXFIFOENL and TXFIFOENR bitsallowenablingthe transmit FIFOs forloadingbeforeenablingthetransmitter.However,as soon as theI2SCLK and I2SSWS signals are active,therighttransmitFIFO isdrained.Inslavemode, thesesignalscan be disabledintheGPIO registersuntiltransmissionisrequired.Inmastermode, theMS bitcan be used tocontrolthesignals.

25.2 Data Alignment

Four alignmentmodes areavailableforthedataregisters,as shown inFigure25-4.The RXALIGN fieldin the I2SRXCTL registerspecifiesthe receivermode, and the TXALIGN fieldin the I2STXCTL register specifiesthetransmittermode. Ifthereceiverformathas more bitsthanthemode, theleastsignificantbits aretruncated.Ifthetransmitterformathas more bitsthanthemode, theleastsignificantbitsarepadded withthevalueintheLSBFILL bit. Figure25-4.Data RegisterAlignment Modes

25.3 I2S InterfaceRegisters

Table25-1liststheregistersintheI2S interface. Table25-1.I2S InterfaceRegisters NAME ADDRESS DESCRIPTION I2SCLK FF 4000h I2S ClockRegister I2SRXCTL FF 4004h I2S ReceiverControlRegister I2STXCTL FF 4008h I2S TransmitterControlRegister I2SSTAT FF 401Ch I2S StatusRegister I2SRXDATALEFT FF 4014h I2S ReceiverLeftChannelData Register I2SRXDATARIGHT FF 4018h I2SReceiverRightChannelData Register I2STXDATALEFT FF 400Ch I2S TransmitterLeftChannelData Register I2STXDATARIGHT FF 4010h I2S TransmitterRightChannelData Register

25.3.1 I2S Clock Register(I2SCLK)

The I2SCLK registerisa 32-bit,read/writeregisterthatcontrolsclockconfiguration,master/slaveselect, and word length.Before enabling master mode (MS bit= 1),the CLKSEL, CLKDIV, and WSRES fieldsmust be loaded.These fieldscan onlybe loadedinslavemode (MS bit= 0),so afterenabling mastermode, theinterfacemust be returnedtoslavemode tochange any oftheirvalues.At reset,this registerisinitializedto0007 0000h. Copyright© 2013,Texas InstrumentsIncorporated 247I2S Interface SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 31 24 23 21 20 16 15 8 7 4 3 2 1 0 Reserved Reserved WSRES CLKDIV Reserved MS CLKSEL CLKEN CLKEN The ClockEnablebitenablesclocktothemodule. 0 – Module disabled. 1 – Module enabled. CLKSEL The ClockSelectfieldselectstheclocksourceforthemodule. 00 – PCLK Clock. 01 – Auxiliaryclock5. 10 – Reserved. 11 – Reserved MS The MasterSelectbitselectswhethertheinterfaceisoperatinginmasterorslavemode. 0 – Slavemode. 1 – Mastermode. CLKDIV The ClockSelectfieldholdsthedivisor(expressedinhalf-periodsoftheclocksourceselected by CLKSEL) forgeneratingtheI2S bus clockoutputI2SCLK inmastermode. The fieldis biasedby 1,so theclocksourceisdividedby ((CLKDIV+ 1)÷ 2)toobtainI2SCLK.Zeroisa reservedvalueforthisfield. WSRES The Word SelectResolutionfieldspecifiesthelengthofone phase (one-halfperiod)ofthe word selectoutputI2SSWS inmastermode. The lengthisspecifiedintermsofI2S bus clock outputI2SCLK periods.The fieldisbiasedby 1,so thedefaultvalueof7 resultsina lengthof 8 clockperiods.Thisfieldisonlydefinedforvaluesfrom00111b to11111b.

25.3.2 I2S ReceiverControlRegister(I2SRXCTL)

The I2SRXCTL registerisa 32-bit,read/writeregisterthatcontrolstheI2S receiver.At reset,thisregister isinitializedto0000 001Ch. 13 12 11 10 9 8 7 6 2 1 0 Reserved RXLD RXRD RXLI RXRI RXER RXRES RXMOD 31 24 23 21 20 19 18 16 15 14 Reserved Reserved RXST Reserved RXFIFOTHRESH RXALIGN RXMOD The ReceiverMode fieldselectstheformatused by thereceiver. 00 – Receiverdisabled. 01 – I2S format. 10 – Left-justifiedformat. 11 – Right-justifiedformat. RXRES The ReceiverResolutionfieldspecifiesthenumber ofdatabitstoreceive.Inright-justified mode, thisfieldalsocontrolsdataalignment.ItisparticularlyimportanttosetRXRES correctlyinright-justifiedmode, otherwisetheMSB ofthereceivedserialdatawillnotbe aligned.ForI2S- and left-justifiedmodes, datawillalwaysbe correctlyaligned(MSB inthe correctposition),however ifRXRES specifiesfewerdatabitsthanareavailableon thebus, theLSBs willbe truncated.The fieldisbiasedby 1,so thedefaultvalueof7 resultsin8 bits.Thisfieldisonlydefinedforvaluesfrom00111b to10111b. RXER The ReceiveErrorbitenablestheerrorinterruptfromthereceiver.A receiveerroroccurs when thereceiverattemptstoloaddataintoa fullFIFO fortheleftorrightchannel.The statusoftheerrorconditionisindicatedby theRXERIRQ bitintheI2SSTAT register. 0 – Interruptdisabled. 1 – Interruptenabled.

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www.ti.com SNOSCW5 –MAY 2013 RXRI The RightChannelReceiveInterruptEnablebitenablesan interruptrequestwhen the number ofempty words intherightreceiveFIFO isequaltoorlessthanthereceiveFIFO thresholdspecifiedintheRXFIFOTHRES field.The statusoftheinterruptisindicatedby theRXRIRQ bitintheI2SSTAT register. 0 – Interruptdisabled. 1 – Interruptenabled. RXLI The LeftChannelReceiveInterruptEnablebitenablesan interruptrequestwhen the number ofempty words intheleftreceiveFIFO isequaltoorlessthanthereceiveFIFO thresholdspecifiedintheRXFIFOTHRES field.The statusoftheinterruptisindicatedby theRXLIRQ bitintheI2SSTAT register. 0 – Interruptdisabled. 1 – Interruptenabled. RXRD The RightChannelReceiveDMA Enablebitenablesa DMA requestwhen thenumber of empty words intherightreceiveFIFO isequaltoorlessthanthereceiveFIFO threshold specifiedintheRXFIFOTHRES field.Iftheinterruptand DMA requestsarebothenabled forthiscondition,onlytheDMA requestisasserted. 0 – DMA disabled. 1 – DMA enabled. RXLD The LeftChannelReceiveDMA Enablebitenablesa DMA requestwhen thenumber of empty words intheleftreceiveFIFO isequaltoorlessthanthereceiveFIFO threshold specifiedintheRXFIFOTHRES field.Iftheinterruptand DMA requestsarebothenabled forthiscondition,onlytheDMA requestisasserted. 0 – DMA disabled. 1 – DMA enabled. RXALIGN The ReceiverData Alignmentfieldcontrolsthepositionofthedataloadedintothe I2SRXDATALEFT and I2SRXDATARIGHT dataregisters,as describedinSection25.2. 00 – 24-bitdataloadedinupper3 bytes.Lowestbytecleared. 01 – 24-bitdataloadedinlower3 bytes. 10 – 16-bitdataloadedintolower2 bytes. 11 – 8-bitdataloadedintolowestbyte. RXFIFOTH The ReceiveFIFO Thresholdspecifiesthenumber ofempty words inthereceiveFIFOs RESH beforean interruptorDMA requestisasserted. RXST The ReceiverStatusbitcontrolswhethertheI2SSTAT.RXSTATUSR and I2SSTAT.RXSTATUSL fieldsindicatethenumber ofempty words inthereceiveFIFOs ratherthanthenumber offilledwords.Thisfielddoes notaffecttheinterpretationofthe RXFIFOTHRES fieldorthegenerationofinterruptand DMA requests. 0 – Statusfieldsindicatethenumber offilledwords intheFIFOs. 1 – Statusfieldsindicatethenumber ofempty words intheFIFOs.

25.3.3 I2S TransmitterControlRegister(I2STXCTL)

The I2STXCTL registeris a 32-bit,read/writeregisterthatcontrolsthe I2S transmitter.At reset,this registerisinitializedto0000 001Ch. 13 12 11 10 9 8 7 6 2 1 0 TXFIFOENL TXFIFOENR TXLD TXRD TXLI TXRI TXER TXRES TXMOD 31 24 23 22 21 20 19 18 16 15 14 Reserved Reserved LSBFILL FLUSH TXST Reserved TXFIFOTHRESH TXALIGN Copyright© 2013,Texas InstrumentsIncorporated 249I2S Interface SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com TXMOD The TransmitterMode fieldselectstheformatused by thetransmitter. 00 – Transmitterdisabled. 01 – I2S format. 10 – Left-justifiedformat. 11 – Right-justifiedformat. TXRES The TransmitterResolutionfieldspecifiesthenumber ofdatabitswhen theright-justified formatisused.Inright-justifiedmode, TXRES must specifyfewerbitsthantheword length, otherwisethetransceiverwilldefaulttoleft-justifiedmode. InI2S-and left-justifiedmodes, ifTXRES specifiesmore databitsthanavailableintheword,theLSBs aretruncated.The fieldisbiasedby 1,so thedefaultvalueof7 resultsin8 bits.Thisfieldisonlydefinedfor valuesfrom00111b to10111b.Thisfieldisnotdefinedforreading TXER The TransmitErrorbitenablestheerrorinterruptfromthetransmitter.A transmiterror occurswhen thetransmitterattemptstounloaddatafroman empty FIFO fortheleftor rightchannel.The statusoftheerrorconditionisindicatedby theTXERIRQ bitinthe I2SSTAT register. 0 – Interruptdisabled. 1 – Interruptenabled. TXRI The RightChannelTransmitInterruptEnablebitenablesan interruptrequestwhen the number offilledwords intherighttransmitFIFO isequaltoorlessthanthetransmitFIFO thresholdspecifiedintheTXFIFOTHRES field.The statusoftheinterruptisindicatedby theTXRIRQ bitintheI2SSTAT register. 0 – Interruptdisabled.1 – Interruptenabled. TXLI The LeftChannelTransmitInterruptEnablebitenablesan interruptrequestwhen the number offilledwords inthelefttransmitFIFO isequaltoorlessthanthetransmitFIFO thresholdspecifiedintheTXFIFOTHRES field.The statusoftheinterruptisindicatedby theTXLIRQ bitintheI2SSTAT register.0 – Interruptdisabled. 1 – Interruptenabled. TXRD The RightChannelTransmitDMA Enablebitenablesa DMA requestwhen thenumber of filledwords intherighttransmitFIFO isequaltoorlessthanthetransmitFIFO threshold specifiedintheTXFIFOTHRES field.Iftheinterruptand DMA requestsarebothenabled forthiscondition,onlytheDMA requestisasserted. 0 – DMA disabled. 1 – DMA enabled. TXLD The LeftChannelTransmitDMA Enablebitenablesa DMA requestwhen thenumber of filledwords inthelefttransmitFIFO isequaltoorlessthanthetransmitFIFO threshold specifiedintheTXFIFOTHRES field.Iftheinterruptand DMA requestsarebothenabled forthiscondition,onlytheDMA requestisasserted. 0 – DMA disabled. 1 – DMA enabled. TXFIFOEN The LeftChannelTransmitDMA Enablebitenablesa DMA requestwhen thenumber of R filledwords inthelefttransmitFIFO isequaltoorlessthanthetransmitFIFO threshold specifiedintheTXFIFOTHRES field.Iftheinterruptand DMA requestsarebothenabled forthiscondition,onlytheDMA requestisasserted. 0 – DMA disabled. 1 – DMA enabled. TXFIFOENL The TransmitFIFO EnableRightChannelbitenablestherightchanneltransmitFIFO.The FIFO must be enabledbeforethetransmitter,so itcan be filledinadvance oftransmission. 0 – FIFO disabled. 1 – FIFO enabled.

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www.ti.com SNOSCW5 –MAY 2013 TXALIGN The TransmitterData Alignmentfieldcontrolsthepositionofthedatareadfromthe I2STXDATALEFT and I2STXDATARIGHT dataregisters,as describedinSection25.2. 00 – 24-bitdatareadfromupper3 bytes. 01 – 24-bitdatareadfromlower3 bytes. 10 – 16-bitdatareadfromlower2 bytes. 11 – 8-bitdatareadfromlowestbyte. TXFIFOTH The TransmitFIFO Thresholdspecifiesthenumber offilledwords inthetransmitFIFOs RESH beforean interruptorDMA requestisasserted. TXST The TransmitterStatusbitcontrolswhethertheI2SSTAT.TXSTATUSR and I2SSTAT.TXSTATUSL fieldsindicatethenumber offilledwords inthetransmitFIFOs ratherthanthenumber ofempty words.Thisfielddoes notaffecttheinterpretationofthe TXFIFOTHRES fieldorthegenerationofinterruptand DMA requests. 0 – Statusfieldsindicatethenumber ofempty words intheFIFOs. 1 – Statusfieldsindicatethenumber offilledwords intheFIFOs. FLUSH The FlushbitclearsthetransmitFIFOs.Softwaremust clearthebitafterflushingthe FIFOs toenablenormaloperation. 0 – Normal operation. 1 – TransmitFIFOs arecleared. LSBFILL The LSB Fillbitspecifiesthevalueoftrailingbitswhen thenumber ofdatabitsislessthan thenumber ofbitsinthedataformat.

25.3.4 I2S StatusRegister(I2SSTAT)

The I2SSTAT registerisa 32-bit,read/writeregisterthatindicatesthe statusof I2S module and clears interruptrequests.The TXRIRQ, TXLIRQ, TXERIRQ, RXRIRQ, RXLIRQ, and RXERIRQ bitsare sticky bitsthatremainsetuntiltheconditionwhichsetsthebithas been removed and softwarehas clearedthe bit.The stateof a conditionisalways visibleinthe I2SSTAT register,but itwillnot assertan interrupt requestunlessitisenabled in the correspondingcontrolregister(eitherI2SRXCTL or I2STXCTL). At reset,thisregisterisinitializedto0000 0808h. 15 14 13 12 8 7 6 5 4 0 RXERIRQ RXLIRQ RXRIRQ TXSTATUSL TXERIRQ TXLIRQ TXRIRQ TXSTATUSR 31 30 29 28 24 23 21 20 16 Reserved WSSTATUS4:3 RXSTATUSL WSSTATUS2:0 RXSTATUSR TXSTATUSR The TransmitFIFO StatusRightChannelfieldindicatesthecurrentfillleveloftheright channeltransmitFIFO.Thisfieldisnotsticky,so an underrunconditionmay disappear beforesoftwarereadsthisfield.Use theTXERIRQ bittodeterminewhethera FIFO underrunhas occurred.The TXST bitintheI2STXCTL registercontrolsthe interpretationofthisfield. TXSTATUSR FIELD TXST BIT DESCRIPTION 1Fh X Overrunerror(writtenwhilefull) 1Eh X Underrunerror(readwhileempty) 00h to08h 0 0 to8 empty words 00h to08h 1 0 to8 filledwords TXRIRQ The TransmitRightChannelInterruptRequestPendingbitissetwhen the I2STXCTL.TXRI bitissetand therightchanneltransmitFIFO filllevelfallsbelowthe thresholdspecifiedintheI2STXCTL.TXFIFOTHRESH field.Once set,theTXRIRQ bit remainssetuntilclearedby writing1 tothebit. 0 – Interruptrequestdeasserted. 1 – Interruptrequestasserted. Copyright© 2013,Texas InstrumentsIncorporated 251I2S Interface SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com TXLIRQ The TransmitLeftChannelInterruptRequestPendingbitissetwhen the I2STXCTL.TXLIbitissetand theleftchanneltransmitFIFO filllevelfallsbelowthe thresholdspecifiedintheI2STXCTL.TXFIFOTHRESH field.Once set,theTXLIRQ bit remainssetuntilclearedby writing1 tothebit. 0 – Interruptrequestdeasserted. 1 – Interruptrequestasserted. TXERIRQ The TransmitErrorInterruptRequestPendingbitissetwhen theI2STXCTL.TXER bitis setand eithertransmitFIFO has been underrun.Once set,theTXERIRQ bitremains setuntilclearedby writing1 tothebit. 0 – Interruptrequestdeasserted. 1 – Interruptrequestasserted. TXSTATUSL The TransmitFIFO StatusLeftChannelfieldindicatesthecurrentfillleveloftheleft channeltransmitFIFO.Thisfieldisnotsticky,so an underrunconditionmay disappear beforesoftwarereadsthisfield.Use theTXERIRQ bittodeterminewhethera FIFO underrunhas occurred.The TXST bitintheI2STXCTL registercontrolsthe interpretationofthisfield. TXSTATUSL FIELD TXST BIT DESCRIPTION 1Fh X Overrunerror(writtenwhilefull) 1Eh X Underrunerror(readwhileempty) 00h to08h 0 0 to8 empty words 00h to08h 1 0 to8 filledwords RXRIRQ The ReceiveRightChannelInterruptRequestPendingbitissetwhen the I2SRXCTL.RXRI bitissetand therightchannelreceiveFIFO filllevelrisesabove the thresholdspecifiedintheI2SRXCTL.RXFIFOTHRESH field.Once set,theRXRIRQ bit remainssetuntilclearedby writing1 tothebit. 0 – Interruptrequestdeasserted. 1 – Interruptrequestasserted. RXLIRQ The ReceiveLeftChannelInterruptRequestPendingbitissetwhen theI2SRXCTL.RXLI bitissetand theleftchannelreceiveFIFO filllevelrisesabove thethresholdspecifiedin theI2SRXCTL.RXFIFOTHRESH field.Once set,theRXLIRQ bitremainssetuntil clearedby writing1 tothebit. 0 – Interruptrequestdeasserted. 1 – Interruptrequestasserted. RXERIRQ The ReceiveErrorInterruptRequestPendingbitissetwhen theI2SRXCTL.RXER bitis setand eitherreceiveFIFO has been overrun.Once set,theRXERIRQ bitremainsset untilclearedby writing1 tothebit. 0 – Interruptrequestdeasserted. 1 – Interruptrequestasserted. RXSTATUSR The ReceiveFIFO StatusRightChannelfieldindicatesthecurrentfillleveloftheright channelreceiveFIFO.Thisfieldisnotsticky,so an overrunconditionmay disappear beforesoftwarereadsthisfield.Use theRXERIRQ bittodeterminewhethera FIFO overrunhas occurred.The RXST bitintheI2SRXCTL registercontrolstheinterpretation ofthisfield. RXSTATUSR FIELD RXST BIT DESCRIPTION 1Fh X Overrunerror(writtenwhilefull) 1Eh X Underrunerror(readwhileempty) 00h to08h 0 0 to8 empty words 00h to08h 1 0 to8 filledwords

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www.ti.com SNOSCW5 –MAY 2013 RXSTATUSL The ReceiveFIFO StatusLeftChannelfieldindicatesthecurrentfillleveloftheleft channelreceiveFIFO.Thisfieldisnotsticky,so an overrunconditionmay disappear beforesoftwarereadsthisfield.Use theRXERIRQ bittodeterminewhethera FIFO overrunhas occurred.The RXST bitintheI2SRXCTL registercontrolstheinterpretation ofthisfield. RXSTATUSL FIELD RXST BIT DESCRIPTION 1Fh X Overrunerror(writtenwhilefull) 1Eh X Underrunerror(readwhileempty) 00h to08h 0 0 to8 empty words 00h to08h 1 0 to8 filledwords WSSTAT The Word SelectStatusfieldindicatesthelengthofone phase oftheword selectsignal US I2SSWS intermsofthenumber ofperiodsoftheI2S bus clockI2SCLK.Thisisusefulin slavemode, so thatsoftwarecan determinethenumber ofbitsbeingsentby themaster.

25.3.5 I2S ReceiverLeftChannel Data Register(I2SRXDATALEFT)

The I2SRXDATALEFT registerisa 32-bit,read-onlyregisterused tounloadtheleftchannelreceiveFIFO. Atreset,thisregisterisinitializedto0000 000h. 31 0 Reserved

25.3.6 I2S ReceiverRightChannel Data Register(I2SRXDATARIGHT)

The I2SRXDATARIGHT registerisa 32-bit,read-onlyregisterused to unloadthe rightchannelreceive FIFO.Atreset,thisregisterisinitializedto0000 000h. 31 0 Reserved

25.3.7 I2S TransmitterLeftChannel Data Register(I2STXDATALEFT)

The I2STXDATALEFT registerisa 32-bit,write-onlyregisterused toloadtheleftchanneltransmitFIFO. Atreset,thisregisterisinitializedto0000 000h. 31 0 Reserved

25.3.8 I2S TransmitterRightChannel Data Register(I2STXDATARIGHT)

The I2STXDATARIGHT registerisa 32-bit,write-onlyregisterused to load the rightchanneltransmit FIFO.Atreset,thisregisterisinitializedto0000 000h. 31 0 Reserved

26 Dual CVSD/PCM Conversion Modules

The CVSD/PCM modules performconversionbetween CVSD data and PCM data,inwhich the CVSD encodingisthatused inBluetoothcommunicationand the PCM encodingmay be 8-bitµ-Law,8-bitA- Law, or13-bitto16-bitlinear. A CVSD module can operateineitheroftwo modes: Copyright© 2013,Texas InstrumentsIncorporated DualCVSD/PCM ConversionModules 253 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

2 MHz

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• Fixed-ratemode — 125 µs (8kHz)perPCM sample,based on a 2 MHz module clockfrequency. Intendedforexchangingdatawithan externalcodec.
• Free-runningmode — runsatany module clockfrequencyup tothePCLK Clockfrequency.CVSD transcoderactivityisgovernedby DMA acknowledgmenton CVSDIN and CVSDOUT channels. IntendedforexchangingPCM dataovera Bluetoothchannel. On theCVSD side,readand writeFIFOs bufferup to8 words ofdata.On thePCM side,double-buffered registersare provided.The intendeduse istomove CVSD datawithan interrupthandler,and tomove PCM datawithDMA. Figure26-1isa blockdiagramofa CVSD/PCM convertermodule. Figure26-1.CVSD/PCM ConverterBlock Diagram

26.1 Operation

Infixed-ratemode, themodule convertsbetween PCM dataand CVSD dataata fixedPCM datarateof8 kHz.Due tocompression,thedatarateon theCVSD sideisonly4 kHz. IfPCM interruptsare enabled,every125 µs (8 kHz) an interruptwilloccurand theinterrupthandlercan operateon some or allof the fouraudio streams:CVSD in,CVSD out,PCM in,and PCM out. Alternatively,a DMA requestisissuedevery125 µs and the DMA controllerisused to move the PCM databetween theCVSD/PCM module and theaudiointerface. IfCVSD interruptsareenabled,an interruptisissuedwhen eitherone oftheCVSD FIFOs isalmostempty or almostfull.On thePCM datasidethereisdoublebuffering,and on theCVSD sidethereisan eight word (8-bit× 16-bit)FIFO forthereadand writepaths. Insidethemodule,a filterenginereceivesthe8-kHzstreamof16-bitsamplesand interpolatestogenerate a 64-kHz streamof16-bitsamples.Thisgoes intoa CVSD encoderwhichconvertsthedataintoa single- bitdeltastreamusingtheCVSD parametersas definedby theBluetoothspecification.There isa similar paththatreversesthisprocess,convertingtheCVSD 64-kHz bitstreamintoa 64-kHz 16-bitdatastream. The filterenginethendecimatesthisstreamintoan 8-kHz,16-bitdatastream.

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26.2 PCM Conversions

Duringconversionbetween CVSD and PCM, any PCM formatchanges aredone automaticallydepending on whetherthePCM dataisµ-Law,A-Law,orlinear.Inadditiontothis,a separatefunctioncan be used to convertbetween thevariousPCM formatsas required.Conversionisperformedby settingup thecontrol bitCVCTRLn.PCMCONV to definethe conversionand then writingto the LOGINn and LINEARINn registersand readingfrom the LOGOUTn and LINEAROUTn registers.There is no delay in the conversionoperation,and itdoes nothave tooperateata fixedrate.Itwillonlyconvertbetween µ-Law/A- Law and linear,not directlybetween µ-Law and A-Law. (Thiscouldeasilybe performedby converting between µ-Law and linearand between linearand A-Law.) Ifa conversionisperformedbetween linearand µ-Law logPCM data,thelinearPCM dataaretreatedin theleft-aligned14-bitlineardataformatwiththetwo LSBs unused.Ifa conversionisperformedbetween linearand A-Law log PCM data,the linearPCM data are treatedin the left-aligned13-bitlineardata formatwiththethreeLSBs unused. Ifthemodule isonlyused forPCM conversions,theCVSD clockcan be disabledby clearingtheCVSD ClockEnablebit(CLKEN) inthecontrolregister.

26.3 CVSD Conversion

The CVSD/PCM convertermodule transformseither8-bitlogarithmicor 13-bitto 16-bitlinearPCM samples at a fixedrateof 8 ksps.The CVSD to PCM conversionformatmust be specifiedby the CVSDCONV controlbitsintheCVSD Controlregister(CVCTRLn). The CVSD algorithmisdesignedfor2’s complement 16-bitdataand istunedforbestperformancewith typicalvoicedata.Milddistortionwilloccurforpeak signalsgreaterthan -6 dB. The BluetoothCVSD standardisdesignedforbestperformancewithtypicalvoicesignals:nominally–6 dB withoccasional peaks to 0 dB ratherthan full-scaleinputs.Distortionof signalsgreaterthan –6 dB isnot considered detrimentaltosubjectivequalitytestsforvoice-bandapplicationsand allowsforgreaterclarityforsignals below–6 dB.The gainoftheinputdeviceshouldbe tunedwiththisinmind. Ifrequired,theRESOLUTION fieldoftheCVCTRLn registercan be used tooptimizethelevelofthe16-bit linearinputdataby providingattenuations(right-shiftswithsignextension)of1,2,or3 bits. Log dataisalways8 bit,buttoperformtheCVSD conversion,thelogdataisfirstconvertedto16-bit2’s complement lineardata.A-lawand µ-lawconversioncan alsoslightlyaffecttheoptimum gainoftheinput data.The CVCTRL.RESOLUTION fieldcan be used toattenuatethedataifrequired. Iftheresolutionisnotsetproperly,theaudiosignalmay be clippedorattenuated.

26.4 Fixed-RatePCM-to-CVSD Conversion

The convertercorereadsthedouble-bufferedPCMIN registerevery125 µs and writesa new 16-bitCVSD datastreamintotheCVSD Out FIFO every250 µs.IfthePCMIN bufferhas notbeen updatedwitha new PCM sample between two readsfromtheCVSD core,theoldPCM dataisused againtomaintaina fixed conversionrate.Once a new 16-bitCVSD datastreamhas been calculated,itiscopiedintothe8 × 16-bit wideCVSD Out FIFO. Ifthereare onlythreeempty words (16-bit)leftin the FIFO, the nearlyfullbit(CVNF) isset,and, if enabled(CVSDINT = 1),an interruptrequestisasserted. Ifthe CVSD Out FIFO isfull,the fullbit(CVF) isset,and, ifenabled(CVSDERRINT = 1),an interrupt requestisasserted.Inthiscase,theCVSD Out FIFO remainsunchanged. Withintheinterrupthandler,theCPU can readoutthenew CVSD data.IftheCPU readsfroman already empty CVSD Out FIFO,a lockupoftheFIFO logicmay occurwhichpersistsuntilthenextreset.Software must check theCVOUTST fieldoftheCVSTAT registertoread thenumber ofvalidwords intheFIFO. Softwaremust notuse theCVNF bitas an indicationofthenumber ofvalidwords intheFIFO. Copyright© 2013,Texas InstrumentsIncorporated DualCVSD/PCM ConversionModules 255 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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26.5 Fixed-RateCVSD-to-PCM Conversion

The convertercorereadsfrom theCVSD InFIFO every250 µs and writesa new PCM sample intothe PCMOUT bufferevery 125 µs. Ifthe previousPCM data has not yet been transferredto the audio interface,itwillbe overwrittenwiththenew PCM sample. Ifthereare onlythreeunread words left,the CVSD In NearlyEmpty bit(CVNE) issetand, ifenabled (CVSDINT = 1),an interruptrequestisgenerated. IftheCVSD InFIFO isempty,theCVSD InEmpty bit(CVE) issetand,ifenabled(CVSDERRINT = 1),an interruptrequestisgenerated.Iftheconvertercorereadsfroman alreadyempty CVSD InFIFO,theFIFO automaticallyreturnsa checkerboardpatterntospecifya minimum levelofdistortionoftheaudiostream.

26.6 Free-RunningMode

The free-runningmode oftheCVSD/PCM converterisenabledby settingtheCVFR, DMACI, and DMACO bitsoftheCVSD ControlRegister(CVCTRL). Inthismode, theCVSD/ PCM converterisexpectedtobe servicedby DMA operationson both itsPCM and CVSD inputand outputchannels.In contrastto the fixed-rateoperatingmode, the clockfrequencyforfree-runningoperationisnot restrictedto 2 MHz. In free-runningmode, activitywithintheCVSD/PCM transcoderisgovernedby theacknowledgmentofDMA requestson theCVSDIN and CVSDOUT channels.Ifa DMA requeston eitherofthesechannelsgoes unacknowledged then the CVSD/PCM module willstallitsinternaloperationjustbeforethe startof the next transcodingcycle.When the outstandingDMA requestsare eventuallyacknowledged then the CVSD/PCM module willresume itsoperationina seamlessfashion.

26.7 InterruptGeneration

An interruptisassertedinany ofthefollowingcases:

• When a new PCM sample has been writtenintothePCMOUT registerand theCVCTRLn.PCMINT bit isset.
• When a new PCM sample has been read from thePCMIN registerand theCVCTRLn.PCMINT bitis set.
• When theCVSD InFIFO isnearlyempty (CVSTATn.CVNE = 1)and theCVCTRLn.CVSDINT bitisset.
• When theCVSD Out FIFO isnearlyfull(CVSTATn.CVNF = 1)and theCVCTRLn.CVSDINT bitisset.
• When theCVSD InFIFO isempty (CVSTATn.CVE = 1)and theCVCTRLn.CVSDERRINT bitisset.
• When theCVSD Out FIFO isfull(CVSTATn.CVF = 1)and theCVCTRLn.CVSDERRINT bitisset Both theCVSD Inand CVSD Out FIFOs have a sizeof8 bit× 16 bit(8words).The warninglimitsforthe two FIFOs aresetat5 words.(The CVSD InFIFO interruptwilloccurwhen thereare3 words leftinthe FIFO,and theCVSD Out FIFO interruptwilloccurwhen thereare3 orlessempty words leftintheFIFO.) The limitis set to 5 words because Bluetoothaudio data is transferredin packages of 10 bytes or multiplesof10 bytes. Because thePCM I/Ointerruptrequestscan be handledby eithertheCPU or DSP interruptcontrollers, theinterruptrequestsarepassed throughtheAudioSubsystem Controller(ASC),whichisprogrammed to routethem totheinterruptcontroller.To use thePCM I/Ointerrupts,theymust be enabledatthreelevels:
• CVSD/PCM module— theinterruptsmust be enabledusingthePCMINT bitsintheCVCTRLn registers.
• ASC module— thePCM I/Ointerruptsare assignedtoASC interruptchannels5 (CVSD/PCM module 0) and 4 (CVSD/PCM module 1),so bits5 and 4 intheASCINTSEL registermust be cleartoselect theCPU interruptcontrollerorsettoselecttheDSP interruptcontroller.
• Interruptcontroller— the interruptrequestsmust be enabledinthe interruptcontroller.For the CPU interruptcontroller,these are interruptrequests IRQ25 (CVSD/ PCM module 0) and IRQ24 (CVSD/PCM module 1).

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26.8 DMA Support

Each CVSD/PCM converterhas fourDMA channelsforprocessorindependentoperation.Both receive and transmitforCVSD dataand PCM datacan be enabledindividually.A CVSD/PCM module assertsa DMA requesttotheon-chipDMA controllerunderthefollowingconditions:

• The DMAPO bitissetand thePCMOUTn registerisfull,because ithas been updatedby theconverter core witha new PCM sample. (The DMA controllercan read out one PCM data word from the PCMOUTn register.)
• The DMAPI bitissetand thePCMINn registerisempty,because ithas been read by theconverter core.(TheDMA controllercan writeone new PCM dataword intothePCMINn register.)
• The DMACO bitissetand a new 16-bitCVSD datastreamhas been copiedintotheCVSD Out FIFO. (TheDMA controllercan readoutone 16-bitCVSD dataword fromtheCVSD Out FIFO.)
• The DMACI bitissetand a 16-bitCVSD datastreamhas been read from theCVSD InFIFO. (The DMA controllercan writeone new 16-bitCVSD dataword intotheCVSD InFIFO.) The DMA controlleronly supportsindirectDMA transfers.Therefore,transferringdata between a CVSD/PCM module and anotheron-chipmodule requirestwo bus cycles. The triggerforDMA may alsotriggeran interruptifthecorrespondingenablebitsintheCVCTRLn register is set.Therefore,care must be taken when settingthe desiredinterruptand DMA enable bits.The followingconditionsmust be avoided:
• SettingthePCMINT bitand eitheroftheDMAPO orDMAPI bits.
• SettingtheCVSDINT bitand eitheroftheDMACO orDMACI bits. Because thePCM I/ODMA requestscan be handledby eithertheCPU orDSP DMA controllers,theDMA requestsarepassed throughtheAudioSubsystem Controller(ASC),whichisprogrammed toroutethem totheDMA controller.To use thePCM I/ODMA requests,theymust be enabledatthreelevels:
• CVSD/PCM module— thePCM I/ODMA requestsmust be enabledusingtheDMAPI and DMAPO bits intheCVCTRLn registers.
• ASC module— the PCM I/O DMA requestsare assignedto ASC DMA channels3 (PCMIN0), 2 (PCMOUT0), 5 (PCMIN1),and 4 (PCMOUT1). These channelsare controlledby bits3,2,5,and 4, respectively,intheASCDMASEL0 register.The bitsmust be cleartoselecttheCPU DMA controlleror settoselecttheDSP DMA controller.IftheDSP DMA controllerisselected,theDSP DMA channel must be enabledintheASCDDMASELn registers.
• DMA controller— the DMA requestsmust be enabled in the DMA controller.For the CPU DMA controller,theseareDMA requests3 (PCMIN0),2 (PCMOUT0), 5 (PCMIN1),and 4 (PCMOUT1). The CVSD I/ODMA requestsareonlyprovidedtotheCPU DMA controller.

26.9 CVSD/PCM Audio Data Flow

CVSD and PCM data can be transferredto and from the CVSD/PCM modules usingDMA channels. Alternatively,CVSD data can be transferredto and from the CVSD/PCM modules by softwaredirectly accessingtheFIFOs,throughtheCVSDINn and CVSDOUTn registers. The CVSDOUT and CVSDIN DMA channelsarelinkedtotheoperationoftheCVSD/PCM module internal FIFOs. Each time the CVSDOUT FIFO reaches itsalmost fulllevelof 5 entries,a DMA requestis generated.Initiallywhen the CVSDIN FIFO contains3 or fewer entries,a singleDMA transferis requested.FurtherDMA requestsaregeneratedeach timetheCVSD InFIFO isreadby theCVSD/PCM converter. Three of the fourAAI channelsare supportedby independentDMA channelsforboth the receiveand transmitdatapaths.Figure26-2shows theflowofaudiodatawhen bothCVSD/PCM modules areused to supportdata exchange between the BluetoothLLC and two externalcodec channelsaccessed through theAAI. Copyright© 2013,Texas InstrumentsIncorporated DualCVSD/PCM ConversionModules 257 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Figure26-2.CVSD/PCM To/From AAI Data Flow The CVSD/PCM modules can operateintwo basicmodes: fixed-ratemode and free-runmode. In the fixed-ratemode, theclockfrequencysuppliedtoCVSD/PCM module 0 on AuxiliaryClock2 (orAuxiliary Clock3 forCVSD/PCM module 1)must be exactly2 MHz. Inthefixed-ratemode, theCVSD/PCM module willexpecttoreceive8000 PCM samples persecond on itsPCMIN input,and itwillproduce4000 words persecond on theCVSDOUT output.Each word holds16 bitsoftheCVSD-encoded bitstream.Itwillalso expecttoreceive16-bitCVSD-encoded datawords ata rateof4000 persecond on itsCVSDIN inputand willproducePCM samplesata rateof8000 persecond on itsPCMOUT output. In the free-runmode the AuxiliaryClockscan be setto any frequencyup to a maximum equalto the PCLK Clockfrequency.Inthismode, theCVSD/PCM module willrequesta new PCM sample every250 cyclesoftheAuxiliaryClock,and itwillproducea new CVSD dataword every500 cyclesoftheAuxiliary Clock. The followingexamplesillustratetheflowofCVSD dataintypicalapplications.

26.9.1 Dual CVSD Channels toAAI

Thismodel isillustratedinFigure26-3and has thefollowingcharacteristics.

• Two bidirectionalCVSD channelsthroughtheBluetoothLLC.
• PCM datareceivedby theAAI.
• CVSD/PCM conversiondone on-chip.
• PCM audiodataistransferredbetween theAAI and theCVSD/PCM module by means ofDMA.
• CVSD audiodataistransferredbetween theCVSD/PCM module and theBluetoothRAM by means of DMA.
• CVSD/PCM modules operateinfixed-ratemode usinga 2 MHz clocksuppliedon AuxiliaryClocks2 and 3.

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www.ti.com SNOSCW5 –MAY 2013 Figure26-3.Dual CVSD Channels toAAI 26.9.1.1PCM TransmitData Path The two AAI receiveregisters,ARDR0 and ARDR1, receivecodec datafortransmissionovera Bluetooth link.These registersareassignedtoseparateDMA channels.The DMA datatransfersfromtheAAI tothe CVSD/PCM modules use indirecttransfers,inwhich each transferconsistsof two adjacentbus cycles (read/write).The operationof the ARDR0 DMA channelisdescribedbelow.The ARDR1 DMA channel operatesina similarway. The AAI requestsa DMA transferwhen ARDR0 isfull.IfARDR0 isassignedtoDeviceA and theDIR bit intheDMA channelcontrolregisterisclear,theDMA controllerreadsdatafrom ARDR0 (deviceA) and writes the data into the PCMIN registerof CVSD0 (device B). Automatic address update (increment/decrement)must be disabled.Withan audiosample rateof8 ksps,ARDR0 willrequesta DMA transferevery125 ms (every1500 CPU clockcyclesata 12 MHz PCLK Clockrate). 26.9.1.2PCM Receive Data Path The two AAI transmitregisters,ATDR0 and ATDR1, are assignedtoseparateDMA channels.The DMA datatransfersfrom theCVSD/PCM modules totheaudiointerfaceuse indirecttransfers,inwhich each transferconsistsof two adjacentbus cycles(read/write).The operationof the ATDR0 DMA channelis describedbelow.The ARDR1 DMA channeloperatesina similarway. The AAI requestsa DMA transferwhen ATDR0 isempty.IfATDR0 isassignedtoDeviceA and theDIR bitinthe DMA channelcontrolregisterisset,then the DMA controllerreads data from the PCMOUT registerof CVSD0 (deviceB) and writesthe data intoATDR0 (deviceA).Automaticaddress update (increment/decrement)must be disabled. Withan audiosample rateof8 ksps,ATDR0 willrequesta DMA transferevery125 ms (every1500 CPU clockcyclesata 12 MHz PCLK Clockrate). 26.9.1.3CVSD Transmit/ReceivePaths The CVSD/PCM modules operateintheirfixed-ratemode withDMA channelsassignedtotheirCVSDINn and CVSDOUTn registers.The activationof these DMA channelsis linkedto the operationof the CVSDINn and CVSDOUTn FIFOs.The operationoftheCVSD/PCM module 0 DMA channelsisdescribed below.The CVSD/PCM module 1 DMA channelsoperateina similarway. Initiallywhen theCVSDIN0 FIFO contains3 orfewerentries,a singleDMA transferisrequested.Further DMA requestsare generatedeach time the CVSDIN0 FIFO isread by the CVSD/PCM converter.If CVSDIN0 isassignedtodeviceA and theDIR bitintheDMA channelcontrolregisterisset,theDMA controllerreadsdatafrom theBluetoothRAM (deviceB) and writesthe data intoCVSDIN0 (deviceA). The DMA channelmust be configuredso thatautomaticupdate of the deviceA (CVSDIN0) addressis disabled.The addressof deviceB (BluetoothRAM) must be configuredto automaticallyincrementor decrementby 2 aftereach DMA transfer. Copyright© 2013,Texas InstrumentsIncorporated DualCVSD/PCM ConversionModules 259 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com When theCVSDOUT0 contains5 entriesormore,a DMA transferisrequested.IfCVSDOUT0 isassigned todeviceA and theDIR bitintheDMA channelcontrolregisterisclear,theDMA controllerreadsdata fromtheCVSDOUT0 (deviceA) and writesthedataintotheBluetoothRAM (deviceB). The CVSD/PCM module introducesan effectivecompressionratioof2 to1,so an audiosample rateof8 ksps resultsinDMA transferson boththeCVSDIN and CVSDOUT DMA channelsata rateof4k transfers persecond.

26.9.2 Dual CVSD Channels toBluetoothHCI

Thisusage model isillustratedinFigure26-4and consistsofthefollowingoperations.

• Two bidirectionalCVSD channelsthroughtheBluetoothLLC.
• CVSD/PCM conversiondone on-chip.
• PCM audiodataistransferredbetween theCVSD/PCM modules and thesystemRAM by DMA.
• CVSD audiodataistransferredbetween theCVSD/PCM modules and theBluetoothRAM by DMA.
• CVSD/PCM modules operateinfree-runningmode, inwhich thesample throughputisdeterminedby thefrequencyofAuxiliaryClocks2 and 3. Figure26-4.Dual CVSD Channels toBluetoothHCI 26.9.2.1PCM TransmitData Path The CVSD/PCM modules have DMA channelsassignedto theirPCMINn registers.DMA data transfers from system RAM totheCVSD/PCM modules use indirecttransfers,inwhich each transferisperformed withtwo adjacentbus cycles(read/write).The operationof the PCMIN0 DMA channelof CVSD/PCM module 0 isdescribedbelow.The PCMIN1 DMA channeloperatesina similarway. The CVSD/PCM module requestsa DMA transfereach time a PCM sample has been processed.If PCMIN0 isassignedto deviceA and the DIR bitinthe DMA channelcontrolregisterisset,the DMA controllerreadsdatafrom system RAM (deviceB) and writesthedataintothePCMIN0 register(device A).The DMA controllermust be configuredso thatautomaticupdateofthedeviceA (PCMIN0) addressis disabled.The address of deviceB (system RAM) must be configuredto automaticallyincrementor decrementby 2 aftereach DMA transfer. CVSD/PCM module 0 requires250 clockcyclesof AuxiliaryClock 2 (AuxiliaryClock 3 forCVSD/PCM module 1)toencode a singlePCM sample.The effectivecompressionratioof2 to1 fromPCM toCVSD means thata new 16-bitCVSD-encoded data word isproduced every500 cycles.Every 250 cycles,a DMA operationisrequestedtotransfera PCM sample forthenextcycleoftheencoder.Similarly,every 500 cycles,a DMA operationisrequestedtotransfera CVSD dataword fromtheCVSD/PCM module to memory. The frequencyof the AuxiliaryClock determinesthe time intervalbetween successiveDMA requests. For example,iftheAuxiliaryClockis2 MHz, theCVSD/PCM module willrequesta DMA transferon the PCMINn channelata rateof8 ksps.IftheAuxiliaryClockis12 MHz, theDMA transferratewillbe 48 ksps.

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www.ti.com SNOSCW5 –MAY 2013 The operationof the CVSD/PCM module (i.e.,PCMINn to CVSDOUTn) is controlledby DMA request/acknowledgeactivityon the CVSDOUTn and CVSDINn DMA channels.The number of DMA transfersrequiredtofilltheCVSD bufferresidentinBluetoothRAM must be programmed intotheDMA controllersblocklengthregister.When the requirednumber of DMA transfershas been executed,the DMA controllerwillnot acknowledge furtherDMA requestson the CVSDOUTn channel.Similarly,the DMA requestson theCVSDINn channelareno longeracknowledgedwhen theterminalcountisreached on the CVSDINn DMA operation.Ifa DMA requeston eitherthe CVSDOUTn or CVSDINn channel remains unacknowledged,the CVSD/PCM module willsuspend operationjustbeforethe end of the currentCVSD encodingcycle.When new CVSD databecomes available,theoutstandingDMA requests willbe acknowledgedand theCVSD/PCM module willrestart. 26.9.2.2PCM Receive Path The CVSD/PCM modules have DMA channelsassignedto theirPCMOUTn registers.The DMA data transfersfrom the CVSD/PCM modules to system RAM use indirecttransfer,inwhich each transferis performedwithtwo adjacentbus cycles(read/write).The operationof the PCMOUT0 DMA channelof CVSD/PCM module 0 isdescribedbelow.The PCMOUT1 DMA channeloperatesina similarway. The CVSD/PCM module requestsa DMA transfereach time a new PCM sample is availablein PCMOUT0. IfPCMOUT0 isassignedtodeviceA and theDIR bitintheDMA channelcontrolregisteris clear,the DMA controllerreads data from the PCMOUT0 register(deviceA) and writesthe data into system RAM (deviceB).The DMA controllermust be configuredso thatautomaticupdateofthedeviceA (PCMOUT0) address is disabled.The address of device B (system RAM) must be configuredto automaticallyincrementordecrementby 2 aftereach DMA transfer. The operationof the CVSD/PCM module (i.e.CVSDINn to PCMOUTn) is controlledby DMA request/acknowledgeactivityon the CVSDINn and CVSDOUTn DMA channels.The number of DMA transfersrequiredtofillthePCM transmitbufferinsystemRAM must be specifiedintheDMA blocklength register.When therequirednumber ofDMA transfershave been performed,theDMA controllerwillnot acknowledgefurtherDMA requestson thePCMINn channel.Similarly,furtherrequestson theCVSDINn and CVSDOUTn channelswillnot be acknowledged when the terminalcountisreached on theirDMA transfers.The CVSD/PCM module willsuspend operationwhen DMA requestson the CVSDINn or CVDOUTn channelsareno longeracknowledgedby theDMA controller. The CVSD/PCM module requires250 clockcyclesoftheAuxiliaryClocktodecode a PCM sample.The frequencyoftheAuxiliaryClockdeterminestherateatwhichDMA requestsaremade on thePCMOUTn Channel. 26.9.2.3CVSD Transmit/ReceivePaths The CVSD/PCM modules operatein theirfree-runningmode with DMA channels assigned to their CVSDINn and CVSDOUTn registers.Activityon these DMA channelsislinkedto the CVSDINn and CVSDOUTn FIFOs. The operationof the CVSD/PCM module 0 channels is describedbelow. The CVSD/PCM module 1 channelsoperateina similarway. Initiallywhen theCVSD/PCM module 0 isenabledand a DMA requeston CVSDIN0 isasserted,a 16-bit CVSD-encoded dataword istransferredfrom memory totheCVSDIN0 FIFO. FurtherDMA requestsare assertedeach timetheCVSDIN0 FIFO isread by theCVSD/PCM converter.The CVSD/PCM converter requires250 clockcyclesoftheAuxiliaryClock2 (AuxiliaryClock3 forCVSD/PCM module 1)toproduce a singlePCM sample.The effectivecompressionratioof2:1resultsina 16-bitword ofCVSD dataevery 500 auxiliaryclockcycles.At thestartofeach decodingcycle(500auxiliaryclockcycles),a DMA request is made to transfera CVSD-encoded data word from BluetoothRAM to the CVSDIN0 FIFO. The frequencyoftheauxiliaryclockdeterminesthetimeintervalbetween successiveDMA requests. Copyright© 2013,Texas InstrumentsIncorporated DualCVSD/PCM ConversionModules 261 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com The number ofDMA transfersrequiredtoservicetheCVSD bufferinBluetoothRAM must be specifiedin theDMA blocklengthregister.When therequirednumber ofDMA transfershas been executed,theDMA controllerwillnotacknowledgefurtherDMA requestson theCVSDIN0 channel.The CVSD/PCM module willsuspend operationjustbeforetheend ofthecurrentCVSD decodingcycle.When a new CVSD buffer becomes available,thentheoutstandingDMA requestswillbe acknowledgedand theCVSD/PCM module willrestart. When the CVSDOUT0 FIFO contains5 entriesor more, a DMA transferisrequested.IfCVSDIN0 is assignedto deviceA and the DIR bitinthe DMA channelcontrolregisterisclear,the DMA controller readsdatafrom theCVSDOUT0 register(deviceA) and writesthedataintotheBluetoothRAM (device B).

26.10 Bus Bandwidth and Latency Considerations

The DMA controllerhas a burstbuffer,whichcan be enabledon a per-channelbasis.When thebufferis enabled,DMA operationsoccur as four-cyclebursttransfers.These bursttransfersoptimizebus bandwidth,because theyeliminateextracyclesused toarbitrateforcontrolofthebus (ascompared to foursingle-cycletransfers). However, burstmode is not recommended foraudio data because of itsimpact on latency.Three additionaldatawords willbe needed tofillthebuffer,so forexample atan 8 ksps rate,3 × 125 ms = 375 ms additionallatency. Latencymay alsobe impactedby competitionwiththeCPU and DSP foraccesstosharedresourcessuch as thesharedRAM and theexternalbus interface.However,thebandwidthrequiredeven forhigh-quality audiosignalsisquitelow compared tothebandwidthavailablefrom theon-chipbuses.For example,a DMA transferbetween two peripheralsfora 48 ksps audiochannelon an APB bus operatingathalfthe speed oftheCPU orDSP corebus wouldrequire6 × 48000 = 0.288M corebus cycles/second.Compared tothe96M corebus cycles/secondavailableon theCPU and DSP buses,thisisa verysmallnumber.It can become significant,however,ifthe core buses are operatedat low clockratesto reduce power consumption. When theCPU and DSP bothattempttoaccessthesame deviceatthesame time,theCPU has priority. Access to slow externaldevicesby the CPU or DSP willnot blockon-chipperipheral-to-peripheralor peripheral-to-memoryDMA transfers.because the EBIU has a writebufferto shieldthe on-chipbuses fromexternalbus writelatencyand thecorebuses aresplit-transactionbuses,so externalbus readsfrom slowdevicesarenon-blocking.

26.11 FreezeMode

When Freezemode isentered,theCVSD/PCM converterswillexhibitthefollowingbehavior:

• CVSD InFIFO willnothave dataremoved by theconvertercore.
• CVSD Out FIFO willnothave dataadded by theconvertercore.
• PCM Out bufferwillnotbe updatedby theconvertercore.
• The automaticclear-on-readfunctionofthefollowingstatusbitsintheCVSTATn registerisdisabled: – PCMINT – CVE – CVF

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26.12 CVSD/PCM ConverterRegisters

Table26-1liststheCVSD/PCM registers Table26-1.CVSD/PCM Registers NAME ADDRESS DESCRIPTION CVSDIN0 FF 4800h CVSD Data InputRegister0 CVSDIN1 FF 4C00h CVSD Data InputRegister1 CVSDOUT0 FF 4804h CVSD Data OutputRegister0 CVSDOUT1 FF 4C04h CVSD Data OutputRegister1 PCMIN0 FF 4808h PCM Data InputRegister0 PCMIN1 FF 4C08h PCM Data InputRegister1 PCMOUT0 FF 480Ch PCM Data OutputRegister0 PCMOUT1 FF 4C0Ch PCM Data OutputRegister1 LOGIN0 FF 4810h LogarithmicPCM Data OutputRegister0 LOGIN1 FF 4C10h LogarithmicPCM Data OutputRegister1 LOGOUT0 FF 4814h LogarithmicPCM Data OutputRegister0 LOGOUT1 FF 4C14h LogarithmicPCM Data OutputRegister1 LINEARIN0 FF 4818h LinearPCM Data InputRegister0 LINEARIN1 FF 4C18h LinearPCM Data InputRegister1 LINEAROUT0 FF 481Ch LinearPCM Data OutputRegister0 LINEAROUT1 FF 4C1Ch LinearPCM Data OutputRegister1 CVCTRL0 FF 4820h CVSD ControlRegister0 CVCTRL1 FF 4C20h CVSD ControlRegister1 CVSTAT0 FF 4824h CVSD StatusRegister0 CVSTAT1 FF 4C24h CVSD StatusRegister1

26.12.1 CVSD Data InputRegistern (CVSDINn)

The CVSDINn registersare16-bit,write-onlyregisters.They areused towriteCVSD dataintotheCVSD toPCM converterFIFOs.The FIFOs are8 words deep.The CVSDIN bit15 representstheCVSD databit att= t0,CVSDIN bit0 representstheCVSD databitatt= t0 – 250 µs. 15 0 CVSDIN

26.12.2 CVSD Data Output Registern (CVSDOUTn)

The CVSDOUTn registersare16-bit,read-onlyregisters.They areused toreadtheCVSD datafromthe PCM toCVSD converterFIFOs.The FIFOs are8 words deep.Reading a CVSDOUTn registerafterreset returnsundefineddata. 15 0 CVSDOUT

26.12.3 PCM Data InputRegistern (PCMINn)

The PCMINn registersare 16-bit,write-onlyregisters.They are used to writePCM data to the PCM to CVSD converterviatheAPB bus.They aredouble-buffered,providinga 125 µs periodforan interruptor DMA requesttorespond. Copyright© 2013,Texas InstrumentsIncorporated DualCVSD/PCM ConversionModules 263 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 15 0 PCMIN

26.12.4 PCM Data Output Register(PCMOUTn)

The PCMOUTn registersare16-bit,read-onlyregisters.They areused toreadPCM datafromtheCVSD toPCM converter.They aredouble-buffered,providinga 125 µs periodforan interruptorDMA requestto respond.AfterresetthePCMOUT registersareclear. 15 0 PCMOUT

26.12.5 LogarithmicPCM Data InputRegistern (LOGINn)

The LOGINn registersare8-bit,write-onlyregisters.They areused toreceive8-bitlogarithmicPCM data fromtheAPB bus and convertitinto13-bitlinearPCM data. 7 0 LOGIN

26.12.6 LogarithmicPCM Data Output Registern (LOGOUTn)

The LOGOUTn registersare 8-bit,read-onlyregisters.They holdlogarithmicPCM data thathas been convertedfromlinearPCM data.Afterreset,theLOGOUT registersareclear. 7 0 LOGOUT

26.12.7 LinearPCM Data InputRegistern (LINEARINn)

The LINEARINn registersare 16-bit,write-onlyregisters.The dataisleft-aligned.When convertingtoA- law,bits2:0areignored.When convertingtoµ-law,bits1:0areignored 15 0 LINEARIN

26.12.8 LinearPCM Data Output Registern (LINEAROUTn)

The LINEAROUTn registersare16-bit,read-onlyregisters.The dataisleft-aligned.When convertingfrom A-law,bits2:0areclear.When convertingfromµ-law,bits1:0areclear.Afterreset,thisregisterisclear. 15 0 LINEAROUT

26.12.9 CVSD ControlRegistern (CVCTRLn)

The CVCTRLn registersare 16-bit,read/writeregistersthatcontrolinterrupts,DMA, and modes of operation.Atreset,allimplementedbitsarecleared. 7 6 5 4 3 2 1 0 DMAPO DMACI DMACO CVSDERRINT CVSDINT PCMINT CLKEN CVEN 15 14 13 12 11 10 9 8 Reserved RESOLUTION PCMCONV CVSDCONV DMAPI

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www.ti.com SNOSCW5 –MAY 2013 CVEN The Module EnablebitenablesordisablestheCVSD conversionmodule interface. When thebitisset,theinterfaceisenabledwhichallowsreadand writeoperationsto therestofthemodule.When thebitisclear,themodule isdisabled.When the module isdisabledthestatusregisterCVSTAT willbe clearedtoitsresetstate. 0 – CVSD module enabled. 1 – CVSD module disabled. CLKEN The CVSD ClockEnablebitenablesthe2-MHz clocktothefilterengineand CVSD encodersand decoders. 0 – CVSD module clockdisabled. 1 – CVSD module clockenabled. PCMINT The PCM InterruptEnablebitcontrolsgenerationofthePCM interrupt.Ifset,thisbit enablesthePCM interrupt.IfthePCMINT bitisclear,thePCM interruptisdisabled. 0 – PCM interruptdisabled. 1 – PCM interruptenabled. CVSDINT The CVSD FIFO InterruptEnablebitcontrolsgenerationoftheCVSD interrupt.Ifset, thisbitenablestheCVSD interruptthatoccursiftheCVSD InFIFO isnearlyempty or theCVSD Out FIFO isnearlyfull.IftheCVSDINT bitisclear,theCVSD nearly full/nearlyempty interruptisdisabled. 0 – CVSD interruptdisabled. 1 – CVSD interruptenabled. CVSDERRINT The CVSD FIFO ErrorInterruptEnablebitcontrolsgenerationoftheCVSD error interrupt.Ifset,thisbitenablesan interrupttooccurwhen theCVSD Out FIFO isfull ortheCVSD InFIFO isempty.IftheCVSDERRINT bitisclear,theCVSD full/empty interruptisdisabled. 0 – CVSD errorinterruptdisabled. 1 – CVSD errorinterruptenabled. DMACO The DMA EnableforCVSD Out bitenableshardwareDMA controlforreadingCVSD datafromtheCVSD Out FIFO.Ifclear,DMA supportisdisabled. 0 – CVSD outputDMA disabled. 1 – CVSD outputDMA enabled. DMACI The DMA EnableforCVSD InbitenableshardwareDMA controlforwritingCVSD dataintotheCVSD InFIFO.Ifclear,DMA supportisdisabled. 0 – CVSD inputDMA disabled. 1 – CVSD inputDMA enabled. DMAPO The DMA EnableforPCM Out bitenableshardwareDMA controlforreadingPCM datafromthePCMOUT register.Ifclear,DMA supportisdisabled. 0 – PCM outputDMA disabled. 1 – PCM outputDMA enabled. DMAPI The DMA EnableforPCM InbitenableshardwareDMA controlforwritingPCM data intothePCMIN register.Ifcleared,DMA supportisdisabled. 0 – PCM inputDMA disabled. 1 – PCM inputDMA enabled. CVSDCONV The CVSD toPCM ConversionFormatfieldspecifiesthePCM formatforCVSD/PCM conversions. 00 – CVSD <-> 8-bitµ-Law PCM. 01 – CVSD <-> 8-bitA-Law PCM. 10 – CVSD <-> LinearPCM. 11 – Reserved. Copyright© 2013,Texas InstrumentsIncorporated DualCVSD/PCM ConversionModules 265 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com PCMCONV The PCM toPCM ConversionFormatbitselectsthePCM formatforPCM/PCM conversions. 0 – LinearPCM <-> 8-bitµ-Law PCM 1 – LinearPCM <-> 8-bitA-Law PCM RESOLUTION The LinearPCM ResolutionfieldspecifiestheattenuationofthePCM dataforthe linearPCM toCVSD conversionsby rightshiftingand signextendingthedata.This affectsthelogPCM dataas wellas thelinearPCM data.The logdataisconvertedto eitherleft-justifiedzero-stuffed13-bit(A-law)or14-bit(µ-law).The RESOLUTION fieldcan be used tocompensate forany change inaveragelevelsresultingfromthis conversion. 00 – No shift. 01 – 1-bitattenuation. 10 – 2-bitattenuation. 11 – 3-bitattenuation.

26.12.10 CVSD StatusRegistern (CVSTATn)

The CVSTATn registersare16-bit,read-onlyregistersthatholdthestatusinformationoftheCVSD/PCM modules.At resetor when themodule isdisabled(CVCTRLn.CVEN bitiscleared),allimplementedbits arecleared. 15 11 10 8 7 5 4 3 2 1 0 Reserved CVOUTST CVINST CVF CVE PCMINT CVNF CVNE CVNE The CVSD InFIFO NearlyEmpty bitindicateswhen onlythreeCVSD datawords areleftin theCVSD InFIFO,so new CVSD datashouldbe writtenintotheCVSD InFIFO.Ifthe CVSDINT bitisset,an interruptwillbe assertedwhen theCVNE bitisset.IftheDMACI bit isset,a DMA requestwillbe assertedwhen thisbitisset.The CVNE bitisclearedwhen theCVSTATn registerisread. 0 – CVSD InFIFO isnotnearlyempty. 1 – CVSD InFIFO isnearlyempty. CVNF The CVSD Out FIFO NearlyFullbitindicateswhen onlythreeempty word locationsareleft intheCVSD Out FIFO,so theCVSD Out FIFO shouldbe read.IftheCVSDINT bitisset,an interruptwillbe assertedwhen theCVNF bitisset.IftheDMACO bitisset,a DMA request willbe assertedwhen thisbitisset.Softwaremust notrelyon theCVNF bitas an indicator ofthenumber ofvalidwords intheFIFO.Softwaremust checktheCVOUTST fieldtoread thenumber ofvalidwords intheFIFO.The CVNF bitisclearedwhen theCVSTATn register isread. 0 – CVSD Out FIFO isnotnearlyfull. 1 – CVSD Out FIFO isnearlyfull. PCMINT The PCM InterruptbitsetindicatesthatthePCMOUTn registerisfulland needs tobe read orthePCMINn registerisempty and needs tobe loadedwithnew PCM data.The PCMINT bitisclearedwhen theCVSTATn registerisread,unlessthedeviceisinFreezemode. 0 – PCM does notrequireservice. 1 – PCM requiresloadingorunloading. CVE The CVSD InFIFO Empty bitindicateswhen theCVSD InFIFO has been readby the CVSD converterwhiletheFIFO was alreadyempty.IftheCVSDERRINT bitisset,an interruptwillbe assertedwhen theCVE bitisset.The CVE bitisclearedwhen the CVSTATn registerisread,unlessthedeviceisinFreezemode. 0 – CVSD InFIFO has notbeen readwhileempty. 1 – CVSD InFIFO has been readwhileempty.

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www.ti.com SNOSCW5 –MAY 2013 CVF The CVSD Out FIFO FullbitsetindicateswhethertheCVSD Out FIFO has been writtenby theCVSD converterwhiletheFIFO was alreadyfull.IftheCVSDERRINT bitisset,an interruptwillbe assertedwhen theCVF bitisset.The CVF bitisclearedwhen the CVSTATn registerisread,unlessthedeviceisinFreezemode. 0 – CVSD Out FIFO has notbeen writtenwhilefull. 1 – CVSD Out FIFO has been writtenwhilefull. CVINST The CVSD InFIFO Statusfieldindicatesthecurrentnumber ofempty 16-bitword locations intheCVSD InFIFO.The fieldisbiasedby 1,so when thereare8 empty words (FIFOis empty),theCVINST fieldwillreadas 111b.When thereare1 or0 empty words (FIFOholds 7 or8 words ofdata),theCVINST fieldwillreadas 000b. CVOUTST CVSD Out FIFO Statusfieldindicatesthecurrentnumber ofvalid16-bitCVSD datawords intheCVSD Out FIFO.When theFIFO isempty,theCVOUTST fieldwillreadas 000b. When theFIFO holds7 or8 words ofdata,theCVOUTST fieldwillreadas 111b.

27 Dual/Quad UART

The CP3SP33 providesfourUniversalAsynchronousReceiver/Transmitter(UART) modules intheFBGA- 224 package,and two UART modules intheFBGA-144 package.Each module supportsa wide rangeof software-programmablebaud rates(up to 3.072 Mbaud) and data formats.Ithandlesautomaticparity generationand severalerrordetectionschemes. AllUART modules offerthefollowingfeatures:

• Full-duplexdouble-bufferedreceiver/transmitter
• Asynchronousoperation
• Programmable baud rate
• Programmable framingformats:7,8,or9 databits;even,odd,orno parity;one ortwo stopbits(mark orspace)
• Hardware paritygenerationfordatatransmissionand paritycheckfordatareception
• InterruptorDMA requestson transmitreadyand receivereadyconditions,separatelyenabled
• Software-controlledbreaktransmissionand detection
• Internaldiagnosticcapability
• Automaticdetectionofparity,framing,and overrunerrors The UART modules arereferredtoas UART0, UART1, UART2, and UART3. UART2 and UART3 arenot availableintheFBGA-144 package. UART0, UART1, and UART2 resideon the CPU peripheralAPB bus.UART3 ison the shared audio peripheralAPB bus. UART0 offerssynchronousoperationusingthe CKX externalclockpininthe FBGA-224 package.The CKX signalisnotavailableintheFBGA-144 package. UART0, UART1, and UART2 supporthardwareflowcontrolusingtheCTSn and RTSn signals.

27.1 FunctionalOverview

Figure27-1isa blockdiagramoftheUART module showingthebasicfunctionalunitsintheUART:

• Transmitter
• Receiver
• Baud Rate Generator
• Controland ErrorDetection The Transmitterblockconsistsofan 8-bittransmitshiftregisterand an 8-bittransmitbuffer.Data bytes areloadedinparallelfromthebufferintotheshiftregisterand thenshiftedoutseriallyon theTXDn pin. Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 267 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com The Receiverblockconsistsofan 8-bitreceiveshiftregisterand an 8-bitreceivebuffer.Data isreceived seriallyon the RXDn pin and shiftedintothe shiftregister.Once eightbitshave been received,the contentsoftheshiftregisteraretransferredinparalleltothereceivebuffer. The Transmitterand Receiverblocksbothcontainextensionsfor9-bitdatatransfers,as requiredby the9- bitand loopbackoperatingmodes. The Baud Rate Generatorgeneratestheclockforthesynchronousand asynchronousoperatingmodes. It consistsoftwo registersand a two-stagecounter.The registersareused tospecifya prescalervalueand a baud ratedivisor.The firststageof the counterdividesthe UART clockbased on the valueof the programmed prescalertocreatea slowerclock.The second stageofthecountercreatesthebaud rate clockby dividingtheoutputofthefirststagebased on theprogrammed baud ratedivisor. The Controland ErrorDetectionblockcontainstheUART controlregisters,controllogic,errordetection circuit,paritygenerator/checker,and interruptgenerationlogic.The controlregistersand controllogic determinethedataformat,mode ofoperation,clocksource,and typeofparityused.The errordetection circuitgeneratesparitybitsand checksforparity,framing,and overrunerrors. The Flow ControlLogicblockprovidesthecapabilityforhardwarehandshakingbetween theUART and a peripheraldevice.When theperipheraldeviceneeds tostoptheflowofdatafromtheUART, itdeasserts theclear-to-send(CTSn) signalwhichcauses theUART topause aftersendingthecurrentframe(ifany). The UART assertstheready-to-send(RTSn) signaltotheperipheralwhen itisreadytosend a character.

27.2 UART Operation

The UART has two basicmodes ofoperation:synchronousand asynchronous.Synchronousmode isonly supportedfortheUART0 module.Inaddition,thereare two special-purposemodes, calledattentionand diagnostic.Thissectiondescribestheoperatingmodes oftheUART.

27.2.1 Asynchronous Mode

The asynchronousmode oftheUART enablesthedevicetocommunicate withotherdevicesusingjust two communicationsignals:transmitand receive. Inasynchronousmode, thetransmitshiftregister(TSFT) and thetransmitbuffer(UnTBUF) double-buffer thedatafortransmission.To transmita character,a databyteisloadedintheUnTBUF register.The data isthentransferredtotheTSFT register.WhiletheTSFT registerisshiftingoutthecurrentcharacter(LSB first)on the TXD pin,the UnTBUF registerisloadedby softwarewiththe nextbyteto be transmitted. When TSFT finishestransmissionofthelaststopbitofthecurrentframe,thecontentsofUnTBUF are transferredto the TSFT registerand the TransmitBufferEmpty bit(UTBE) is set.The UTBE bitis automaticallyclearedby theUART when softwareloadsa new characterintotheUnTBUF register.During transmission,theUXMIP bitissethighby theUART. ThisbitisresetonlyaftertheUART has sentthe laststop bitof the currentcharacterand the UnTBUF registeris empty. The UnTBUF registeris a read/writeregister.The TSFT registerisnotsoftwareaccessible. Inasynchronousmode, theinputfrequencytotheUART is16 timesthebaud rate.Inotherwords,there are16 clockcyclesperbittime.Inasynchronousmode, thebaud rategeneratorisalwaystheUART clock source. The receiveshiftregister(RSFT) and thereceivebuffer(UnRBUF) doublebufferthedatabeingreceived. The UART receivercontinuouslymonitorsthe signalon the RXDn pin fora low levelto detectthe beginningof a startbit.On sensingthislow level,the UART waitsforseven inputclockcyclesand samples againthreetimes.Ifallthreesamples stillindicatea validlow,thenthereceiverconsidersthisto be a validstartbit,and theremainingbitsinthecharacterframe are each sampled threetimes,around themid-bitposition.For any bitfollowingthestartbit,thelogicvalueisfoundby majorityvoting,i.e.the two samples withthesame valuedefinethevalueofthedatabit.Figure27-2 illustratestheprocessof startbitdetectionand bitsampling.

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16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Sample Sample Sample DATA (LSB)STARTBIT DATABIT DS061 TXDTransmitter Control and Error Detection Parity Generator/Checker RXDReceiver CKXBaud Rate Generator Baud Clock Baud Clock PCLK Clock APB Bus DS345 RTS CTS Flow Control Logic CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Data bitsare sensed by takinga majorityvoteofthreesamples latchednear themidpointofeach baud (bittime).Normally,thepositionofthesamples withinthebaud isdeterminedautomatically,butsoftware can overridetheautomaticselectionby settingtheUSMD bitintheUnMDSL2 registerand programming theUnSPOS register. Serialdatainputon theRXDn pinisshiftedintotheRSFT register.On receivingthecompletecharacter, the contentsof the RSFT registerare copiedintothe UnRBUF registerand the Receive BufferFullbit (URBF) isset.The URBF bitisautomaticallyclearedwhen softwarereadsthecharacterfromtheURBUF register.The RSFT registerisnotsoftwareaccessible. Figure27-1.UART Block Diagram Figure27-2.UART Asynchronous Communication Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 269 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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27.2.2 Synchronous Mode

The synchronousmode of UART0 enablesthe deviceto communicate withotherdevicesusingthree communicationsignals:transmit,receive,and clock.Inthismode, databitsaretransferredsynchronously withthe UART0 clocksignal.Data bitsare transmittedon the risingedges and receivedon the falling edges of the clocksignal,as shown in Figure27-3. Data bytes are transmittedand receivedleast significantbit(LSB)first. Figure27-3.UART Synchronous Communication Insynchronousmode, thetransmitshiftregister(TSFT) and thetransmitbuffer(U0TBUF) double-buffer thedatafortransmission.To transmita character,a databyteisloadedintheU0TBUF register.The data isthentransferredtotheTSFT register.The TSFT registershiftsoutone bitofthecurrentcharacter,LSB first,on each risingedge oftheclock.WhiletheTSFT isshiftingoutthecurrentcharacteron theTXD0 pin,theU0TBUF registermay be loadedby softwarewiththenextbytetobe transmitted.When theTSFT finishestransmissionofthelaststopbitwithinthecurrentframe,thecontentsofU0TBUF aretransferred totheTSFT registerand theTransmitBufferEmpty bit(UTBE) isset.The UTBE bitisautomaticallyreset by the UART when softwareloadsa new characterintothe U0TBUF register.Duringtransmission,the UXMIP bitissetby theUART. ThisbitisclearedonlyaftertheUART has sentthelastframe bitofthe currentcharacterand theU0TBUF registerisempty. The receiveshiftregister(RSFT) and thereceivebuffer(URBUF) double-bufferthedatabeingreceived. Serialdatareceivedon theRXD0 pinisshiftedintotheRSFT registeron thefirstfallingedge oftheclock. Each subsequentfallingedge oftheclockcauses an additionalbittobe shiftedintotheRSFT register. The UART assumes a completecharacterhas been receivedafterthecorrectnumber ofrisingedges on CKX (basedon theselectedframe format)have been detected.On receivinga completecharacter,the contentsoftheRSFT registerarecopiedintotheU0RBUF registerand theReceiveBufferFullbit(URBF) is set.The URBF bitis automaticallyclearedwhen softwarereads the characterfrom the U0RBUF register. The transmitterand receivermay be clockedby eitheran externalsourceprovidedtotheCKX pinorthe internalbaud rategenerator.Inthelattercase,theclocksignalisplacedon theCKX pinas an output.

27.2.3 AttentionMode

The Attentionmode isavailablefornetworkingthisdevicewithotherprocessors.Thismode requiresthe 9-bitdatafor-mat withno parity.The number ofstartbitsand number ofstopbitsareprogrammable.In thismode, two typesof 9-bitcharactersare sent on the network:address charactersconsistingof 8 addressbitsand a 1 intheninthbitpositionand datacharactersconsistingof8 databitsand a 0 inthe ninthbitposition.

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www.ti.com SNOSCW5 –MAY 2013 WhileinAttentionmode, theUART receivermonitorsthecommunicationflowbutignoresallcharacters untilan ad- dresscharacterisreceived.On receivingan addresscharacter,thecontentsofthereceive shiftregisterare copied to the receivebuffer.The URBF bitis set and an interrupt(ifenabled)is generated.The UATN bitis automaticallycleared,and the UART begins receivingallsubsequent characters.Softwaremust examine the contentsof the URBUF registerand respond by acceptingthe subsequentcharacters(byleavingtheUATN bitclear)orwaitingforthenextaddresscharacter(bysetting theUATN bitagain). The operationoftheUART transmitterisnotaffectedby theselectionofthismode. The valueoftheninth bittobe transmittedisprogrammed by settingorclearingtheUXB9 bitintheUART Frame Selectregister. The valueoftheninthbitreceivedisreadfromURB9 intheUART StatusRegister.

27.2.4 DiagnosticMode

The Diagnosticmode isavailablefortestingof the UART. In thismode, the TXDn and RXDn pinsare internallyconnectedtogether,and datashiftedoutofthetransmitshiftregisterisimmediatelytransferred tothereceiveshiftregister.Thismode supportsonlythe9-bitdataformatwithno parity.The number of startand stopbitsisprogrammable.

27.2.5 Frame Format Selection

The formatshown inFigure27-4consistsofa startbit,seven databits(excludingparity),and one ortwo stop bits.Ifparitybitgenerationis enabled by settingthe UPEN bit,a paritybitis generatedand transmittedfollowingtheseven databits. Figure27-4.7-BitData Frame Options The formatshown inFigure27-5consistsofone startbit,eightdatabits(excludingparity),and one ortwo stop bits.Ifparitybitgenerationis enabled by settingthe UPEN bit,a paritybitis generatedand transmittedfollowingtheeightdatabits. Figure27-5.8-BitData Frame Options Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 271 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

3 Start

SNOSCW5 –MAY 2013 www.ti.com The formatshown inFigure27-6 consistsofone startbit,ninedatabits,and one or two stopbits.This formatalsosupportstheUART attentionfeature.When operatinginthisformat,alleightbitsofUnTBUF and UnRBUF areused fordata.The ninthdatabitistransmittedand receivedusingtwo bitsinthecontrol registers,calledUXB9 and URB9. Parityisnotgeneratedorverifiedinthismode. Figure27-6..9-bitData Frame Options

27.2.6 Baud Rate Generator

The Baud Rate Generatorcreatesthebasicbaud clockfromthePCLK Clock.The PCLK Clockispassed througha two-stagedividerchainconsistingofa 5-bitbaud rateprescaler(UnPSC) and an 11-bitbaud ratedivisor(UnDIV). The relationshipbetween the5-bitprescalerselect(UnPSC) settingand theprescalerfactorsisshown in Table27-1. Table27-1.PrescalerFactors PRESCALER PRESCALER FACTOR PRESCALER SELECT PRESCALER FACTORSELECT 00000 No clock 10000 8.5 00001 1 10001 9 00010 1.5 10010 9.5 00011 2 10011 10 00100 2.5 10100 10.5 00101 3 10101 11 00110 3.5 10110 11.5 00111 4 10111 12 01000 4.5 11000 12.5 01001 5 11001 13 01010 5.5 11010 13.5 01011 6 11011 14 01100 6.5 11100 14.5 01101 7 11101 15 01110 7.5 11110 15.5 01111 8 11111 16 A prescalerfactorofzerocorrespondsto“no clock.” The “no clock” conditionistheUART power down mode, inwhichtheUART clockisturnedofftoreducepower consumption.Softwaremust selectthe“no clock” conditionbeforeenteringa new baud rate.Otherwise,itcouldcause incorrectdatatobe received ortransmitted.The UnPSR registermust containa valueotherthanzerowhen an externalclockisused atCKX.

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27.2.7 Interrupts

The UART modules arecapableofgeneratinginterruptson:

• ReceiveBufferFull
• ReceiveError
• TransmitBufferEmpty
• ClearTo Send Figure27-7shows a diagramoftheinterruptsourcesand associatedenablebits. Figure27-7.UART Interrupts The interruptscan be individuallyenabledordisabledusingtheEnableTransmitInterrupt(UETI),Enable ReceiveInterrupt(UERI),and EnableReceiveErrorInterrupt(UEER) bitsintheUnICTRL register. A transmitinterruptisassertedwhen both the UTBE and UETI bitsare set.To remove thisinterrupt, softwaremust eitherdisabletheinterruptby clearingtheUETI bitorwritetotheUnTBUF register(which clearstheUTBE bit). A receiveinterruptisassertedon theseconditions:
• Both the URBF and UERI bitsare set.To remove thisinterrupt,softwaremust eitherdisablethe interruptby clearingtheUERI bitorreadfromtheURBUF register(whichclearstheURBF bit).
• Both theUERR and theUEEI bitsare set.To remove thisinterrupt,softwaremust eitherdisablethe interruptby clearingtheUEEI bitorreadtheUnSTAT register(whichclearstheUERR bit). A flowcontrolinterruptisassertedwhen both the UDCTS and the UEFCI bitsare set.To remove this interrupt,softwaremust eitherdisablethe interruptby clearingthe UEFCI bitor readingthe UnICTRL register(whichclearstheUDCTS bit). Because theUART3 transmitand receiveinterruptrequestscan be handledby eithertheCPU or DSP interruptcontrollers,the interruptrequestsare passed throughthe Audio Subsystem Controller(ASC), which must be programmed to routeitto the interruptcontroller.To use theseinterrupts,theymust be enabledatthreelevels:
• UART3 module— theinterruptmust be enabledintheU3ICTRL register. Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 273 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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• ASC module— the UART3 interruptsare assigned to ASC interruptchannels 2 (transmit)and 3 (receive),so bits2 and 3 in the ASCINTSEL registermust be clearto selectthe CPU interrupt controllerorsettoselecttheDSP interruptcontroller.
• Interruptcontroller— the interruptrequestmust be enabled in the interruptcontroller.For the CPU interruptcontroller,theseareinterruptrequestsIRQ12 (transmit)and IRQ13 (receive).

27.2.8 DMA Support

Any UART module can operatewithone or two DMA chan-nels.For processor-independentfull-duplex operation,two DMA channels must be used. Both receiveand transmitDMA can be enabled simultaneously. IftransmitDMA isenabled(theUETD bitisset),theUART generatesa DMA requestwhen theUTBE bit changes statefrom clearto set.EnablingtransmitDMA automaticallydis-ables transmitinterrupts, withoutregardtothestateoftheUETI bit. IfreceiveDMA isenabled(theUERD bitisset),theUART generatesa DMA requestwhen theURBF bit changes statefromcleartoset.EnablingreceiveDMA automaticallydis-ablesreceiveinterrupts,without regardtothestateoftheUERI bit.However,receiveerrorinterruptsshouldbe en-abled(theUEEI bitis set)toallowdetectionofreceiveerrorswhen DMA isused. Because theUART3 DMA requestscan be handledby ei-thertheCPU orDSP DMA controllers,theDMA requestsarepassed throughtheAudioSubsystem Controller(ASC),whichmust be programmed toroute them totheDMA con-troller.To use theUART3 DMA requests,theymust be en-abledatthreelevels:

• UART3 module— theUART3 DMA requestsmust be enabledintheU3MDSL1 register.
• ASC module— the UART3 DMA requestsare assignedto ASC DMA channels0 (receive)and 1 (transmit).These channelsarecontrolledby bits0 and 1 intheASCDMASEL0 register.The bitsmust be cleartoselecttheCPU DMA controlleror settoselecttheDSP DMA controller.IftheDSP DMA controllerisselected,theDSP DMA channelmust be programmed intheASCDDMASELn registers.
• DMA controller— the DMA requestsmust be enabled in the DMA controller.For the CPU DMA controller,theseareDMA requests0 (receive)and 1 (transmit).

27.2.9 Break Generationand Detection

A linebreakisgeneratedwhen theUBRK bitissetintheUnMDSL1 register.The TXDn lineremainslow untiltheprogramresetstheUBRK bit. A linebreakisdetectedifRXDn remainslowfor10 bittimesorlongeraftera missingstopbitisdetected.

27.2.10 ParityGenerationand Detection

Parityisonlygeneratedorchecked withthe7-bitand 8-bitdataformats.Itisnotgeneratedorchecked in the diagnosticloopbackmode, the attentionmode, or innormal mode withthe 9-bitdata format.Parity generationand checkingareenabledand disabledusingthePEN bitintheUnFRS register.The UPSEL bitsintheUnFRS registerareused toselectodd,even,orno parity.

27.3 UART Registers

SoftwareinteractswiththeUART modules by accessingtheUART registers,as listedinTable27-2. Table27-2.UART Registers NAME ADDRESS DESCRIPTION U0ICTRL FF 9408h UART0 InterruptControlRegister U0STAT FF 940Ch UART0 StatusRegister U0MDSL1 FF 9414h UART0 Mode SelectRegister1 U0MDSL2 FF 9424h UART0 Mode SelectRegister2

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www.ti.com SNOSCW5 –MAY 2013 Table27-2.UART Registers(continued) NAME ADDRESS DESCRIPTION U0PSR FF 941Ch UART0 Baud Rate Prescaler U0BAUD FF 9418h UART0 Baud Rate Divisor U0FRS FF 9410h UART0 Frame SelectRegister U0SPOS FF 9428h UART0 Sample PositionRegister U0OVR FF 9420h UART0 OversampleRate Register U0RBUF FF 9404h UART0 ReceiveData Buffer U0TBUF FF 9400h UART0 TransmitData Buffer U1ICTRL FF 9808h UART1 InterruptControlRegister U1STAT FF 980Ch UART1 StatusRegister U1MDSL1 FF 9814h UART1 Mode SelectRegister1 U1MDSL2 FF 9824h UART1 Mode SelectRegister2 U1PSR FF 981Ch UART1 Baud Rate Prescaler U1BAUD FF 9818h UART1 Baud Rate Divisor U1FRS FF 9810h UART1 Frame SelectRegister U1SPOS FF 9828h UART1 Sample PositionRegister U1OVR FF 9820h UART1 OversampleRate Register U1RBUF FF 9804h UART1 ReceiveData Buffer U1TBUF FF 9800h UART1 TransmitData Buffer U2ICTRL FF 9C08h UART2 InterruptControlRegister U2STAT FF 9C0Ch UART2 StatusRegister U2MDSL1 FF 9C14h UART2 Mode SelectRegister1 U2MDSL2 FF 9C24h UART2 Mode SelectRegister2 U2PSR FF 9C1Ch UART2 Baud Rate Prescaler U2BAUD FF 9C18h UART2 Baud Rate Divisor U2FRS FF 9C10h UART2 Frame SelectRegister U2SPOS FF 9C28h UART2 Sample PositionRegister U2OVR FF 9C20h UART2 OversampleRate Register U2RBUF FF 9C04h UART2 ReceiveData Buffer U2TBUF FF 9C00h UART2 TransmitData Buffer U3ICTRL FF 5C08h UART3 InterruptControlRegister U3STAT FF 5C0Ch UART3 StatusRegister U3MDSL1 FF 5C14h UART3 Mode SelectRegister1 U3MDSL2 FF 5C24h UART3 Mode SelectRegister2 U3PSR FF 5C1Ch UART3 Baud Rate Prescaler U3BAUD FF 5C18h UART3 Baud Rate Divisor U3FRS FF 5C10h UART3 Frame SelectRegister U3SPOS FF 5C28h UART3 Sample PositionRegister U3OVR FF 5C20h UART3 OversampleRate Register U3RBUF FF 5C04h UART3 ReceiveData Buffer U3TBUF FF 5C00h UART3 TransmitData Buffer Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 275 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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27.3.1 UART InterruptControlRegister(UnICTRL)

The UnICTRL registersare8-bit,read/writeregistersthatcontainthereceiveand transmitinterruptstatus bits(read-onlybits)and theinterruptenablebits(read/writebits).The registerisinitializedto01h atreset. 7 6 5 4 3 2 1 0 UEEI UERI UETI UEFCI UCTS UDCTS URBF UTBE UTBE The TransmitBufferEmpty bitissetby hard-ware when theUART transfersdatafromthe UnTBUF registertothetransmitshiftregisterfortransmission.Itisautomaticallyclearedby thehardwareon thenextwritetotheUnTBUF register. 0 – Transmitbufferisloaded. 1 – Transmitbufferisempty. URBF The ReceiveBufferFullbitissetby hardwarewhen theUART has receiveda completedata frameand has transferredthedatafromthereceiveshiftregistertotheUnRBUF register.Itis automaticallyclearedby thehardwarewhen theUnRBUF registerisread. 0 – Receivebufferisempty. 1 – Receivebufferisloaded. UDCTS The DeltaClearTo Send bitindicateswhethertheCTSn inputhas changed statesincethe CPU lastreadthisregister.Thisbitisonlyused withUART0, UART1, and UART2. 0 – No change sincelastread. 1 – Statehas changed sincelastread. UCTS UCTS The ClearTo Send bitindicatesthestateon theCTS input.Thisbitisonlyused with UART0, UART1, and UART2. 0 – CTSn inputishigh. 1 – CTSn inputislow. UEFCI The EnableFlow ControlInterruptbitcontrolswhethera flowcontrolinterruptisasserted when theUDCTS bitchanges fromcleartoset.Thisbitisonlyused withUART0, UART1, and UART2. 0 – Flow controlinterruptdisabled. 1 – Flow controlinterruptenabled. UETI The EnableTransmitterInterruptbit,when set,enablesgenerationofan interruptwhen the hardwaresetstheUTBE bit. 0 – Transmitbufferempty interruptdisabled. 1 – Transmitbufferempty interruptenabled. UERI The EnableReceiverInterruptbit,when set,enablesgenerationofan interruptwhen the hardwaresetstheURBF bit. 0 – Receivebufferfullinterruptdisabled. 1 – Receivebufferfullinterruptenabled. UEEI The EnableReceiveErrorInterruptbit,when set,enablesgenerationofan interruptwhen the hardwaresetstheUERR bitintheUn-STAT register. 0 – Receiveerrorinterruptdisabled. 1 – Receiveerrorinterruptenabled.

27.3.2 UART StatusRegister(UnSTAT)

The UnSTAT registersare 8-bit,read-onlyregistersthatcontainthe receiveand transmitstatusbits. These registersare clearedatreset.Any attemptby softwaretowritetotheseregistersisignored.The registerformatisshown below. 7 6 5 4 3 2 1 0 Reserved UXMIP URB9 UBKD UERR UDOE UFE UPE

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www.ti.com SNOSCW5 –MAY 2013 UPE The ParityErrorbitindicateswhethera parityerrorisdetectedwithina receivedcharacter. Thisbitisautomaticallyclearedby thehardwarewhen theUnSTAT registerisread. 0 – No parityerroroccurred. 1 – Parityerroroccurred. UFE The FramingErrorbitindicateswhethertheUART failstoreceivea validstopbitattheend of a frame.Thisbitisautomaticallyclearedby thehardwarewhen theUnSTAT registerisread. 0 – No framingerroroccurred. 1 – Framingerroroccurred. UDOE The Data OverrunErrorbitissetwhen a new characterisreceivedand transferredtothe UnRBUF registerbeforesoftwarehas readthepreviouscharacterfromtheUnRBUF register. Thisbitisautomaticallyclearedby thehardwarewhen theUnSTAT registerisread. 0 – No receiveoverrunerroroccurred. 1 – Receiveoverrunerroroccurred. UERR The ErrorStatusbitindicateswhen a parity,framing,oroverrunerroroccurs(anytimethat theUPE, UFE, orUDOE bitisset).Itisautomaticallyclearedby thehardwarewhen theUPE, UFE, and UDOE bitsareall0. 0 – No receiveerroroccurred. 1 – Receiveerroroccurred. UBKD The BreakDetectbitindicateswhen a linebreakconditionoccurs.Thisconditionisdetectedif RXDn remainslowforatleasttenbittimesaftera missingstopbithas been detectedatthe end ofa frame.The hardwareautomaticallyclearstheUBKD biton readingtheUnSTAT register,butonlyifthebreakconditionon RXDn no longerexists.IfreadingtheUnSTAT registerdoes notcleartheUBKD bitbecause thebreakisstillactivelydrivenon theline,the hardwareclearsthebitas soon as thebreakconditionno longerexists(when theRXDn input returnstoa highlevel). 0 – No breakconditionoccurred. 1 – Breakconditionoccurred. URB9 The Received9thData Bitholdstheninthdatabit,when theUART isconfiguredtooperatein the9-bitdataformat. UXMIP The TransmitInProgressbitindicateswhen theUART istransmitting.The hardwaresetsthis bitwhen theUART istransmittingdataand clearsthebitattheend ofthelastframebit. 0 – UART isnottransmitting. 1 – UART istransmitting.

27.3.3 UART Mode SelectRegister1 (UnMDSL1)

The UnMDSL1 registersare8-bit,read/writeregistersthatselecttheclocksource,synchronizationmode, attentionmode, and linebreak generation.These registersare clearedat reset.The registerformatis shown below. 7 6 5 4 3 2 1 0 URTS UFCE UERD UETD UCKS UBRK UATN UMOD UMOD The Mode bitselectsbetween synchronousand asynchronousmode. Synchronousmode is onlyavailablefortheUART0 module. 0 – Asynchronousmode. 1 – Synchronousmode. UATN The AttentionMode bitisused toenableAttentionmode. When set,thisbitselectsthe attentionmode ofoperationfortheUART. When clear,theattentionmode isdisabled.The hardwareclearsthisbitafteran addressframeisreceived.An addressframeisa 9-bit characterwitha 1 intheninthbitposition. 0 – Attentionmode disabled. 1 – Attentionmode enabled. Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 277 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com UBRK The ForceTransmissionBreakbitisused toforcetheTXD outputlow.Settingthisbitto1 causestheTXD pintogo low.TXD remainslowuntiltheUBRK bitisclearedby software. 0 – Normal operation. 1 – TXD pinforcedlow. UCKS The SynchronousClockSourcebitcontrolstheclocksourcewhen theUART operatesinthe synchronousmode (UMOD = 1).ThisfunctionalityisonlyavailablefortheUART0 module.If theUCKS bitisset,theUART operatesfroman externalclockprovidedon theCKX pin.Ifthe UCKS bitisclear,theUART operatesfromthebaud rateclockproducedby theUART on the CKX pin.Thisbitisignoredwhen theUART operatesintheasynchronousmode. 0 – Internalbaud rateclockisused. 1 – Externalclockisused. UETD The EnableTransmitDMA bitcontrolswhetherDMA isused forUART transmitoperations. EnablingtransmitDMA automaticallydisablestransmitinterrupts,withoutregardtothestateof theUETI bit. 0 – TransmitDMA disabled. 1 – TransmitDMA enabled. UERD The EnableReceiveDMA bitcontrolswhetherDMA isused forUART receiveoperations. EnablingreceiveDMA automaticallydisablesreceiveinterrupts,withoutregardtothestateof theUERI bit.Receiveerrorinterruptsareunaffectedby theUERD bit. 0 – ReceiveDMA disabled. 1 – ReceiveDMA enabled. UFCE The Flow ControlEnablebitcontrolswhetherflowcontrolinterruptsareenabled.This functionalityisonlyavailablefortheUART0, UART1, and UART2 modules. 0 – Flow controlinterruptsdisabled. 1 – Flow controlinterruptsenabled. URTS The Ready To Send bitdirectlycontrolsthestateoftheRTS output.Thisfunctionalityisonly availablefortheUART0, UART1, and UART2 modules. 0 – RTS outputishigh. 1 – RTS outputislow.

27.3.4 UART Mode SelectRegister2 (UnMDSL2)

The UnMDSL2 registersare 8-bit,read/writeregistersthatcontrolthe sample mode used to recover asynchronousdata.Atreset,theUnMDSL2 registersarecleared.The registerformatisshown below. 7 1M 0 Reserved USMD USMD The USMD bitcontrolsthesample mode forasynchronoustransmission. 0 – UART determinesthesample positionautomatically. 1 – The UnSPOS registerdeterminesthesample position.

27.3.5 UART Baud Rate Prescaler(UnPSR)

The UnPSR registersare 8-bit,read/writeregistersthatcontainsthe5-bitclockprescalerand theupper threebitsof the baud ratedivisor.These registersare clearedat reset.The registerformatisshown below. 7 3M M 2 0 UPSC UDIV10:8

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www.ti.com SNOSCW5 –MAY 2013 UPSC The Prescalerfieldspecifiestheprescalervalueused fordividingthePCLK Clockinthefirst stageofthetwo-stagedividerchain.Fortheprescalerfactorscorrespondingtoeach 5-bit value,see Table27-1. UDIV10:8 The Baud Rate Divisorfieldholdsthethreemost significantbits(bits10,9,and 8)ofthe UART baud ratedivisorused inthesecond stageofthetwo-stagedividerchain.The remainingbitsofthebaud ratedivisorareheldintheUnBAUD register.

27.3.6 UART Baud Rate Divisor(UnBAUD)

The UnBAUD registersare 8-bit,read/writeregistersthatcontainthe lowereightbitsof the baud rate divisor.The registercontentsareunknown atpower-upand areleftun-changed by a resetoperation.The registerformatisshown below. 7 0 UDIV7:0 UDIV7:0 The Baud Rate Divisorfieldholdstheeightlowest-orderbitsoftheUART baud ratedivisor used inthesecond stageofthetwo-stagedividerchain.The threemost significantbitsare heldintheUnPSR register.The divisorvalueused is(UDIV[10:0]+ 1).

27.3.7 UART Frame SelectRegister(UnFRS)

The UnFRS registersare8-bit,read/writeregistersthatcon-troltheframeformat,includingthenumber of databits,number ofstopbits,and paritytype.These registersareclearedatreset.The registerformatis shown below. 7 6 5 4 3 2 1 0 Reserved UPEN UPSEL UXB9 USTP UCHAR UCHAR The CharacterFrame Formatfieldselectsthenumber ofdatabitsperframe,notincluding theparitybit. 00 – 8 databitsperframe. 01 – 7 databitsperframe. 10 – 9 databitsperframe. 11 – Loop-backmode, 9 databitsperframe. USTP The StopBitsbitspecifiesthenumber ofstopbitstransmittedineach frame. 0 – One stopbitperframe. 1 – Two stopbitsperframe. UXB9 The Transmit9thData Bitholdsthevalueoftheninthdatabit,either0 or1,transmitted when theUART isconfiguredtotransmitninedatabitsperframe.Ithas no effectwhen the UART isconfiguredtotransmitseven oreightdatabitsperframe. UPSEL The ParitySelectfieldselectsthetreatmentoftheparitybit.When theUART isconfigured totransmitninedatabitsperframe,theparitybitisomittedand theUPSEL fieldisignored. 00 – Odd parity. 01 – Even parity. 10 – No parity,transmit1 (mark). 11 – No parity,transmit0 (space). UPEN The ParityEnablebitenablesordisablesparitygenerationand paritychecking.When the UART isconfiguredtotransmitninedatabitsperframe,thereisno paritybitand the UnPEN bitisignored. 0 – Paritygenerationand checkingdisabled. 1 – Paritygenerationand checkingenabled. Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 279 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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27.3.8 UART Sample PositionRegister(UnSPOS)

The UnSPOS registersare8-bit,read/writeregistersthatspecifythesample positionwhen theUSMD bit intheUnMDSL2 registerisset.At reset,theUnSPOS registersareinitializedto06h.The registerformat isshown below. 7 4M M 3 0 Reserved USAMP USAMP The Sample Positionfieldspecifiestheoversampleclockperiodatwhichtotakethefirstof threesamplesforsensingthevalueofdatabits.The clocksarenumbered startingat0 and may rangeup to15 for16× oversampling.The maximum valueforthisfieldis(oversampling rate– 3).The tablebelowshows theclockperiodatwhicheach ofthethreesamplesis taken,when automaticsamplingisenabled(UnMDSL2.USMD = 0). SAMPLE POSITION OVERSAMPLING RATE 1 2 3 7 2 3 4 8 2 3 4 9 3 4 5 10 3 4 5 11 4 5 6 12 4 5 6 13 5 6 7 14 5 6 7 15 6 7 8 16 6 7 8 The USAMP fieldmay be used tooverridetheautomaticselection,tochoose any otherclockperiodat whichtostarttakingthethreesamples.

27.3.9 UART Oversample Rate Register(UnOVR)

The UnOVR registersare8-bit,read/writeregistersthatspecifytheoversamplerate.At reset,theUnOVR registersarecleared.The registerformatisshown below. 7 4M M 3 0 Reserved UOVSR UOVSO The OversamplingRate fieldspecifiestheoversamplingrate,as giveninthefollowingtable. UOVSR3:0 OVERSAMPLING RATE 0000–0110 16 111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15

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6(5 10 )BR 9615.385(16 5 6.5) (9615.385 9600)%error 0.16 9600 u u u 32.552N 5.008 (N 5)6.5 6(5 10 )N P 32.552(16 9600) uu u CLKBR (O N P) u u CP3SP33 www.ti.com SNOSCW5 –MAY 2013

27.3.10 UART Receive Data Buffer(UnRBUF)

The UnRBUF registersare8-bit,read-onlyregistersused toreceiveeach databyte. 7 0 URBUF

27.3.11 UART TransmitData Buffer(UnTBUF)

The UnTBUF registersare8-bit,read/writeregistersused totransmiteach databyte. 7 0 UnTBUF

27.4 Baud Rate Calculations

The UART baud rateisdeterminedby thePCLK Clockfrequencyand thevaluesintheUnOVR, UnPSR, and Un- BAUD registers.Unless the PCLK Clock isan exactmultipleof the baud rate,therewillbe a smallamount oferrorintheresultingbaud rate.

27.4.1 Asynchronous Mode

The equationtocalculatethebaud rateinasynchronousmode is: (7) where BR isthebaud rate,CLK isthePCLK Clock,O istheoversamplerate,N isthebaud ratedivisor+ 1,and P istheprescalerdivisorselectedby theUPSR register. Assuming an PCLK Clockof5 MHz, a desiredbaud rateof9600,and an oversamplerateof16,theN × P termaccordingtotheequationabove is: (8) The N × P termisthendividedby each PrescalerFactorfromTable27-1toobtaina valueclosesttoan integer.The factorforthisexample is6.5. (9) The baud rateregisterisprogrammed witha baud ratedivisorof 4 (N = baud ratedivisor+ 1).This producesa baud clockof: (10) Note thatthepercenterrorismuch lowerthanwould be possiblewithoutthenon-integerprescalerfactor. Errorgreaterthan 3% is marginaland may resultin unreliableoperation.See Table 27-3 through Table27-5forrecommended baud rateprogrammingvalues. Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 281 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

CLKBR (2 N P) u u CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

27.4.2 Synchronous Mode

Synchronousmode isonlyavailablefortheUART0 module.When synchronousmode isselectedand the UCKS bitisset,theUART operatesfrom a clockreceivedon theCKX pin.When theUCKS bitisclear, theUART uses theclockfromtheinternalbaud rategeneratorwhichisalsodrivenon theCKX pin.When theinternalbaud rategeneratorisused,theequationforcalculatingthebaud rateis: (11) where BR isthebaud rate,CLK isthePCLK Clock,N isthevalueofthebaud ratedivisor+ 1,and P is the prescalerdividefactorselectedby the valuein the UnPSR register.Oversamplingisnot used in synchronousmode. Use thesame proceduretodeterminethevaluesofN and P as intheasynchronousmode. Inthiscase, however,onlyintegerprescalervaluesareallowed.

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www.ti.com SNOSCW5 –MAY 2013 Table27-3.Baud Rate Programming PCLK = 48 MHz PCLK = 45 MHz PCLK = 30 MHz PCLK = 24 MHz Baud Rate O N P %err O N P %err O N P %err O N P %err 300 16 2000 5 0 16 1875 5 0 16 6250 1 0 16 2000 2.5 0 600 16 2000 2.5 0 16 1875 2.5 0 16 3125 1 0 16 1250 2 0 1200 16 1250 2 0 8 3125 1.5 0 8 3125 1 0 16 1250 1 0 1800 7 401 9.5 0 8 3125 1 0 13 1282 1 0 8 1111 1.5 0.01 2000 16 1500 1 0 8 1875 1.5 0 8 1875 1 0 16 750 1 0 2400 16 1250 1 0 10 1875 1 0 10 1250 1 0 16 625 1 0 4800 16 625 1 0 10 625 1.5 0 10 625 1 0 16 125 2.5 0 7200 12 101 5.5 0.01 10 625 1 0 9 463 1 0.01 11 303 1 0.01 9600 16 125 2.5 0 15 125 2.5 0 10 125 2.5 0 10 250 1 0 19200 10 250 1 0 8 293 1 0.01 11 142 1 0.03 10 125 1 0 38400 10 125 1 0 11 71 1.5 0.03 11 71 1 0.03 10 25 2.5 0 128000 15 25 1 0 8 4 11 0.12 9 2 13 0.16 15 5 2.5 0 230400 13 16 1 0.16 13 15 1 0.16 10 1 13 0.16 13 8 1 0.16 2211840 11 2 1 1.36 10 2 1 1.73 9 1 1.5 0.47 2764800 7 1 2.5 0.79 8 2 1 1.73 3072000 8 1 2 2.34 10 1 1.5 2.34 Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 283 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table27-4.Baud Rate Programming Baud Rate PCLK = 12 MHz PCLK = 10 MHz PCLK = 8 MHz PCLK = 6 MHz O N P %err O N P %err O N P %err O N P %err 300 16 1250 2 0 13 1282 2 0 7 401 9.5 0 16 1250 1 0 600 16 1250 1 0 13 1282 1 0 12 1111 1 0.01 16 625 1 0 1200 16 625 1 0 13 641 1 0 12 101 5.5 0.01 16 125 2.5 0 2000 16 250 1.5 0 16 125 2.5 0 16 250 1 0 16 125 1.5 0 2400 16 125 2.5 0 9 463 1 0.01 11 303 1 0.01 10 250 1 0 4800 10 250 1 0 7 119 2.5 0.04 11 101 1.5 0.01 10 125 1 0 9600 10 125 1 0 7 149 1 0.13 14 17 3.5 0.04 10 25 2.5 0 691200 7 1 2.5 0.79 806400 10 1 1.5 0.79 921600 13 1 1 0.16 1105920 9 1 1 0.47

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www.ti.com SNOSCW5 –MAY 2013 Table27-5.Baud Rate Programming PCLK = 5 MHz PCLK = 4 MHz PCLK = 3 MHz PCLK = 2 MHz Baud Rate O N P %err O N P %err O N P %err O N P %err 2000 10 250 1 0 16 125 1 0 15 100 1 0 16 25 2.5 0 230400 11 2 1 1.36 7 1 2.5 0.79 13 1 1 0.16 PCLK = 1 MHz PCLK = 500 kHz Baud Rate O N P %err O N P %err 300 11 202 1.5 0.01 11 101 1.5 0.01 600 11 101 1.5 0.01 14 17 3.5 0.04 1200 14 17 3.5 0.04 7 17 3.5 0.04 1800 15 37 1 0.1 9 31 1 0.44 2000 10 50 1 0 10 25 1 0 2400 7 17 3.5 0.04 16 13 1 0.16 3600 9 31 1 0.44 9 1 15.5 0.44 4800 16 13 1 0.16 16 1 6.5 0.16 7200 9 1 15.5 0.44 10 7 1 0.79 9600 16 1 6.5 0.16 8 1 6.5 0.16 14400 10 7 1 0.79 10 1 3.5 0.79 19200 8 1 6.5 0.16 13 2 1 0.16 38400 13 2 1 0.16 13 1 1 0.16 56000 9 2 1 0.79 57600 7 1 2.5 0.79 Copyright© 2013,Texas InstrumentsIncorporated Dual/QuadUART 285 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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28 Dual Microwire/SPIInterfaces

Microwire/Plusis a synchronous serialcommunicationsprotocol,originallyimplemented in National Semiconduc-tor'sCOPS ® and HPC familiesofmicrocontrollerstomini-mize thenumber ofconnections, and thereforethecost,ofcommunicatingwithperipherals. The CP3SP33 has an Microwire/SPIinterfacemodule (MWSPI) thatcan communicate withallperipherals thatconformtoMicrowire/PlusorSerialPeripheralInterface(SPI)specifications.ThisMicrowireinterface iscapableofoperatingas eithera masteror slaveand in8- or 16-bitmode. Figure101 shows a typical Microwireinterfaceappli-cation. Two modules areprovided:module 0 on theCPU APB bus and module 1 on thesharedaudioperipheral APB bus.Module 1 can be accessedby eithertheCPU orDSP, so itsinterruptand DMA requestsignals areroutedthroughtheASC module. The Microwireinterfacemodule includesthefollowingfea-tures:

• Programmable operationas a masterorslave
• Programmable shift-clockfrequency(masteronly)
• Programmable 8-or16-bitmode ofoperation
• 8-or16-bitserialI/Odatashiftregister
• Two modes ofclockingdata
• Serialclockcan be loworhighwhen idle
• 16-bitreadbuffer
• Busy bit,Read BufferFullbit,and Overrunbitforpollingand as interruptsources
• Supportsmultiplemasters
• DMA capability
• Maximum bus clockfrequencyof12 MHz runningfroma 48 MHz PCLK Clock
• Supportsverylow-endslaveswiththeSlaveReady output
• Echo back enable/disable(slaveonly) Figure28-1.MicrowireInterface

28.1 MicrowireOperation

The Microwireinterfaceallowsseveraldevicestobe connectedon one three-wiresystem.At any given time,one of these devicesoperatesas the master whileallotherdevicesoperateas slaves.The Microwireinterfaceallowsthedevicetooperateeitheras a masterorslavetransferring8-bitsor16-bitsof data.

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www.ti.com SNOSCW5 –MAY 2013 The master devicesuppliesthe synchronousclock(MSK) forthe serialinterfaceand initiatesthe data transfer.The slavedevicesrespondby sending(orreceiving)therequesteddata.Each slavedeviceuses themaster’s clockforseriallyshiftingdataout(orin),whilethemastershiftsthedatain(orout). The three-wiresystem includes:the serialdata in signal(MDIDO formaster mode, MDODI forslave mode),theserialdataoutsignal(MDODI formastermode, MDIDO forslavemode),and theserialclock (MSK). Inslavemode, an optionalfourthsignal(MWCS) may be used toenabletheslavetransmit.At any given time,onlyone slavecan respondtothemaster.Each slavedevicehas itsown chipselectsignal(MWCS) forthispurpose. Figure28-2shows a blockdiagramoftheMicrowireserialinterfaceinthedevice.

28.1.1 Shifting

The Microwireinterfaceisa fullduplextransmitter/receiver.A 16-bitshiftregister,whichcan be splitintoa lowand highbyte,isused forbothtransmittingand receiving.In8-bitmode, onlythelower8-bitsareused to transferdata.The transmitdata isshiftedout throughMDODIn pin (mastermode) or MDIDOn pin (slavemode),startingwiththeMSB. At thesame time,thereceivedataisshiftedinthroughMDIDOn pin (mastermode) orMDODIn pin(slavemode),alsostartingwiththeMSB first. The shiftinand shiftoutare controlledby theMSK clock.Ineach clockcycleofMSK, one bitofdatais transmitted/received.The 16-bitshiftregisteris accessibleas the MWnDAT register.Reading the MWnDAT registerreturnsthevalueinthereceivebuffer.WritingtotheMWnDAT registerupdatesthe16- bittransmitbuffer. Figure28-2.MicrowireBlock Diagram Copyright© 2013,Texas InstrumentsIncorporated DualMicrowire/SPIInterfaces 287 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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28.1.2 Reading

The Microwireinterfaceimplementsa doublebufferon read.As illustratedinFigure28-2,thedoubleread bufferconsistsofthe16-bitshiftregisterand a readbuffer. The 16-bitshiftregisterloadsthereadbufferwithnew datawhen thedatatransfersequence iscompleted and previousdataintheread bufferhas been read.Inmastermode, an overrunerroroccurswhen the readbufferisfull,the16-bitshiftregisterisfulland a new datatransfersequence starts. When 8-bitmode isselected,thelowerbyteoftheshiftregisterisloadedintothelowerbyteoftheread bufferand thereadbuffer’s higherbyteremainsunchanged. The RBF bitindicatesifthe MWnDAT registerholdsvaliddata.The OVR bitindicatesthatan overrun conditionhas occurred.

28.1.3 Writing

The BSY bitindicateswhethertheMWnDAT registercan be written.AllwriteoperationstotheMWnDAT registerupdate the shiftregisterwhilethe data containedinthe read bufferisnot affected.Undefined resultswilloccuriftheMWnDAT registeriswrittenwhiletheBSY bitisset.

28.1.4 ClockingModes

Two clockingmodes aresupported:

• Normal mode — outputdatatransmittedon theMDODIn pin(mastermode) or theMDIDOn pin(slave mode) isclockedouton thefallingedge oftheshiftclockMSKn. Inputdata,whichisreceivedviathe MDIDOn pin(mastermode) ortheMDODIn pin(slavemode),issampled on therisingedge ofMSKn.
• Alternatemode — outputdata isshiftedout on the risingedge of MSKn on the MDODIn pin(master mode) or MDIDOn pin(slavemode). Inputdata,which isreceivedviaMDIDOn pin(mastermode) or MDODIn pin(slavemode),issampled on thefallingedge ofMSKn. The clockingmode isselectedwiththe SCM bit.The SCIDL bitallowsselectionof the valueof MSKn when itisidle(when thereisno databeingtransferred).Inmastermode, theMSKn clockfrequencycan be programmed intheSCDV fieldoftheMWnCTL1 register.Figure28-3,Figure28-4,Figure28-5,and Figure28-6show thedatatransfertimingforthenormaland thealternatemodes withtheSCIDL bitclear and set. Note thatwhen dataisshiftedouton MDODIn (mastermode) or MDIDOn (slavemode) on theleading edge oftheMSKn clock,bit15 (16-bitmode) isshiftedouton thesecond leadingedge oftheMSKn clock. When dataare shiftedouton MDODIn (mastermode) or MDIDOn (slavemode) on thetrailingedge of MSKn, bit15 (16-bitmode) isshiftedouton thefirsttrailingedge ofMSKn.

28.2 Master Mode

In master mode, the MSKn pin is an outputforthe shiftclock,MSKn. When data is writtento the MWnDAT register,eightorsixteenMSKn clocks,dependingon themode selected,aregeneratedtoshift the8 or16 bitsofdata,and thenMSKn goes idleagain.The MSKn idlestatecan be eitherhighorlow, dependingon theSCIDL bit.

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(LSB)Bit 1MSB - 2MSB - 1 MSKn End of Transfer Data Out MSB Bit 0 (LSB)Bit 1MSB - 2MSB - 1Data In MSB Sample Point Shift Out DS350 Bit 0 (LSB)Bit 1MSB - 2MSB - 1 MSKn End of Transfer Data Out MSB Bit 0 (LSB)Bit 1MSB - 2MSB - 1Data In MSB Sample Point Shift Out DS349 Bit 0 (LSB)Bit 1MSB - 2MSB - 1 MSKn End of Transfer Sample Point Shift Out Data Out MSB Bit 0 (LSB)Bit 1MSB - 2MSB - 1Data In MSB DS348 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure28-3.Normal Mode (SCIDL = 0) Figure28-4.Normal Mode (SCIDL = 1) Figure28-5.AlternateMode (SCIDL = 0) Copyright© 2013,Texas InstrumentsIncorporated DualMicrowire/SPIInterfaces 289 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

(LSB)Bit 1MSB - 2MSB - 1 MSKn End of Transfer Sample Point Shift Out Data Out MSB Bit 0 (LSB)Bit 1MSB - 2MSB - 1Data In MSB DS351 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure28-6.AlternateMode (SCIDL = 1)

28.3 SlaveMode

Inslavemode, theMSKn pinisan inputfortheshiftclockMSKn. MDIDOn isputinTRI-STATE mode when MWCSn isinactive.Data transferisenabledwhen MWCSn isactive. The slavestartsdrivingMDIDOn when MWCSn isactive.The most significantbit(lowerbytein8-bitmode orupperbytein16-bitmode) isoutputontotheMDIDOn pinfirst.Aftereightorsixteenclocks(depending on theselectedmode),thedatatransferiscompleted. Ifa new shiftprocessstartsbeforeMWnDAT was written,i.e.,whileMWnDAT does notcontainany valid data,and theECHO bitisset,thedatareceivedfrom MDODIn istransmittedon MDIDOn inadditionto beingshiftedtoMWnDAT. IftheECHO bitisclear,thedatatransmittedon MDIDOn isthedataheldinthe MWnDAT register,regardlessofitsvalidity.The mastermay negatetheMWCSn signaltosynchronizethe bitcountbetween themasterand theslave.Iftheslaveistheonlyslaveinthesystem,MWCSn can be tiedtoground.

28.4 InterruptSupport

Interruptsmay be enabledforany oftheconditionsshown inTable28-1. Table28-1.MicrowireInterruptTriggerCondition InterruptEnable BitStatusBitintheCondition inthe DescriptionMWnSTAT Register MWnCTRL1 Register Not Busy BSY EIW The shiftregisterisreadyforthenextdatatransfersequence. Read BufferFull RBF EIR The readbufferisfulland waitingtobe unloaded. Overrun OVF EIO A new datatransfersequence startedwhileboththeshiftregister and thereadbufferwere full.

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OVR = 1 EIO RBF = 1 EIR BSY = 0 EIW DS073 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure28-7illustratestheinterruptgenerationlogicofthismodule. Figure28-7.MWSPI Interrupts Module 0 uses IRQ29,and module 1 uses IRQ10. Because theinterruptrequestformodule 1 can be handledby eithertheCPU orDSP interruptcontrollers, theinterruptrequestispassed throughtheAudio Subsystem Controller(ASC),which isprogrammed to routeittotheinterruptcontroller.To use theinterrupt,itmust be enabledatthreelevels:

• Microwiremodule— theinterruptmust be enabledintheMW1CTL1 register.
• ASC module— theinterruptisassignedtoASC interruptchannel0,so bit0 intheASCINTSEL register must be cleartoselecttheCPU interruptcontrollerorsettoselecttheDSP interruptcontroller.
• Interruptcontroller— the interruptrequestmust be enabled in the interruptcontroller.For the CPU interruptcontroller,thisisinterruptrequestIRQ10.

28.5 DMA Support

The Microwiremodule may be operatedwitheitherone or two DMA channels.Two DMA channelsare requiredforprocessor-independentfull-duplexoperation.Both receiveand transmitDMA can be enabled individually.IftransmitDMA isenabled(EDW = 1),a DMA requestisassertedeverytimetheBSY flagis cleared.EnablingreceiveDMA (EDR = 1)assertsa DMA requesteverytimetheReceiveBufferFullflag (RBF) isset.The Enable Interrupton Read (EIR)bitmust be clearwhen theEDR bitissettoavoidan interruptrequestwhileusingreceiveDMA. The EnableInterrupton Write(EIW)bitmust be clearwhen the EDW bitisset.However,a dataoverrunconditionmay occur,so theEnableInterrupton Overrun(EIO)bit shouldbe set. Module 0 uses DMA requests33 (read)and 34 (write),and module 1 uses DMA requests18 (read)and 19 (write). Because module 1 DMA requestscan be handledby eithertheCPU or DSP DMA controllers,theDMA requestsarepassed throughtheAudioSubsystem Controller(ASC),whichisprogrammed toroutethem totheDMA controller.To use theDMA requests,theymust be enabledatthreelevels:

• Microwiremodule— theDMA requestsmust be enabledusingtheEDR and EDW bitsintheMW1CTL2 register.
• ASC module— theDMA requestsareassignedtoASC DMA channels18 (read)and 19 (write).These channelsarecontrolledby bits2 and 3 intheASCDMASEL1 register.The bitsmust be cleartoselect the CPU DMA controlleror set to selectthe DSP DMA controller.Ifthe DSP DMA controlleris selected,theDSP DMA channelmust be enabledintheASCDDMASELn registers.
• DMA controller— the DMA requestsmust be enabled in the DMA controller.For the CPU DMA controller,theseareDMA requests18 (read)and 19 (write). Copyright© 2013,Texas InstrumentsIncorporated DualMicrowire/SPIInterfaces 291 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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28.6 FreezeMode

WhileFreezemode isasserted,themodule willexhibitthefollowingbehavior: In master mode, the transactionwillbe stalledat the bitthatwhich isbeingcurrentlytransferred.The MSKn and MDOD- Insignalswillretainthecurrentlevel.Once Freeze mode isde-asserted,themodule willcompletethecurrenttransaction. Inslavemode, themodule willcontinuetooperatenormally.Data willbe shiftedattherateoftheMSK clock. Reading theMWnDAT registerwillnotcause theRBF flagtobe cleared,and itwillnotupdatetheread bufferifnew dataisreadyintotheshiftregister.

28.7 MicrowireInterfaceRegisters

SoftwareinteractswiththeMicrowireinterfaceby accessingtheMicrowireregisters.There arethreesuch registers: Table28-2.MicrowireInterfaceRegisters NAME ADDRESS DESCRIPTION MW0CTL1 FF 8404h MicrowireModule 0 ControlRegister1 MW1CTL1 FF 5804h MicrowireModule 1 ControlRegister1 MW0CTL2 FF 840Ah MicrowireModule 0 ControlRegister2 MW1CTL2 FF 580Ah MicrowireModule 1 ControlRegister2 MW0STAT FF 8408h MicrowireModule 0 StatusRegister MW1STAT FF 5808h MicrowireModule 1 StatusRegister MW0DAT FF 8400h MicrowireModule 0 Data Register MW1DAT FF 5800h MicrowireModule 1 Data Register

28.7.1 MicrowireModule n ControlRegister1 (MWnCTL1)

The MWnCTL1 registersare 16-bit,read/writeregistersused tocontroltheMicrowiremodule.To avoid clockglitches,theMWEN bitmust be clearwhilechangingthestatesofany otherbitsintheregister.At reset,allnon-reservedbitsarecleared.The registerformatisshown below. 15 9 8 7 6 5 4 3 2 1 0 SCDV SCIDL SCM EIW EIR EIO ECHO MOD MNS MWEN MWEN MWEN The MicrowireEnablebitcontrolswhethertheMicrowireinterfacemodule isenabled. 0 – Microwiremodule disabled. 1 – Microwiremodule enabled. Clearingthisbitdisablesthemodule,clearsthestatusbitsintheMicrowirestatusregister(the BSY, RBF, and OVR bitsinMWnSTAT), and placestheMicrowireinterfacepinsinthestates describedbelow. PIN STATE WHEN DISABLED MSKn Master– SCIDL Bit Slave– Input MDIDOn Master– Input Slave– TRI-STATE MDODIn Master– Known value Slave– Input

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www.ti.com SNOSCW5 –MAY 2013 MNS The Master/SlaveSelectbitcontrolswhethertheCP3SP33 isa masterorslave.When clear, thedeviceoperatesas a slave.When set,thedeviceoperatesas themaster. 0 – CP3SP33 isslave. 1 – CP3SP33 ismaster. MOD The Mode Selectbitcontrolswhether8-or16-bitmode isused.When clear,thedevice operatesin8-bitmode. When set,thedeviceoperatesin16-bitmode. Thisbitmust onlybe changed when themodule isdisabledoridle(MWnSTAT.BSY = 0). 0 – 8-bitmode. 1 – 16-bitmode. ECHO The Echo Back bitcontrolswhethertheecho back functionisenabledinslavemode. Thisbit must be writtenonlywhen theMicrowireinterfaceisidle(MWnSTAT.BSY=0). The ECHO bitis ignoredinmastermode. The MWnDAT registerisvalidfromthetimetheregisterhas been writtenuntiltheend ofthetransfer.Intheecho back mode, MDODIn istransmitted(echoed back)on MDIDOn iftheMWnDAT registerdoes notcontainany validdata.Withtheecho back functiondisabled,thedataheldintheMWnDAT registeristransmittedon MDIDOn, whetheror notthedataisvalid. 0 – Echo back disabled. 1 – Echo back enabled. EIO The EnableInterrupton Overrunbitenablesordisablestheoverruninterrupt.When set,an interruptisassertedwhen theReceiveOverrunbit(MWnSTAT.OVR) isset.Otherwise,no interruptisassertedwhen an overrunoccurs.Thisbitmust onlybe enabledinmastermode. 0 – Disableoverruninterrupts. 1 – Enableoverruninterrupts. EIR The EnableInterruptforRead bitcontrolswhetheran interruptisassertedwhen thereadbuffer becomes full.When set,an interruptisassertedwhen theRead BufferFullbit(MWnSTAT.RBF) isset.Otherwise,no interruptisassertedwhen thereadbufferisfull. 0 – No readbufferfullinterrupt. 1 – Interruptwhen readbufferbecomes full. EIW The EnableInterruptforWritebitcontrolswhetheran interruptisassertedwhen theBusy bit (MWnSTAT.BSY) iscleared,whichindicatesthata datatransfersequence has been completed and thereadbufferisreadytoreceivethenew data.Otherwise,no interruptisassertedwhen theBusy bitiscleared. 0 – No interrupton datatransfercomplete. 1 – Interrupton datatransfercomplete. SCM The ShiftClockMode bitselectsbetween thenormalclockingmode and thealternateclocking mode. Inthenormalmode, theoutputdataisclockedouton thefallingedge ofMSKn and the inputdataissampled on therisingedge ofMSKn. Inthealternatemode, theoutputdatais clockedouton therisingedge ofMSKn and theinputdataissampled on thefallingedge of MSKn. 0 – Normal clockingmode. 1 – Alternateclockingmode. SCIDL The ShiftClockIdlebitcontrolsthevalueoftheMSKn outputwhen theMicrowiremodule isidle. Thisbitmust be changed onlywhen theMicrowiremodule isdisabled(MEN = 0)orwhen no bus transactionisinprogress(MWnSTAT.BSY = 0). 0 – MSKn islowwhen idle. 1 – MSKn ishighwhen idle SCDV The ShiftClockDividerValuefieldspecifiesthedivisorused forgeneratingtheMSKn shiftclock fromthePCLK Clock.The divisoris2 × (SCDV6:0 + 1).Validvaluesare0000001b to 1111111b,so thedivisionratiomay rangefrom4 to256.Thisfieldisignoredinslavemode (MWnCTL1.MNS = 0). Copyright© 2013,Texas InstrumentsIncorporated DualMicrowire/SPIInterfaces 293 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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28.7.2 MicrowireModule n ControlRegister2 (MWnCTL2)

The MWnCTL2 registersare 16-bit,read/writeregistersused toenableDMA requests.At reset,allnon- reservedbitsarecleared.The registerformatisshown below. 7 2M 1 0 Reserved EDW EDR EDR The EnableDMA Read bitcontrolswhethera DMA requestisenabledwhen theRBF bitinthe MWnSTAT registerisset. 0 – DMA requestdisabled. 1 – DMA requestenabled. EDW The EnableDMA Read bitcontrolswhethera DMA requestisenabledwhen theBSY bitinthe MWnSTAT registeriscleared. 0 – DMA requestdisabled. 1 – DMA requestenabled.

28.7.3 MicrowireModule n StatusRegister(MWnSTAT)

The MWnSTAT registersare 16-bit,read-onlyregistersthatshows the currentstatusof the Microwire interfacemodule.Atreset,allnon-reservedbitsareclear.The registerformatisshown below. 15 3 2 1 0 Reserved OVR RBF BSY BSY The Busy bit,when set,indicatesthattheMicrowireshiftregisterisbusy.Inmastermode, the BSY bitissetwhen theMWnDAT registeriswritten.Inslavemode, thebitisseton thefirst leadingedge ofMSKn when MWCSn isassertedorwhen theMWnDAT registeriswritten, whicheveroccursfirst.Inbothmasterand slavemodes, thisbitisclearedwhen theMicrowire datatransfersequence iscompletedand thereadbufferisreadytoreceivethenew data;in otherwords,when thepreviousdataheldinthereadbufferhas alreadybeen read.Ifthe previousdatainthereadbufferhas notbeen readand new datahas been receivedintotheshift register,theBSY bitwillnotbe cleared,as thetransfercouldnotbe completedbecause the contentsoftheshiftregistercouldnotbe transferredintothereadbuffer. 0 – Shiftregisterisnotbusy. 1 – Shiftregisterisbusy. RBF The Read BufferFullbit,when set,indicatesthatthereadbufferisfulland readytobe readby software.Itissetwhen theshiftregisterloadsthereadbuffer,whichoccursupon completionofa transfersequence ifthereadbufferisempty.The RBF bitisupdatedwhen theMWnDAT register isread.Atthattime,theRBF bitisclearediftheshiftregisterdoes notcontainany new data(in otherwords,theshiftregisterisnotreceivingdataorhas notyetreceiveda fullbyteofdata).The RBF bitremainssetiftheshiftregisteralreadyholdsnew dataatthetimethatMWnDAT isread. Inthatcase,MWnDAT isimmediatelyreloadedwiththenew dataand isreadytobe readby software. 0 – Read bufferisnotfull. 1 – Read bufferisfull. OVR The ReceiveOverrunbit,when setinmastermode, indicatesthata receiveoverrunhas occurred.An overrunoccurswhen thereadbufferisfull,the8-bitshiftregisterisfull,and a new datatransfersequence starts.Thisbitisundefinedinslavemode. The OVR bit,once set, remainssetuntilclearedby software.Softwareclearsthisbitby writinga 1 toitsbitposition. Writinga 0 tothisbitpositionhas no effect.No otherbitsintheMWnSTAT registerareaffected by writestotheregister. 0 – No receiveoverrunhas occurred. 1 – Receiveoverrunhas occurred.

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(High Byte) Data In Write Data Out MOD MWnDA T Shift Register (Low Byte) Read Buffer (High Byte) Read Buffer (Low Byte) Read DS442 CP3SP33 www.ti.com SNOSCW5 –MAY 2013

28.7.4 MicrowireModule n Data Register(MWnDAT)

The MWnDAT registersare 16-bit,read/writeregistersused to transmitand receivedata throughthe MDODIn and MDIDOn pins. 7 0 MWDAT Figure28-8shows thehardwarestructureoftheregister. Figure28-8.MWnDAT Register 29 Dual ACCESS.bus Interfaces The ACCESS.bus interfacemodules (ACB) providea two- wire serialinterfacecompatiblewiththe ACCESS.bus physicallayer.Itpermitseasy interfacingto a wide range of low-costmemories and I/O devices,including:EEPROMs, RAMs, timers,A/D converters,D/A converters,clockchips,and peripheral drivers.ItiscompatiblewithIntel’s SMBus and Philips’I2C bus.The ACB modules can be configuredas a bus masteror slave,and can maintainbidirectionalcommunicationswithbothmultiplemasterand slave devices Two modules areprovided,module 0 on theCPU APB bus and module 1 on thesharedaudioperipheral APB bus.Module 1 can be accessedby eithertheCPU orDSP, so itsinterruptand DMA requestsignals areroutedthroughtheASC module. Thissectionpresentsan overviewofthebus protocol,and itsimplementationby theACB module.

• ACCESS.bus masterand slave
• Supportspollingand interrupt-controlledoperation
• Generatea wake-up signalon detectionofa StartCondition,whileinpower-down mode
• Optionalinternalpullupon SDA and SCL pins
• Interruptand DMA capability
• Up to400 kHz bus clockfrequency(Fast-mode) 29.1 ACCESS.bus ProtocolOverview The ACCESS.bus protocoluses a two-wireinterfaceforbi-directionalcommunicationbetween the devicesconnectedto the bus.The two interfacesignalsare the SerialData Line(SDA) and the Serial ClockLine(SCL).These signalsshouldbe connectedtothepositivesupply,throughpullupresistors,to keep thesignalshighwhen thebus isidle. The ACCESS.bus protocolsupportsmultiplemaster and slavetransmittersand receivers.Each bus devicehas a uniqueaddressand can operateas a transmitterora receiver(thoughsome peripheralsare onlyreceivers). Copyright© 2013,Texas InstrumentsIncorporated DualACCESS.bus Interfaces 295 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

S SCL P DS076 SDA Data Line Stable: Data Valid Change of Data Allowed SCL DS075 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Duringdata transactions,the master deviceinitiatesthe transaction,generatesthe clocksignal,and terminatesthetransaction.For example,when theACB initiatesa datatransactionwithan ACCESS.bus peripheral,theACB becomes themaster.When theperipheralrespondsand transmitsdatatotheACB, theirmaster/slave(datatransactioninitiatorand clockgenerator)relationshipisunchanged,even though theirtransmitter/receiverfunctionsarereversed.

29.1.1 Data Transactions

One databitistransferredduringeach clockperiod.Data issampled duringthehighphase oftheserial clock (SCL). Consequently,throughout the clock high phase, the data must remain stable (see Figure29-1).Any change on the SDA signalduringthe highphase of the SCL clockand inthe middleofa transactionabortsthecurrenttransaction.New datamust be drivenduringthelow phase of theSCL clock.Thisprotocolpermitsa singledatalinetotransferbothcommand/controlinformationand datausingthesynchronousserialclock. Figure29-1.BitTransfer Each data transactioniscomposed of a StartCondition,a number of byte transfers(programmed by software),and a Stop Conditionto terminatethe transaction.Each byte istransferredwiththe most significantbitfirst,and aftereach byte,an Acknowledgesignalmust follow. At each clockcycle,theslavecan stallthemasterwhileithandlesthepreviousdata,or preparesnew data.Thiscan be performedforeach bittransferredoron a byteboundaryby theslaveholdingSCL low toextendtheclock-lowperiod.Typically,slavesextendthefirstclockcycleofa transferifa bytereadhas not yetbeen stored,or ifthe nextbyteto be transmittedisnot yetready.Some microcontrollerswith limitedhardware supportforACCESS.bus extend the access aftereach bit,to allowsoftwaretime to handlethisbit. 29.1.1.1Startand Stop The ACCESS.bus mastergeneratesStartand Stop Conditions(controlcodes).Aftera StartConditionis generated,thebus isconsideredbusy and itretainsthisstatusuntila certaintimeaftera Stop Condition isgenerated.A high-to-lowtransitionofthedataline(SDA) whiletheclock(SCL) ishighindicatesa Start Condition.A low-to-hightransitionoftheSDA linewhiletheSCL ishighindicatesa Stop Condition(see Figure29-2). Figure29-2.Startand Stop Conditions 296 DualACCESS.bus Interfaces Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

S Start Condition DS078 SDA S MSB ACK ACK Stop Condition Start Condition Clock Line Held Low by Receiver While Interrupt is Serviced Byte Complete Interrupt Within Receiver Acknowledgment Signal from Receiver SCL 2 1 2 3-873 - 6 8 9 9 P DS077 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 In additionto the firstStartCondition,a repeatedStartConditioncan be generatedinthe middleof a transaction.Thisallowsanotherdevicetobe accessed,ora change inthedirectionofthedatatransfer. 29.1.1.2Acknowledge Cycle The Acknowledge Cycle consistsof two signals:the ac- knowledge clockpulsethe master sends with each bytetransferred,and theacknowledgesignalsentby thereceivingdevice(Figure29-3). Figure29-3.ACCESS.bus Data Transaction The master generatesthe acknowledge clockpulseon the ninthclockpulseof the bytetransfer.The transmitterreleasesthe SDA line(permitsitto go high)to allowthe receiverto send the acknowledge signal.The receivermust pulldown theSDA lineduringtheacknowledgeclockpulse,which signalsthe correctreceptionofthelastdatabyte,and itsreadinesstoreceivethenextbyte.Figure29-4 illustrates theacknowledgecycle. Figure29-4.ACCESS.bus Acknowledge Cycle The master generatesan acknowledge clockpulse aftereach byte transfer.The receiversends an acknowledgesignalaftereverybytereceived.There are two exceptionstothe“acknowledgeafterevery byte”rule.

• When the master isthe receiver,itmust indicateto the transmitteran end-of-dataconditionby not- acknowledging(“negativeacknowledge”) the lastbyte clocked out of the slave.This “negative acknowledge”stillincludestheacknowledgeclockpulse(generatedby themaster),buttheSDA lineis notpulleddown.
• When the receiveris full,otherwiseoccupied,or a problem has occurred,itsends a negative acknowledgetoindicatethatitcannotacceptadditionaldatabytes. 29.1.1.3Addressing TransferFormats Each deviceon thebus has a uniqueaddress.Beforeany dataistransmitted,themastertransmitsthe addressoftheslavebeingaddressed.The slavedeviceshouldsend an acknowledgesignalon theSDA signal,once itrecognizesitsaddress. Copyright© 2013,Texas InstrumentsIncorporated DualACCESS.bus Interfaces 297 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

S Stop Condition Start Condition P 8 9 1 - 7 8 9 1 - 7 8 9 R/W DataACK ACK DS079 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com The addressisthefirstseven bitsaftera StartCondition.The directionofthedatatransfer(R/W)depends on the bitsent afterthe address (theeighthbit).A low-to-hightransitionduringa SCL high period indicatestheStopCondition,and ends thetransaction(Figure29-5). Figure29-5.A Complete ACCESS.bus Data Transaction When the addressissent,each deviceinthe system compares thisaddresswithitsown. Ifthereisa match,thedeviceconsidersitselfaddressedand sends an acknowledgesignal.Dependingupon thestate oftheR/W bit(1= read,0 = write),thedeviceactsas a transmitterora receiver. The ACCESS.bus protocolallowssendinga generalcalladdresstoallslavesconnectedtothebus.The firstbytesentspecifiesthegeneralcalladdress(00h)and thesecond bytespecifiesthemeaning ofthe generalcall(forexample,“Writeslaveaddressby softwareonly”).Those slavesthatrequirethe data acknowledgethecalland become slavereceivers;theotherslavesignorethecall. 29.1.1.4Arbitrationon theBus Arbitrationisrequiredwhen multiplemaster devicesattemptto gaincontrolof the bus simultaneously. Controlofthebus isinitiallydeterminedaccordingtoaddressbitsand clockcycle.Ifthemastersaretrying toaddressthesame bus device,datacomparisonsdeterminetheoutcome ofthisarbitration.Inmaster mode, thedeviceimmediatelyabortsa transactionifthevaluesampled on theSDA linesdiffersfromthe valuedrivenby thedevice.(ExceptionstothisruleareSDA whilereceivingdata;inthesecases thelines may be drivenlowby theslavewithoutcausingan abort.) The SCL signalismonitoredforclocksynchronizationand allowstheslavetostallthebus.The actual clockperiodwillbe theone setby themasterwiththelongestclockperiodor by theslavestallperiod. The clockhighperiodisdeterminedby themasterwiththeshortestclockhighperiod. When an abortoccursduringtheaddresstransmission,themasterthatidentifiestheconflictshouldgive up the bus,switchto slavemode, and continueto sample SDA to see ifitisbeingaddressedby the winningmasteron theACCESS.bus.

29.2 ACB FunctionalDescription

The ACB modules providesthephysicallayerforACCESS.bus-compliantserialinterfaces.The modules are configurableas eithermasteror slavedevices.As slaves,theACB modules may issuea requestto become thebus master.

29.2.1 Master Mode

An ACCESS.bus transactionstartswitha master devicerequestingbus mastership.Itsends a Start Condition,followedby the addressof the deviceitwants to access.Ifthistransactionissuccessfully completed,softwarecan assume thatthedevicehas become thebus master. Fora devicetobecome thebus master,softwareshouldperformthefollowingsteps: 1. SettheACBnCTL1.START bit,and configuretheACBnCTL1.INTEN bittothedesiredoperationmode (PollingorInterrupt).ThiscausestheACB toissuea StartConditionon theACCESS.bus, as soon as theACCESS.bus isfree(ACBnCST.BB=0). Itthenstallsthebus by holdingSCLn low. 2. Ifa bus conflictisdetected,(i.e.,some otherdevicepullsdown theSCLn signalbeforethisdevice 298 DualACCESS.bus Interfaces Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

www.ti.com SNOSCW5 –MAY 2013 does),theACBnST.BER bitisset. 3. Ifthereisno bus conflict,theACBnST.MASTER and ACBnST.SDAST bitsareset. 4. IftheACBnCTL1.INTEN bitisset,and eithertheACBnST.BER bitortheACBnST.SDAST bitisset,an interruptisasserted. 29.2.1.1Sending theAddress Byte Once thisdeviceisthe activemaster of the ACCESS.bus (ACBnST.MASTER = 1),itcan send the address on the bus. The address must not be thisdevice’s own address as specifiedin the ACBnADDR.ADDR fieldifthe ACBnAD- DR.SAEN bitis set or the ACBnADDR2.ADDR fieldifthe ACBnADDR2.SAEN bit is set. The address also must not be the global calladdress if the ACBnST.GCMTCH bitissetortheARP addressiftheACBnST.ARPMATCH bitisset. To send theaddressbyte,use thefollowingsequence: 1. Load theACBnCTL1.INTEN and ACBnCTL1.DMAEN bitsforthedesiredoperationmode. Fora receivetransactionwhere softwarewantsonlyone byteofdata,itshouldsettheACBnCTL1.ACK bit. Ifonlyan addressneeds tobe sent,settheACBnCTL1.STASTRE bit. 2. Writetheaddressbyte(7-bittargetdeviceaddress),and thedirectionbit,totheACBnSDA register. Thiscausesthemodule togeneratea transaction.Attheend ofthistransaction,theacknowledgebit receivediscopiedtotheACBnST.NEGACK bit.Duringthetransaction,theSDAn and SCLn signals arecontinuouslycheckedforconflictswithotherdevices.Ifa conflictisdetected,thetransactionis aborted,theACBnST.BER bitisset,and theACBnST.MASTER bitiscleared. Copyright© 2013,Texas InstrumentsIncorporated DualACCESS.bus Interfaces 299 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 3. IftheACBnCTL1.STASTRE bitisset,and thetransactionwas successfullycompleted(i.e.,boththe ACBnST.BER and ACBnST.NEGACK bitsarecleared),theACBnST.STASTR bitisset.Inthiscase, set,an interruptisasserted. 4. Iftherequesteddirectionistransmit,and thestarttransactionwas completedsuccessfully(i.e.,neither theACBnST.NEGACK norACBnST.BER bitisset,and no othermasterhas accessedthedevice),the ACBnST.SDAST bitissettoindicatethatthemodule iswaitingforservice. 5. Iftherequesteddirectionisreceive,thestarttransactionwas completedsuccessfully,and the ACBnCTL1.STASTRE bitisclear,themodule startsreceivingthefirstbyteautomatically. 6. Check thatboththeACBnST.BER and ACBnST.NEGACK bitsareclear.Ifeitherthe ACBnCTL1.INTEN orACBnCTL1.DMAEN bitisset,an interruptisassertedwhen eitherthe ACBnST.BER orACBnST.NEGACK bitisset. 29.2.1.2Master Transmit Afterbecoming thebus master,thedevicecan starttransmittingdataon theACCESS.bus. To transmita byteusinginterruptsorpolling,softwaremust: 1. Check thattheBER and NEGACK bitsintheACBnST registerareclearand theACBnST.SDAST bitis set.Also,iftheACBnCTL1.STASTRE bitisset,checkthattheACBnST.STASTR bitisclear. 2. Writethedatabytetobe transmittedtotheACBnSDA register. To transmita byteusingDMA, softwaremust: 1. IftheACBnCTL1.DMAEN bitwas setbeforethestarttransaction,a DMA requestisgenerated automaticallyattheend oftheaddresstransactionand each followingtransactionunlessforsome reason(e.g.,ACBCST, MATCH, orBER were set)an interruptwas asserted 2. When theACBnST.NEGACK orACBnST.BER bitsareset,an interruptisasserted,and themodule stopssendingDMA requests. When the slave responds with a negativeacknowledge,the ACBnST.NEGACK bitis set and the ACBnST.SDAST bitre-mains clear.In thiscase,ifthe ACBnCTL1.INTEN or ACBnCTL1.DMAEN bitis set,an interruptisasserted. 29.2.1.3Master Receive Afterbecoming thebus master,thedevicecan startreceivingdataon theACCESS.bus. To receivea byte usinginterruptsorpolling,softwaremust: 1. Check thattheACBnST.SDAST bitissetand theACBnST.BER bitisclear.Also,ifthe ACBnCTL1.STASTRE bitisset,checkthattheACBnST.STASTR bitisclear. 2. SettheACBnCTL1.ACK bit,ifthenextbyteisthelastbytethatshouldbe read.Thiscausesa negativeacknowledgetobe sent. 3. Read thedatabytefromtheACBnSDA register. To receivea byteusingDMA, softwaremust: 1. The DMA requestbecomes activeafterthemodule receivesa byteofdata.Ifan erroroccursduring thetransaction(e.g.,ACBCST.NMATCH orACBST.BER isset),an interruptisassertedand theDMA operationisstalled. 2. Beforereceivingthelastbyteofdata,settheACBnCTL1.ACK bit.Thisshouldbe done by programmingtheDMA tointerrupttheCPU one bytebeforetheend ofthetransmissionand lettingthe softwaresettheACBnCTL1.ACK bit. 300 DualACCESS.bus Interfaces Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

www.ti.com SNOSCW5 –MAY 2013 29.2.1.4Master Stop A Stop Conditionmay be issuedonlywhen thisdeviceistheactivebus master(ACBnST.MASTRER = 1). To end a transaction,set the ACBnCTL1.STOP bitbefore clearingthe currentstallbit(i.e.,the ACBnST.SDAST, ACBnST.NEGACK, or ACBnST.STASTR bit).Thiscauses themodule tosend a Stop Conditionimmediately,and cleartheACBnCTL1.STOP bit. 29.2.1.5Master Bus Stall The ACB module can stallthe ACCESS.bus between trans-ferswhilewaitingforthe APB bus master (CPU, DSP, or DMA controller)response.The ACCESS.bus isstalledby holdingthe SCLn signallow aftertheacknowledgecycle.Note thatthisisinterpretedas thebeginningofthefollowingbus operation. Softwaremust make surethatthenextoperationispreparedbeforethebitthatcauses thebus stallis cleared. The bitsthatcan cause a stallinmastermode are:

• Negativeacknowledgeaftersendinga byte(ACBnST.NEGACK = 1).
• ACBnST.SDAST bitisset.
• IftheACBnCTL1.STASTRE bitisset,aftera successfulstart(ACBnST.STASTR = 1). 29.2.1.6Repeated Start A repeatedstartisperformedwhen thisdeviceisalreadythebus master(ACBnST.MASTER = 1).Inthis case,the ACCESS.bus isstalledand the ACB waitsforsoftwareinterventionto handlethe condition: negativeacknowledge(ACBnST.NEGACK = 1),empty buffer(ACBnST.SDAST = 1),or a stop-after-start (ACBnST.STASTR = 1). Fora repeatedstart: 1. SettheACBnCTL1.START bit. 2. Inmasterreceivemode, readthelastdataitemfromtheACBnSDA register. 3. Followtheaddresssend sequence,as describedin“SendingtheAddressByte”on page 225 4. IftheACB was waitingforhandlingdue toACBnST.STASTR = 1,clearitonlyafterwritingthe requestedaddressand directiontotheACBnSDA register. 29.2.1.7Master ErrorDetections The ACB detectsillegalStartorStop Conditions(i.e.,a StartorStop Conditionwithinthedatatransferor theacknowledgecycle)and a conflicton thedatalinesoftheACCESS.bus. Ifan illegalactionisdetected, theBER bitisset,and theMASTER mode isexited(theMASTER bitiscleared). 29.2.1.8Bus IdleErrorRecovery When a requesttobecome theactivebus masterora restartoperationfails,theACBnST.BER bitissetto indicatetheerror.Insome cases,boththisdeviceand theotherdevicemay identifythefailureand leave thebus idle.Inthiscase,thestartsequence may notbe completedand theACCESS.bus may remain deadlocked. To recoverfromdeadlock,use thefollowingsequence: 1. CleartheACBnST.BER and ACBnCST.BB bits. 2. Waitfora timeoutperiodtocheckthatthereisno otheractivemasteron thebus (i.e.,the ACBnCST.BB bitremainsclear). 3. Disable,and re-enabletheACB toputitinthenon-ad-dressedslavemode. 4. Atthispoint,some oftheslavesmay notidentifythebus error.To recover,theACB becomes thebus masterby issuinga StartConditionand sends an addressfield.Then,itissuesa StopConditionto synchronizealltheslaves. Copyright© 2013,Texas InstrumentsIncorporated DualACCESS.bus Interfaces 301 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com

29.2.2 SlaveNode

A slavedevicewaitsinIdlemode fora mastertoinitiatea bus transaction.Whenever theACB isenabled witha clearACBnST.MASTER bit,itactsas a slavedevice. Once a StartConditionon thebus isdetected,thisdevicecheckswhethertheaddresssentby thecurrent mastermatches either:

• ACBnADDR.ADDR, iftheACBnADDR.SAEN bitisset.
• ACBnADDR2.ADDR, iftheACBnADDR2.SAEN bitisset.
• The generalcalladdress,iftheACBnCTL1.GCM bitisset.
• The globalARP address,iftheACBnCTL3.ARPMEN bitisset. Thismatch ischecked even when theACBnST.MASTER bitisset.Ifa bus conflict(onSDAn orSCLn) is detected,theACBnST.BER bitisset,theACBnST.MASTER bitiscleared,and thisdevicecontinuesto search the receivedmessage fora match. Ifan address match, ARP match, or a globalmatch, is detected: 1. Thisdeviceassertsitsdatapinduringtheacknowledgecycle. 2. The ACBnCST.MATCH, ACBnCST.MATCHAF (orACBnCST.GCMTCH ifitisa globalcalladdress match,orACBnCST.ARPMATCH ifitisan ARP address),and ACBnST.NMATCH intheACBnCST settoindicatethatthebufferisempty. 3. IftheACBnCTL1.INTEN bitisset,an interruptisassertedifboththeINTEN and NMINTE bitsinthe ACBnCTL1 registerareset. 4. SoftwarethenreadstheACBnST.XMIT bittoidentifythedirectionrequestedby themasterdevice.It clearstheACBnST.NMATCH bitso futurebytetransfersareidentifiedas databytes. 29.2.2.1SlaveReceive and Transmit Slave Receive and Transmitare performedaftera match isdetectedand the data transferdirectionis identified.Aftera bytetransfer,theACB extendstheacknowledgeclockuntilsoftwarereadsorwritesthe ACBnSDA register.The receiveand transmitsequence areidenticaltothoseused inthemasterroutine. 29.2.2.2SlaveBus Stall When operatingas a slave,thisdevicestallsthe ACCESS.bus by extendingthe firstclockcycleof a transactioninthefollowingcases: 1. The ACBnST.SDAST bitisset. 2. The ACBnST.NMATCH, and ACBnCTL1.NMINTE bitsareset. 29.2.2.3SlaveErrorDetections The ACB detectsillegalStartand Stop Conditionson the ACCESS.bus (i.e.,a Startor Stop Condition withinthedatatransferortheacknowledgecycle).When an illegalStartorStop Conditionisdetected,the BER bitissetand theMATCH and GMATCH bitsarecleared,causingthemodule tobe an unaddressed slave. 29.2.2.4Power Down When thisdeviceisinPower Save,Idle,orHaltmode, theACB module isnotactivebutretainsitsstatus. Ifthe ACB isenabled(ACBnCTL2.ENABLE = 1) on detectionof a StartCondition,a wake-up signalis issuedtotheMIWU module.Use thissignaltoswitchthisdevicetoActivemode. The ACB module cannotcheck theaddressbytefora match followingthestartconditionthatcaused the wake-up eventforthisdevice.The ACB respondswitha negativeacknowledge,and thedeviceshould resendboththeStartConditionand theaddressafterthisdevicehas had timetowake up. 302 DualACCESS.bus Interfaces Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

www.ti.com SNOSCW5 –MAY 2013 Check thatthe ACBnCST.BUSY bitisinactivebeforeenteringPower Save, Idle,or Haltmode. This assuresthatthedevicedoes notacknowledgean addresssentand stoprespondinglater.

29.2.3 SDAn nand SCLn Pin Configuration

The SDA and SCL pinsare drivenas open-drainsignals.Internalpullupsmay be enabledforeitherpin. Formore information,see theI/Oconfigurationsection.

29.2.4 ACB Clock Frequency Configuration

The ACB module permitssoftwareto selectthe frequencyused forthe ACCESS.bus clock.The clock periodissetby theACBCTL2.SCLFRQ6:0 and ACBCTL3.SCLFRQ8:7 fields.Together,theyforma 9-bit valuethatspecifiestheSCL clockperiod.Thisclocklow periodmay be extendedby stallperiodsinitiated by theACB module or by anotherACCESS.bus device.Incase ofa conflictwithanotherbus master,a shorterclockhighperiodmay be forcedby theotherbus masteruntiltheconflictisresolved.

29.3 InterruptSupport

ACB module 0 uses IRQ23,and module 1 uses IRQ11. Because theinterruptrequestformodule 1 can be handledby eithertheCPU orDSP interruptcontrollers, theinterruptrequestispassed throughtheAudio Subsystem Controller(ASC),which isprogrammed to routeittotheinterruptcontroller.To use theinterrupt,itmust be enabledatthreelevels:

• ACB module— theinterruptmust be enabledintheACBnCTL1 register.
• ASC module— theinterruptisassignedtoASC interruptchannel1,so bit1 intheASCINTSEL register must be cleartoselecttheCPU interruptcontrollerorsettoselecttheDSP interruptcontroller.
• Interruptcontroller— the interruptrequestmust be enabled in the interruptcontroller.For the CPU interruptcontroller,thisisinterruptrequestIRQ11.

29.4 SMA Support

ACB module 0 uses DMA request35,and module 1 uses DMA request20. Because themodule 1 DMA requestcan be handledby eithertheCPU orDSP DMA controllers,theDMA requestispassed throughtheAudioSubsystem Controller(ASC),whichmust be programmed torouteit totheDMA controller. To use theDMA request,itmust be enabledatthreelevels:

• ACB module— theDMA requestmust be enabled.
• ASC module— theDMA requestisassignedtoASC DMA channel20.Thischanneliscontrolledby bit 4 inthe ASCDMASEL1 register.The bitmust be clearto selectthe CPU DMA controlleror setto selecttheDSP DMA controller.IftheDSP DMA controllerisselected,theDSP DMA channelmust be enabledintheASCDDMASELn registers.
• DMA controller— the DMA requestmust be enabled in the DMA controller.For the CPU DMA controller,thisisDMA request20. 29.5 ACCESS.bus InterfaceRegisters The ACCESS.bus interfaceuses theregisterslistedinTable29-1. Table29-1.ACCESS.bus InterfaceRegisters NAME ADDRESS DESCRIPTION ACB0SDA FF 8000h ACB0 SerialData Register ACB1SDA FF 5400h ACB1 SerialData Register ACB0ST FF 8004h ACB0 StatusRegister ACB1ST FF 5404h ACB1 StatusRegister Copyright© 2013,Texas InstrumentsIncorporated DualACCESS.bus Interfaces 303 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table29-1.ACCESS.bus InterfaceRegisters(continued) NAME ADDRESS DESCRIPTION ACB0CST FF 8008h ACB0 ControlStatusRegister ACB1CST FF 5408h ACB1 ControlStatusRegister ACB0CTL1 FF 800Ch ACB0 ControlRegister1 ACB1CTL1 FF 540Ch ACB1 ControlRegister1 ACB0CTL2 FF 8014h ACB0 ControlRegister2 ACB1CTL2 FF 5414h ACB1 ControlRegister2 ACB0CTL3 FF 801Ch ACB0 ControlRegister3 ACB1CTL3 FF 541Ch ACB1 ControlRegister3 ACB0ADDR1 FF 8010h ACB0 Own AddressRegister1 ACB1ADDR1 FF 5410h ACB1 Own AddressRegister1 ACB0ADDR2 FF 8018h ACB0 Own AddressRegister2 ACB1ADDR2 FF 5418h ACB1 Own AddressRegister2

29.5.1 ACBn SerialData Register(ACBnSDA)

The ACBnSDA registersare 8-bit,read/writeshiftregistersused totransmitand receivedata.The most significantbitis transmitted(received)firstand the leastsignificantbitis transmitted(received)last. Reading orwritingtheACBnSDA registersisallowedwhen ACBnST.SDAST isset;orforrepeatedstarts aftersettingthe START bit.An attemptto access the registerin othercases produces unpredictable results. 7 0 DATA

29.5.2 ACBn StatusRegister(ACBnST)

The ACBnST registersare 8-bit,read/writeregistersthatindicatethe ACB status.The NMATCH, STASTR, NEGACK, BER, and SLVSTP bitsmay be clearedby writing1 tothem.Writing0 has no effect on thesebits.Followingreset,Idlemode, Haltmode, and disablingthemodule,theseregistersareclear. 7 6 5 4 3 2 1 0 SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT XMIT The DirectionBitbitissetwhen theACB module iscurrentlyinmaster/slavetransmitmode. Otherwiseitiscleared. 0 – Receivemode. 1 – Transmitmode. MASTER The Masterbitindicatesthatthemodule iscurrentlyinmastermode. Itissetwhen a requestforbus mastershipsucceeds.Itisclearedupon arbitrationloss(BER isset)orthe recognitionofa StopCondition. 0 – Slavemode. 1 – Mastermode. NMATCH The New match bitissetwhen theaddressbytefollowinga StartCondition,orrepeated starts,causesa match ora global-callmatch.The NMATCH bitisclearedwhen writtenwith 1.Writing0 toNMATCH isignored.IftheACBnCTL1.INTEN bitisset,an interruptissent when thisbitisset.When NMATCH issetDMA requestsarenotasserted. 0 – No match. 1 – Match orglobal-callmatch. 304 DualACCESS.bus Interfaces Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

www.ti.com SNOSCW5 –MAY 2013 STASTR The StallAfterStartbitissetby thesuccessfulcompletionofan addresssending(i.e.,a StartConditionsentwithouta bus error,ornegativeacknowledge),ifthe ACBnCTL1.STASTRE bitisset.Thisbitisignoredinslavemode. When theSTASTR bitis set,itstallsthebus by pullingdown theSCLn line,and suspendsany otheractionon the bus (e.g.,receivesfirstbyteinmasterreceivemode).Inaddition,iftheACBnCTL1.INTEN bitisset,italsosends an interrupttothecore.Writing1 totheSTASTR bitclearsit.Itis alsoclearedwhen themodule isdisabled.Writing0 totheSTASTR bithas no effect.0 – No stallafterstartcondition.1 – Stallaftersuccessfulstart. NEGACK The NegativeAcknowledgebitissetby hardwarewhen a transmissionisnotacknowledged on theninthclock.(Inthiscase,theSDAST bitisnotset.)Writing1 toNEGACK clearsit.It isalsoclearedwhen themodule isdisabled.Writing0 totheNEGACK bitisignored. 0 – No transmissionnotacknowledgedcondition. 1 – Transmissionnotacknowledged. BER The Bus Errorbitissetby thehardwarewhen a StartorStopConditionisdetectedduring datatransfer(i.e.,StartorStopConditionduringthetransferofbits2 through8 and acknowledgecycle),orwhen an arbitrationproblemisdetected.Writing1 totheBER bit clearsit.Itisalsoclearedwhen themodule isdisabled.Writing0 totheBER bitisignored. 0 – No bus erroroccurred. 1 – Bus erroroccurred. SDST The SDA StatusbitindicatesthattheSDA dataregisteriswaitingfordata(transmit,as masterorslave)orholdsdatathatshouldbe read(receive,as masterorslave).Thisbitis clearedwhen readingfromtheACBnSDA registerduringa receive,orwhen writtento duringa transmit.When theACBnCTL1.START bitisset,readingtheACBnSDA register does notcleartheSDAST bit.ThisenablestheACB tosend a repeatedstartinmaster receivemode. 0 – ACB module isnotwaitingfordatatransfer. 1 – ACB module iswaitingfordatatobe loadedorunloaded. SLVSTP The SlaveStopbitindicatesthata StopConditionwas detectedaftera slavetransfer(i.e., aftera slavetransferinwhichMATCH orGCMATCH isset).Writing1 toSLVSTP clearsit. Itisalsoclearedwhen themodule isdisabled.Writing0 toSLVSTP isignored. 0 – No stopconditionafterslavetransferoccurred. 1 – Stopconditionafterslavetransferoccurred.

29.5.3 ACBn ControlStatusRegister(ACBnCST)

The ACBnCST registersare 8-bit,read/writeregistersthatmaintainthe currentACB status.Following reset,Idlemode, Haltmode, and disablingthemodule,thenon-reservedbitsoftheACBnCST registers arecleared. 7 6 5 4 3 2 1 0 ARPMATCH MATCHAF TGSCL TSDA GCMTCH MATCH BB BUSY BUSY The BUSY bitindicatesthattheACB module is:

• Generatinga StartCondition
• InMastermode (ACBnST.MASTER isset)
• InSlavemode (ACBnCST.MATCH orACBnCST.GCMTCH isset)
• Intheperiodbetween detectinga Startand completingthereceptionoftheaddress byte.Afterthis,theACB eitherbecomes notbusy orentersslavemode. The BUSY bitisclearedby thecompletionofany oftheabove states,and by disabling themodule.BUSY isa readonlybit.Itmust alwaysbe writtenwith0. 0 – ACB module isnotbusy. 1 – ACB module isbusy. Copyright© 2013,Texas InstrumentsIncorporated DualACCESS.bus Interfaces 305 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com BB The Bus Busy bitindicatesthebus isbusy.Itissetwhen thebus isactive(i.e.,a low levelon eitherSDAn orSCLn) orby a StartCondition.Itisclearedwhen themodule is disabled,on detectionofa StopCondition,orwhen writing1 tothisbit.See section Section29.6Usage Notesfora descriptionoftheuse ofthisbit. 0 – Bus isnotbusy. 1 – Bus isbusy. MATCH The AddressMatch bitindicatesinslavemode when ACBnADDR.SAEN issetand the firstseven bitsoftheaddressbyte(thefirstbytetransferredaftera StartCondition) matches the7-bitaddressintheACBnADDR register,orwhen ACBnADDR2.SAEN is setand thefirstseven bitsoftheaddressbytematches the7-bitaddressinthe ACBnADDR2 register.Itisclearedby StartConditionorrepeatedStartand Stop Condition(includingillegalStartorStopCondition). 0 – No addressmatch occurred. 1 – Addressmatch occurred. GCMTCH The GlobalCallMatch bitissetinslavemode when theACBnCTL1.GCMEN bitisset and theaddressbyte(thefirstbytetransferredaftera StartCondition)is00h.Itis clearedby a StartConditionorrepeatedStartand StopCondition(includingillegalStart orStopCondition). 0 – No globalcallmatch occurred. 1 – Globalcallmatch occurred. TSDA The TestSDA bitsamplesthestateoftheSDAn signal.Thisbitcan be used while recoveringfroman errorconditioninwhichtheSDAn signalisconstantlypulledlowby a slavethatwent outofsync.Thisbitisa read-onlybit.Data writtentoitisignored. TGSCL The ToggleSCL bitenablestogglingtheSCLn signalduringerrorrecovery.When the SDAn signalislow,writing1 tothisbitdrivestheSCn signalhighforone cycle.Writing1 toTGSCL when theSDAn signalishighisignored.The bitisclearedwhen theclock toggleiscompleted. 0 – Writing0 has no effect. 1 – Writing1 togglestheSDAn signalhighforone cycle. MATCHAF The Match AddressFieldbitindicateswhichoftwo addressfieldsmatched theslave address.Ifbothfieldsmatch,theMATCHAF bitiscleared.The MATCHAF bitiscleared by a Startcondition,repeatedStartcondition,orStopcondition.IllegalStartand Stop conditionsalsocleartheMATCHAF bit. 0 – ACBnADDR.ADDR fieldmatched theslaveaddress. 1 – ACBnADDR2.ADDR fieldmatched theslaveaddress. ARPMATCH The ARP AddressMatch bitindicateswhen an ARP match occurs.Thisbitissetinslave mode when ACBnCTL3.ARPEN issetand theaddressbyte(firstbytetransferredaftera Startcondition)is110 0001b.The ARPMATCH bitisclearedby a Startcondition, repeatedStartcondition,orStopcondition.IllegalStartand Stopconditionsalsoclear theARPMATCH bit. 0 – Slaveaddresswas not110 0001b. 1 – ARP addressmatch enabled,and slaveaddresswas 110 0001b.

29.5.4 ACBn ControlRegister1 (ACBnCTL1)

The ACBnCTL1 registersare 8-bit,read/writeregistersthatconfigureand controlthe ACB modules. Followingreset,Idlemode, Haltmode, and disablingthemodule,theACBnCTL1 registeriscleared. 7 6 5 4 3 2 1 0 STASTRE NMINTE GCMEN ACK DMAEN INTEN STOP START 306 DualACCESS.bus Interfaces Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

www.ti.com SNOSCW5 –MAY 2013 START The Startbitissettogeneratea StartConditionon theACCESS.bus. The START bitis clearedwhen theStartConditionissent,orupon detectionofa Bus Error(ACBnST.BER = 1).Thisbitshouldbe setonlywhen inMastermode, orwhen requestingMastermode. Ifthis deviceisnottheactivemasterofthebus (ACBnST.MASTER = 0),settingtheSTART bit generatesa StartConditionas soon as theACCESS.bus isfree(ACBnCST.BB = 0).An addresssend sequence shouldthenbe performed.Ifthisdeviceistheactivemasterofthe bus (ACBnST.MASTER = 1),when theSTART bitisset,a writetotheACBnSDA register generatesa StartCondition,thentheACBnSDA dataistransmittedas theslave’s address and therequestedtransferdirection.Thiscase isa repeatedStartCondition.Itmay be used toswitchthedirectionofthedataflowbetween themasterand theslave,ortochoose anotherslavedevicewithoutusinga StopConditioninbetween. 0 – Writing0 has no effect. 1 – Writing1 generatesa Startcondition. STOP The Stopbitinmastermode generatesa StopConditionthatcompletesorabortsthecurrent message transfer.ThisbitclearsitselfaftertheStopconditionisissued. 0 – Writing0 has no effect. 1 – Writing1 generatesa Stopcondition. INTEN The InterruptEnablebitcontrolsassertingACB interrupts.When theINTEN bitiscleared, interruptsaredisabled.When theINTEN bitisset,interruptsareenabled. 0 – Interruptsdisabled. 1 – Interruptsenabled. An interruptisassertedon any ofthefollowingevents:

• An addressMATCH isdetected(ACBnST.NMATCH = 1)and theNMINTE bitisset.
• A Bus Erroroccurs(ACBnST.BERR = 1).
• Negativeacknowledgeaftersendinga byte(ACBnST.NEGACK = 1).
• IfDMA isnotenabled,an interruptisassertedon acknowledgementofeach transaction (same as hardwaresettingtheACBnST.SDAST bit).
• IfACBnCTL1.STASTRE = 1,inmastermode aftera successfulstart(ACBnST.STASTR = 1).
• Detectionofa StopConditionwhileinslavereceivemode (ACBnST.SLVSTP = 1). DMAEN The DMA EnablebitcontrolswhetherDMA requestsareenabled.A DMA requestisasserted attheend ofany datatransaction(ACBnST.SDAST = 1).IfINTEN isset,interruptsare generatedupon occurrenceofany errorora new match). 0 – DMA requestsdisabled. 1 – DMA requestsenabled. ACK The Acknowledgebitholdsthevaluethisdevicesends inmasterorslavemode duringthe nextacknowledgecycle.Settingthisbitto1 instructsthetransmittingdevicetostopsending data,sincethereceivereitherdoes notneed,orcannotreceive,any more data.Thisbitis clearedafterthefirstacknowledgecycle.Thisbitisignoredwhen intransmitmode. GCMEN The GlobalCallMatch Enablebitenablesthematch ofan incomingaddressbytetothe generalcalladdress(StartConditionfollowedby addressbyteof00h)whiletheACB isin slavemode. When cleared,theACB does notrespondtoa globalcall. 0 – Globalcallmatchingdisabled. 1 – Globalcallmatchingenabled. NMINTE The New Match InterruptEnablecontrolswhetherACB interruptsaregeneratedon new matches.SettheNMINTE bittoenabletheinterrupton a new match (i.e.,when ACBnST.NMATCH isset).The interruptisissuedonlyiftheACBnCTL1.INTEN bitisset. Thisbitmust be setwhen usingDMA forthedatatransfer. 0 – New match interruptsdisabled. 1 – New match interruptsenabled. Copyright© 2013,Texas InstrumentsIncorporated DualACCESS.bus Interfaces 307 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com STASTRE The StallAfterStartEnablebitenablesthestallafterstartmechanism.When enabled,the ACB isstalledaftertheaddressbyte.When theSTASTRE bitisclear,theACBnST.STASTR bitisalwaysclear. 0 – No stallafterstart. 1 – Stall-after-startenabled.

29.5.5 ACBn ControlRegister2 (ACBnCTL2)

The ACBnCTL2 registersare 8-bit,read/writeregistersthatcontrolthemodule and selecttheACB clock rate.Atreset,theACBnCTL2 registeriscleared. 7 1M 0 SCLFRQ6:0 ENABLE ENABLE The EnablebitcontrolstheACB module.When thisbitisset,theACB module isenabled. When theEnablebitisclear,theACB module isdisabled,theACBnCTL1, ACBnST, and ACBnCST registersarecleared,and theclocksarehalted. 0 – ACB module disabled. 1 – ACB module enabled. SCLFRQ6: The SCL Frequencyfieldspecifiesthelow7 bitsoftheSCLn period(lowtimeplushigh 0 time)inmastermode. The ACBnCTL3 registerholdsthehigh2 bits.The clocklowtimeand hightimearedefinedas follows: tSCLl = tSCLh = 2 × SCLFRQ8:0 × tCLK inwhichtCLK isthePCLK Clockperiod.The SCLFRQ8:0 fieldmay have valuesintherangeof008h through1FFh.Othervaluesare reserved.

29.5.6 ACBn ControlRegister3 (ACBnCTL3)

The ACBnCTL3 registersare 8-bit,read/writeregistersthatexpand theclockprescalerfieldand enable ARP matches.Atreset,theACBnCTL3 registersarecleared. 7 3 2 1 0 Reserved ARPMEN SCLFRQ8:7 ARPMEN The ARP Match Enablebitenablesthematchingofan incomingaddressbytetotheSMBus ARP address110 0001b generalcalladdress(Startconditionfollowedby addressbyteof 00h),whiletheACB isinslavemode. 0 – ACB does notrespondtoARP addresses. 1 – ARP addressmatchingenabled. SCLFRQ The SCL FrequencyfieldspecifiestheSCL period(lowtimeplushightime)inmastermode. The ACBnCTL3 registerprovidesa 2-bitexpansionofthisfield,withtheremaining7 bits beingheldintheACBnCTL2 register.

29.5.7 ACBn Own Address Register1 (ACBnADDR1)

The ACBnADDR1 registersare 8-bit,read/writeregistersthathold the module’s firstACCESS.bus address.Afterreset,theirvaluesareundefined. 7 6 0 SAEN ADDR 308 DualACCESS.bus Interfaces Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

www.ti.com SNOSCW5 –MAY 2013 ADDR The Own Addressfieldholdsthefirst7-bitACCESS.bus addressofthisdevice.When inslave mode, thefirst7 bitsreceivedaftera StartConditionarecompared tothisfield(firstbitreceived tobit6,and thelasttobit0).Iftheaddressfieldmatches thereceiveddataand theSAEN bitis set,a match isdetected. SAEN The SlaveAddressEnablebitcontrolswhetheraddressmatchingisperformedinslavemode. When set,theSAEN bitindicatesthattheADDR fieldholdsa validaddressand enablesthe match ofADDR toan incomingaddressbyte.When cleared,theACB does notcheckforan addressmatch. 0 – Addressmatchingdisabled. 1 – Addressmatchingenabled.

29.5.8 ACBn Own Address Register2 (ACBnADDR2)

The ACBnADDR2 registersare 8-bit,read/writeregistersthathold the module’s second ACCESS.bus address.Afterreset,theirvaluesareundefined. 7 6 0 SAEN ADDR ADDR The Own Addressfieldholdsthesecond 7-bitACCESS.bus addressofthisdevice.When in slavemode, thefirst7 bitsreceivedaftera StartConditionarecompared tothisfield(firstbit receivedtobit6,and thelasttobit0).Iftheaddressfieldmatches thereceiveddataand the SAEN bitisset,a match isdetected. SAEN The SlaveAddressEnablebitcontrolswheth-eraddressmatchingisperformedinslavemode. When set,theSAEN bitindicatesthattheADDR fieldholdsa validaddressand enablesthe match ofADDR toan incomingaddressbyte.When cleared,theACB does notcheckforan addressmatch. 0 – Addressmatchingdisabled. 1 – Addressmatchingenabled.

29.6 Usage Notes

• When the ACB module is disabled,the ACBnCST.BB bitis cleared.Afterenablingthe ACB (ACBnCTL2.ENABLE = 1) insystems withmore thanone master,thebus may be inthemiddleofa transactionwithanotherdevice,whichisnotreflectedintheBB bit.There isa need toallowtheACB tosynchronizetothebus activitystatusbeforeissuinga requesttobecome thebus master,toprevent bus errors.Therefore,beforeissuinga requesttobecome thebus masterforthefirsttime,software shouldcheck thatthereisno activityon thebus by checkingtheBB bitafterthebus allowedtimeout period.
• When waking up from power down, before checking the ACBnCST.MATCH bit,test the ACBnCST.BUSY bittomake surethattheaddresstransactionhas finished.
• The BB bitisintendedtosolvea deadlockinwhich two,or more, devicesdetecta usage conflicton thebus and bothdevicescease beingbus mastersatthesame time.Inthissituation,theBB bitsof both devicesare active(becauseeach deduces thatthereisanothermaster currentlyperforminga transaction,whileinfactno deviceisexecutinga transaction),and the bus would staylockeduntil some devicesends a ACBnCTL1.STOP condition.The ACBnCST.BB bitallowssoftwareto monitor bus usage,so itcan avoidsendinga STOP signalinthe middleof the transactionof some other deviceon thebus.Thisbitdetectswhetherthebus remainsunused overa certainperiod,whiletheBB bitisset. Copyright© 2013,Texas InstrumentsIncorporated DualACCESS.bus Interfaces 309 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

(IRQ69) DS445 5-Bit Clock Divider 16-Bit Prescaler (RTPRD) 32-Bit Counter (RTCLD/RTCRD) Compare Register 2 (RTCCMP2) Compare Register 3 (RTCCMP3) Compare Register 1 (RTCCMP1) Interrupt Enable Register (RTCIEN) 32.768 kHz Slow Clock

1 Hz Clock

(Typ.) Reset 1024 Hz Clock (Typ.) Wake-Up Input (WUI63) Wake-Up Input (WUI62) Wake-Up Input (WUI61) CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

• In some cases,the bus may get stuckwiththe SCLn or SDAn linesactive.A possiblecause isan erroneousStartorStop Conditionthatoccursinthemiddleofa slavereceivesession.When theSCLn signalisstuckactive,thereisnothingthatcan be done,and itistheresponsibilityofthemodule that holdsthebus toreleaseit.When theSDAn signalisstuckactive,theACB module enablestherelease ofthebus by usingthefollowingsequence.Note thatinnormalcases,theSCLn signalmay be toggled onlyby thebus master.Thisprotocolisa recoveryscheme whichisan exceptionthatshouldbe used onlyinthecase when thereisno othermasteron thebus.The recoveryprocedureisas follows: 1. Disableand re-enablethemodule tosetitintothenotaddressedslavemode 2. SettheACBnCTL1.START bittomake an attempttoissuea StartCondition. 3. Check iftheSDAn signalisactive(low)by readingACBnCST.TSDA bit.Ifitisactive,issuea single SCLn cycleby writing1 toACBnCST.TGSCL bit.IftheSDAn lineisnotactive,continuefrom step5. 4. Check iftheACBnST.MASTER bitisset,whichindicatesthattheStartConditionwas sent.Ifnot, repeatstep3 and 4 untiltheSDAn signalisreleased. 5. CleartheBB bit.ThisenablestheSTART bittobe executed.Continueaccordingtosection Section29.2.1.8Bus IdleErrorRecovery

30 Real Time Clock

The Real Time Clockmodule (RTC) implementsa 32-bitcounterwitha 16-bitprogrammable prescaler, drivenby the32.768kHz Slow Clockthrougha 5-bitclockdivider,as shown inFigure30-1.Thisprovides a timebase witha longwraparoundperiod(over136 years)and theabilitytoschedulelong-durationtime delaysand periodicinterrupts.Three compare registersare implemented:one registerforassertingan interrupton wraparoundoftheprogrammableprescalerand two registersforassertinginterruptswhen the 32-bitcounterreachesspecifiedvalues. The RTC istypicallyprogrammed todividea 32.768kHz Slow Clockby 32,which providesa 1024 Hz clockinputtothe16-bitprescaler.The prescaleristypicallyprogrammed fordivisionby 1024,resultingin a 1 Hz clockinputto the 32-bitcounter.However, the RTC can operatewitha differentSlow Clock frequency,an inputclockdivisorof1,2,4,8,16,or32,and any integerprescalerdivisorbetween 1 and 65,536(decimal). Figure30-1.Real Time Clock

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30.1 Programming

When softwarechanges any of the timingparameters,the change isdelayeduntilitcan be accepted synchronouslytotheoperationoftheRTC. Softwarecan pollregisterbitswhichindicatewhen thechange has been accepted.

• Clockdivider— when theRTDIV fieldoftheRTCCST registeriswritten,thenew divisorisnotaccepted untilthe end of the dividerperiodusingthe old divisor.While the change ispending but not yet accepted,theRTUDIV bitintheRTUDST registerwillbe set.
• Prescaler— theprescalerdivisoriscontrolledby theRTCCMP1 register.When thisregisterisloaded, theRTUCP1 bitintheRTUDIV registerisset,and itremainssetuntilthenew valueisaccepted.
• Counter— the counteris loaded by writingthe RTCLD register.When thisregisteris written,the RTURTC bitintheRTUDST registerisset,and itremainssetuntilthenew valueisaccepted,which occursatthenextrisingedge ofthecounterinputclock(prescaleroutput). When softwarereadsthecurrentprescalervalueintheRTPRD registerorthecurrentcountervalueinthe RTCRD register,thedataisdelayedby fourPCLK Clockcyclesforsynchronizationtothebus.Reading theseregisterswithinone second afterwake-up from Idlemode may returnincorrectvalues.Raisingthe clockinputto the 32-bitcounterabove 1 Hz providesa proportionalreductionof the timeduringwhich incorrectvaluesmay be returned.Timekeepingisnotaffectedby theseincorrectvalues.

30.2 Interrupt

The eventsenabledinthe RTCIEN registerare ORed togetherto generatethe interruptrequestsignal IRQ69. The threeindividualeventsRTCEVT1, RTCEVT2, and RTCEVT3 are mapped to MIWU inputs WUI63, WUI62, and WUI61, respectively.

30.3 Reset

AftersoftwarestartstheRTC by settingtheRTSTRT bitintheRTCCST register,softwarecannotstopthe RTC. The RTC can onlybe stoppedby a power-onreset. A system reset(excepta power-on reset)does not affectthe contentsof the timingparameters,which allowstheRTC tocontinuefunctioningthroughsystemresetevents.Onlya power-onresetstopscounting and resetstheRTC registerstotheirdefaultvalues.Ifa system resetoccurswhilechanges tothetiming parametersarepending,thosechanges willbe discardedwithoutbeingaccepted. The prescalercan be resetby settingtheRTPRST bitintheRTCCST register.The resetwilloccuron the nextrisingedge oftheprescalerinputclock(divideroutput).Aftersoft-waresetstheRTPRST bit,thebit remainssetuntiltheprescalerisreset.

30.4 Real-TimeClock InterfaceRegisters

The Real-TimeClockinterfaceuses theregisterslistedinTable30-1. Table30-1.Real-TimeClock InterfaceRegisters NAME ADDRESS DESCRIPTION RTCCST FF A800h RTC Controland StatusRegister RTUDST FF A804h RTC Update StatusRegister RTCEIST FF A808h RTC Eventand InterruptStatusRegister RTCIEN FF A80Ch RTC InterruptEnableRegister RTPRD FF A810h RTC PrescalerRead Register RTCRD FF A814h RTC CounterRead Register RTCLD FF A818h RTC CounterLoad Register RTCCMP1 FF A81Ch RTC Compare Register1 RTCCMP2 FF A820h RTC Compare Register2 RTCCMP3 FF A824h RTC Compare Register3 Copyright© 2013,Texas InstrumentsIncorporated RealTime Clock 311 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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30.4.1 RTC Controland StatusRegister(RTCCST)

The RTCCST registerisan 8-bit,read/writeregisterthatprovidescontroland statusforthe RTC. At system reset,theRTPRST bitiscleared,buttheotherbitsinthisregisterretaintheirvalues.At power-on reset,thisregisterisclearedto00h. 7 5 4 3 2 0 Reserved RTSTRT RTPRST RTDIV RTDIV The RTC Dividerfieldselectsthedivisorforthe5-bitclockdivider.Valuesabove 101b are reserved. 000 – ÷1 001 – ÷2 010 – ÷4 011 – ÷8 100 – ÷16 101 – ÷32 RTPRST The RTC PrescalerResetbitisused toclearthe16-bitprescalerto0000h.The resetwill occuron thenextrisingedge oftheprescalerinputclock(divideroutput).Aftersoftware writes1 tothebittoresettheprescaler,thebitremainssetuntiltheprescaleriscleared. 0 – Normal operation. 1 – Prescalerresetpending. RTSTRT The RTC StartbitenablestheRTC tocount.Thisbitiscan onlybe clearedby a power-on reset. 0 – RTC suspended. 1 – RTC counting.

30.4.2 RTC Update StatusRegister(RTUDST)

The RTUDST registerisan 8-bit,read-onlyregisterthatindicatespendingchanges toRTC registers.At systemresetorpower-onreset,thisregisterisclearedto00h. 7 5 4 3 2 1 0 Reserved RTUCP3 RTUCP2 RTUCP1 RTURPTC RTUDIV RTUDIV The RTC Update ClockDivisorbitindicatesa new divisorforthe5-bitclockdividerhas been loaded,butnotyetaccepted. 0 – No new divisorloaded. 1 – Pendingchange totheclockdivisor. RTURTC The RTC Update Counterbitindicatesa new valueforthe32-bitcounterhas been loaded,but notyetaccepted. 0 – No new countervalueloaded. 1 – Pendingchange tothecountervalue. RTUCP1 The RTC Update Compare Register1 bitindicatesa new terminalcountvalueforthe16-bit prescalerhas been loadedintotheRTCCMP1 register,butnotyetaccepted. 0 – No new prescalerterminalcountloaded. 1 – Pendingchange totheterminalcount. RTUCP2 The RTC Update Compare Register2 bitindicatesa new interrupttriggervalueforthe32-bit counterhas been loadedintotheRTCCMP2 register,butnotyetaccepted. 0 – No new triggervalueloaded. 1 – Pendingchange tothetriggervalue. RTUCP3 The RTC Update Compare Register3 bitindicatesa new interrupttriggervalueforthe32-bit counterhas been loadedintotheRTCCMP3 register,butnotyetaccepted. 0 – No new triggervalueloaded. 1 – Pendingchange tothetriggervalue.

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30.4.3 RTC Event and InterruptStatusRegister(RTCEIST)

The RTCEIST registerisan 8-bit,read/writeregisterthatindicatesthe statusof match eventsfrom the compare registers.Individualbitsinthisregistercan be clearedby writingthem with1.At system resetor power-onreset,thisregisterisclearedto00h. 7 3 2 1 0 Reserved RTCEVT3 RTCEVT2 RTCEVT1 RTCEVT1 The RTC Event1 bitindicatesa match occurredbetween theRTCCMP1 registerand the16- bitprescaler. 0 – No match occurredsincethisbitwas lastcleared. 1 – A match occurred. RTCEVT2 The RTC Event2 bitindicatesa match occurredbetween theRTCCMP2 registerand the32- bitcounter. 0 – No match occurredsincethisbitwas lastcleared. 1 – A match occurred. RTCEVT3 The RTC Event3 bitindicatesa match occurredbetween theRTCCMP3 registerand the32- bitcounter. 0 – No match occurredsincethisbitwas lastcleared. 1 – A match occurred.

30.4.4 RTC InterruptEnable Register(RTCIEN)

The RTCIEN registerisan 8-bit,read/writeregisterthatenablesinterruptsfromthecompare registers.At systemresetorpower-onreset,thisregisterisclearedto00h. 7 3 2 1 0 Reserved RTCIEN3 RTCIEN2 RTCIEN1 RTCIEN1 The RTC InterruptEnable1 bitisused toen-ablean interruptwhen a match occursbetween the16-bitprescalarand theRTCCMP1 register. 0 – Interruptdisabled. 1 – Interruptenabled. RTCIEN2 The RTC InterruptEnable2 bitisused toen-ablean interruptwhen a match occursbetween the32-bitcounterand theRTCCMP2 register. 0 – Interruptdisabled. 1 – Interruptenabled. RTCIEN3 The RTC InterruptEnable3 bitisused toen-ablean interruptwhen a match occursbetween the32-bitcounterand theRTCCMP3 register. 0 – Interruptdisabled. 1 – Interruptenabled.

30.4.5 RTC PrescalerRead Register(RTPRD)

The RTPRD registerisa 16-bit,read-onlyregisterused toread thecurrentvalueofthe16-bitprescaler. System resetdoes notaffectthisregister.Atpower-onreset,thisregisterisclearedto0000h. 15 0 RTPRD

30.4.6 RTC Counter Read Register(RTCRD)

The RTCRD registerisa 32-bit,read-onlyregisterused toread thecurrentvalueofthe32-bitcounter. System resetdoes notaffectthisregister.Atpower-onreset,thisregisterisinitializedto0000 0001h. Copyright© 2013,Texas InstrumentsIncorporated RealTime Clock 313 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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30.4.7 RTC Counter Load Register(RTCLD)

The RTCLD registerisa 32-bit,read/writeregisterused toloada new valueintothe32-bitcounter.The counterwillbe loadedon the nextrisingedge of itsinputclock(prescaleroutput).When the RTCLD registeriswritten,theRTURTC bitintheRTUDST registerisset.Thisbitisclearedwhen thevalueinthe RTCLD registerisloadedintothecounter.When theRTCLD registerisread,itreturnsthelastvaluethat was writtentoit.Atsystemresetorpower-onreset,thisregisterisclearedto0000 0000h. 15 0 RTCLD

30.4.8 RTC Compare Register1 (RTCCMP1)

The RTCCMP registerisa 16-bit,read/writeregisterwhich holdsa valuecompared withthecontentsof the16-bitprescaler.When thisregisterisloaded,theRTUCP1 bitintheRTUDST registerisset,and the bitremains set untilthe up- dated RTCCMP1 registervalue takes effect.When the contentsof the RTCCMP1 registermatches thecontentsoftheprescaler,theprescalerwillbe clearedon thenextrising edge of itsinputclock(divideroutput),and the RTCEVT1 bitin the RTCEIST registerisset.Ifthe RTCIEN1 bitinthe RTCIEN registerisset,an interruptisasserted.System resetdoes not affectthis register.Atpower-onreset,thisregisterisinitializedto7FFFh. 15 0 RTCCMP1

30.4.9 RTC Compare Register2 (RTCCMP2)

The RTCCMP2 registerisa 32-bit,read/writeregisterwhichholdsa valuecompared withthecontentsof the32-bitcounter.When thisregisterisloaded,theRTUCP2 bitintheRTUDST registerisset,and thebit remainssetuntiltheup-datedRTCCMP2 registervaluetakeseffect.When thecontentsoftheRTCCMP2 registermatches the contentsof the counter,the RTCEVT2 bitin the RTCEIST registerisset.Ifthe RTCIEN2 bitinthe RTCIEN registerisset,an interruptisasserted.System resetdoes not affectthis register.Atpower-onreset,thisregisterisinitializedtoFFFF FFFFh. 31 0 RTCCMP2

30.4.10 RTC Compare Register3 (RTCCMP3)

The RTCCMP3 registerisa 32-bit,read/writeregisterwhichholdsa valuecompared withthecontentsof the32-bitcounter.When thisregisterisloaded,theRTUCP3 bitintheRTUDST registerisset,and thebit remainssetuntiltheupdatedRTCCMP3 registervaluetakeseffect.When thecontentsoftheRTCCMP3 registermatches the contentsof the counter,the RTCEVT3 bitin the RTCEIST registerisset.Ifthe RTCIEN3 bitinthe RTCIEN registerisset,an interruptisasserted.System resetdoes not affectthis register.Atpower-onreset,thisregisterisinitializedtoFFFF FFFFh. 31 0 RTCCMP3

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31 Timing and Watchdog Module

The Timingand Watchdog Module (TWM) generatesthe clocksand interruptsused fortimingperiodic functionsinthesystem;italsoprovidesWatchdog protectionoversoft-ware execution. The TWM isdesignedto provideflexibilityinsystem designby configuringvariousclockratiosand by selectingtheWatchdog clocksource.AftersettingtheTWM configuration,softwarecan lockitfora higher levelofprotectionagainsterroneoussoftwareaction.Once theTWM islocked,onlyresetcan releaseit.

31.1 TWM Structure

Figure115 isa blockdiagramshowingtheinternalstructureoftheTimingand Watchdog module.There are two main sections:the Real-TimeTimer (T0)sectionat the top and the Watchdog sectionon the bottom. Allcountingactivitiesofthemodule are based on theSlow Clock(SLCLK).A prescalercounterdivides thisclockto make a slowerclock.The prescalerfactorisdefinedby a 3- bitfieldin the Timer and Watchdog Prescalerregister,which selectseither1, 2, 4, 8, 16, or 32 as the divisor.Therefore,the prescaledclockperiodcan be 2,4,8,16,or32 timestheSlow Clockperiod.The prescaledclocksignalis calledT0IN.

31.2 Timer toOperation

Timer T0 is a programmable 16-bitdown counterthatcan be used as the time base forreal-time operationssuch as a periodicaudibletick.Itcan alsobe used todrivetheWatch-dog circuit. The timerstartscountingfromthevalueloadedintotheTWMT0 registerand countsdown on each rising edge of T0IN.When the timerreacheszero,itisautomaticallyreloadedfrom the TWMT0 registerand continuescountingdown fromthatvalue.Therefore,thefrequencyofthetimeris: (12) When an externalcrystaloscillatoris used as the SLCLK source or when the fastclockis divided accordingly,fSLCLK is32.768kHz. The valuestoredinTWMT0 can rangefrom0001h toFFFFh. Copyright© 2013,Texas InstrumentsIncorporated Timingand Watchdog Module 315 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

(TWCP) REAL TIME TIMER (T0) WA TCHDOG Restart Restart Underflow Underflow Slow Clock T0LINT (to ICU) T0OUT (to Multi-Input- Wake-Up) WDERRWatchdog Error 16-Bit Timer (Timer0) WA TCHDOG Timer WA TCHDOG Service Logic TWW/MT0 Register T0CSR Contrl. Reg. WDSDM WDCNT DS080 T0IN CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure31-1.Timing and Watchdog Module Block Diagram When the counterreacheszero,an internaltimersignalcalledT0OUT issetforone T0IN clockcycle. ThissignalsetstheTC bitintheTWMT0 Controland StatusRegister(T0CSR).Italsoassertsan interrupt (IRQ70),when enabledby theT0CSR.T0INTE bit.T0OUT isalsoan inputtotheMIWU (seeSection17), so an edge-triggeredinterruptisalsoavailablethroughthisalternativemechanism. Ifsoftwareloadsthe TWMT0 registerwitha new value,the timeruses thatvaluethe nexttimethatit reloadsthe16-bittimerregister(inotherwords,afterreachingzero).Softwarecan restartthetimeratany time(ontheverynextedge oftheT0IN clock)by settingtheRestart(RST) bitintheT0CSR register.The T0CSR.RST bitisclearedautomaticallyupon restartofthe16-bittimer. NOTE To enterPower Save or Idlemode aftersettingtheT0CSR.RST bit,softwaremust waitfor theresetoperationtocompletebeforeperformingtheswitch.

31.3 Watchdog Operation

The Watchdog isan 8-bitdown counterthatoperateson therisingedge ofa specifiedclocksource.At reset,theWatchdog isdisabled;itdoes notcountand no Watchdog signalisgenerated.A writetoeither theWatchdog Count (WDCNT) registerortheWatchdog ServiceData Match (WDSDM) registerstartsthe counter.The Watchdog countercountsdown from thevalueprogrammed intheWDCNT register.Once started,onlya resetcan stoptheWatchdog fromoperating. The Watchdog can be programmed touse eitherT0OUT orT0IN as itsclocksource(theoutputand input ofTimerT0,respectively).The TWCFG.WDCT0I bitselectstheclocksource. Softwaremust periodicallyservicetheWatchdog.Therearetwo ways toservicetheWatchdog,thechoice depending on the programmed value of the WDSDME bitin the Timer and Watchdog Configuration (TWCFG) register. IftheTWCFG.WDSDME bitisclear,theWatchdog isservicedby writinga valuetotheWDCNT register. The valuewrittento the registerisreloadedintothe Watchdog counter.The counterthen continues countingdown fromthatvalue.

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www.ti.com SNOSCW5 –MAY 2013 IftheTWCFG.WDSDME bitisset,theWatchdog isservicedby writingthevalue5Ch totheWatchdog ServiceData Match (WDSDM) register.This reloadsthe Watchdog counterwiththe valuepreviously programmed intotheWDCNT register.The counterthencontinuescountingdown fromthatvalue. A Watchdog errorsignalisgeneratedby any ofthefollowingevents:

• The Watchdog servicedtoolate.
• The Watchdog servicedtoooften.
• The WDSDM registeriswrittenwitha valueotherthan5Ch when WDSDM typeservicingisenabled (TWCFG.WDSDME = 1). A Watchdog errorconditionresetsthedevice.

31.3.1 RegisterLocking

The Timer and Watchdog Configuration(TWCFG) registerisused tosettheWatchdog configuration.It controlstheWatchdog clocksource(T0INor T0OUT), thetypeofWatchdog servicing(usingWDCNT or WDSDM), and the lockingstateof the TWCFG, TWCPR, TIMER0, T0CSR, and WDCNT registers.A registerthatislockedcannotbe readorwritten.A writeoperationisignoredand a readoperationreturns unpredictableresults. IftheTWCFG registerisitselflocked,itremainslockeduntilthedeviceisreset.Any otherlockedregisters alsoremainlockeduntilthedeviceisreset.Thisfeaturepreventsa run-away program from tampering withtheprogrammed Watchdog function.

31.3.2 Power Save Mode Operation

The Timer and Watchdog Module isactivein both the Power Save and Idlemodes. The clocksand counterscontinuetooperatenormallyinthesemodes. The WDSDM registerisaccessibleinthePower Save and Idlemodes, but the otherTWM registersare accessibleonlyinthe Activemode. Therefore, Watchdog servicingmust be carriedoutusingtheWDSDM registerinthePower Save orIdlemode. In the Haltmode, the entiredeviceisfrozen,includingthe Timer and Watchdog Module.On returnto Activemode, operationofthemodule resumes atthepointatwhichitwas stopped. NOTE Aftera restartor Watchdog servicethroughWDCNT, do notenterPower Save mode fora periodequivalentto5 Slow Clockcycles.

31.4 TWM Registers

The TWM registerscontrolsthe operationof the Timing and Watchdog Module. There are sixsuch registers: Table31-1.TWM Registers NAME ADDRESS DESCRIPTION TWCFG FF A000h Timerand Watchdog ConfigurationRegister TWCP FF A004h Timerand Watchdog ClockPrescalerRegister TWMT0 FF A008h TWM Timer0 Register T0CSR FF A00Ch TWMT0 Controland StatusRegister WDCNT FF A010h Watchdog Count Register WDSDM FF A014h Watchdog ServiceData Match Register Copyright© 2013,Texas InstrumentsIncorporated Timingand Watchdog Module 317 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com The WDSDM registerisaccessibleinbothActiveand Power Save mode. The otherTWM registersare accessibleonlyinActivemode.

31.4.1 Timer and Watchdog ConfigurationRegister(TWCFG)

The TWCFG registerisa byte-wide,read/writeregisterthatselectstheWatchdog clockinputand service method,and alsoallowstheWatchdog registerstobe selectivelylocked.A lockedregistercannotbe read orwritten;a readoperationreturnsunpredictablevaluesand a writeoperationisignored.Once a lockbit isset,itcannotbe cleareduntilthe deviceisreset.At reset,the non-reservedbitsof the registerare cleared.The registerformatisshown below. 7 6 5 4 3 2 1 0 Reserved WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG LTWCFG The Lock TWCFG RegisterbitcontrolsaccesstotheTWCFG register.When clear,access totheTWCFG registerisallowed.When set,theTWCFG registerislocked. 0 – TWCFG registerunlocked. 1 – TWCFG registerlocked. LTWCP The Lock TWCP RegisterbitcontrolsaccesstotheTWCP register.When clear,accessto theTWCP registerisallowed.When set,theTWCP registerislocked. 0 – TWCP registerunlocked. 1 – TWCP registerlocked. LTWMT0 The Lock TWMT0 RegisterbitcontrolsaccesstotheTWMT0 register.When clear,access totheTWMT0 and T0CSR registersareallowed.When set,theTWMT0 and T0CSR registersarelocked. 0 – TWMT0 registerunlocked. 1 – TWMT0 registerlocked. LWDCNT The Lock LDWCNT RegisterbitcontrolsaccesstotheLDWCNT register.When clear, accesstotheLDWCNT registerisallowed.When set,theLDWCNT registerislocked. 0 – LDWCNT registerunlocked. 1 – LDWCNT registerlocked. WDCT0I The Watchdog ClockfromT0IN bitselectstheclocksourcefortheWatchdog timer.When clear,theT0OUT signal(theoutputofTimerT0)isused as theWatchdog clock.When set, theT0IN signal(theprescaledSlow Clock)isused as theWatchdog clock. 0 – Watchdog timerisclockedby T0OUT. 1 – Watchdog timerisclockedby T0IN. WDSDME The Watchdog ServiceData Match Enablebitcontrolswhichmethod isused toservicethe Watchdog timer.When clear,Watchdog servicingisaccomplishedby writinga countvalue totheWDCNT register;writeoperationstotheWatchdog ServiceData Match (WDSDM) registerareignored.When set,Watchdog servicingisaccomplishedby writingthevalue 5Ch totheWDSDM register. 0 – Writea countvaluetotheWDCNT registertoservicetheWatchdog timer. 1 – Write5Ch totheWDSDM registertoservicetheWatchdog timer.

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31.4.2 Timer and Watchdog Clock PrescalerRegister(TWCP)

The TWCP registerisa byte-wide,read/writeregisterthatspecifiestheprescalervalueused fordividing the low-frequencyclockto generatethe T0IN clock.At reset,the non-reservedbitsof the registerare cleared.The registerformatisshown below. 7 3M M 2 0 Reserved MDIV MDIV Main ClockDivide.This3-bitfielddefinestheprescalerfactorused fordividingthelowspeed deviceclocktocreatetheT0IN clock.The allowed3-bitvaluesand thecorrespondingclock divisorsand clockratesarelistedbelow. Clock DivisorMDIV T0IN Frequency(fSCLK = 32.768kHz) 000 1 32.768kHz 001 2 16.384kHz 010 4 8.192kHz 011 8 4.096kHz 100 16 2.056kHz 101 32 1.024kHz Other Reserved N/A

31.4.3 TWM Timer 0 Register(TWMT0)

The TWMT0 registerisa 16-bit,read/writeregisterthatde- finesthe T0OUT interruptrate.At reset, TWMT0 registerisinitializedtoFFFFh. The registerformatisshown below. 15 0 PRESET PRESET The TimerT0 Presetfieldholdsthevalueused toreloadTimerT0 on each underflow. Therefore,thefrequencyoftheTimerT0 interruptisthefrequencyofT0IN dividedby (PRESET+1). The allowedvaluesofPRESET are0001h throughFFFFh.

31.4.4 TWMT0 Controland StatusRegister(T0CSR)

The T0CSR registerisa byte-wide,read/writeregisterthatcontrolsTimerT0 and shows itscurrentstatus. Atreset,thenon-reservedbitsoftheregisterarecleared.The registerformatisshown below. 7 5 4 3 2 1 0 Reserved FRZT0E WDLTD T0INTE TC RST RST The Restartbitisused toresetTimerT0.When thisbitisset,itforcesthetimertoreloadthe valueintheTWMT0 registeron thenextrisingedge oftheselectedinputclock.The RST bit isresetautomaticallyby thehardwareon thesame risingedge oftheselectedinputclock. Writinga 0 tothisbitpositionhas no effect.Atreset,thenon-reservedbitsoftheregisterare cleared. 0 – Writing0 has no effect. 1 – Writing1 resetsTimerT0. TC The TerminalCount bitissetby hardwarewhen theTimerT0 countreacheszeroand is clearedwhen softwarereadstheT0CSR register.Itisa read-onlybit.Any datawrittentothis bitpositionisignored. 0 – TimerT0 didnotcountdown to0. 1 – TimerT0 counteddown to0. Copyright© 2013,Texas InstrumentsIncorporated Timingand Watchdog Module 319 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Peripheral Bus ClockPRESET 6 2 Watchdog Clock © ¹ © ¹ CP3SP33 SNOSCW5 –MAY 2013 www.ti.com T0INTE The TimerT0 InterruptEnablebitenablesan interrupttotheCPU each timetheTimerT0 countreacheszero.When thisbitisclear,TimerT0 interruptsaredisabled. 0 – TimerT0 interruptsdisabled. 1 – TimerT0 interruptsenabled. WDLTD The Watchdog LastTouch Delaybitissetwhen eitherWDCNT orWDSDM iswrittenand the datatransfertotheWatchdog isinprogress(seeWDCNT and WDSDM registerdescription). When clear,itissafetoswitchtoPower Save mode. 0 – No datatransfertotheWatchdog isinprogress,safetoenterPower Save mode. 1 – Data transfertotheWatchdog inprogress. FRZT0E The FreezeTimer0 EnablebitcontrolswhetherTimer0 isstoppedinFreezemode. Ifthisbit isset,theTimer0 isfrozen(stopped)when theFreezeinputtotheTWM isasserted.Ifthe FRZT0E bitisclear,onlytheWatchdog timerisfrozenby assertingtheFreezeinputsignal. Afterreset,thisbitisclear. 0 – TimerT0 unaffectedby Freezemode. 1 – TimerT0 stoppedinFreezemode.

31.4.5 Watchdog Count Register(WDCNT)

The WDCNT registeris a byte-wide,write-onlyregisterthatholds the value thatis loaded intothe Watchdog countereach timetheWatchdog isserviced.The Watchdog isstartedby thefirstwritetothis register.Each successivewritetothisregisterrestartstheWatchdog countwiththewrittenvalue.Atreset, thisregisterisinitializedto0Fh. 7 0 PRESET The WDCNT registeroperatesfrom PCLK Clock,not Slow Clock.Because the restof the Watchdog servicemechanism operatesfromSlow Clock,thereisa smallamount oflatencybetween thewritetothe WDCNT registerand theactualserviceoftheWatchdog.Due tothislatencyitisnotrecommended touse smallPRESET values.InPower Save mode, itiseven more importantbecause thelatencytime(inclock cycles)iseven longerthaninActivemode. The minimum PRESET valuemust be largeenough tosatisfy thislatency,whichisexpressedinthisrelation: (13)

31.4.6 Watchdog ServiceData Match Register(WDSDM)

The WSDSM registerisa byte-wide,write-onlyregisterused forservicingtheWatchdog. When thistype ofservicingisenabled(TWCFG.WDSDME = 1),theWatchdog isservicedby writingthevalue5Ch tothe WSDSM register.Each such servicingreloadstheWatchdog counterwiththevaluepreviouslywrittento theWDCNT register.Writingany dataotherthan5Ch triggersa Watchdog error.Writingtotheregister more thanonce inone Watchdog clockcyclealsotriggersa Watchdog errorsignal.Ifthistypeofservicing isdisabled(TWCFG.WDSDME = 0),any writetotheWSDSM registerisignored. 7 0 RSTDATA

31.5 Watchdog Programming Procedure

The highestlevelofprotectionagainstsoftwareerrorsisachievedby programming and thenlockingthe Watchdog registersand usingtheWDSDM registerforservicing.Thisistheprocedure: 1. WritethedesiredvaluesintotheTWM ClockPrescalerregister(TWCP) and theTWM Timer0 register (TWMT0) tocontroltheT0IN and T0OUT clockrates.The frequencyofT0IN can be programmed to any ofsixfrequenciesrangingfrom1/32× fSLCLK tofSLCLK.The frequencyofT0OUT isequaltothe

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TCRA_n Timer/Counter Clock Source Action TAn Interrupt B Interrupt A Toggle/Capture/Interrupt Clock Prescaler/Selector Timer/Counter 1 TCNT1_n Reload/Capture B TCRB_n Timer/Counter 2 TCNT2_n PWM/Capture/Counter Mode Select + ControlExternal Event PCLK Clock TBn DS448 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 frequencyofT0IN dividedby (1+PRESET), inwhichPRESET isthevaluewrittentotheTWMT0 register. 2. ConfiguretheWatchdog clocktouse eitherT0IN orT0OUT by settingorclearingtheTWCFG.WDCT0I bit. 3. WritetheinitialvalueintotheWDCNT register.ThisstartsoperationoftheWatchdog and specifiesthe maximum allowednumber ofWatchdog clockcyclesbetween serviceoperations.Startingfromthis point,theWatchdog must be periodicallyservicedtopreventa devicereset. 4. SettheT0CSR.RST bittorestarttheTWMT0 timer. 5. Lock theWatchdog registersand enabletheWatchdog ServiceData Match Enablefunctionby setting bits0,1,2,3,and 5 intheTWCFG register. 6. ServicetheWatchdog by periodicallywritingthevalue5Ch totheWDSDM registeratan appropriate rate.Servicingmust occuratleastonce perperiodprogrammed intotheWDCNT register,butno more thanonce ina singleWatchdog inputclockcycle.

32 Dual Multi-FunctionTimers

The two Multi-FunctionTimermodules each containa pairof16-bittimer/counters.Each timer/counterunit offersa choiceof clocksourcesforoperationand can be configuredto operateinany of the following modes:

• Processor-IndependentPulseWidthModulation(PWM) mode, whichgeneratespulsesofa specified widthand dutycycle,and whichalsoprovidesa general-purposetimer/counter.
• Dual-InputCapturemode, whichmeasures theelapsedtimebetween occurrencesofexternalevents, and whichalsoprovidesa general-purposetimer/counter.
• DualIndependentTimermode, whichgeneratessystemtimingsignalsorcountsoccurrencesof externalevents.
• Single-InputCaptureand SingleTimermode, whichprovidesone externaleventcounterand one systemtimer. Each timerunituses two I/Opins,calledTAn and TBn. (OnlyTA0 isavailableintheFBGA-144 package.)

32.1 Timer Structure

Figure32-1 isa blockdiagramshowing theinternalstructureoftheMFT. There are two main functional blocks:a Timer/Counterand Actionblockand a ClockSource block.The Timer/Counterand Actionblock containstwo separatetimer/counterunits,calledTimer/Counter1 and Timer/Counter2. Figure32-1.Multi-FunctionTimer Block Diagram Copyright© 2013,Texas InstrumentsIncorporated DualMulti-FunctionTimers 321 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Synchr. External Event Pulse Accumulator 5-Bit Prescaler Counter Prescaler Register TPRSC_n Reset PCLK Clock TBn Prescaled Clock No Clock DS449Slow Clock Slow Clock Synchr. CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

32.1.1 Timer/CounterBlock

The Timer/Counterblockcontainsthefollowingfunctionalblocks:

• Two 16-bitcounters,Timer/Counter1 (TCNT1_n) and Timer/Counter2 (TCNT2_n)
• Two 16-bitreload/captureregisters,TCRA_n and TCRB_n
• Controllogicnecessarytoconfigurethetimertooperateinany ofthefouroperatingmodes
• Interruptcontroland I/Ocontrollogic

32.1.2 Clock Source Block

The ClockSource blockgeneratesthesignalsused toclockthetwo timer/counterregisters.The internal structureoftheClockSourceblockisshown inFigure32-2. Figure32-2.Multi-FunctionTimer Clock Source 32.1.2.1Counter Clock Source Select There aretwo clocksourceselectorsthatallowsoftwaretoindependentlyselecttheclocksourceforeach ofthetwo 16-bitcountersfromany ofthefollowingsources:

• No clock(whichstopsthecounter)
• PrescaledPCLK Clock
• Externaleventcountbased on TBn
• Pulseaccumulatemode based on TBn
• Slow Clock 32.1.2.2Prescaler The 5-bitclockprescalerallowssoftwareto run the timerwitha prescaledclocksignal.The prescaler consistsofa 5-bitread/writeprescalerregister(TPRSC_n) and a 5-bitdown counter.The PCLK Clockis dividedby thevaluecontainedintheprescalerregisterplus1.Therefore,thePCLK Clockfrequencycan be dividedby any valuefrom 1 to 32. The prescalerregisterand down counterare both clearedupon reset. 32.1.2.3ExternalEvent Clock The TBn pincan be configuredto operateas an externaleventinputclockforeitherof the two 16-bit counters.Thisinputcan be programmed todetecteitherrisingorfallingedges.The minimum pulsewidth of the externalsignalisone PCLK Clock cycle.Thismeans thatthe maximum frequencyat which the countercan runinthismode isone-halfofthePCLK Clockfrequency.Thisclocksourceisnotavailablein thecapturemodes (modes 2 and 4)because theTBn pinisused as one ofthetwo captureinputs.

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www.ti.com SNOSCW5 –MAY 2013 32.1.2.4Pulse Accumulate Mode The countercan alsobe configuredtocountprescaleroutputclockpulseswhen theTBn inputishighand notcountwhen theTBn inputislow,as illustratedinFigure32-3.The resultingcountisan indicatorofthe cumulativetimethattheTBn inputishigh.Thisiscalledthe"pulse-accumulate"mode. Inthismode, an AND gategeneratesa clocksignalforthecounterwhenever a prescalerclockpulseisgeneratedand the TBn inputishigh.(The polarityoftheTBn signalisprogrammable,so thecountercan countwhen the TBn inputislow ratherthan high.)The pulse-accumulatemode isnot availableinthe capturemodes (modes 2 and 4)because theTBn pinisused as one ofthetwo captureinputs. Figure32-3.Pulse-AccumulateMode 32.1.2.5Slow Clock Slow Clockcan be selectedas theclocksourceforthetwo 16-bitcounters.Because Slow Clockcan be asynchronous,itmust be synchronizedtoPCLK Clock,thereforethemaximum inputfrequencyofSlow ClockisthePCLK Clockfre-quency dividedby four. 32.1.2.6LimitationsinLow-Power Modes The Power Save mode drivesSlow ClockontoHCLK Clock.Inthismode, Slow Clockcannotbe used as a clocksourceforthetimersbecause itwould have thesame frequencyora higherfrequencythanPCLK Clock,and theclockrationeeded forsynchronizationtoPCLK Clockwould notbe maintained.However, theExternalEventClockand PulseAccumulateMode willstillwork,as longas theexternaleventpulses areatleastthelengthofthePCLK Clockperiod. Idleand Haltmodes stop HCLK Clock and PCLK Clock.IfPCLK Clock isstopped,the timerstops countinguntilPCLK Clockresumes operation.

32.2 Timer OperatingModes

Each timer/counterunitcan be configuredtooperateinthefollowingmodes:

• Processor-IndependentPulseWidthModulation(PWM) mode
• Dual-InputCapturemode
• DualIndependentTimermode
• Single-InputCaptureand SingleTimermode At reset,thetimersaredisabled.To configureand startthetimers,softwaremust writea setofvaluesto theregistersthatcontrolthetimers.The registersaredescribedinSectionSection32.4

32.2.1 Mode 1:Processor-IndependentPWM

Mode 1 istheProcessor-IndependentPulseWidthModulation(PWM) mode, whichgeneratespulsesofa specifiedwidthand dutycycle,and whichalsoprovidesa separategeneral-purposetimer/counter. Copyright© 2013,Texas InstrumentsIncorporated DualMulti-FunctionTimers 323 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

TCNT1_n Timer 1 Clock Reload B = Time 2 TCRB_n Reload A = Time 1 TCRA_n TAPND TBPND TAIEN Timer Interrupt A TAEN TAn TBn TBIEN Timer Interrupt B Underflow Underflow TDIEN Timer Interrupt D TDPND Timer/Counter 2 TCNT2_n Timer 2 Clock Clock Selector DS451 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure32-4isa blockdiagramoftheMulti-FunctionTimerconfiguredtooperateinMode 1.Timer/Counter 1 (TCNT1_n) functionsas thetimebase forthePWM timer.Itcountsdown attheclockrateselectedfor thecounter.When an underflowoccurs,thetimerregisterisreloadedalternatelyfrom theTCRA_n and TCRB_n registers,and countingproceedsdownward fromtheloadedvalue. On thefirstunderflow,thetimerisloadedfrom theTCRA_n register,thenfrom theTCRB_n registeron thenextunderflow,thenfromtheTCRA_n registeragainon thenextunderflow,and so on.Everytimethe counterisstoppedand restarted,italwaysobtainsitsfirstreloadvaluefromtheTCRA_n register.Thisis truewhetherthetimerisrestartedupon reset,afterenteringMode 1 fromanothermode, orafterstopping and restartingtheclockwiththeTimer/Counter1 clockselector. The timercan be configuredtotoggletheTAn outputbiton each underflow.Thisgeneratesa clocksignal on the TAn outputwiththe widthand dutycycledeterminedby the valuesstoredinthe TCRA_n and TCRB_n registers.Thisisa “processor-independent” PWM clockbecause once the timerissetup, no more actionisrequiredfromtheCPU togeneratea continuousPWM signal. The timercan be configuredtogenerateseparateinterruptsupon reloadfromtheTCRA_n and TCRB_n registers.The interruptscan be enabledor disabledunder softwarecontrol.The CPU can determinethe cause ofeach interruptby lookingattheTAPND and TBPND bits,whichareupdatedby thehardwareon each occurrenceofa timerreload. InMode 1,Timer/Counter2 (TCNT2_n) can be used eitheras a simplesystem timer,an externalevent counter,or a pulse-accumulatecounter.The clockcounts down using the clockselectedwith the Timer/Counter2 clockselector.Itassertsan interruptupon each underflowiftheinterruptisenabledwith theTDIEN bit. Figure32-4.Processor-IndependentPWM Mode

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TCNT1_n Timer 1 Clock Capture A TCRA_n TAPND TAn TAIEN Timer Interrupt 1 Preset Underflow TAEN TCPND TCIEN Timer Interrupt 1Capture B TCRB_n TBn Timer/Counter 2 TnCNT2_n Timer 2 Clock Underflow TDPND TDIEN Timer Interrupt 2 TBPND TBIEN Timer Interrupt 1 Preset TBEN DS452 CP3SP33 www.ti.com SNOSCW5 –MAY 2013

32.2.2 Mode 2:Dual InputCapture

Mode 2 isthe Dual InputCapture mode, which measures the elapsedtime between occurrencesof externalevents,and whichalsoprovidesa separategeneral-purposetimer/counter. Figure32-5isa blockdiagramoftheMulti-FunctionTimerconfiguredtooperateinMode 2.The timebase ofthecapturetimerdepends on Timer/Counter1,which countsdown usingtheclockselectedwiththe Timer/Counter1 clockselector.The TAn and TBn pinsfunctionas captureinputs.A transitionreceivedon theTAn pintransfersthetimercontentstotheTCRA_n register.Similarly,a transitionreceivedon theTBn pintransfersthetimercontentstotheTCRB_n register.Each inputpincan be configuredtosense either risingorfallingedges. The TAn and TBn inputscan be configuredtopresetthecountertoFFFFh on receptionofa validcapture event.Inthiscase,thecurrentvalueofthecounteristransferredtothecorrespondingcaptureregister and thenthecounterispresettoFFFFh. Using thisapproachallowssoftwaretodeterminetheon-time and off-timeand periodofan externalsignalwitha minimum ofCPU overhead. The valuescapturedintheTCRA_n registeratdifferenttimesreflecttheelapsedtimebetween transitions on theTAn pin.The same istruefortheTCRB_n registerand theTBn pin.The inputsignalon theTAn or TBn pinmust have a pulsewidthequaltoorgreaterthanone PCLK Clockcycle. There are threeseparateinterruptsassociatedwiththecapturetimer,each withitsown enablebitand pending bit.The threeinterruptevents are receptionof a transitionon the TAn pin,receptionof a transitionon theTBn pin,and underflowoftheTCNT1_n counter.The enablebitsfortheseeventsare TAIEN, TBIEN, and TCIEN, respectively. InMode 2,Timer/Counter2 (TCNT2_n) can be used as a simplesystem timer.The clockcountsdown using the clockselectedwiththe Timer/Counter2 clockselector.Itassertsan interruptupon each underflowiftheinterruptisenabledwiththeTDIEN bit. NeitherTimer/Counter1 (TCNT1_n) norTimer/Counter2 (TCNT2_n) can be configuredtooperateas an externaleventcounteror tooperateinthepulse-accumulatemode because theTBn inputisused as a captureinput.Attemptingtoselectone oftheseconfigurationswillcause one orbothcounterstostop. Figure32-5.Dual-InputCapture Mode Copyright© 2013,Texas InstrumentsIncorporated DualMulti-FunctionTimers 325 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

TCNT1_n Timer 1 Clock Reload A TCRA_n TAPND TAIEN Timer Interrupt 1TAEN TAn TBn Underflow Timer/Counter 2 TCNT2_n Timer 2 Clock Reload B TCRB_n TDPND TDIEN Timer Interrupt 2 Underflow Clock Selector DS453 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

32.2.3 Mode 3:Dual IndependentTimer/Counter

Mode 3 is the Dual IndependentTimer mode, which generatessystem timingsignalsor counts occurrencesofexter-nalevents. Figure32-6isa blockdiagramoftheMulti-FunctionTimerconfiguredtooperateinMode 3.The timeris configuredto operateas a dualindependentsystem timeror dualexternaleventcounter.In addition, Timer/Counter1 can generatea 50% dutycyclePWM signalon theTAn pin.The TBn pincan be used as an externaleventinputor pulse-accumulateinputand can be used as theclocksourceforeitherTimer/ Counter1 orTimer/Counter2.Bothcounterscan alsobe clockedby theprescaledPCLK Clock. Timer/Counter1 (TCNT1_n) countsdown attherateoftheselectedclock.On underflow,itisreloaded fromtheTCRA_n registerand countingproceedsdown fromthereloadedvalue.Inaddition,theTAn pin istoggledon each underflowifthisfunctionisenabledby theTAEN bit.The initialstateoftheTAn pinis software-programmable.When the TAn pin is toggledfrom low to high,itsets the TCPND interrupt pendingbitand alsoassertsan interruptifenabledby theTAIEN bit. Because theTAn pintoggleson everyunderflow,a 50% dutycyclePWM signalcan be generatedon the TAn pinwithoutany furtheractionfromtheCPU. Timer/Counter2 (TCNT2_n) countsdown attherateoftheselectedclock.On underflow,itisreloaded from the TCRB_n registerand countingproceeds down from the reloadedvalue.In addition,each underflowsetstheTDPND interruptpendingbitand assertsan interruptiftheinterruptisenabledby the TDIEN bit. Figure32-6.Dual-IndependentTimer/CounterMode

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32.2.4 Mode 4:InputCapture Plus Timer

Mode 4 istheSingleInputCaptureand SingleTimer mode, which providesone externaleventcounter and one systemtimer. Figure32-7 isa blockdiagramoftheMulti-FunctionTimer configuredtooperateinMode 4.Thismode offersa combinationofMode 3 and Mode 2 functions.Timer/Counter1 isused as a system timeras in Mode 3 and Timer/Counter2 isused as a capturetimeras inMode 2,butwitha singleinputratherthan two inputs. Timer/Counter1 (TCNT1_n) operatesthesame as inMode 3.Itcountsdown attherateoftheselected clock.On underflow,itisreloadedfrom the TCRA_n registerand countingproceeds down from the reloadedvalue.The TAn pinistoggledon each underflow,when thisfunctionisenabledby theTAEN bit. When theTAn pinistoggledfromlow tohigh,itsetstheTCPND interruptpendingbitand alsoassertsan interruptiftheinterruptisenabledby theTAIEN bit.A 50% dutycyclePWM signalcan be generatedon TAn withoutany furtheractionfromtheCPU. Timer/Counter2 (TCNT1_n) countsdown attherateoftheselectedclock.The TBn pinfunctionsas the captureinput.A transitionreceivedon TBn transfersthetimercontentstotheTCRB_n register.The input pincan be configuredtosense eitherrisingorfallingedges. The TBn inputcan be configuredtopresetthecountertoFFFFh on receptionofa validcaptureevent.In thiscase,thecurrentvalueofthecounteristransferredtothecaptureregisterand thenthecounteris presettoFFFFh. The valuescapturedintheTCRB_n registeratdifferenttimesreflecttheelapsedtimebetween transitions on theTBn pin.The inputsignalon TBn must have a pulsewidthequaltoorgreaterthanone PCLK Clock cycle. There are two separateinterruptsassociatedwiththe capturetimer,each withitsown enablebitand pendingbit.The two interrupteventsarereceptionofa transitionon TBn and underflowoftheTCNT2_n counter.The enablebitsfortheseeventsareTBIEN and TDIEN, respectively. NeitherTimer/Counter1 (TCNT1_n) norTimer/Counter2 (TCNT2_n) can be configuredtooperateas an externaleventcounteror tooperateinthepulse-accumulatemode because theTBn inputisused as a captureinput.Attemptingtoselectone oftheseconfigurationswillcause one orbothcounterstostop.In thismode, Timer/Counter2 must be enabledatalltimes. Copyright© 2013,Texas InstrumentsIncorporated DualMulti-FunctionTimers 327 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

TCNT1_n Timer 1 Clock Reload A TCRA_n TAPND TAIEN Timer Interrupt 1TAEN TAn Underflow TDPND TDIEN Timer Interrupt 2 Timer/Counter 2 TnCNT2_n Timer 2 Clock Capture B TCRB_n TBn TBPND TBIEN Timer Interrupt 1 Preset TBEN DS454 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure32-7.InputCapture Plus Timer Mode

32.3 Timer Interrupts

The Multi-FunctionTimerunithas fourinterruptsources,designatedA, B, C, and D. InterruptsourcesA, B, and C are mapped intoa singlesystem interruptcalledTimer Interrupt1,whileinterruptsourceD is mapped intoa system interruptcalledTimer Interrupt2. Each of the fourinterruptsourceshas itsown enablebitand pendingbit.The enablebitsare named TAIEN, TBIEN, TCIEN, and TDIEN. The pending bitsarenamed TAPND, TBPND, TCPND, and TDPND. TimerInterrupts1 and 2 aresysteminterruptsTAn and TBn, respectively. Table32-1 shows theeventsthattriggerinterruptsA, B, C, and D ineach ofthefouroperatingmodes. Note thatsome interruptsourcesarenotused insome operatingmodes.

32.4 Timer I/OFunctions

The Multi-FunctionTimer unituses two I/Opins,calledTAn and TBn. The functionofeach pindepends on thetimeroperatingmode and theTAEN and TBEN enablebits.Table32-2shows thefunctionsofthe pinsineach operatingmode, and foreach combinationofenablebitsettings. When theTAn pinisconfiguredtooperateas a PWM output(TAEN = 1),thestateofthepinistoggledon each underflowof the TCNT1_n counter.In thiscase,the initialvalueon the pinisdeterminedby the TAOUT bit.For example,to startwithTAn high,softwaremust setthe TAOUT bitbeforeenablingthe timerclock.Thisoptionisavailableonlywhen thetimerisconfiguredtooperateinMode 1,3,or 4 (in otherwords,when TCRA_n isnotused inCapturemode). Table32-1.Timer InterruptsOverview Mode 2 Mode 4Interrupt Mode 1 Mode 3Sys.Int. Dual InputCapture + SingleCapture +Pending Bit PWM + Counter Dual CounterCounter Counter TimerInt.1 TAPND TCNT1_n reloadfrom Inputcaptureon TAn TCNT1_n reloadfrom TCNT1_n reloadfrom (TAn Int.) TCRA_n transition TCRA_n TCRA_n TBPND TCNT1_n reloadfrom InputCaptureon TBn N/A InputCaptureon TBn TCRB_n transition transition TCPND N/A TCNT1_n underflow N/A N/A

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www.ti.com SNOSCW5 –MAY 2013 Table32-1.Timer InterruptsOverview (continued) Mode 2 Mode 4Interrupt Mode 1 Mode 3Sys.Int. Dual InputCapture + SingleCapture +Pending Bit PWM + Counter Dual CounterCounter Counter TimerInt.2 TDPND TCNT2_n underflow TCNT2_n underflow TCNT2_n reloadfrom TCNT2_n underflow (TBn Int.) TCRB_n Table32-2.Timer I/OFunctions TAEN Mode 1 Mode 2 Mode 3 Mode 4I/O TBEN PWM + Counter Dual InputCapture + Counter Dual Counter SingleCapture + Counter TAEN = 0 No Output CaptureTCNT1 intoTCRA No OutputToggle No OutputToggleTBEN = X TA TAEN = 1 ToggleOutputon CaptureTCNT1 into ToggleOutputon ToggleOutputon TBEN = X UnderflowofTCNT1 TCRA and PresetTCNT1 UnderflowofTCNT1 UnderflowofTCNT1 TAEN = X Ext.Eventor Ext.Eventor TBEN = 0 PulseAccumulate CaptureTCNT1 intoTCRB PulseAccumulate CaptureTCNT2 intoTCRB Input Input TB TAEN = X Ext.Eventor Ext.EventorCaptureTCNT1 into CaptureTCNT2 intoTBEN = 1 PulseAccumulate PulseAccumulateTCRB and PresetTCNT1 TCRB and PresetTCNT2Input Input

32.5 Timer Registers

Table32-3liststheCPU-accessibleregistersused tocontroltheMulti-FunctionTimers. Table32-3.Multi-FunctionTimer Registers NAME ADDRESS DESCRIPTION TPRSC_0 FF 9010h MFT0 ClockPrescalerRegister TPRSC_1 FF 6010h RMFT1 ClockPrescaleRegister TCKC_0 FF 9014h MFT0 ClockUnitControlRegister TCKC_1 FF 6014h MFT1 ClockUnitControlRegister TCNT1_0 FF 9000h MFT0 Timer/Counter1 Register TCNT1_1 FF 6000h MFT1 Timer/Counter1 Register TCNT2_0 FF 900Ch MFT0 Timer/Counter2 Register TCNT2_1 FF 600Ch MFT1 Timer/Counter2 Register TCRA_0 FF 9004h MFT0 Reload/CaptureA Register TCRA_1 FF 6004h MFT1 Reload/CaptureA Register TCRB_0 FF 9008h MFT0 Reload/CaptureB Register TCRB_1 FF 6008h MFT1 Reload/CaptureB Register TMCTRL_0 FF 9018h MFT0 TimerMode ControlRegister TMCTRL_1 FF 6018h MFT1 TimerMode ControlRegister TICTL_0 FF 901Ch MFT0 TimerInterruptControlRegister TICTL_1 FF 601Ch MFT1 TimerInterruptControlRegister TICLR_0 FF 9020h MFT0 TimerInterruptClearRegister TICLR_1 FF 6020h MFT1 TimerInterruptClearRegister

32.5.1 Clock PrescalerRegistern (TPRSC_n)

The TPRSC_n registerisa byte-wide,read/writeregisterthatholdsthe currentvalueof the 5-bitclock prescaler(CLKPS).Thisregisterisclearedon reset.The registerformatisshown below. Copyright© 2013,Texas InstrumentsIncorporated DualMulti-FunctionTimers 329 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 7 5M M 4 0 Reserved CLKPS CLKPS The ClockPrescalerfieldspecifiesthedivisorused togeneratetheTimerClockfromPCLK Clock.When thetimerisconfiguredtouse theprescaledclock,PCLK Clockisdividedby (CLKPS + 1)toproducethetimerclock.Therefore,thePCLK Clockdivisorcan rangefrom1 to32.

32.5.2 Clock UnitControlRegistern (TCKC_n)

The TCKC_n registeris a byte-wide,read/writeregisterthat selectsthe clock source for each timer/counter.Selectingtheclocksourcealsostartsthecounter.Thisregisterisclearedon reset,which disablesthetimer/counters.The registerformatisshown below. 7 6 5 3 2 0 Reserved C2CSEL C1CSEL C1CSEL The Counter1 ClockSelectfieldspecifiestheclockmode forTimer/Counter1 as follows: 000 – No clock(Timer/Counter1 stopped,modes 1,2,and 3 only). 001 – PrescaledPCLK Clock. 010 – Externaleventon TBn (modes 1 and 3 only). 011 – Pulse-accumulatemode based on TBn (modes 1 and 3 only). 100 – Slow Clock. 101 – Reserved. 110 – Reserved. 111 – Reserved. C2CSEL The Counter2 ClockSelectfieldspecifiestheclockmode forTimer/Counter2 as follows: 000 – No clock(Timer/Counter2 stopped,modes 1,2,and 3 only). 001 – PrescaledPCLK Clock. 010 – Externaleventon TBn (modes 1 and 3 only). 011 – Pulse-accumulatemode based on TBn (modes 1 and 3 only). 100 – Slow Clock. 101 – Reserved. 110 – Reserved. 111 – Reserved.

32.5.3 Timer/Counter1 Registern (TCNT1_n)

The TCNT1_n registerisa 16-bit,read/writeregisterthatholdsthecurrentcountvalueforTimer/Counter 1.The registercontentsarenotaffectedby a resetand areunknown afterpower-up. 15 0 TCNT1

32.5.4 Timer/Counter2 Registern (TCNT2_n)

The TCNT2_n registerisa 16-bit,read/writeregisterthatholdsthecurrentcountvalueforTimer/Counter 2.The registercontentsarenotaffectedby a resetand areunknown afterpower-up. 15 0 TCNT2

32.5.5 Reload/CaptureA Registern (TCRA_n)

The TCRA_n registeris a 16-bit,read/writeregisterthat holds the reload or capture value for Timer/Counter1.The registercontentsarenotaffectedby a resetand areunknown afterpower-up.

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www.ti.com SNOSCW5 –MAY 2013 15 0 TCRA

32.5.6 Reload/CaptureB Registern (TCRB_n)

The TCRB_n registeris a 16-bit,read/writeregisterthat holds the reload or capture value for Timer/Counter2.The registercontentsarenotaffectedby a resetand areunknown afterpower-up. 15 0 TCRB

32.5.7 Timer Mode ControlRegistern (TMCTRL_n)

The TMCTRL_n registeris a byte-wide,read/writeregisterthat sets the operatingmode of the timer/counterand theTAn and TBn pins.Thisregisterisclearedatreset.The registerformatisshown below. 7 6 5 4 3 2 1 0 TEN TAOUT TBEN TAEN TBEDG TAEDG MDSEL MDSEL The Mode Selectfieldsetstheoperatingmode ofthetimer/counteras follows: 00 – Mode 1:PWM plussystemtimer. 01 – Mode 2:Dual-InputCaptureplussystemtimer. 10 – Mode 3:DualTimer/Counter. 11 – Mode 4:Single-InputCaptureand SingleTimer. TAEDG The TAn Edge Polaritybitselectsthepolarityoftheedges thattriggertheTAn input. 0 – TAn inputissensitivetofallingedges (hightolowtransitions). 1 – TAn inputissensitivetorisingedges (lowtohightransitions). TBEDG The TBn Edge Polaritybitselectsthepolarityoftheedges thattriggertheTBn input.Inpulse- accumulatemode, when thisbitisset,thecounterisenabledonlywhen TBn ishigh;when thisbitisclear,thecounterisenabledonlywhen TBn islow. 0 – TBn inputissensitivetofallingedges (hightolowtransitions). 1 – TBn inputissensitivetorisingedges (lowtohightransitions). TAEN The TAn EnablebitcontrolswhethertheTAn pinisenabledtooperateas a presetinputoras a PWM output,dependingon thetimeroperatingmode. InMode 2 (DualInputCapture),a transitionon theTAn pinpresetstheTCNT1_n countertoFFFFh. Intheothermodes, TAn functionsas a PWM output.When thisbitisclear,operationofthepinforthetimer/counteris disabled. 0 – TAn inputdisabled. 1 – TAn inputenabled. TBEN The TBn EnablebitcontrolswhethertheTBn pininenabledtooperateinMode 2 (DualIn- putCapture)orMode 4 (SingleInputCaptureand SingleTimer).A transitionon theTBn pin presetsthecorrespondingtimer/countertoFFFFh (TCNT1_n inMode 2 orTCNT2_n inMode 4).When thisbitisclear,operationofthepinforthetimer/counterisdisabled.Thisbitsetting has no effectinMode 1 orMode 3. 0 – TBn inputdisabled. 1 – TBn inputenabled. TAOUT The TAn OutputData bitindicatesthecurrentstateoftheTAn pinwhen thepinisused as a PWM output.The hardwaresetsand clearsthisbit,butsoftwarecan alsoreadorwritethisbit atany timeand thereforecontrolthestateoftheoutputpin.Incase ofconflict,a software writehas precedenceovera hardwareupdate.Thisbitsettinghas no effectwhen theTAn pin isused as an input. 0 – TAn pinislow. 1 – TAn pinishigh. Copyright© 2013,Texas InstrumentsIncorporated DualMulti-FunctionTimers 331 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com TEN The TimerEnablebitcontrolswhethertheMulti-FunctionTimerisenabled.When themodule isdisabledallclockstothecounterunitarestoppedtominimizepower consump- tion.For thatreason,thetimer/counterregisters(TCNT1_n and TCNT2_n), thecapture/reload registers(TCRA_n and TCRB_n), and theinterruptpendingbits(TXPND) cannotbe writtenin thismode. Also,the5-bitclockprescalerand theinterruptpendingbitsarecleared,and the TAn I/Opinisan input. 0 – Multi-FunctionTimerisdisabled. 1 – Multi-FunctionTimerisenabled.

32.5.8 Timer InterruptControlRegistern (TICTL_n)

The TICTL_n registerisa byte-wide,read/writeregisterthatcontainstheinterruptenablebitsand interrupt pendingbitsforthe fourtimerinterruptsources,designatedA, B, C, and D. The conditionthatcauses each typeofinterruptdepends on theoperatingmode, as shown inTable32-1. Thisregisterisclearedupon reset.The registerformatisshown below. 7 6 5 4 3 2 1 0 TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND TAPND The TimerInterruptSourceA PendingbitindicatesthattimerinterruptconditionA has occurred.Foran explanationofinterruptconditionsA,B,C, and D, see Table32-1.Thisbit can be setby hardwareorby software.To clearthisbit,softwaremust use theTimerInterrupt ClearRegister(TICLR_n).Attemptingtodirectlywritea 0 tothisbitisignored. 0 – InterruptsourceA has nottriggered. 1 – InterruptsourceA has triggered. TBPND The TimerInterruptSourceB PendingbitindicatesthattimerinterruptconditionB has occurred.Foran explanationofinterruptconditionsA,B,C, and D, see Table32-1.Thisbit can be setby hardwareorby software.To clearthisbit,softwaremust use theTimerInterrupt ClearRegister(TICLR_n).Attemptingtodirectlywritea 0 tothisbitisignored. 0 – InterruptsourceB has nottriggered. 1 – InterruptsourceB has triggered. TCPND The TimerInterruptSourceC PendingbitindicatesthattimerinterruptconditionC has occurred.Foran explanationofinterruptconditionsA,B,C, and D, see Table32-1.Thisbit can be setby hardwareorby software.To clearthisbit,softwaremust use theTimerInterrupt ClearRegister(TICLR_n).Attemptingtodirectlywritea 0 tothisbitisignored. 0 – InterruptsourceC has nottriggered. 1 – InterruptsourceC has triggered. TDPND The TimerInterruptSourceD PendingbitindicatesthattimerinterruptconditionD has occurred.Foran explanationofinterruptconditionsA,B,C, and D, see Table32-1.Thisbit can be setby hardwareorby software.To clearthisbit,softwaremust use theTimerInterrupt ClearRegister(TICLR_n).Attemptingtodirectlywritea 0 tothisbitisignored. 0 – InterruptsourceD has nottriggered. 1 – InterruptsourceD has triggered. TAIEN The TimerInterruptA Enablebitcontrolswhetheran interruptisassertedon each occurrence ofinterruptconditionA.Foran explanationofinterruptconditionsA,B,C, and D, see Table32-1. 0 – ConditionA interruptsdisabled. 1 – ConditionA interruptsenabled. TBIEN The TimerInterruptB Enablebitcontrolswhetheran interruptisassertedon each occurrence ofinterruptconditionB.Foran explanationofinterruptconditionsA,B,C, and D, see Table32-1. – ConditionB interruptsdisabled. 1 – ConditionB interruptsenabled.

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www.ti.com SNOSCW5 –MAY 2013 TCIEN The TimerInterruptC Enablebitcontrolswhetheran interruptisassertedon each occurrence ofinterruptconditionC. Foran explanationofinterruptconditionsA,B,C, and D, see Table32-1. 0 – ConditionC interruptsdisabled. 1 – ConditionC interruptsenabled. TDIEN The TimerInterruptD Enablebitcontrolswhetheran interruptisassertedon each occurrence ofinterruptconditionD. Foran explanationofinterruptconditionsA,B,C, and D, see Table32-1. 0 – ConditionD interruptsdisabled. 1 – ConditionD interruptsenabled.

32.5.9 Timer InterruptClearRegistern (TICLR_n)

The TICLR_n registerisa byte-wide,write-onlyregisterthatallowssoftwaretocleartheTAPND, TBPND, TCPND, and TDPND bitsintheTimerInterruptControl(TICTL_n)register.Do notmodifythisregisterwith instructionsthataccess the registeras a read-modify-writeoperand,such as the bitmanipulation instructions.The registerreadsas FFh.The registerformatisshown below. 7 4 3 2 1 0 Reserved TDCLR TCCLR TBCLR TACLR TACLR The TimerPendingA Clearbitisused tocleartheTimerInterruptSourceA Pendingbit (TAPND) intheTimerInterruptControlregiter(TICTL). 0 – Writinga 0 has no effect. 1 – Writinga 1 clearstheTAPND bit. TBCLR The TimerPendingA Clearbitisused tocleartheTimerInterruptSourceB Pendingbit(TB- PND) intheTimerInterruptControlregister(TICTL). 0 – Writinga 0 has no effect. 1 – Writinga 1 clearstheTBPND bit. TCCLR The TimerPendingC Clearbitisused tocleartheTimerInterruptSourceC Pendingbit (TCPND) intheTimerInterruptControlregister(TICTL_n). 0 – Writinga 0 has no effect. 1 – Writinga 1 clearstheTCPND bit. TDCLR The TimerPendingD Clearbitisused tocleartheTimerInterruptSourceD Pendingbit(TD- PND) intheTimerInterruptControlregister(TICTL_n). 0 – Writinga 0 has no effect. 1 – Writinga 1 clearstheTDPND bit. Copyright© 2013,Texas InstrumentsIncorporated DualMulti-FunctionTimers 333 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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33 Dual VersatileTimer Units(VTU)

Each VersatileTimer Unit(VTU) containsfourfullyindependent16-bittimersubsystems.Each timer subsystem can operateeitheras dual8-bitPWM timers,as a single16-bitPWM timer,or as a 16-bit counterwith 2 inputcapturechannels.These timersubsystems offersan 8-bitclockprescalerto accommodate a widerangeofsystemfrequencies. Each ofthetwo VTUs providedon theCP3SP33 offersthefollowingfeatures:

• The VTU can be configuredtoprovide: – Eightfullyindependent8-bitPWM channels – Fourfullyindependent16-bitPWM channels – Eight16-bitinputcapturechannels
• The VTU consistsoffourtimersubsystems,each ofwhichcontains: – A 16-bitcounter – Two 16-bitcapture/compare registers – An 8-bitfullyprogrammableclockprescaler
• Each ofthefourtimersubsystemscan operateinthefollowingmodes: – Low power mode, i.e.,allclocksarestopped – Dual8-bitPWM mode – 16-bitPWM mode – Dual16-bitinputcapturemode
• The VTU controlsa totalofeightI/Opins,each ofwhichcan functionas either: – PWM outputwithprogrammableoutputpolarity – Captureinputwithprogrammableeventdetectionand timerreset
• A flexibleinterruptscheme with – Fourseparatesystemlevelinterruptrequests – A totalof16 interruptsourceseach witha separateinterruptpendingbitand interruptenablebit

33.1 VTU FunctionalDescription

Each VTU iscomprisedoffourtimersubsystems.Each timersubsystemcontainsan 8-bitclockprescaler, a 16-bitup-counter,and two 16-bitregisters.Each timersubsystem controlstwo I/Opinswhich either functionas PWM outputsor captureinputsdependingon themode ofoperation.There are foursystem- levelinterruptrequests,one foreach timersubsystem.Each system-levelinterruptrequestiscontrolledby four interruptpending bitswith associatedenable/disablebits.Allfour timersubsystems are fully independent,and each may operateas a dual8-bitPWM timer,a 16-bitPWM timer,or as a dual16-bit capturetimer.Figure33-1shows themain elementsoftheVTU.

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INTCTL_n 015 MODE_n 015 COUNT1_n TIOn_1 015 PERCAP1_n Compare Capture- DTYCAP1_n Compare Capture- C1 PRSC Timer Subsystem 1 = = Prescaler Counter I/O Control INTPND_n 015 IO1CTL_n 015 IO2CTL_n 015 TIOn_2 I/O Control COUNT2_n TIOn_3 015 PERCAP2_n Compare Capture- DTYCAP2_n Compare Capture- C2 PRSC = = Prescaler Counter I/O Control TIOn_4 I/O Control COUNT4_n TIOn_7 015 PERCAP4_n Compare Capture- DTYCAP4_n Compare Capture- C4RSC = = Prescaler Counter I/O Control TIOn_8 I/O Control COUNT3_n TIOn_5 015 PERCAP3_n Compare Capture- DTYCAP3_n Compare Capture- C3 PRSC = = Prescaler Counter I/O Control TIOn_6 I/O Control Timer Subsystem 2 Timer Subsystem 3 Timer Subsystem 4 DS353 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure33-1.VersatileTimer UnitBlock Diagram

33.1.1 Dual 8-bitPWM Mode

Each timersubsystem may be configuredto generatetwo fullyindependentPWM waveforms on the respectiveTIOx pins.Inthismode, thecounterCOUNTx_n issplitand operatesas two independent8-bit counters.(Inthissection,n istheVTU module number whichiseither0 or1,and x istheVTU subsystem number whichmay be 1 to4.)Each counterincrementsattheratedeterminedby theclockprescaler. Each ofthetwo 8-bitcountersmay be startedand stoppedseparatelyusingthecorrespondingTxRUN bits.Once eitherof the two 8-bittimersisrunning,the clockprescalerstartscounting.Once the clock prescalercountervalue matches the value of the associatedCxPRSC registerfield,COUNTx_n is incremented. The periodof the PWM outputwaveform isdeterminedby the valueof the PERCAPx_n register.The TIOn_y outputstartsatthedefaultvalueas programmed intheIOxCTL_n.PxPOL bit.(Inthissection,y is the TIOn I/Onumber, which may be 1 to 8.)Once the countervaluereachesthe valueof the period registerPERCAPx_n, the counterisclearedon the nextcounterincrement.On the followingincrement from00h to01h,theTIOn_y outputwillchange totheoppositeofthedefaultvalue. The dutycycleof the PWM outputwaveform iscontrolledby the DTYCAPx_n registervalue.Once the countervaluereachesthevalueofthedutycycleregisterDTYCAPx_n, thePWM outputTIOn_y changes back toitsdefaultvalueon thenextcounterincrement.Figure33-2illustratesthisconcept. Copyright© 2013,Texas InstrumentsIncorporated DualVersatileTimerUnits(VTU) 335 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

TIOn_y (PxPOL = 0) DTYCAPx_n TxRUN = 1 COUNTx_n TIOn_y (PxPOL = 1) PERCAPx_n DS354 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure33-2.VTU PWM Generation The periodtimeisdeterminedby thefollowingformula: PWM Period= (PERCAPx_n + 1)× (CxPRSC + 1)× TCLK The dutycycleinpercentiscalculatedas follows: DutyCycle= (DTYCAPx_n /(PERCAPx_n + 1))× 100 Ifthedutycycleregister(DTYCAPx_n) holdsa valuewhich isgreaterthanthevalueheldintheperiod register(PERCAPx_n) the TIOn_y output willremain at the oppositeof itsdefaultvalue which correspondstoa dutycycleof100%. Ifthedutycycleregister(DTYCAPx_n) registerholdsa valueof00h, theTIOn_y outputwillremainatthedefaultvaluewhichcorrespondstoa dutycycleof0%, inwhichcase thevalueinthePERCAPx_n registerisirrelevant.Thisscheme allowsthedutycycletobe programmed in a rangefrom0% to100%. Inordertoallowfullysynchronizedupdatesoftheperiodand dutycyclecompare values,thePERCAPx_n and DTYCAPx_n registersare double bufferedwhen operatingin PWM mode. Therefore,ifsoftware writestoeithertheperiodordutycycleregisterwhileeitherofthetwo PWM channelsisenabled,thenew valuewillnottakeeffectuntilthecountervaluematches thepreviousperiodvalueorthetimerisstopped. ReadingthePERCAPx_n orDTYCAPx_n registerwillalwaysreturnthemost recentvaluewrittentoit. The counterregisterscan be writtenifboth8-bitcountersarestopped.Thisallowssoftwaretopresetthe countersbeforestarting,which can be used to generatePWM outputwaveforms witha phase shift relativetoeach other.Ifthecounteriswrittenwitha valueotherthan00h,itwillstartincrementingfrom thatvalue.The TIOn_y outputwillremain at itsdefaultvalueuntilthe first00h to 01h transitionof the countervalueoccurs.Ifthecounterispresettovalueswhich are lessthanor equaltothevalueheldin theperiodregister(PERCAPx_n) thecounterwillcountup untila match between thecountervalueand the PERCAPx_n registervalue occurs.The counterwillthen be clearedand continuecountingup. Alternatively,thecountermay be writtenwitha valuewhich isgreaterthanthevalueheldintheperiod register.Inthatcase thecounterwillcountup toFFh, thenrolloverto00h.Inany case,theTIOn_y pin alwayschanges itsstateatthe00h to01h transitionofthecounter. Softwaremay onlywritetotheCOUNTx_n registerifbothTxRUN bitsofa timersubsystemareclear.Any writestothecounterregisterwhileeithertimerisrunningwillbe ignored.

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COUNT1_n[15:8]Res 015 [15:8] P2POL TIOn_2 PERCAP1_n[15:8] Compare DTYCAP1_n[15:8] Compare R Q S C1PRSC = = 7 0 Prescaler Counter COUNT1_n[7:0]Res [7:0] P1POL TIOn_1 PERCAP1_n[7:0] Compare DTYCAP1_n[7:0] Compare R Q S T1RUN TMOD1 = 01 T2RUN DS355 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 The two I/Opinsassociatedwitha timersubsystemfunctionareindependentPWM outputsinthedual8- bitPWM mode. Ifa PWM timerisstoppedusingitsassociatedMODE_n.TxRUN bitthefollowingactions result:

• The associatedTIOn_y pinwillreturntoitsdefaultvalueas definedby theIOxCTL_n.PxPOL bit.
• The counterwillstopand willretainitslastvalue.
• Any pendingupdatesofthePERCAPx_n and DTYCAPx_n registerwillbe completed.
• The prescalercounterwillbe stoppedand resetifbothMODE_n.TxRUN bitsarecleared. Figure33-3illustratestheconfigurationofa timersubsystemwhileoperatingindual8-bitPWM mode. The numbering in Figure33-3 refersto timersubsystem 1 but equallyappliesto the otherthreetimer subsystems. Figure33-3.VTU Dual 8-BitPWM Mode 33.1.2 16-BitPWM Mode Each of the fourtimersubsystems may be independentlyconfiguredto providea single16-bitPWM channel.Inthiscase thelowerand upper bytesofthecounterare concatenatedtoform a single16-bit counter. Operationin16-bitPWM mode isconceptuallyidenticaltothedual8-bitPWM operationas outlinedunder Dual 8-bitPWM Mode on page 254. The 16-bittimermay be startedor stopped with the lower MODE_n.TxRUN bit,i.e.,T1RUN fortimersubsystem1. The two TIOn_y outputsassociatedwitha timersubsystem can be used toproduceeithertwo identical PWM waveforms ortwo PWM waveforms ofoppositepolarities.Thiscan be accomplishedby settingthe two PxPOL bitsoftherespectivetimersubsystemtoeitheridenticaloroppositevalues. Figure33-4 illustratestheconfigurationofa timersubsystem whileoperatingin16-bitPWM mode. The numbering in Figure33-4 refersto timersubsystem 1 but equallyappliesto the otherthreetimer subsystems. Copyright© 2013,Texas InstrumentsIncorporated DualVersatileTimerUnits(VTU) 337 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

COUNT1_n[15:0]Restart 015 [15:0] P2POL TIOn_2 PERCAP1_n[15:0] Compare DTYCAP1_n[15:0] Compare R Q S C1PRSC = = 7 0 Prescaler Counter P1POL TIOn_1 R Q S TMOD1 = 10 T1RUN DS356 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure33-4.VTU 1-bitPWM Mode

33.1.3 Dual 16-BitCapture Mode

In additionto the two PWM modes, each timersubsystem may be configuredto operatein an input capturemode which providestwo 16-bitcapturechannels.The inputcapturemode can be used to preciselymeasure theperiodand dutycycleofexternalsignals. In capturemode the counterCOUNTx_n operatesas a 16- bitup-counterwhilethe two TIOn_y pins associatedwitha timersubsystemoperateas captureinputs.A captureeventon theTIOn_y pinscauses the contentsof the counterregister(COUNTx_n) to be copied to the PERCAPx_n or DTYCAPx_n registers,respectively. Startingthecounterisidenticaltothe16-bitPWM mode, i.e.,settingthelowerofthetwo MODE_n.TxRUN bitswillstartthecounterand theclockprescaler.Inaddition,thecaptureeventinputsare enabledonce theMODE_n.TxRUN bitisset. The TIOn_y captureinputscan be independentlyconfiguredtodetecta captureeventon eithera positive transition,a negativetransitionorbotha positiveand a negativetransition.Inaddition,any captureevent may be used toresetthecounterCOUNTx_n and theclockprescalercounter.Thisavoidstheneed for softwareto keep trackof timeroverflowconditionsand greatlysimplifiesthe directfrequencyand duty cyclemeasurement ofan externalsignal. Figure33-5 illustratesthe configurationof a timersubsystem whileoperatingin capturemode. The numbering in Figure33-5 refersto timersubsystem 1 but equallyappliesto the otherthreetimer subsystems.

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COUNT1_n[15:0]Restart 015 15:0 C1EDG PERCAP1_n[15:0] Compare DTYCAP1_n[15:0] Compare C1PRSC = = 7 0 Prescaler Counter rst cap TMOD1=11 T1RUN C2EDG TIOn_2 rst cap DS357 TIOn_1 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure33-5.VTU Dual 16-BitCapture Mode

33.1.4 Low Power Mode

Ifa timersubsystem is not used, softwarecan place itin a low-powermode. Allclocksto a timer subsystem are stopped and the counterand prescalercontentsare frozenonce low-powermode is entered.Softwaremay continuetowritetotheMODE_n, INTCTL_n, IOxCTL_n, and CLKxPS_n registers. WriteoperationstotheINTPND_n registerareallowed;butifa timersubsystemisinlow-powermode, its associatedinterruptpending bitscannot be cleared.Software cannot writeto the COUNTx_n, PERCAPx_n, and DTYCAPx_n registersofa timersubsystemwhileitisinlow-powermode. Allregisters can be readatany time.

33.1.5 Interrupts

Each VTU has a totalof 16 interruptsources,fourforeach of the fourtimersubsystems.Allinterrupt sourceshave a pendingbitand an enablebitassociatedwiththem.Allinterruptpendingbitsaredenoted IxAPD throughIxDPD where “x” relatesto the specifictimersubsystem.There is one system level interruptrequestforeach ofthefourtimersubsystems. Figure33-6illustratestheinterruptstructureoftheversatiletimermodule. Copyright© 2013,Texas InstrumentsIncorporated DualVersatileTimerUnits(VTU) 339 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Figure33-6.VTU InterruptRequest Structure Each ofthetimerpendingbits,IxAPD throughIxDPD, issetby a specifichardwareeventdependingon the mode of operation,i.e.,PWM or Capturemode. Table 33-1 outlinesthe specifichardware events relativetotheoperationmode whichcause an interruptpendingbittobe set. Table33-1.VTU InterruptSources PENDING FLAG DUAL 8-BITPWM MODE 16-BITPWM MODE CAPTURE MODE IxAPD Low ByteDutyCyclematch DutyCyclematch CapturetoPERCAPx_n IxBPD Low BytePeriodmatch Periodmatch CapturetoDTYCAPx_n IxCPD HighByteDutyCyclematch N/A CounterOverflow IxDPD HighBytePeriodmatch N/A N/A

33.1.6 FreezeMode

IfFreeze ismode isentered,alltimercounterclockswillbe inhibitedand thecurrentvalueofthetimer registerswillbe frozen;incapturemode, allfurthercaptureeventsare disabled.Once Freeze mode is exited,countingwillresume fromthepreviousvalueand thecaptureinputeventsarereenabled.

33.2 VTU Registers

Each ofthetwo VTUs has a totalof19 user-accessibleregisters,as listedinTable33-2.Allregistersare word-wideand are initializedto a known valueupon reset.Allsoftwareaccesses to the VTU registers must be word accesses. Table33-2.VTU Registers NAME ADDRESS DESCRIPTION MODE_0 FF 8800h Mode ControlRegisterModule 0 MODE_1 FF 8C00h Mode ControlRegisterModule 1

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www.ti.com SNOSCW5 –MAY 2013 Table33-2.VTU Registers(continued) NAME ADDRESS DESCRIPTION IO1CTL_0 FF 8804h I/OControlRegister1 Module 0 IO1CTL_1 FF 8C04h I/OControlRegister1 Module 1 IO2CTL_0 FF 8808h I/OControlRegister2 Module 0 IO2CTL_1 FF 8C08h I/OControlRegister2 Module 1 INTCTL_0 FF 880Ch InterruptControlRegisterModule 0 INTCTL_1 FF 8C0Ch InterruptControlRegisterModule 1 INTPND_0 FF 8810h InterruptPendingRegisterModule 0 INTPND_1 FF 8C10h InterruptPendingRegisterModule 1 CLK1PS_0 FF 8814h ClockPrescalerRegister1 Module 0 CLK1PS_1 FF 8C14h ClockPrescalerRegister1 Module 1 CLK2PS_0 FF 8830h ClockPrescalerRegister2 Module 0 CLK2PS_1 FF 8C30h ClockPrescalerRegister2 Module 1 COUNT1_0 FF 8818h Counter1 RegisterModule 0 COUNT1_1 FF 8C18h Counter1 RegisterModule 1 PERCAP1_0 FF 881Ch Period/Capture1 RegisterModule 0 PERCAP1_1 FF 8C1Ch Period/Capture1 RegisterModule 1 DTYCAP1_0 FF 8820h DutyCycle/Capture1 RegisterModule 0 DTYCAP1_1 FF 8C20h DutyCycle/Capture1 RegisterModule 1 COUNT2_0 FF 8824h Counter2 RegisterModule 0 COUNT2_1 FF 8C24h Counter2 RegisterModule 1 PERCAP2_0 FF 8828h Period/Capture2 RegisterModule 0 PERCAP2_1 FF 8C28h Period/Capture2 RegisterModule 1 DTYCAP2_0 FF 882Ch DutyCycle/Capture2 RegisterModule 0 DTYCAP2_1 FF 8C2Ch DutyCycle/Capture2 RegisterModule 1 COUNT3_0 FF 8834h Counter3 RegisterModule 0 COUNT3_1 FF 8C34h Counter3 RegisterModule 1 PERCAP3_0 FF 8838h Period/Capture3 RegisterModule 0 PERCAP3_1 FF 8C38h Period/Capture3 RegisterModule 1 DTYCAP3_0 FF 883Ch DutyCycle/Capture3 RegisterModule 0 DTYCAP3_1 FF 8C3Ch DutyCycle/Capture3 RegisterModule 1 COUNT4_0 FF 8840h Counter4 RegisterModule 0 COUNT4_1 FF 8C40h Counter4 RegisterModule 1 PERCAP4_0 FF 8844h Period/Capture4 RegisterModule 0 PERCAP4_1 FF 8C44h Period/Capture4 RegisterModule 1 DTYCAP4_0 FF 8848h DutyCycle/Capture4 RegisterModule 0 DTYCAP4_1 FF 8C48h DutyCycle/Capture4 RegisterModule 1

33.2.1 Mode ControlRegisterModule n (MODE_n)

The MODE_n registersare 16-bit,read/writeregisterswhich controlthemode selectionofthefourtimer subsystemsineach module.The registersareclearafterreset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMOD4 T8RUN T7RUN TMOD3 T6RUN T5RUN TMOD2 T4RUN T3RUN TMOD1 T2RUN T1RUN TxRUN The TimerRun bitcontrolswhetherthecorrespondingtimerisstoppedorrunning.Ifset,the associatedcounterand clockprescalerisstarteddependingon themode ofoperation.Once set,theclocktotheclockprescalerand thecounterareenabledand thecounterwillincrement each timetheclockprescalercountervaluematches thevaluedefinedintheassociatedclock prescalerfield(CxPRSC). Copyright© 2013,Texas InstrumentsIncorporated DualVersatileTimerUnits(VTU) 341 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com 0 – Timerstopped. 1 – Timerrunning. TMODx The TimerSystem OperatingMode fieldenablesordisablestheTimerSubsystem and defines itsoperatingmode. 00 Low-Power Mode. Allclockstothecountersubsystemarestopped.The counteris – stoppedregardlessofthevalueoftheTxRUN bits.Read operationstotheTimer Subsystem willreturnthelastvalue;softwaremust notperformany writeoperationstothe TimerSubsystem whileitisdisabledsincethosewillbe ignored. 01 Dual8-bitPWM mode. Each 8-bitcountermay individuallybe startedorstoppedviaits – associatedTxRUN bit.The TIOn_y pinswillfunctionas PWM outputs. 10 16-bitPWM mode. The two 8-bitcountersareconcatenatedtoforma single16-bit – counter.The countermay be startedorstoppedwiththelowerofthetwo TxRUN bits,i.e,. T1RUN, T3RUN, T5RUN, and T7RUN. The TIOn_y pinswillfunctionas PWM outputs. 11 CaptureMode. Both8-bitcountersareconcatenatedand operateas a single16-bit – counter.The countermay be startedorstoppedwiththelowerofthetwo TxRUN bits,i.e., T1RUN, T3RUN, T5RUN, and T7RUN. The TIOn_y pinswillfunctionas captureinputs.

33.2.2 I/OControlRegister1 Module n (IO1CTL_n)

The IO1CTL_n registersare16-bit,read/writeregisters.The registerscontroltheI/OpinsTIOn_1 through TIOn_4 dependingon theselectedmode ofoperation.The registersareclearafterreset. 15 14 12 11 10 8 7 6 4 3 2 0 P4POL C4EDG P3POL C3EDG P2POL C2EDG P1POL C2EDG CxEDG The CaptureEdge Controlfieldspecifiesthepolarityofa captureeventand theresetofthe counter.The valueofthisthreebitfieldhas no effectwhileoperatinginPWM mode. CxEDG CAPTURE COUNTER RESET

000 Risingedge No

001 Fallingedge No

010 Risingedge Yes

011 Fallingedge Yes

100 Bothedges No

101 Bothedges Risingedge

110 Bothedges Fallingedge

111 Bothedges Bothedges

PxPOL The PWM Polaritybitselectstheoutputpolarity.WhileoperatinginPWM mode thebitspecifies thepolarityofthecorrespondingPWM output(TIOn_y).Once a counterisstopped,theoutput willassume thevalueofPxPOL, i.e.,itsinitialvalue.The PxPOL bithas no effectwhile operatingincapturemode. 0 – The PWM outputgoes highatthe00h to01h transitionofthecounterand willgo low once thecountervaluematches thedutycyclevalue. 1 – The PWM outputgoes lowatthe00h to01h transitionofthecounterand willgo high once thecountervaluematches thedutycyclevalue.

33.2.3 I/OControlRegister2 Module n (IO2CTL_n)

The IO2CTL_n registersare16-bit,read/writeregisters.The registerscontroltheI/OpinsTIOn_5 through TIOn_8 dependingon theselectedmode ofoperation.The registersareclearedatreset.

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www.ti.com SNOSCW5 –MAY 2013 15 14 12 11 10 8 7 6 4 3 2 0 P6POL C8EDG P7POL C7EDG P6POL C6EDG P5POL C5EDG The functionalityof the bitfieldsof the IO2CTL_n registeris identicalto the ones describedin the IO1CTL_n registersection.

33.2.4 InterruptControlRegisterModule n (INTCTL_n)

The INTCTL_n registersare 16-bit,read/writeregisters.They containtheinterruptenablebitsforthe16 interruptsourcesofeach VTU. Each interruptenablebitcorrespondstoan interruptpendingbitlocatedin theInterruptPending Register(INTPND_n).AllINTCTL_n registerbitsare solelyunder softwarecontrol. The registersareclearafterreset. 7 6 5 4 3 2 1 0 I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN 15 14 13 12 11 10 9 8 I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN IxAEN The Timerx InterruptA Enablebitcontrolsinterruptrequeststriggeredon thecorresponding IxAPD bitbeingset.The associatedIxAPD bitwillbe updatedregardlessofthevalueofthe IxAEN bit. 0 – DisablesysteminterruptrequestfortheIxAPD pendingbit. 1 – EnablesysteminterruptrequestfortheIxAPD pendingbit. IxBEN The Timerx InterruptB Enablebitcontrolsinterruptrequeststriggeredon thecorresponding IxBPD bitbeingset.The associatedIxBPD bitwillbe updatedregardlessofthevalueofthe IxBEN bit. 0 – DisablesysteminterruptrequestfortheIxBPD pendingbit. 1 – EnablesysteminterruptrequestfortheIxBPD pendingbit. IxCEN The Timerx InterruptC Enablebitcontrolsinterruptrequeststriggeredon thecorresponding IxCPD bitbeingset.The associatedIxCPD bitwillbe updatedregardlessofthevalueofthe IxCEN bit. 0 – DisablesysteminterruptrequestfortheIxCPD pendingbit. 1 – EnablesysteminterruptrequestfortheIxCPD pendingbit. IxDEN Timerx InterruptD Enablebitcontrolsinterruptrequeststriggeredon thecorrespondingIxDPD bitbeingset.The associatedIxDPD bitwillbe updatedregardlessofthevalueoftheIxDEN bit. 0 – DisablesysteminterruptrequestfortheIxDPD pendingbit. 1 – EnablesysteminterruptrequestfortheIxDPD pendingbit.

33.2.5 InterruptPending RegisterModule n (INTPND_n)

The INTPND_n registersare16-bit,read/writeregisterswhichcontainall16 interruptpendingbits.There are fourinterruptpending bitscalledIxAPD throughIxDPD foreach timersubsystem.Each interrupt pendingbitissetby a hardwareeventand can be clearedifsoftwarewritesa 1 tothebitposition.The valuewillremainunchanged ifa 0 iswrittentothebitposition.Allinterruptpendingbitsare clearedat reset. 7 6 5 4 3 2 1 0 I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD 15 14 13 12 11 10 9 8 I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD Copyright© 2013,Texas InstrumentsIncorporated DualVersatileTimerUnits(VTU) 343 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com IxAPD The Timerx InterruptA Pendingbitindicatesthatan interruptconditionfortherelatedtimer subsystemhas occurred.Table33-1liststhehardwareconditionwhichcausesthisbittobe set. 0 – No interruptpending. 1 – Timerinterruptconditionoccurred. IxBPD The Timerx InterruptB Pendingbitindicatesthatan interruptconditionfortherelatedtimer subsystemhas occurred.Table33-1liststhehardwareconditionwhichcausesthisbittobe set. 0 – No interruptpending. 1 – Timerinterruptconditionoccurred. IxCPD The Timerx InterruptC Pendingbitindicatesthatan interruptconditionfortherelatedtimer subsystemhas occurred.Table33-1liststhehardwareconditionwhichcausesthisbittobe set. 0 – No interruptpending. 1 – Timerinterruptconditionoccurred. IxDPD The Timerx InterruptD Pendingbitindicatesthatan interruptconditionfortherelatedtimer subsystemhas occurred.Table33-1liststhehardwareconditionwhichcausesthisbittobe set. 0 – No interruptpending. 1 – Timerinterruptconditionoccurred.

33.2.6 Clock PrescalerRegister1 Module n (CLK1PS_n)

The CLK1PS_n registersare16-bit,read/writeregisters.The registersaresplitintotwo 8-bitfieldscalled C1PRSC and C2PRSC. Each fieldholdsthe8-bitclockprescalercompare valuefortimersubsystems1 and 2 respectively.The registersareclearedatreset. 15 8M M 7 0 C2PRSC C1PRSC C1PRSC The ClockPrescaler1 Compare Valuefieldholdsthe8-bitprescalervaluefortimersub- system1.The counteroftimersubsystemisincrementedeach timewhen theclockprescaler compare valuematches thevalueoftheclockprescalercounter.The divisionratioisequalto (C1PRSC + 1).Forexample,00h isa ratioof1,and FFh isa ratioof256. C2PRSC The ClockPrescaler2 Compare Valuefieldholdsthe8-bitprescalervaluefortimersub- system2.The counteroftimersubsystemisincrementedeach timewhen theclockprescaler compare valuematches thevalueoftheclockprescalercounter.The divisionratioisequalto (C2PRSC + 1).

33.2.7 Clock PrescalerRegister2 Module n (CLK2PS_n)

The CLK2PS_n registersare16-bit,read/writeregisters.The registersaresplitintotwo 8-bitfieldscalled C3PRSC and C4PRSC. Each fieldholdsthe8-bitclockprescalercompare valuefortimersubsystems3 and 4 respectively.The registersareclearedatreset. 15 8M M 7 0 C3PRSC C4PRSC C4PRSC The ClockPrescaler3 Compare Valuefieldholdsthe8-bitprescalervaluefortimersub- system3.The counteroftimersubsystemisincrementedeach timewhen theclockprescaler compare valuematches thevalueoftheclockprescalercounter.The divisionratioisequalto (C3PRSC + 1). C3PRSC The ClockPrescaler4 Compare Valuefieldholdsthe8-bitprescalervaluefortimersub- system4.The counteroftimersubsystemisincrementedeach timewhen theclockprescaler compare valuematches thevalueoftheclockprescalercounter.The divisionratioisequalto (C4PRSC + 1).

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www.ti.com SNOSCW5 –MAY 2013

33.2.8 Counter Registerx Module n (COUNTx_n)

The COUNTx_n registersare 16-bit,read/writeregisters.There are fourregistersineach module,called COUNT1_n throughCOUNT4_n, one foreach of the fourtimersubsystems.Softwaremay read the registersatany time.Reading theregisterwillreturnthecurrentvalueofthecounter.The registermay onlybe writtenifthecounterisstopped(i.e.,ifbothTxRUN bitsassociatedwitha timersub-system are clear).The registersareclearedatreset. 15 0 CNTx

33.2.9 Period/CaptureRegisterx Module n (PERCAPx_n)

The PERCAPx_n registersare 16-bit,read/writeregisters.There are fourregisterscalledPERCAP1_n throughPERCAP4_n, one foreach timersubsystem.The registersholdtheperiodcompare valueinPWM mode of the countervalueat the timethe lastassociatedcaptureeventoccurred.In PWM mode the registerisdoublebuffered.Ifa new periodcompare valueiswrittenwhilethecounterisrunning,thewrite willnottakeeffectuntilcountervaluematches thepreviousperiodcompare valueor untilthecounteris stopped.Reading may takeplaceatany timeand willreturnthemost recentvaluewhichwas written.The PERCAPx_n registersareclearedatreset. 15 0 PCAPx

33.2.10 Duty Cycle/CaptureRegisterx Module n (DTYCAPx_n)

The DTYCAPx_n registersare 16-bit,read/writeregisters.There are fourregisterscalledDTYCAP1_n throughDTYCAP4_n, one foreach timersubsystem.The registersholdtheperiodcompare valueinPWM mode or the countervalueat the timethe lastassociatedcaptureeventoccurred.In PWM mode, the registerisdoublebuffered.Ifa new dutycyclecompare valueiswrittenwhilethecounterisrunning,the writewillnottakeeffectuntilthecountervaluematches thepreviousperiodcompare valueor untilthe counterisstopped.The updatetakeseffecton periodboundariesonly.Reading may takeplaceatany timeand willreturnthe most recentvaluewhich was written.The DTYCAPx_n registersare clearedat reset. 15 0 DCAPx

34 RegisterMap

Table34-1isa detailedmemory map showingthespecificmemory addressofthememory, I/Oports,and registers.The tableshows thestartingaddress,thesize,and a briefdescriptionofeach memory block and register.For detailedinformationon usingthesememory locations,see theapplicablesectionsinthe datasheet. Alladdressesnotlistedinthetablearereservedand must notbe readorwritten.An attempttoaccessan unlistedaddresswillhave unpredictableresults. Each byte-wideregisteroccupiesa singleaddressand can be accessed onlyina byte-widetransaction. Each wordwide registeroccupiestwo consecutivememory addressesand can be accessed onlyin a word-widetransaction.Both the byte-wideand word-wideregistersresideat word boundaries(even addresses).Therefore,each byte-wideregisteruses onlythelowesteightbitsoftheinternaldatabus. Most deviceregistersare read/writeregisters.However, some registersare read-onlyor write-only,as indicatedinthe table.An attemptto read a write-onlyregisteror to writea read-onlyregisterwillhave unpredictableresults. Copyright© 2013,Texas InstrumentsIncorporated RegisterMap 345 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com When softwarewritestoa registerinwhich one or more bitsare reserved,itmust writea zerotoeach reservedbitunlessindicatedotherwiseinthedescriptionoftheregister.Reading a reservedbitreturnsan undefinedvalue. Table34-1.DetailedDevice Mapping Value AfterRegisterName Size Address Access Type CommentsReset BluetoothLLC Registers PLN Byte 01 2000h Write-Only WHITENING_CHANNEL_SELECTION Byte 01 2001h Write-Only SINGLE_FREQUENCY_SELECTION Byte 01 2002h Write-Only CORRELATOR_CLOCK_SEL Byte 01 2003h Write-Only LN_BT_CLOCK_0 Byte 01 2018h Read-Only LN_BT_CLOCK_1 Byte 01 2019h Read-Only LN_BT_CLOCK_2 Byte 01 201Ah Read-Only LN_BT_CLOCK_3 Byte 01 201Bh Read-Only RX_CN Byte 01 201Ch Read-Only TX_CN Byte 01 201Dh Read-Only AC_ACCEPTLVL Word 01 201Eh Write-Only LAP_ACCEPTLVL Byte 01 2020h Write-Only RFSYNCH_DELAY Byte 01 2021h Write-Only SPI_READ Word 01 2022h Read-Only SPI_MODE_CONFIG Byte 01 2024h Write-Only M_COUNTER_0 Byte 01 2026h Read/Write M_COUNTER_1 Byte 01 2027h Read/Write M_COUNTER_2 Byte 01 2028h Read/Write N_COUNTER_0 Byte 01 202Ah Write-Only N_COUNTER_1 Byte 01 202Bh Write-Only BT_CLOCK_WR_0 Byte 01 202Ch Write-Only BT_CLOCK_WR_1 Byte 01 202Dh Write-Only BT_CLOCK_WR_2 Byte 01 202Eh Write-Only BT_CLOCK_WR_3 Byte 01 202Fh Write-Only WTPTC_1SLOT Word 01 2030h Write-Only WTPTC_3SLOT Word 01 2032h Write-Only WTPTC_5SLOT Word 01 2034h Write-Only SEQ_RESET Byte 01 2036h Write-Only SEQ_CONTINUE Byte 01 2037h Write-Only RX_STATUS Byte 01 2038h Read-Only CHIP_ID Byte 01 203Ah Read-Only INT_VECTOR Byte 01 203Ch Read-Only SYSTEM_CLK_EN Byte 01 203Eh Write-Only LINKTIMER_WR_RD Word 01 2040h Read-Only LINKTIMER_SELECT Byte 01 2042h Read-Only LINKTIMER_STATUS_EXP_FLAG Byte 01 2044h Read-Only LINKTIMER_STATUS_RD_WR_FLAG Byte 01 2045h Read-Only LINKTIMER_ADJUST_PLUS Byte 01 2046h Read-Only LINKTIMER_ADJUST_MINUS Byte 01 2047h Read-Only SLOTTIMER_WR_RD Byte 01 2048h Read-Only RX_CRC Byte 01 204Ah Read-Only RX_CRC Byte 01 204Bh Read-Only AFH_PLN_SEL Byte 01 204Ch Read/Write AFH_SAME_CN_CONFIG Byte 01 204Dh Read/Write AFH_CN_MAP_0 Byte 01 204Eh Read/Write AFH_CN_MAP_1 Byte 01 204Fh Read/Write

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www.ti.com SNOSCW5 –MAY 2013 Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset AFH_CN_MAP_2 Byte 01 2050h Read/Write AFH_CN_MAP_3 Byte 01 2051h Read/Write AFH_CN_MAP_4 Byte 01 2052h Read/Write AFH_CN_MAP_5 Byte 01 2053h Read/Write AFH_CN_MAP_6 Byte 01 2054h Read/Write AFH_CN_MAP_7 Byte 01 2055h Read/Write AFH_CN_MAP_8 Byte 01 2056h Read/Write AFH_CN_MAP_9 Byte 01 2057h Read/Write USB Registers FADDR Byte FF 0800h Read/Write 00h POWER Byte FF 0801h Read/Write 20h INTRTX Word FF 0802h Read-Only 0000h INTRRX Word FF 0804h Read-Only 0000h INTRTXE Word FF 0806h Read/Write 000Fh INTRRXE Word FF 0808h Read/Write 000Eh INTRUSB Byte FF 080Ah Read-Only 00h INTRUSBE Byte FF 080Bh Read/Write 06h FRAME Word FF 080Ch Read-Only 0000h INDEX Byte FF 080Eh Read/Write 00h INDEXED 8-Word FF 0810h-FF 081Fh Read/Write EP0FIFO Dword FF 0820h Read/Write EP1FIFO Dword FF 0824h Read/Write EP2FIFO Dword FF 0828h Read/Write EP3FIFO Dword FF 082Ch Read/Write DEVCTL Byte FF 0860h Read/Write 00h EP0NIND 8-Word FF 0900h-FF 090Fh Read/Write EP1NIND 8-Word FF 0910h-FF 091Fh Read/Write EP2NIND 8-Word FF 0920h-FF 092Fh Read/Write EP3NIND 8-Word FF 0930h-FF 093Fh Read/Write VCTRL Word FF 0C00h Write-Only 0000h VSTATUS Byte FF 0C02h Read-Only 00h XXX CAN Module 0 Message Buffers C0MB0_CNSTAT Word FF B800h Read/Write xxxxh C0MB0_TSTP Word FF B804h Read/Write xxxxh C0MB0_DATA3 Word FF B808h Read/Write xxxxh C0MB0_DATA2 Word FF B80Ch Read/Write xxxxh C0MB0_DATA1 Word FF B810h Read/Write xxxxh C0MB0_DATA0 Word FF B814h Read/Write xxxxh C0MB0_ID0 Word FF B818h Read/Write xxxxh C0MB0_ID1 Word FF B81Ch Read/Write xxxxh C0MB1 16-word FF B820h-FF B83Fh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB2 16-word FF B840h-FF B85Fh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB3 16-word FF B860h-FF B87Fh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB4 16-word FF B880h-FF B89Fh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB5 16-word FF B8A0h-FF B8BFh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB6 16-word FF B8C0h-FF B8DFh Read/Write xxxxh Same registerlayoutas C0MB0. Copyright© 2013,Texas InstrumentsIncorporated RegisterMap 347 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset C0MB7 16-word FF B8E0h-FF B8FFh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB8 16-word FF B900h-FF B91Fh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB9 16-word FF B892h-FF B93Fh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB10 16-word FF B940h-FF B95Fh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB11 16-word FF B960h-FF B97Fh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB12 16-word FF B980-FF B99Fh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB13 16-word FF B9A0h-FF B9BFh Read/Write xxxxh Same registerlayoutas C0MB0. C0MB14 16-word FF B9C0h-FF B9DFh Read/Write xxxxh Same registerlayoutas C0MB0. CAN Module 0 Registers CGCR0 Word FF BA00h Read/Write 0000h CTIM0 Word FF BA04h Read/Write 0000h GMSKX0 Word FF BA08h Read/Write 0000h GMSKB0 Word FF BA0Ch Read/Write 0000h BMSKX0 Word FF BA10h Read/Write 0000h BMSKB0 Word FF BA14h Read/Write 0000h CIEN0 Word FF BA18h Read/Write 0000h CIPND0 Word FF BA1Ch Read-Only 0000h CICLR0 Word FF BA20h Write-Only 0000h CICEN0 Word FF BA24h Read/Write 0000h CSTPND0 Word FF BA28h Read-Only 0000h CANEC0 Word FF BA2Ch Read-Only 0000h CEDIAG0 Word FF BA30h Read-Only 0000h CTMR0 Word FF BA34h Read-Only 0000h CAN Module 1 Message Buffers C1MB0_CNSTAT Word FF BC00h Read/Write xxxxh C1MB0_TSTP Word FF BC04h Read/Write xxxxh C1MB0_DATA3 Word FF BC08h Read/Write xxxxh C1MB0_DATA2 Word FF BC0Ch Read/Write xxxxh C1MB0_DATA1 Word FF BC10h Read/Write xxxxh C1MB0_DATA0 Word FF BC14h Read/Write xxxxh C1MB0_ID0 Word FF BC18h Read/Write xxxxh C1MB0_ID1 Word FF BC1Ch Read/Write xxxxh C1MB1 16-word FF BC20h -FF BC3Fh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB2 16-word FF BC40h -FF BC5Fh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB3 16-word FF BC60h -FF BC7Fh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB4 16-word FF BC80h -FF BC9Fh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB5 16-word FF BCA0h -FF BCBFh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB6 16-word FF BCC0h -FF BCDFh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB7 16-word FF BCE0h -FF BCFFh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB8 16-word FF BD00h -FF BD1Fh Read/Write xxxxh Same registerlayoutas C1MB0.

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www.ti.com SNOSCW5 –MAY 2013 Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset C1MB9 16-word FF B892h -FF BD3Fh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB10 16-word FF BD40h -FF BD5Fh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB11 16-word FF BD60h -FF BD7Fh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB12 16-word FF BD80h -FF BD9Fh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB13 16-word FF BDA0h -FF BDBFh Read/Write xxxxh Same registerlayoutas C1MB0. C1MB14 16-word FF BDC0h -FF BDDFh Read/Write xxxxh Same registerlayoutas C1MB0. CAN Module 1 Registers CGCR1 Word FF BE00h Read/Write 0000h CTIM1 Word FF BE04h Read/Write 0000h GMSKX1 Word FF BE08h Read/Write 0000h GMSKB1 Word FF BE0Ch Read/Write 0000h BMSKX1 Word FF BE10h Read/Write 0000h BMSKB1 Word FF BE14h Read/Write 0000h CIEN1 Word FF BE18h Read/Write 0000h CIPND1 Word FF BE1Ch Read Only 0000h CICLR1 Word FF BE20h WriteOnly 0000h CICEN1 Word FF BE24h Read/Write 0000h CSTPND1 Word FF BE28h Read Only 0000h CANEC1 Word FF BE2Ch Read Only 0000h CEDIAG1 Word FF BE30h Read Only 0000h CTMR1 Word FF BE34h Read Only 0000h Bus Arbiter MASTGP Dword FF F000h Read/Write 0000 0000h ARBALGO Dword FF F004h Read/Write 0000 0001h DFTMASK Dword FF F008h Read/Write 0000 0002h ARBCFGLK Dword FF F00Ch Read/Write 0000 0000h DMA Controller ADCA0 Dword FF 0400h Read/Write 0000 0000h ADRA0 Dword FF 0404h Read/Write 0000 0000h ADCB0 Dword FF 0408h Read/Write 0000 0000h ADRB0 Dword FF 040Ch Read/Write 0000 0000h BLTC0 Dword FF 0410h Read/Write 0000 0000h BLTR0 Dword FF 0414h Read/Write 0000 0000h RQTR0 Dword FF 0418h Read/Write 0000 0000h RQTCNT0 Dword FF 041Ch Read/Write 0000 0000h DMACNT0 Dword FF 0420h Read/Write 000C 0000h DMASTAT0 Dword FF 0424h Read/Write 0000 0000h ADCA1 Dword FF 0440h Read/Write 0000 0000h ADRA1 Dword FF 0444h Read/Write 0000 0000h ADCB1 Dword FF 0448h Read/Write 0000 0000h ADRB1 Dword FF 044Ch Read/Write 0000 0000h BLTC1 Dword FF 0450h Read/Write 0000 0000h BLTR1 Dword FF 0454h Read/Write 0000 0000h RQTR1 Dword FF 0458h Read/Write 0000 0000h RQTCNT1 Dword FF 045Ch Read/Write 0000 0000h DMACNT1 Dword FF 0460h Read/Write 000C 0000h DMASTAT1 Dword FF 0464h Read/Write 0000 0000h Copyright© 2013,Texas InstrumentsIncorporated RegisterMap 349 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset ADCA2 Dword FF 0480h Read/Write 0000 0000h ADRA2 Dword FF 0484h Read/Write 0000 0000h ADCB2 Dword FF 0488h Read/Write 0000 0000h ADRB2 Dword FF 048Ch Read/Write 0000 0000h BLTC2 Dword FF 0490h Read/Write 0000 0000h BLTR2 Dword FF 0494h Read/Write 0000 0000h RQTR2 Dword FF 0498h Read/Write 0000 0000h RQTCNT2 Dword FF 049Ch Read/Write 0000 0000h DMACNT2 Dword FF 04A0h Read/Write 000C 0000h DMASTAT2 Dword FF 04A4h Read/Write 0000 0000h ADCA3 Dword FF 04C0h Read/Write 0000 0000h ADRA3 Dword FF 04C4h Read/Write 0000 0000h ADCB3 Dword FF 04C8h Read/Write 0000 0000h ADRB3 Dword FF 04CCh Read/Write 0000 0000h BLTC3 Dword FF 04D0h Read/Write 0000 0000h BLTR3 Dword FF 04D4h Read/Write 0000 0000h RQTR3 Dword FF 04D8h Read/Write 0000 0000h RQTCNT3 Dword FF 04DCh Read/Write 0000 0000h DMACNT3 Dword FF 04E0h Read/Write 000C 0000h DMASTAT3 Dword FF 04E4h Read/Write 0000 0000h ADCA4 Dword FF 0500h Read/Write 0000 0000h ADRA4 Dword FF 0504h Read/Write 0000 0000h ADCB4 Dword FF 0508h Read/Write 0000 0000h ADRB4 Dword FF 050Ch Read/Write 0000 0000h BLTC4 Dword FF 0510h Read/Write 0000 0000h BLTR4 Dword FF 0514h Read/Write 0000 0000h RQTR4 Dword FF 0518h Read/Write 0000 0000h RQTCNT4 Dword FF 051Ch Read/Write 0000 0000h DMACNT4 Dword FF 0520h Read/Write 000C 0000h DMASTAT4 Dword FF 0524h Read/Write 0000 0000h ADCA5 Dword FF 0540h Read/Write 0000 0000h ADRA5 Dword FF 0544h Read/Write 0000 0000h ADCB5 Dword FF 0548h Read/Write 0000 0000h ADRB5 Dword FF 054Ch Read/Write 0000 0000h BLTC5 Dword FF 0550h Read/Write 0000 0000h BLTR5 Dword FF 0554h Read/Write 0000 0000h RQTR5 Dword FF 0558h Read/Write 0000 0000h RQTCNT5 Dword FF 055Ch Read/Write 0000 0000h DMACNT5 Dword FF 0560h Read/Write 000C 0000h DMASTAT5 Dword FF 0564h Read/Write 0000 0000h ADCA6 Dword FF 0580h Read/Write 0000 0000h ADRA6 Dword FF 0584h Read/Write 0000 0000h ADCB6 Dword FF 0588h Read/Write 0000 0000h ADRB6 Dword FF 058Ch Read/Write 0000 0000h BLTC6 Dword FF 0590h Read/Write 0000 0000h BLTR6 Dword FF 0594h Read/Write 0000 0000h RQTR6 Dword FF 0598h Read/Write 0000 0000h RQTCNT6 Dword FF 059Ch Read/Write 0000 0000h DMACNT6 Dword FF 05A0h Read/Write 000C 0000h DMASTAT6 Dword FF 05A4h Read/Write 0000 0000h ADCA7 Dword FF 05C0h Read/Write 0000 0000h

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www.ti.com SNOSCW5 –MAY 2013 Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset ADRA7 Dword FF 05C4h Read/Write 0000 0000h ADCB7 Dword FF 05C8h Read/Write 0000 0000h ADRB7 Dword FF 05CCh Read/Write 0000 0000h BLTC7 Dword FF 05D0h Read/Write 0000 0000h BLTR7 Dword FF 05D4h Read/Write 0000 0000h RQTR7 Dword FF 05D8h Read/Write 0000 0000h RQTCNT7 Dword FF 05DCh Read/Write 0000 0000h DMACNT7 Dword FF 05E0h Read/Write 000C 0000h DMASTAT7 Dword FF 05E4h Read/Write 0000 0000h ADCA8 Dword FF 0600h Read/Write 0000 0000h ADRA8 Dword FF 0604h Read/Write 0000 0000h ADCB8 Dword FF 0608h Read/Write 0000 0000h ADRB8 Dword FF 060Ch Read/Write 0000 0000h BLTC8 Dword FF 0610h Read/Write 0000 0000h BLTR8 Dword FF 0614h Read/Write 0000 0000h RQTR8 Dword FF 0618h Read/Write 0000 0000h RQTCNT8 Dword FF 061Ch Read/Write 0000 0000h DMACNT8 Dword FF 0620h Read/Write 000C 0000h DMASTAT8 Dword FF 0624h Read/Write 0000 0000h ADCA9 Dword FF 0640h Read/Write 0000 0000h ADRA9 Dword FF 0644h Read/Write 0000 0000h ADCB9 Dword FF 0648h Read/Write 0000 0000h ADRB9 Dword FF 064Ch Read/Write 0000 0000h BLTC9 Dword FF 0650h Read/Write 0000 0000h BLTR9 Dword FF 0654h Read/Write 0000 0000h RQTR9 Dword FF 0658h Read/Write 0000 0000h RQTCNT9 Dword FF 065Ch Read/Write 0000 0000h DMACNT9 Dword FF 0660h Read/Write 000C 0000h DMASTAT9 Dword FF 0664h Read/Write 0000 0000h ADCA10 Dword FF 0680h Read/Write 0000 0000h ADRA10 Dword FF 0684h Read/Write 0000 0000h ADCB10 Dword FF 0688h Read/Write 0000 0000h ADRB10 Dword FF 068Ch Read/Write 0000 0000h BLTC10 Dword FF 0690h Read/Write 0000 0000h BLTR10 Dword FF 0694h Read/Write 0000 0000h RQTR10 Dword FF 0698h Read/Write 0000 0000h RQTCNT10 Dword FF 069Ch Read/Write 0000 0000h DMACNT10 Dword FF 06A0h Read/Write 000C 0000h DMASTAT10 Dword FF 06A4h Read/Write 0000 0000h ADCA11 Dword FF 06C0h Read/Write 0000 0000h ADRA11 Dword FF 06C4h Read/Write 0000 0000h ADCB11 Dword FF 06C8h Read/Write 0000 0000h ADRB11 Dword FF 06CCh Read/Write 0000 0000h BLTC11 Dword FF 06D0h Read/Write 0000 0000h BLTR11 Dword FF 06D4h Read/Write 0000 0000h RQTR11 Dword FF 06D8h Read/Write 0000 0000h RQTCNT11 Dword FF 06DCh Read/Write 0000 0000h DMACNT11 Dword FF 06E0h Read/Write 000C 0000h DMASTAT11 Dword FF 06E4h Read/Write 0000 0000h ADCA12 Dword FF 0700h Read/Write 0000 0000h ADRA12 Dword FF 0704h Read/Write 0000 0000h Copyright© 2013,Texas InstrumentsIncorporated RegisterMap 351 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset ADCB12 Dword FF 0708h Read/Write 0000 0000h ADRB12 Dword FF 070Ch Read/Write 0000 0000h BLTC12 Dword FF 0710h Read/Write 0000 0000h BLTR12 Dword FF 0714h Read/Write 0000 0000h RQTR12 Dword FF 0718h Read/Write 0000 0000h RQTCNT12 Dword FF 071Ch Read/Write 0000 0000h DMACNT12 Dword FF 0720h Read/Write 000C 0000h DMASTAT12 Dword FF 0724h Read/Write 0000 0000h ADCA13 Dword FF 0740h Read/Write 0000 0000h ADRA13 Dword FF 0744h Read/Write 0000 0000h ADCB13 Dword FF 0748h Read/Write 0000 0000h ADRB13 Dword FF 074Ch Read/Write 0000 0000h BLTC13 Dword FF 0750h Read/Write 0000 0000h BLTR13 Dword FF 0754h Read/Write 0000 0000h RQTR13 Dword FF 0758h Read/Write 0000 0000h RQTCNT13 Dword FF 075Ch Read/Write 0000 0000h DMACNT13 Dword FF 0760h Read/Write 000C 0000h DMASTAT13 Dword FF 0764h Read/Write 0000 0000h ADCA14 Dword FF 0780h Read/Write 0000 0000h ADRA14 Dword FF 0784h Read/Write 0000 0000h ADCB14 Dword FF 0788h Read/Write 0000 0000h ADRB14 Dword FF 078Ch Read/Write 0000 0000h BLTC14 Dword FF 0790h Read/Write 0000 0000h BLTR14 Dword FF 0794h Read/Write 0000 0000h RQTR14 Dword FF 0798h Read/Write 0000 0000h RQTCNT14 Dword FF 079Ch Read/Write 0000 0000h DMACNT14 Dword FF 07A0h Read/Write 000C 0000h DMASTAT14 Dword FF 07A4h Read/Write 0000 0000h ADCA15 Dword FF 07C0h Read/Write 0000 0000h ADRA15 Dword FF 07C4h Read/Write 0000 0000h ADCB15 Dword FF 07C8h Read/Write 0000 0000h ADRB15 Dword FF 07CCh Read/Write 0000 0000h BLTC15 Dword FF 07D0h Read/Write 0000 0000h BLTR15 Dword FF 07D4h Read/Write 0000 0000h RQTR15 Dword FF 07D8h Read/Write 0000 0000h RQTCNT15 Dword FF 07DCh Read/Write 0000 0000h DMACNT15 Dword FF 07E0h Read/Write 000C 0000h DMASTAT15 Dword FF 07E4h Read/Write 0000 0000h ExternalBus InterfaceUnit SMCTLR Dword FF 00A4h Read/Write 0000 0401h SCSLR0 Dword FF 0014h Read/Write 0040 0000h SMSKR0 Dword FF 0054h Read/Write 0000 0028h SCSLR1 Dword FF 0018h Read/Write 0080 0000h SMSKR1 Dword FF 0058h Read/Write 0000 0128h SCSLR2 Dword FF 001Ch Read/Write 0100 0000h SMSKR2 Dword FF 005Ch Read/Write 0000 0229h SMTMGR_SET0 Dword FF 0094h Read/Write 0002 0D45h SMTMGR_SET1 Dword FF 0098h Read/Write 0012 0D45h SMTMGR_SET2 Dword FF 009Ch Read/Write 001A 0D45h FLASH_TPRDR Dword FF 00A0h Read/Write 0000 00C8h

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www.ti.com SNOSCW5 –MAY 2013 Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset System Configuration MCFG Byte FF F400h Read/Write 00h MSTAT Byte FF F404h Read-Only ENV2:0 pins Bit6 clearon write SWRESET Byte FF F408h Write-Only N/A SYSCFG Byte FF F40Ch Read/Write 00h CVSD/PCM ConverterModule 0 CVSDIN0 Word FF 4800h Write-Only 0000h CVSDOUT0 Word FF 4804h Read-Only 0000h PCMIN0 Word FF 4808h Write-Only 0000h PCMOUT0 Word FF 480Ch Read-Only 0000h LOGIN0 Byte FF 4810h Write-Only 00h LOGOUT0 Byte FF 4814h Read-Only 00h LINEARIN0 Word FF 4818h Write-Only 0000h LINEAROUT0 Word FF 481Ch Read-Only 0000h CVCTRL0 Word FF 4820h Read/Write 0000h CVSTAT0 Word FF 4824h Read-Only 0000h CVSD/PCM ConverterModule 1 CVSDIN1 Word FF 4C00h Write-Only 0000h CVSDOUT1 Word FF 4C04h Read-Only 0000h PCMIN1 Word FF 4C08h Write-Only 0000h PCMOUT1 Word FF 4C0Ch Read-Only 0000h LOGIN1 Byte FF 4C10h Write-Only 00h LOGOUT1 Byte FF 4C14h Read-Only 00h LINEARIN1 Word FF 4C18h Write-Only 0000h LINEAROUT1 Word FF 4C1Ch Read-Only 0000h CVCTRL1 Word FF 4C20h Read/Write 0000h CVSTAT1 Word FF 4C24h Read-Only 0000h Clock Generationand Power Management PMMCKCTL Byte FF A400h Read/Write 0001 100Xb PMMSTCTL Byte FF A404h Read/Write 00h PMMSR Byte FF A408h Read/Write 0000 00XXb PMMPRSHC Word FF A40Ch Read/Write 001Fh PMMPRSPC Byte FF A410h Read/Write 00h PMMPRSSC Word FF A414h Read/Write 02DBh PMMPLL1CTL1 Word FF A420h Read/Write 0000h PMMPLL1CTL2 Word FF A424h Read/Write 0000h PMMPLL1MDIV Byte FF A428h Read/Write 00h PMMPLL1NDIV Byte FF A42Ch Read/Write 00h PMMPLL1PDIV Byte FF A430h Read/Write 00h PMMPLL1NMOD Word FF A434h Read/Write 0000h PMMPLL1STUP Word FF A438h Read/Write 007Fh PMMPLL2CTL1 Word FF A440h Read/Write 0000h PMMPLL2CTL2 Word FF A444h Read/Write 0000h PMMPLL2MDIV Byte FF A448h Read/Write 00h PMMPLL2NDIV Byte FF A44Ch Read/Write 00h PMMPLL2PDIV Byte FF A450h Read/Write 00h PMMPLL2NMOD Word FF A454h Read/Write 0000h PMMPLL2STUP Word FF A458h Read/Write 007Fh PMMAUX1CTL Byte FF A500h Read/Write 06h PMMAUX1PRSC Word FF A504h Read/Write 00FFh PMMAUX2CTL Byte FF A510h Read/Write 06h Copyright© 2013,Texas InstrumentsIncorporated RegisterMap 353 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset PMMAUX2PRSC Word FF A514h Read/Write 00FFh PMMAUX3CTL Byte FF A520h Read/Write 06h PMMAUX3PRSC Word FF A524h Read/Write 00FFh PMMAUX4CTL Byte FF A530h Read/Write 06h PMMAUX4PRSC Word FF A534h Read/Write 00FFh PMMAUX5CTL Byte FF A540h Read/Write 06h PMMAUX5PRSC Word FF A544h Read/Write 00FFh PMMAUX6CTL Byte FF A550h Read/Write 06h PMMAUX6PRSC Word FF A554h Read/Write 00FFh PMMAUX7CTL Byte FF A560h Read/Write 07h PMMAUX7PRSC Word FF A564h Read/Write 0001h PMMAUX8CTL Byte FF A570h Read/Write 06h PMMAUX8PRSC Word FF A574h Read/Write 00FFh Multi-InputWake-Up WKRPND1 Dword FF C020h Read/Set 0000 0000h WKRPND2 Dword FF C024h Read/Set 0000 0000h WKFPND1 Dword FF C030h Read/Set 0000 0000h WKFPND2 Dword FF C034h Read/Set 0000 0000h WKCLR1 Dword FF C040h Write-Only N/A WKCLR2 Dword FF C044h Write-Only N/A WKREN1 Dword FF C000h Read/Write 0000 0000h WKREN2 Dword FF C004h Read/Write 0000 0000h WKFEN1 Dword FF C010h Read/Write 0000 0000h WKFEN2 Dword FF C014h Read/Write 0000 0000h WKRIEN1 Dword FF C050h Read/Write 0000 0000h WKRIEN2 Dword FF C054h Read/Write 0000 0000h WKFIEN1 Dword FF C060h Read/Write 0000 0000h WKFIEN2 Dword FF C064h Read/Write 0000 0000h WKICTL1 Dword FF C070h Read/Write 0000 0000h WKICTL2 Dword FF C074h Read/Write 0000 0000h WKICTL3 Dword FF C078h Read/Write 0000 0000h WKICTL4 Dword FF C07Ch Read/Write 0000 0000h WKISTAT Dword FF C090h Read/Write 0000 0000h General-PurposeI/OPorts PEDIR Word FF C404h Read/Write 0000h PEDIN Word FF C408h Read-Only XXXXh PEDOUT Word FF C40Ch Read/Write XXXXh PEIEN Word FF C41Ch Read/Write 0000h PEALT Word FF C400h Read/Write 0000h PEALTS Word FF C418h Read/Write 0000h PEWPU Word FF C410h Read/Write 0000h PEPDR Word FF C420h Read/Write FFFFh PFDIR Word FF C804h Read/Write 0000h PFDIN Word FF C808h Read-Only XXXXh PFDOUT Word FF C80Ch Read/Write XXXXh PFIEN Word FF C81Ch Read/Write 0000h PFALT Word FF C800h Read/Write 0000h PFALTS Word FF C818h Read/Write 0000h PFWPU Word FF C810h Read/Write 0000h PFPDR Word FF C820h Read/Write FFFFh PGDIR Word FF 6404h Read/Write 0000h

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www.ti.com SNOSCW5 –MAY 2013 Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset PGDIN Word FF 6408h Read-Only XXXXh PGDOUT Word FF 640Ch Read/Write XXXXh PGIEN Word FF 641Ch Read/Write 0000h PGALT Word FF 6400h Read/Write 0000h PGALTS Word FF 6418h Read/Write 0000h PGWPU Word FF 6410h Read/Write 0000h PGPDR Word FF 6420h Read/Write FFFFh PHDIR Word FF CC04h Read/Write 0000h PHDIN Word FF CC08h Read-Only XXXXh PHDOUT Word FF CC0Ch Read/Write XXXXh PHIEN Word FF CC1Ch Read/Write 0000h PHALT Word FF CC00h Read/Write 0000h PHALTS Word FF CC18h Read/Write 0000h PHWPU Word FF CC10h Read/Write 0000h PHPDR Word FF CC20h Read/Write FFFFh Advanced Audio Interface ARFR Word FF 5000h Read-Only 0000h ARDR0 Word FF 5004h Read-Only 0000h ARDR1 Word FF 5008h Read-Only 0000h ARDR2 Word FF 500Ch Read-Only 0000h ARDR3 Word FF 5010h Read-Only 0000h ATFR Word FF 5014h Write-Only XXXXh ATDR0 Word FF 5018h Write-Only 0000h ATDR1 Word FF 501Ch Write-Only 0000h ATDR2 Word FF 5020h Write-Only 0000h ATDR3 Word FF 5024h Write-Only 0000h AGCR Word FF 5028h Read/Write 0000h AISCR Word FF 502Ch Read/Write 0000h ARSCR Word FF 5030h Read/Write 0000h Becomes 0004h after enablingclock. ATSCR Word FF 5034h Read/Write F000h Becomes F003h after enablingclock. ACCR Word FF 5038h Read/Write 0000h ADMACR Word FF 503Ch Read/Write 0000h InterruptControlUnit IVECT Dword FF FE00h Read-Only 0000 0010h FixedAddr. NMISTAT Dword FF FE04h Read-Only 0000 0000h EXNMI Dword FF FE08h Read/Write 0000 0000h ISTR0 Dword FF FE10h Read-Only 0000 0000h ISTR1 Dword FF FE14h Read-Only 0000 0000h ISTR2 Dword FF FE18h Read-Only 0000 0000h IENR0 Dword FF FE20h Read/Write 0000 0000h IENR1 Dword FF FE24h Read/Write 0000 0000h IENR2 Dword FF FE28h Read/Write 0000 0000h SOFTR0 Dword FF FE40h Read/Write 0000 0000h SOFTR1 Dword FF FE44h Read/Write 0000 0000h SOFTR2 Dword FF FE48h Read/Write 0000 0000h INTGPAR0 Dword FF FE50h Read/Write 0000 0000h INTGPBR0 Dword FF FE54h Read/Write 0000 0000h INTGPAR1 Dword FF FE58h Read/Write 0000 0000h INTGPBR1 Dword FF FE5Ch Read/Write 0000 0000h Copyright© 2013,Texas InstrumentsIncorporated RegisterMap 355 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset INTGPAR2 Dword FF FE60h Read/Write 0000 0000h INTGPBR2 Dword FF FE64h Read/Write 0000 0000h IDBG Dword FF FEFCh Read-Only 0000 0000h UART0 U0TBUF Byte FF 9400h Read/Write XXh U0RBUF Byte FF 9404h Read-Only XXh U0ICTRL Byte FF 9408h Read/Write 01h Bits0:1readonly U0STAT Byte FF 940Ch Read-Only 00h U0FRS Byte FF 9410h Read/Write 00h U0MDSL1 Byte FF 9414h Read/Write 00h U0BAUD Byte FF 9418h Read/Write 00h U0PSR Byte FF 941Ch Read/Write 00h U0OVR Byte FF 9420h Read/Write 00h U0MDSL2 Byte FF 9424h Read/Write 00h U0SPOS Byte FF 9428h Read/Write 06h UART1 U1TBUF Byte FF 9800h Read/Write XXh U1RBUF Byte FF 9804h Read-Only XXh U1ICTRL Byte FF 9808h Read/Write 01h Bits0:1readonly U1STAT Byte FF 980Ch Read-Only 00h U1FRS Byte FF 9810h Read/Write 00h U1MDSL1 Byte FF 9814h Read/Write 00h U1BAUD Byte FF 9818h Read/Write 00h U1PSR Byte FF 981Ch Read/Write 00h U1OVR Byte FF 9820h Read/Write 00h U1MDSL2 Byte FF 9824h Read/Write 00h U1SPOS Byte FF 9828h Read/Write 06h UART2 U2TBUF Byte FF 9C00h Read/Write XXh U2RBUF Byte FF 9C04h Read-Only XXh U2ICTRL Byte FF 9C08h Read/Write 01h Bits0:1readonly U2STAT Byte FF 9C0Ch Read-Only 00h U2FRS Byte FF 9C10h Read/Write 00h U2MDSL1 Byte FF 9C14h Read/Write 00h U2BAUD Byte FF 9C18h Read/Write 00h U2PSR Byte FF 9C1Ch Read/Write 00h U2OVR Byte FF 9C20h Read/Write 00h U2MDSL2 Byte FF 9C24h Read/Write 00h U2SPOS Byte FF 9C28h Read/Write 06h UART3 U3TBUF Byte FF 5C00h Read/Write XXh U3RBUF Byte FF 5C04h Read-Only XXh U3ICTRL Byte FF 5C08h Read/Write 01h Bits0:1readonly U3STAT Byte FF 5C0Ch Read-Only 00h U3FRS Byte FF 5C10h Read/Write 00h U3MDSL1 Byte FF 5C14h Read/Write 00h U3BAUD Byte FF 5C18h Read/Write 00h U3PSR Byte FF 5C1Ch Read/Write 00h U3OVR Byte FF 5C20h Read/Write 00h U3MDSL2 Byte FF 5C24h Read/Write 00h U3SPOS Byte FF 5C28h Read/Write 06h

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www.ti.com SNOSCW5 –MAY 2013 Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset Microwire/SPIInterfaces MW0DAT Word FF 8400h Read/Write XXXXh MW0CTL1 Word FF 8404h Read/Write 0000h MW0STAT Word FF 8408h Read-Only Allimplementedbitsare0 MW1DAT Word FF 5800h Read/Write xxxxh MW1CTL1 Word FF 5804h Read/Write 0000h MW1STAT Word FF 5808h Read-Only Allimplementedbitsare0 ACCESS.bus Module 0 ACB0SDA Byte FF 8000h Read/Write XXh ACB0ST Byte FF 8004h Read/Write 00h ACB0CST Byte FF 8008h Read/Write 00h ACB0CTL1 Byte FF 800Ch Read/Write 00h ACB0ADDR Byte FF 8010h Read/Write XXh ACB0CTL2 Byte FF 8014h Read/Write 00h ACB0ADDR2 Byte FF 8018h Read/Write XXh ACB0CTL3 Byte FF 801Ch Read/Write 00h ACCESS.bus Module 1 ACB1SDA Byte FF 5400h Read/Write XXh ACB1ST Byte FF 5404h Read/Write 00h ACB1CST Byte FF 5408h Read/Write 00h ACB1CTL1 Byte FF 540Ch Read/Write 00h ACB1ADDR Byte FF 5410h Read/Write XXh ACB1CTL2 Byte FF 5414h Read/Write 00h ACB1ADDR2 Byte FF 5418h Read/Write XXh ACB1CTL3 Byte FF 541Ch Read/Write 00h Timing and Watchdog Module TWCFG Byte FF A000h Read/Write 00h TWCP Byte FF A004h Read/Write 00h TWMT0 Word FF A008h Read/Write FFFFh T0CSR Byte FF A00Ch Read/Write 00h WDCNT Byte FF A010h Write-Only 0Fh WDSDM Byte FF A014h Write-Only 5Fh Multi-FunctionTimer Module 0 TCNT1_0 Word FF 9000h Read/Write XXXXh TCRA_0 Word FF 9004h Read/Write XXXXh TCRB_0 Word FF 9008h Read/Write XXXXh TCNT2_0 Word FF 900Ch Read/Write XXXXh TPRSC_0 Byte FF 9010h Read/Write 00h TCKC_0 Byte FF 9014h Read/Write 00h TMCTRL_0 Byte FF 9018h Read/Write 00h TICTL_0 Byte FF 901Ch Read/Write 00h TICLR_0 Byte FF 9020h Write-Only FFh Multi-FunctionTimer Module 1 TCNT1_1 Word FF 6000h Read/Write XXXXh TCRA_1 Word FF 6004h Read/Write XXXXh TCRB_1 Word FF 6008h Read/Write XXXXh TCNT2_1 Word FF 600Ch Read/Write XXXXh TPRSC_1 Byte FF 6010h Read/Write 00h TCKC_1 Byte FF 6014h Read/Write 00h TMCTRL_1 Byte FF 6018h Read/Write 00h TICTL_1 Byte FF 601Ch Read/Write 00h Copyright© 2013,Texas InstrumentsIncorporated RegisterMap 357 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset TICLR_1 Byte FF 6020h Write-Only FFh VersatileTimer UnitModule 0 MODE_0 Word FF 8800h Read/Write 0000h IO1CTL_0 Word FF 8804h Read/Write 0000h IO2CTL_0 Word FF 8808h Read/Write 0000h INTCTL_0 Word FF 880Ch Read/Write 0000h INTPND_0 Word FF 8810h Read/Write 0000h CLK1PS_0 Word FF 8814h Read/Write 0000h COUNT1_0 Word FF 8818h Read/Write 0000h PERCAP1_0 Word FF 881Ch Read/Write 0000h DTYCAP1_0 Word FF 8820h Read/Write 0000h COUNT2_0 Word FF 8824h Read/Write 0000h PERCAP2_0 Word FF 8828h Read/Write 0000h DTYCAP2_0 Word FF 882Ch Read/Write 0000h CLK2PS_0 Word FF 8830h Read/Write 0000h COUNT3_0 Word FF 8834h Read/Write 0000h PERCAP3_0 Word FF 8838h Read/Write 0000h DTYCAP3_0 Word FF 883Ch Read/Write 0000h COUNT4_0 Word FF 8840h Read/Write 0000h PERCAP4_0 Word FF 8844h Read/Write 0000h DTYCAP4_0 Word FF 8848h Read/Write 0000h VersatileTimer UnitModule 1 MODE_1 Word FF 8C00h Read/Write 0000h IO1CTL_1 Word FF 8C04h Read/Write 0000h IO2CTL_1 Word FF 8C08h Read/Write 0000h INTCTL_1 Word FF 8C0Ch Read/Write 0000h INTPND_1 Word FF 8C10h Read/Write 0000h CLK1PS_1 Word FF 8C14h Read/Write 0000h COUNT1_1 Word FF 8C18h Read/Write 0000h PERCAP1_1 Word FF 8C1Ch Read/Write 0000h DTYCAP1_1 Word FF 8C20h Read/Write 0000h COUNT2_1 Word FF 8C24h Read/Write 0000h PERCAP2_1 Word FF 8C28h Read/Write 0000h DTYCAP2_1 Word FF 8C2Ch Read/Write 0000h CLK2PS_1 Word FF 8C30h Read/Write 0000h COUNT3_1 Word FF 8C34h Read/Write 0000h PERCAP3_1 Word FF 8C38h Read/Write 0000h DTYCAP3_1 Word FF 8C3Ch Read/Write 0000h COUNT4_1 Word FF 8C40h Read/Write 0000h PERCAP4_1 Word FF 8C44h Read/Write 0000h DTYCAP4_1 Word FF 8C48h Read/Write 0000h SDC ADCGCR Word FF AC00h Read/Write 0000h ADCACR Word FF AC04h Read/Write 0000h ADCCNTRL Word FF AC08h Read/Write 0000h ADCSTART Word FF AC0Ch Write-Only N/A ADCSCDLY Word FF AC10h Read/Write 0000h ADCRESLT Word FF AC14h Read-Only 0000h I2S Interface I2SCLK Dword FF 4000h Read/Write 0007 0000h

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www.ti.com SNOSCW5 –MAY 2013 Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset I2SRXCTL Dword FF 4004h Read/Write 0000 001Ch I2STXCTL Dword FF 4008h Read/Write 0000 001Ch I2SSTAT Dword FF 401Ch Read/Write 0000 0808h I2STXDATALEFT Dword FF 400Ch Write-Only 0000 0000h I2STXDATARIGHT Dword FF 4010h Write-Only 0000 0000h I2SRXDATALEFT Dword FF 4014h Read-Only 0000 0000h I2SRXDATARIGHT Dword FF 4018h Read-Only 0000 0000h Audio Subsystem Controller ADMAC Word FF 6820h Read/Write 0000h ADMAS Word FF 681Ch Read-Only 0000h ASCINTSEL Word FF 6818h Read/Write 0000h ASCDMASEL0 Word FF 6800h Read/Write 0000h ASCDMASEL1 Word FF 6804h Read/Write 0000h ASCDDMASEL0 Word FF 6808h Read/Write 0000h ASCDDMASEL1 Word FF 680Ch Read/Write 0000h ASCDDMASEL2 Word FF 6810h Read/Write 0000h ASCDDMASEL3 Word FF 6814h Read/Write 0000h DSP Interface PDATA Word FF EC00h Read/Write 0000h PADR Word FF EC04h Write-Only 0000h PCFG Word FF EC08h Read/Write 0000h PSTS Word FF EC0Ch Read-Only 0000h PSEM Word FF EC10h Read/Write 0000h PMASK Word FF EC14h Read/Write 0000h PCLEAR Word FF EC18h Write-Only 0000h APBP_SEM Word FF EC1Ch Read-Only 0000h APBP_COM0 Word FF EC20h Read/Write 0000h APBP_REP0 Word FF EC24h Read-Only 0000h APBP_COM1 Word FF EC28h Read/Write 0000h APBP_REP1 Word FF EC2Ch Read-Only 0000h APBP_COM2 Word FF EC30h Read/Write 0000h APBP_REP2 Word FF EC34h Read-Only 0000h TelematicsCodec TCDCBASIC Word FF 4400h Read/Write 0000h TCDCDACSTATUS Word FF 4404h Read-Only 1010h TCDCADCSTATUS Word FF 4408h Read-Only 1010h TCDCDSP Word FF 440Ch Read/Write 0000h TCDCADCANA1 Word FF 4410h Read/Write 0000h TCDCADCANA2 Word FF 4414h Read/Write 0000h TCDCADC1CLK Word FF 4418h Read/Write 0000h TCDCADC2CLK Word FF 441Ch Read/Write 0000h TCDCDACCLK Word FF 4420h Read/Write 0000h TCDCFIFO Word FF 4424h Read/Write 0000h TCDCIRQEN Word FF 4428h Read/Write 0000h TCDCIRQPNDCLR Word FF 442Ch Read/Write 0000h TCDCCOMPC0 Word FF 4430h Read/Write 0000h TCDCCOMPC1 Word FF 4434h Read/Write 0000h TCDCCOMPC2 Word FF 4438h Read/Write 0000h TCDCDEBUG Word FF 443Ch Read/Write 0000h TCDCADC1 Word FF 4448h Read-Only 0000h TCDCADC2 Word FF 444Ch Read-Only 0000h Copyright© 2013,Texas InstrumentsIncorporated RegisterMap 359 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table34-1.DetailedDevice Mapping (continued) Value AfterRegisterName Size Address Access Type CommentsReset TCDCLEFT Word FF 4450h Read/Write 0000h TCDCRIGHT Word FF 4454h Read/Write 0000h TCDCMONITOR Word FF 4458h Read/Write 0000h Real Time Clock RTCCST Byte FF A800h Read/Write 00h RTUDST Byte FF A804h Read-Only 00h RTCEIST Byte FF A8008h Read/Write 00h RTCIEN Byte FF A80Ch Read/Write 00h RTPRD Word FF A810h Read-Only 0000h RTCRD Dword FF A814h Read-Only 0000 0001h RTCLD Dword FF A818h Read/Write 0000 0000h RTCCMP1 Word FF A81Ch Read/Write 7FFFh RTCCMP2 Dword FF A820h Read/Write FFFF FFFFh RTCCMP3 Dword FF A824h Read/Write FFFF FFFFh

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www.ti.com SNOSCW5 –MAY 2013

35 RegisterBitFields

The followingtablesshow thefunctionsofthebitfieldsofthedeviceregisters.For more informationon usingtheseregisters,see thedetailed descriptionoftheapplicablefunctionelsewhereinthisdatasheet. Thisparagraphisforspace between tableand firstparagraph BluetoothLLC Registers 7 6 5 4 3 2 1 0 PLN Reserved PLN2:0 WHITENING_ CHANNEL_ Reserved CHANNEL_ SELECTION1:0 WHITENINGSELECTION SINGLE_FREQUENCY Reserved SINGLE_FREQUENCY_SEL6:0_SELECTION CORRELATOR_CLOCK _SEL Reserved CDEL Reserved CCS LN_BT_CLOCK_0 LN_BT_CLOCK7:0 LN_BT_CLOCK_1 LN_BT_CLOCK15:8 LN_BT_CLOCK_2 LN_BT_CLOCK23:16 LN_BT_CLOCK_3 Reserved LN_BT_CLOCK27:23 RX_CN Reserved RX_CN6:0 TX_CN Reserved TX_CN6:0 AC_ACCEPTLVL[7:0] AC_ACCEPTLVL7:0 AC_ACCEPTLVL[15:8] Reserved AC_ACCEPTLVL9:8 LAP_ACCEPTLVL Reserved LAP_ACCEPTLVL5:0 RFSYNCH_DELAY Reserved RFSYNCH_DELAY5:0 SPI_READ[7:0] SPI_READ7:0 SPI_READ[15:8] SPI_READ15:8 SPI_MODE_CONFIG Reserved SPI_CLK_CONF1:0 SPI_LEN_ CONF SPI_DATA _CONF3 SPI_DATA _CONF2 SPI_DATA_ CONF1 M_COUNTER_0 M_COUNTER7:0 M_COUNTER_1 M_COUNTER15:8 M_COUNTER_2 Reserved FORCE_ WAKEUP M_COUNTER20:16 N_COUNTER_0 N_COUNTER7:0 N_COUNTER_1 Reserved N_COUNTER9:8 BT_CLOCK_WR_0 BT_CLOCK_WR7:1 Reserved BT_CLOCK_WR_1 BT_CLOCK_WR15:8 BT_CLOCK_WR_2 BT_CLOCK_WR23:16 BT_CLOCK_WR_3 Reserved BT_CLOCK_WR27:24 WTPTC_1SLOT[7:0] WTPTC_1SLOT7:0 WTPTC_1SLOT[15:8] WTPTC_1SLOT15:8 WTPTC_3SLOT[7:0] WTPTC_3SLOT7:0 WTPTC_3SLOT[15:8] WTPTC_3SLOT15:8 WTPTC_5SLOT[7:0] WTPTC_5SLOT7:0 Copyright© 2013,Texas InstrumentsIncorporated RegisterBitFields 361 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com BluetoothLLC Registers 7 6 5 4 3 2 1 0 WTPTC_5SLOT[15:8] WTPTC_5SLOT15:8 SEQ_RESET Reserved SEQ_RESET SEQ_CONTINUE Reserved SEQ_ CONTINUE Header Error PayloadErrorRX_STATUS Reserved HEC Error AM_ ADDR Error PayloadCRC Error PayloadLengthError PACKET_ DONECorrection Correction CHIP_ID Reserved CHIP_ID INT_VECTOR INT_VECTOR7:0 SYSTEM_CLK_EN Reserved CLK_EN3 CLK_EN2 INT_SEQ_ EN CLK_EN1 LINK_TIMER_WR_RD[7:0] LINKTIMER_WR_RD7:0 LINK_TIMER_WR_RD[15:8] LINKTIMER_WR_RD15:8 LINK_TIMER_SELECT Reserved LINKTIMER_SELECT LINK_TIMER_STATUS_ LINK_TIMER_STATUS_EXP_FLAG7:0EXP_FLAG LINK_TIMER_STATUS_ LINK_ TIMER LINK_ TIMER_ReservedRD_WR_FLAG _WRITE_ DONE READ_ VALID LINK_TIMER_ADJUST_PLUS LINKTIMER_ADJUST_PLUS7:0 LINK_TIMER_ADJUST_MINUS LINKTIMER_ADJUST_MINUS7:0 SLOTTIMER_WR_RD Reserved SLOT_TIMER_WR_RD5:0 RX_CRC RX_CRC AFH_PLN_SEL Reserved AFH_PLN_SEL AFH_SAME_CN_CONFIG Reserved HOP_ CALC_TX SCDIS AFH_CN_MAP_0 CHANNEL_NUMBER7:0 AFH_CN_MAP_1 CHANNEL_NUMBER15:8 AFH_CN_MAP_2 CHANNEL_NUMBER23:16 AFH_CN_MAP_3 CHANNEL_NUMBER31:24 AFH_CN_MAP_4 CHANNEL_NUMBER39:32 AFH_CN_MAP_5 CHANNEL_NUMBER47:40 AFH_CN_MAP_6 CHANNEL_NUMBER55:48 AFH_CN_MAP_7 CHANNEL_NUMBER63:56 AFH_CN_MAP_8 CHANNEL_NUMBER71:64 AFH_CN_MAP_9 AFH_EN CHANNEL_NUMBER78:72

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www.ti.com SNOSCW5 –MAY 2013 USB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Controller FADDR Reserved 0 FunctionAddress POWER Reserved ISUP SC Reserved RST RESU SUSP ENSP INTRTX Reserved EPTX3:1 EP0 INTRRX Reserved EPRX3:1 Res. INTRTXE Reserved EPTX3:1 EP0 INTRRXE Reserved EPRX3:1 Res. INTRUSB Reserved VBER SESR DISC CON SOF RST BABL RESU SUSP INTRUSBE Reserved VBER SESR DISC CON SOF RST BABL RESU SUSP FRAME Reserved FRAME10:0 INDEX Reserved EP3:0 DEVCTL Reserved BD FSD LSD VBUS HM HRQ SESS CSR0 0 FF SSE SRP SDS SUE DE STS TPR RPR TXMAXP Reserved MAX_PAYLOAD TXCSR AS ISO MODE DMAEN FDT DMAMD 0 ICTX CDAT STS SDS FF UR FNE TPR RXMAXP Reserved MAX_PAYLOAD DMAMRXCSR AS ISO DMAEN DN 0 ICTX CDAT STS SDS FF DE OR FF RPRD RXCNT Reserved EPRX_CNT11:0 VCTRL DWEN ADDRESS DATA FORCESUSPOTG SUSP FORCEVSTATUS Reserved _SUSPC_CTRL _CTRL _SUSP TRL Copyright© 2013,Texas InstrumentsIncorporated RegisterBitFields 363 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com CAN Control/ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Status INTE LOOP BUFFCGCRn Reserved EIT DIA GEN IGN ACK LO DD IR TST PEN CRX CTX CAN ENRNAL BACK LOCK CTIMn PSC6:0 SJW1:0 TSEG1[3:0] TSEG2[2:0] GMSKBn GM28:18 RTR IDE GM17:15 GMSKXn GM14:0 XRTR BMSKBn BM28:18 RTR IDE BM17:15 BMSKXn BM14:0 XRTR CIENn EIEN IEN14:0 CIPNDn EIPND IPND14:0 CICLRn EICLR ICLR14:0 CICENn EICEN ICEN14:0 CSTPNDn Reserved NS2:0 IRQ IST3:0 CANECn REC7:0 TEC7:0 CEDIAGn Res. DRIVE MON CRC STUFF TXE EBID5:0 EFID3:0 CTMRn CTMR15:0 Thisparagraphisused forspace between tables CAN Memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Registers XI28 XI27 XI26 XI25 XI24 XI23 XI22 XI21 XI20 XI19 XI18 SRRCnMBn.ID1 IDE XI17 XI16 XI15ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR CnMBn.ID0 XI14 XI13 XI12 XI11 XI10 XI9 XI8 XI7 XI6 XI5 XI4 XI3 XI2 XI1 XI0 RTR CnMBn. Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data CnMBn. Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data CnMBn. TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CnMBn. DLC3 DLC2 DLC1 DLC0 Reserved PRI3 PRI2 PRI1 PRI0 ST3 ST2 ST1 ST0CNTSTAT Thisparagraphisused forspace between tables EBIU Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCSLRn (low) Reserved SCSLRn (high) EXT_BASE_ADDRESS31:15 SMSKRn (low) Reserved REG_SEL MEM_TYPE MEM_SIZE SMSKRn (high) Reserved SMTMGR_SETn (low) T_WP T_WR T_AS T_RC SMTMGR_SETn (high) Reserved SMRP Reserved PS PM T_PRC T_BTA FLASH_TRPDR (low) Reserved T_RPD FLASH_TRPDR (high) Reserved SMCTLR (low) SM_DW_S2 SM_DW_S1 SM_DW_S0 Reserved SMCTLR (high) Reserved Thisparagraphisused forspace between tables

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www.ti.com SNOSCW5 –MAY 2013 DMAC Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAn (low) ADCAn15:0 ADCAn (high) ADCAn31:16 ADRAn (low) ADRAn15:0 ADRAn (high) ADRAn31:16 ADCBn (low) ADCBn15:0 ADCBn (high) ADCBn31:16 ADRBn (low) ADRBn15:0 ADRBn (high) ADRBn31:16 BLTCn (low) BLTCn15:0 BLTCn (high) BLTCn31:16 BLTRn (low) BLTRn15:0 BLTRn (high) BLTRn31:16 RQTRn (low) RQTRn15:0 RQTRn (high) Reserved RQTCNTn (low) RQTCNTn15:0 RQTCNTn (high) Reserved SWRDMACNTn (low) WMO DE INCB ADB INCA ADA BPC OT DIR TCS ETO EOVR ETC CHENQ DMACNTn (high) Reserved SRCRQ TOEN HPROT PF BBE DMASTATn (low) Reserved TO BLV Reserved BNE ERR VLD CHAC OVR TC DMASTATn (high) Reserved Thisparagraphisused forspace between tables Bus Arbiter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Registers MASTGP (low) Reserved MAS4 MAS3 MAS2 MASTGP (high) Reserved ARBALGO (low) Reserved GRD GRC GRB GRA ARBALGO (high) Reserved DFTMAST (low) Reserved DFTMAST DFTMAST (high) Reserved ARBCFGLK (low) Reserved LOCK ARBCFGLK (high) Reserved Thisparagraphisused forspace between tables System Configuration 7 6 5 4 3 2 1 0 Registers MCFG Reserved FREEZE Reserved ENV1SEL ENV0SEL ENV1OE ENV0OE MSTAT ISPRST WDRST Reserved OENV1 OENV0 SWRESET Key Values BTHCLKDISYSCFG XDPUDIS Reserved USBIDDIG-PUEN USBHCLKDIS RFCKENS Thisparagraphisused forspace between tables CVSD/PCM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Registers CVSDINn CVSDIN CVSDOUTn CVSDOUT PCMINn PCMIN PCMOUTn PCMOUT LOGINn Reserved LOGIN LOGOUTn Reserved LOGOUT Copyright© 2013,Texas InstrumentsIncorporated RegisterBitFields 365 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com CVSD/PCM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Registers LINEARINn LINEARIN LINEAROUTn LINEAROUT CVSCV RESOLUTI PCMCO DMA DMA DMA DMAC CVS PCMI CLKCVCTRLn Res. CVSDCONV DER CVENFR ON NV PI PO CI O DINT NT ENRINT PCMI CVNCVSTATn Reserved CVOUTST CVINST CVF CVE CVNENT F Thisparagraphisused forspace between tables 7 6 5 4 3 2 1 0 Clock and PMM Registers 15 14 13 12 11 10 9 8 PMMCKCTL Reserved FCLKSRC SCLK MAIN_DCOE POR PMMSTCTL DSC WACK HCCM DMC WBPSM HALT IDLE PSM PMMSR Reserved MCLKSTB SCLKSTB PMMPRSHC (low) HPHCLK7:0 PMMPRSHC (high) Reserved HPHCLK11:8 PMMPRSPC Reserved DIVPCLK PMMPRSSC (low) HPSCLK7:0 PMMPRSSC (high) Reserved HPSCLK13:8 PMMPLLnCTL1 (low) Reserved PLLIPSEL PLLDCOE PLLEN PMMPLLnCTL1 (high) Reserved PMMPLLnCTL2 (low) Reserved HCCPLL DPLLC PCLKSTB PMMPLLnCTL2 (high) Reserved PMMPLLnMDIV MDIV PMMPLLnNDIV NDIV PMMPLLnPDIV PDIV PMMPLLnNMOD (low) NMOD PMMPLLnNMOD (high) NMOD_DITH Reserved PMMPLLnSTUP (low) CLKCNT7:0 PMMPLLnSTUP (high) Reserved CLKCNT9:8 PMMAUXnCTL Reserved AUXCLKSRC AUXCLKEN PMMAUXnPRSC (low) HPACLK7:0 PMMAUXnPRSC (high) Reserved HPACLK11:8 Thisparagraphisused forspace between tables MIWU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Registers WKREN1 WKREN31:0 WKREN2 WKREN63:32 WKFEN1 WKFEN31:0 WKFEN2 WKFEN63:32 WKRPND1 WKRPD31:0 WKRPND2 WKRPD63:32 WKFPND1 WKFPD31:0 WKFPND2 WKFPD63:32 WKCLR1 WKCL31:0 WKCLR2 WKCL63:32 WKRIEN1 WKRIEN31:0 WKRIEN2 WKRIEN63:32 WKFIEN1 WKFIEN31:0 WKFIEN2 WKFIEN63:32 WKICTL1 WKINTR15:0 (2-bitfields) WKICTL2 WKINTR31:16

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www.ti.com SNOSCW5 –MAY 2013 MIWU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Registers WKICTL3 WKINTR47:32 WKICTL4 WKINTR63:48 WKISTAT Reserved WKISTAT7:0 Thisparagraphisused forspace between tables GPIO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Registers PxDIR Px PortDirection PxDIN Px PortInputData PxDOUT Px PortOutputData PxALT Px PinsAlternateFunctionEnable PxALTS Px PinsAlternateFunctionSourceSelection PxWPU Px PortWeak Pullup/PulldownEnable PxPDR Px PortWeak Pullup/PulldownDirection PxIEN Px PortInterruptEnable Thisparagraphisused forspace between tables AAI Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARFR ARFH ARFL ARDR0 ARDH ARDL ARDR1 ARDH ARDL ARDR2 ARDH ARDL ARDR3 ARDH ARDL ATFR ATFH ATFL ATDR0 ATDH ATDL ATDR1 ATDH ATDL ATDR2 ATDH ATDL ATDR3 ATDH ATDL AGCR CLKEN AAIEN IOM2 IFS FSL CTF CRF IEBC FSS IEFS SCS LPB DWL ASS AISCR Reserved TXEIC TXIC RXEIC RXIC TXEIP TXIP RXEIP RXIP TXEIE TXIE RXEIE RXIE ARSCR RXFWM RXDSA RXSA RXO RXE RXF ATSCR TXFWM TXDSA TXSA TXU TXF TXE TXAE ACCR BCPRS FCPRS CSS ADMACR Reserved ACO ACD TMD RMD Thisparagraphisused forspace between tables IVECT Reserved INTVECT NMISTAT Reserved EXT EXNMI Reserved ENLCK PIN EN ISTAT0 IST31:1 Reserved ISTAT1 IST63:32 ISTAT2 Reserved IST70:64 IENAM0 IENAM31:1 Reserved IENAM1 IENAM63:32 IENAM2 Reserved IENAM70:64 SOFTINT0 SOFTINT31:1 Reserved SOFTINT1 SOFTINT63:32 SOFTINT2 Reserved SOFTINT70:64 INTGPAR0 INTGPA31:1 Reserved INTGPAR1 INTGPA63:32 INTGPAR2 Reserved INTGPA70:64 INTGPBR0 INTGPB31:1 Reserved INTGPBR1 INTGPB63:32 Copyright© 2013,Texas InstrumentsIncorporated RegisterBitFields 367 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com INTGPBR2 Reserved INTGPB70:64 IDBG Reserved IRQVECT INTVECT Thisparagraphisused forspace between tables UART 7 6 5 4 3 2 1 0Registers UnTBUF UnTBUF UnRBUF URBUF UnICTRL UEEI UERI UETI UEFCI UCTS UDCTS URBF UTBE UnSTAT Reserved UXMIP URB9 UBKD UERR UDOE UFE UPE UnFRS Reserved UPEN UPSEL UXB9 USTP UCHAR UnMDSL1 URTS UFCE UERD UETD UCKS UBRK UATN UMOD UnBAUD UDIV7:0 UnPSR UPSC UDIV10:8 UnOVR Reserved UOVSR UnMDSL2 Reserved USMD UnSPOS Reserved USAMP Thisparagraphisused forspace between tables Microwire/SPI 15 ...9 8 7 6 5 4 3 2 1 0Registers MWnDAT MWDAT MWnCTL1 SCDV SCIDL SCM EIW EIR EIO ECHO MOD MNS MWEN MWnSTAT Reserved OVR RBF BSY Thisparagraphisused forspace between tables ACB Registers 7 6 5 4 3 2 1 0 ACBnSDA DATA ACBnST SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT ACBnCST ARPMATCH MATCHAF TGSCL TSDA GMATCH MATCH BB BUSY ACBnCTL1 STASTRE NMINTE GCMEN ACK DMAEN INTEN STOP START ACBnADDR SAEN ADDR ACBnCTL2 SCLFRQ6:0 ENABLE ACBnADDR2 SAEN ADDR ACBnCTL3 Reserved ARPEN SCLFRQ8:7 Thisparagraphisused forspace between tables ADC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Registers ADCGCR MUXOUTEN INTEN NREF_CFG PREF_CFG Reserved MUX_CFG DIFF ADCIN CLKEN ADCACR CNVT TRG PRM Reserved CLKDIV CLKSEL ADCCNTRL Reserved AUTO EXT POL ADCSTART Writeany value. ADCSCDLY ADC_DIV ADC_DELAY1 ADC_DELAY2 ADCRESLT ADC_DONE ADC_OFLW Reserved SIGN ADC_RESULT Thisparagraphisused forspace between tables TWM 15 ...8 7 6 5 4 3 2 1 0Registers TWCFG Reserved WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG TWCP Reserved MDIV TWMT0 PRESET T0CSR Reserved FRZT0E WDTLD T0INTE TC RST WDCNT Reserved PRESET WDSDM Reserved RSTDATA

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www.ti.com SNOSCW5 –MAY 2013 Thisparagraphisused forspace between tables MFT16 15 ...8 7 6 5 4 3 2 1 0Registers TCNT1_n TCNT1 TCRA_n TCRA TCRB_n TCRB TCNT2_n TCNT2 TPRSC_n Reserved CLKPS TCKC_n Reserved C2CSEL C1CSEL TMCTRL_n Reserved TEN TAOUT TBEN TAEN TBEDG TAEDG TMDSEL TICTL_n Reserved TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND TICLR_n Reserved TDCLR TCCLR TBCLR TACLR Thisparagraphisused forspace between tables Copyright© 2013,Texas InstrumentsIncorporated RegisterBitFields 369 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com VTU Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE_n TMOD4 T8RUN T7RUN TMOD3 T6RUN T5RUN TMOD2 T4RUN T3RUN TMOD1 T2RUN T1RUN IO1CTL_n P4POL C4EDG P3POL C3EDG P2POL C2EDG P1POL C1EDG IO2CTL_n P7POL C7EDG P6POL C6EDG P5POL C5EDG P5POL C5EDG INTCTL_n I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN INTPND_n I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD CLK1PS_n C2PRSC C1PRSC COUNT1_n CNT1 PERCAP1_n PCAP1 DTYCAP1_n DCAP1 COUNT2_n CNT2 PERCAP2_n PCAP2 DTYCAP2_n DCAP2 CLK2PS_n C4PRSC C3PRSC COUNT3_n CNT3 PERCAP3_n PCAP3 DTYCAP3_n DCAP3 COUNT4_n CNT4 PERCAP4_n PCAP4 DTYCAP4_n DCAP4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0I2S Registers I2SCLK Reserved WSRES CLKDIV Reserved M S CLKSEL CLKEN RX RX RX RXI2SRXCTL Reserved Res RXFIFOTHRESH RXALIGN Res. RX LI RX RI RXRES RXMODST LD RD ER TX TXLSB FLU TX TXI2STXCTL Reserved TX ST Res. TXFIFOTHRESH TXA IGN FIFO FIFO TX LD TX LI TX RI TXRES TXMODFILL SH RD ERENL ENR I2STXDATALEFT TXDATALEFT I2STXDATARIGHT TXDATARIGHT I2SRXDATALEFT RXDATALEFT I2SRXDATARIGHT RXDATARIGHT WSSTATUS RXER RXL RXR TXER TXL TXRI2SSTAT Res. RXSTATUSL WSSTATUS2:0 RXSTATUSR TXSTATUSL TXSTATUSR4:3 IRQ IRQ IRQ IRQ IRQ IRQ

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www.ti.com SNOSCW5 –MAY 2013 ASC Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASCDMASEL0 DCH15:0 ASCDMASEL1 Reserved DCH17:16 ASCDDMASELn Reserved DDMA[2n+1] Reserved DDMA[2n] ASCINTSEL Reserved ICH8:0 ADMAS Reserved RRSTN PBUSY ADMAC Reserved DSPRSTN DSP Interface 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Registers PDATA PDATA PADR PADR PCFG MEMSEL RRIE2 RRIE1 RRIE0 WFEIE WFFIE RFNEIE RFFIE RS DRS AIM DSPR PSTS RCOMIM2:0 RRI2 RRI1 RRI0 PSEMI WFEI WFFI RFNEI RFFI R PRST WTIP RTIP PSEM PSEM PMASK PMASK PCLEAR PCLEAR APBP_SEM APBP_SEM APBP_COM0 APBP_COM0 APBP_REP0 APBP_REP0 APBP_COM1 APBP_COM1 APBP_REP1 APBP_REP1 APBP_COM2 APBP_COM2 APBP_REP2 APBP_REP2 Copyright© 2013,Texas InstrumentsIncorporated RegisterBitFields 371 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Codec Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCDCBASIC DFS AFS FLSDAC FLSADC Reserved SEN MUTER MUTEL DACOSR DACSTMODE ADC2ON ADC1ON DACTCDCDACSTATUS Reserved RIGHTFIFO Reserved LEFTFIFOSTATUS ADC1 ADC2TCDCADCSTATUS Res. ADC2FIFO Reserved ADC1FIFOSTATUS STATUS ADC2DIT ADC1DITTCDCDSP Res. ST CLPR ST CLPL SIDETONEATTEN CLKPH DIGMICGAIN CUST COMP DACDIT OFF DACDIT ONOFF OFF TCDCADCANA1 Res. HPF MUTE MICSEL Reserved MICMODE Reserved MICGAIN TCDCADCANA2 Res. HPF MUTE MICSEL Reserved MICMODE Reserved MICGAIN TCDCADC1CLK Reserved CLKTIE ADCCLKSRC ADCCLKDIV TCDCADC2CLK Reserved CLKTIE ADCCLKSRC ADCCLKDIV TCDCDACCLK Reserved SEL6M DACRNG DACCLKSRC DACCLKDIV DMATCDCFIFO DMAR DMAL DMA ADC1 DACFIFOTRIG ADC2FIFOTRIG ADC1FIFOTRIGADC2 TCDCIRQEN Reserved STCLP MICCLP ZXDR ZXDL DAC DOWN ADC2 DOWN ADC1 DOWN DACUP ADC2UP ADC1UP RGT FIFO LFT FIFO ADC2FIFO ADC1FIFO TCDCIRQPNDCLR Reserved STCLP MICCLP ZXDR ZXDL DAC DOWN ADC2DOWN ADC1DOWN DAC UP ADC2UP ADC1UP RGT FIFO LFT FIFO ADC2FIFO ADC1FIFO TCDCCOMPC0 COMPC0 TCDCCOMPC1 COMPC1 TCDCCOMPC2 COMPC2 TCDCDEBUG Reserved SFTRST Reserved GPIO TCDCADC1 ADCDATA TCDCADC2 ADCDATA TCDCLEFT LEFTDATA TCDCRIGHT RIGHTDATA TCDCMONITOR Res. SDE SDLIMIT MD DCLIMIT RTCCST Reserved RTSTRT RTPRST RTDIV RTUDST Reserved RTUCP3 RTUCP2 RTUCP1 RTURTC RTUDIV RTCEIST Reserved RTCEVT3 RTCEVT2 RTCEVT1 RTCIEN Reserved RTCIEN3 RTCIEN2 RTCIEN1 RTCPRD Reserved RTPCNT RTCRD RTCCNT RTCLD RTCCLD RTCCMP1 Reserved RTCCMP1 RTCCMP2 RTCCMP2 RTCCMP3 RTCCMP3

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36 ElectricalSpecifications

36.1 AbsoluteMaximum Ratings(1)

IfMilitary/Aerospacespecifieddevicesarerequired,contacttheTexas InstrumentsSemiconductorSalesOffice/Distributors foravailabilityand specifications. MIN MAX UNIT Supplyvoltage(IOVCC, RFVCC, TCDACVCC, UVCC) 3.6 V Supplyvoltage(VCC, PLLVCC, ADVCC, TCADCVCC) 2.0 V Allinputand outputvoltageswithrespecttoGND –2.0 Supply+0.2 V ESD protectionlevel(Human Body Model) 2 kV Allowablesink/sourcecurrentpersignalpin ±10 mA TotalcurrentintoIOVCC pins 200 mA TotalcurrentintoVCC pins(source) 200 mA TotalcurrentoutofGND pins(sink) 200 mA Latch-upimmunity ±200 mA Temperatureunderbias –40 85 °C Storagetemperaturerange –65 150 °C (1) Absolutemaximum ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.DC and AC electricalspecificationsarenot ensuredwhen operatingthedeviceatabsolutemaximum ratings.

36.2 DC ElectricalCharacteristics:Temperature:–40°C ≤ TA ≤ 85°C)

PARAMETER CONDITIONS MIN MAX UNIT VCC Core LogicSupplyVoltage 1.62 1.98 V IOVCC I/OSupplyVoltage 2.25/2.97 3.6 V RFV CC RF I/OSupplyVoltage 2.25 3.6 V PLLV CC AnalogPLL SupplyVoltage 1.62 1.98 V ADV CC ADC SupplyVoltage 1.62 1.98 V UV CC USB SupplyVoltage 3 3.6 V TCADCV CC Codec ADC SupplyVoltage 1.62 1.98 V TCDACV CC Codec DAC Voltage 2.97 3.6 V VIL Logical0 InputVoltage(exceptas notedbelow) –0.2 0.2IOVCC V VIH Logical1 InputVoltage(exceptas notedbelow) 0.7IOVCC IOVCC + 0.2 V Vxl1 X1CKI Logical0 InputVoltage(1) ExternalX1 clock -0.2 0.2PLLV CC V Vxh1 X1CKI Logical1 InputVoltage(1) ExternalX1 clock 0.7PLLV CC PLLVcc + 0.2 V Vxl2 X2CKI Logical0 InputVoltage(1) ExternalX2 clock -0.2 0.2PLLV CC V Vxh2 X2CKI Logical1 InputVoltage(1) ExternalX2 clock 0.7PLLV CC PLLV CC + 0.2 V Vhys HysteresisLoop Width (1) 0.05IOVCC V IOL Logical0 OutputCurrent(exceptas notedbelow) VOL = 0.4V,IOVCC = 3 V 10 mA IOH Logical1 OutputCurrent(exceptas notedbelow) VOH = 2.4V,IOVCC = 3 V –10 mA IOLACB SDAn, SCLn Logical0 OutputCurrent VOL = 0.4V,IOVCC = 2.25V 3 mA IOHW Weak PullupCurrent(1) VIL= 0 V,IOVCC = 3.6V –50 –200 µA IL HighImpedance InputLeakage Current(2) 0 V ≤ Vin≤ IOVCC –2 2 µA IO(Off) OutputLeakage Current(I/Opinsininputmode) 0 V ≤ Vout≤ IOVCC –2 2 µA Icca1 DigitalSupplyCurrentActiveMode (3) VCC = 1.98V,IOVCC = 3.6V 200 mA Iccps DigitalSupplyCurrentPower Save Mode (4) VCC = 1.98V,IOVCC = 3.6V 4 mA Iccid DigitalSupplyCurrentIdleMode (5) VCC = 1.98V,IOVCC = 3.6V 2 mA (1) Specifiedby design (2) Onlyfordigitalinputs.Some analoginputssuch as TCMIC1P and TCMIC2P have inputprotectiondeviceswhichconductiftheinputis takenhigh. (3) Run frominternalmemory (RAM),Iout= 0 mA, X1CKI = 12 MHz, bothPLLs enabledat60 MHz (4) Runningfrominternalmemory (RAM),Iout= 0 mA, XCKI1 = 12 MHz, PLLs disabled,X2CKI = 32.768kHz (5) Iout= 0 mA, XCKI1 = Vcc,X2CKI = 32.768kHz Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 373 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com DC ElectricalCharacteristics:Temperature:–40°C ≤ TA ≤ 85°C) (continued) PARAMETER CONDITIONS MIN MAX UNIT Iccq DigitalSupplyCurrentHaltMode (5)(6) VCC = 1.98V,IOVCC = 3.6V,20°C 400 µA (6) Haltcurrentapproximatelydoublesforevery20°C.

36.3 USB TransceiverElectricalCharacteristics

Temperature:–40°C ≤ TA ≤ 85°C) PARAMETER CONDITIONS MIN MAX UNIT VIL USB InputLow Voltage 0.8 V VIH USB InputHighVoltage(driven) 2 V VIHZ USB InputHighVoltage(floating)(1) 2.7 3.6 V VDI DifferentialInputSensitivity(1) (D+)– (D–) –0.2 0.2 V VCM DifferentialCommon Mode Range (1) 0.8 2.5 V VSE Single-EndedReceiverThreshold(1) 0.8 2 V VOL OutputLow Voltage R L = 1.5kΩ to3.6V 0 0.3 V VOH OutputHighVoltage R L = 15 kΩ to0 V 2.8 V VOSE0 SE0 Voltage(1) 0.8 V VOSE1 SE1 Voltage(1) 0.8 V VCRS CrossoverVoltage(1) 1.3 2 V IOZ TRI-STATE Data LineLeakage Current(1) 0 V < VIN < 3.3V –10 10 µA C TRN TransceiverCapacitance(1) 20 pF R PUI Bus Pullupon Upstream Port(idlebus)(1) 0.9 1.575 kΩ R PUA Bus Pullupon Upstream Port(portreceiving)(1) 1.425 3.09 kΩ R PD Bus Pulldownon Downstream Port(1) 14.25 24.8 kΩ ZINP InputImpedance ExclusiveofPullup/Pulldown(1) 300 kΩ VTERM TerminationVoltage(1) 3 3.6 V (1) Specifiedby design.

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36.4 TelematicsCodec ElectricalCharacteristics

Temperature:–40°C ≤ TA ≤ 85°C) PARAMETER (1) CONDITIONS MIN TYP MAX UNIT DUAL AUDIO ADC Lower (HPF Mode 1),Fs = 8 kHz 300 VADC PB Passband Hz Upper,Fs = 8 kHz 3300 VADC RIP Ripple Same as above,relativeto1 kHz ±0.25 dB Above 4.5kHz 60 dB VADC SBA StopbandAttenuation HPF Notch,50/60Hz,HPF = 1 and HPF = 2,worst 55 dBcase 1 kHz,–3 dBFS relativetoidlenoise, 85 dBFs = 8 kHz,differential,A-weightedVADC SNR Signal-to-NoiseRatio Same as above,butsingle-ended 75 dB 1 kHz,–60 dB input,AES-17,VADC DR Dynamic Range 87 dBFs = 8 kHz,differential,A-weighted

0.13 VRMS

VADC LEVEL InputLevel –3 dBFS, MICGAIN = 0,differential

0.354 VP-P(diff)

Per applicationschematic,VRIPPLE = 200 mVP-P,VADC PSRR Power SupplyRejectionRatio 40 dBFRIPPLE = 217 Hz,MICGAIN = 0 TotalHarmonicDistortion,VADC THD+N –3 dB,1 kHz input,relativeto0 dBFS, differential 0.015%ADC + microphone+ noise Common Mode Voltage,VADC CM 0.9 VADC + microphone VADC OFFSET Offset,microphonepreamp InputreferencedtoMICGAIN = 1111 2.6 mV VADC RMICDIFF DifferentialInputResistance TCMICxP toTCMICxN pins 150 kΩ VADC RMICSE Single-EndedInputResistance TCMICxP/TCMICxN pintoAC ground(TCVBUFx pin) 75 kΩ VADC ROVRP VREF OutputResistance 10 Ω Per applicationschematic,VADC PSRRVRP VREF PSRR 40 dBVRIPPLE = 200 mV P-P,FRIPPLE = 217 Hz Minimum 0 dB VADC GCR Gain ControlRange Maximum 30 dB VADC SS Gain ControlStepSize 2 dB VADC DELAY ADC Group Delay Mean from300 Hz to3.3kHz 0.2 ms STEREO DAC SDAC PB Passband Frequency -3dB point,FIR optimized(2) 22 kHz SDAC RIP Ripple DC to20 kHz,Fs = 48 kHz,FIR optimized(2) ±0.08 dB SDAC SBA StopBand Attentuation Above Nyquistfrequency,FIR optimized(2) 70 dB 1 kHz,0 dBFS relativetoidlenoise,differential, SDAC SNR SignaltoNoiseRatio A-weighted,DAC asynchronoustoHCLK Clock, 86 dB clockedfromPLL 1 kHz,–60 dBFS, AES-17,differential,A-weighted, SDAC DR Dynamic Range DAC synchronoustoHCLK Clock,clockedfrom12 95 dB MHz Main Clock SDAC THD+N TotalHarmonicDistortion+ noise –3 dB,1 kHz input,relativeto0 dBFS, differential 0.01% SDAC LEVEL LineOutputLevel 1 kHz,20 kΩ load 1 VRMS SDAC LOAD Minimum LineOutputLoad 1 kHz,1 V RMS 20 kΩ SDAC DLY DAC Group Delay Fs = 48 kHz 0.8 ms (1) Specifiedby design (2) DAC frequencyresponseistestedusingFIR compensationfiltercoefficientsoptimizedfortheCP3-DB-SP33 developmentboardata 48 kHz samplingfrequency.Ata 125× oversamplingrate,theseareC0 = 0121h,C1 = FB44h, C2 = 6C79h. Ata 128× oversamplingrate, theseareC0 = 00E2h,C1 = FA7Dh, C2 = 6999h. Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 375 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

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36.5 ADC ElectricalCharacteristics

Temperature:–40°C ≤ TA ≤ 85°C) PARAMETER CONDITIONS MIN TYP MAX UNIT VPREF ADC PositiveReferenceInput(1) 1.62 1.98 V VNREF ADC NegativeReferenceInput(1) 0 0.25 V ADC InputRange (1) VNREF VPREF V ClockFrequency 12 MHz tC ConversionTime (10-bitresult)(1) 14 µs INL IntegralNon-Linearity ±2 LSB DNL DifferentialNon-Linearity ±0.7 LSB C ADCIN TotalCapacitanceofADC Input(1) 9 20 pF C ADCINS SwitchedCapacitanceofADC Input(1) 8 10 pF R ADCIN ResistanceofADC InputPath (1) 0.1 12 kΩ C ADCIN TotalCapacitanceofADC ReferenceInput(1) 50 100 pF C ADCINS SwitchedCapacitanceofADC ReferenceInput(1) 8 10 pF R ADCIN ResistanceofADC ReferenceInputPath(1) 0.2 0.6 kΩ (1) Specifiedby design.

36.6 Output SignalLevels

The followingoutputsignalsarepowered by thedigitalIO supply(IOVCC )or,inthecase oftheBluetooth signalsand portpinsPF[6:0],theRF supply(RFVCC ). summarizes the statesof the outputsignalsduringthe resetstate(when VCC power existsinthe reset state)and duringthePower Save mode. Thisdevicehas many dedicatedinputsignalswhich are notinternallypulledtoa supply;thesemust be drivenor tiedofftoa voltagelowerthan0.5V or higherthanIOVCC – 0.5V,toassurethatthecurrentin Power Save mode does notexceed 1 mA. An inputvoltagebetween 0.5V and (VCC – 0.5V)may resultin power consumptionexceeding1 mA. Table36-1.Output Pins During Reset and Power-Save Mode RESET STATESIGNALS ON A PIN POWER SAVE MODE COMMENTS(withVCC ) PE[15:0] TRI-STATE Previousstate I/Oportswillmaintaintheirvalueswhen enteringpower- save mode. Thereisno logicfunctiontosupportthis,so ifPF[15:0] TRI-STATE Previousstate theCPU and GPIO peripheralhave a clock,thedeviceis PG[15:0] TRI-STATE Previousstate capableofalteringthestateofitsportpins. PH[7:0] TRI-STATE Previousstate

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36.7 Clock and Reset Timing

Table36-2.Clock and Reset Signals DESCRIPTION (1) REFERENCE MIN MAX UNIT CLOCK INPUT SIGNALS tX1p CLKIN period RisingEdge (RE)tonextRE, See Figure36-1 83.33 83.33 ns tX1h CLKIN hightime,externalclock At2 V level(bothedges),See Figure36-1 (0.5Tclk)– 5 ns tX1l CLKIN lowtime,externalclock At0.8V level(bothedges),See Figure36-1 (0.5Tclk)– 5 ns tX2p X2 period(2) RE on X2 tonextRE on X2,See Figure36-1 10,000 ns tX2h X2 hightime,externalclock At2V level(bothedges),See Figure36-1 (0.5Tclk)– 500 ns tX2l X2 lowtime,externalclock At0.8Vlevel(bothedges),See Figure36-1 (0.5Tclk)– 500 ns CLOCK OUTPUT SIGNALS tCLKp HCLK Clockperiod(3) RisingEdge (RE)tonextRE, See Figure36-1 42,667 16.6 ns tCLKh HCLK Clockhightime At2 V level(bothedges),See Figure36-1 21,333 20.83 ns tCLKl HCLK Clocklowtime At0.8V level(bothedges),See Figure36-1 21,333 20.83 ns tCLKr HCLK Clockrisetimeon RE ofCLKIN At2 V level(bothedges),See Figure36-1 5 ns tCLKf HCLK Clockfalltimeon FE ofCLKIN At0.8V level(bothedges),See Figure36-1 5 ns RESET AND NMI INPUT SIGNALS tIW NMI PulseWidth,See (1) NMI FallingEdge (FE)toRE 20 tRST RESET PulseWidth RESET FE toRE, See Figure36-3 100 VTRIP POR RisingTriggerVoltage See Figure36-4 1.11 1.54 V tTRIP VCC RiseTime toVTRIP See Figure36-4 50 ms tD VCC RiseTime fromVTRIP toVCC See Figure36-4 800 µs (1) Specifiedby design. (2) Onlywhen operatingwithan externalsquarewave on X2CKI;otherwisea 32 kHz crystalnetworkmust be used between X2CKI and X2CKO. IfSlow ClockisinternallygeneratedfromMain Clock,itmay notexceed thislimit. (3) TclkistheactualclockperiodoftheCPU clockused inthesystem. The valueofTclkissystemdependent. The maximum cycletimeinPower Save mode is42,667ns (=1/12MHz × 2 × 256). The maximum cycletimeinActivemode is1333 ns (=1/12MHz × 16). The minimum cycletimeinActivemode is16.6ns (=1/60MHz). Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 377 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

(Internal only) 400 mV >950 µs tD tIW NMI DS477 tRST RESET DS478 X2CKI tX2h tX2l tX2p CLKIN tX1h tX1l tX1p DS358 HCLK tCLKh tCLKl tCLKp tCLKf tCLKr CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure36-1.Clock Timing Figure36-2.NMI SignalTiming Figure36-3.Non-Power-On Reset Figure36-4.Power-On Reset

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t t ls lh tCOv1 1 1 2 2 2 1 1 1 2 2 2 DS479 DS534 VCC VTRIP Failure to have stable VCC within minimum tD. CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure36-5.Bad Power-On Reset

36.8 UART Timing

Table36-3.UART Signals DESCRIPTION (1) REFERENCE MIN MAX UNIT UART INPUT SIGNALS tIs InputsetuptimeRXD (asynchronousmode) BeforeRisingEdge (RE)on PCLK Clock, ns See Figure36-6 tIh InputholdtimeaRXD (asynchronousmode) AfterRE on PCLK Clock,See Figure36-6 ns tCKX CKX period(synchronousmode) See Figure36-7 250 ns tRXS RXD setuptime(synchronousmode) BeforeFallingEdge (FE)on CKX, See Figure36-7 40 ns tRXH RXD holdtime(synchronousmode) BeforeFallingEdge (FE)on CKX, See Figure36-7 40 ns UART OUTPUT SIGNALS tCOv1 TXD outputvalid(allsignalswithpropagation AfterRE on PCLK Clock,See Figure36-6 35 ns delayfromCLKRE) tTXD TXD outputvalid AfterRE on CKX, See Figure36-7 40 ns (1) Specifiedby design. Figure36-6.UART Asynchronous Mode Timing Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 379 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Ports PE through PH (input) Ports PE through PH (output) tIS tCOv1 tlH tCOv1 tOF DS480 tTXD tRXS tCKX tRXH CKX TXD RXD DS099 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure36-7.UART Synchronous Mode Timing

36.9 I/OPortTiming

Table36-4.I/OPortTiming DESCRIPTION (1) REFERENCE MIN MAX UNIT I/OPORT INPUT SIGNALS tIs Inputsetuptime BeforeRisingEdge (RE)on PCLK Clock,See Figure36-8 ns tIh Inputholdtime AfterRE on PCLK Clock,See Figure36-8 ns I/OPORT OUTPUT SIGNALS tCOv1 Outputvalidtime AfterRE on PCLK Clock,See Figure36-8 15 ns tTXD OutputFloatingTime AfterRE on PCLK Clock,See Figure36-8 15 ns (1) Specifiedby design. Figure36-8.I/OPortTiming

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36.10 Advanced Audio Interface(AAI)Timing

Table36-5.Advanced Audio Interface(AAI)Signals DESCRIPTION (1) REFERENCE MIN MAX UNIT AAI INPUT SIGNALS BeforeFallingEdge (FE)on SRCLK,tRDS ReceiveData SetupTime 20 nsSee Figure36-9and Figure36-11 tRDH ReceiveData HoldTime AfterFE on SRCLK, See Figure36-9and Figure36-11 20 ns tFSS Frame Sync SetupTime BeforeRisingEdge (RE)on SRCLK ,See Figure36-9 20 ns tFSH Frame Sync HoldTime AfterRE on SRCLK, See Figure36-9 20 ns AAI OUTPUT SIGNALS tCP Receive/TransmitClockPeriod RE on SRCLK/SCK toRE on SRCLK/SCK ,SeeFigure36-9 976.6 ns tCL Receive/TransmitLow Time FE on SRCLK/SCK toRE on SRCLK/SCK ,See Figure36-9 488.3 ns tCH Receive/TransmitHighTim RE on SRCLK/SCK toFE on SRCLK/SCK, See Figure36-9 488.3 ns RE on SRCLK/SCK toRE on SRFS/SFS ,See Figure36-9andtFSVH Frame Sync ValidHigh 20 nsFigure36-11 RE on SRCLK/SCK toFE on SRFS/SFS, See Figure36-9andtFSVL Frame Sync ValidLow 20 nsFigure36-11 tTDV TransmitData Valid RE on SCK toSTD Valid,See Figure36-10and Figure36-12 20 ns (1) Specifiedby design. Figure36-9.Receive Timing,ShortFrame Sync Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 381 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

N 0SRD SRCLK SRFS DS118 0 1 2 tFSVH tFSVL tRDHtRDS N 0STD SCK SFS DS117 0 1 2 tTDV CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure36-10.TransmitTiming,ShortFrame Sync Figure36-11.Receive Timing,Long Frame Sync Figure36-12.TransmitTiming,Long Frame Sync

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36.11 Microwire/SPITiming

Table36-6.Microwire/SPITiming DESCRIPTION (1) REFERENCE MIN MAX UNIT MICROWIRE/SPI INPUT SIGNALS tMSKh MicrowireClockHigh At2.0V(bothedges),See Figure36-13 80 ns tMSKl MicrowireClockLow At0.8V(bothedges),See Figure36-13 80 ns SCIDL bit= 0;RisingEdge (RE)MSKn tonextRE MSKn, See 200Figure36-13 tMSKp MicrowireClockPeriod ns SCIDL bit= 1;FallingEdge (FE)MSKn tonextFE MSKn, See 200Figure36-14 tMSKh MSKn Hold(slaveonly) AfterMWCSn goes inactive,See Figure36-13 40 ns tMSKs MSKn Setup(slaveonly) BeforeMWCSn goes active,See Figure36-13 80 ns SCIDL bit= 0:AfterFE MSKn, See Figure36-13 40tMWCS MWCSn Hold(slaveonly) ns h SCIDL bit= 1:AfterRE MSKn, See Figure36-14 40 SCIDL bit= 0:BeforeRE MSKn, See Figure36-13 80tMWCS MWCSn Setup(slaveonly) ns s SCIDL bit= 1:BeforeFE MSKn, See Figure36-14 80 Normal Mode: AfterRE MSKn, See Figure36-13 0 MicrowireData InHold(master) ns AlternateMode: AfterFE MSKn, See Figure36-15 0 tMDIh Normal Mode: AfterRE MSKn, See Figure36-13 40 MicrowireData InHold(slave) ns AlternateMode: AfterFE MSKn, See Figure36-15 40 Normal Mode: BeforeRE MSKn, See Figure36-13 80 tMDIs MicrowireData InSetup ns AlternateMode: BeforeFE MSKn, See Figure36-15 80 MICROWIRE/SPI OUTPUT SIGNALS tMSKh MicrowireClockHigh At2.0V (bothedges),See Figure36-13 40 ns tMSKl MicrowireClockLow At0.8V (bothedges),See Figure36-13 40 ns SCIDL bit= 0:RisingEdge (RE)MSKn tonextRE MSKn, See Figure36-13 tMSKp MicrowireClockPeriod ns SCIDL bit= 1:FallingEdge (FE)MSKn tonextFE MSKn, See 100Figure36-14 tMSKd MSKn LeadingEdge Delayed(masteronly) Data Out Bit7 Valid,See Figure36-13 0.5tMSK 1.5tMSK ns tMDOf MicrowireData Float(slaveonly) AfterRE on MWCSn, See Figure36-13 25 ns Normal Mode: AfterFE MSKn, See Figure36-13 tMDOh MicrowireData Out Hold ns AlternateMode: AfterRE MSKn, SeeFigure36-14 0 tMDOnf MicrowireData No Float(slaveonly) AfterFE on MWCSn, See Figure36-14 0 25 ns Normal Mode: AfterFE on MSKn, See Figure36-13 tMDOv MicrowireData Out Valid ns AlternateMode: AfterRE on MSKn, See Figure36-13 25 PropagationTime Valueisthesame inallclockingmodes ofthetMITOp MDODIn toMDIDOn (slaveonly) 25 nsMicrowire,See Figure36-17 (1) Specifiedby design. Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 383 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

(master) lsbmsb MDIDOn (slave) tMSKh MWCS (slave) tMSKhd DS361 lsbmsb tMSKp tMSKh tMDlh tMSKd tMWCSs tMWCSh tMDls tMSKs tMDOf tMDOv tMDOff tMDOh tMSKhd Data In lsbmsb MDODIn (master) msb lsbMDIDOn (slave) MSKn MWCSn (slave) tMSKl DS360 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure36-13.MicrowireTransactionTiming,Normal Mode, SCIDL = 0 Figure36-14.MicrowireTransactionTiming,Normal Mode, SCIDL = 1

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(master) lsbmsbMDIDOn (slave) tMSKh MWCS (slave only) tMSKhd DS363 MSKn lsbmsbData In lsbmsbMDODIn (master) lsbmsbMDIDOn (slave) MWCS (slave) tMSKp tMSKh tMDlhtMDls tMWCSs tMWCSh tMSKs tMDOf tMDOv tMDOf tMDOh tMSKl tMSKhd DS362 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Figure36-15.MicrowireTransactionTiming,AlternateMode, SCIDL = 0 Figure36-16.MicrowireTransactionTiming,AlternateMode, SCIDL = 1 Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 385 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

(slave) DO lsbDO msbMDIDOn (slave) MWCSn tMSKp tMSKh tMDlhtMDls tMWCSs tMWCSh tMSKs tMDOnf tMITOptMITOp tMDOf tMSKl tMSKhd DS364 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure36-17.MicrowireTransactionTiming,Data Echoed toOutput, Normal Mode, SCIDL = 0,ECHO = 1,SlaveMode 36.12 ACCESS.BUS Timing Table36-7.ACCESS.BUS Timing DESCRIPTION (1) REFERENCE MIN MAX UNIT ACCESS.BUS INPUT SIGNALS Bus freetimebetween Stopand StarttBUFi See Figure36-19 tSCLhigho nsCondition BeforeStopCondition,See Figure36-tCSTOsi SCLn setuptime (8× tCLK )-tSCLri ns19 tCSTRhi SCLn holdtime AfterStartCondition,See Figure36-19 (8× tCLK )-tSCLri ns BeforeStartCondition,See Figure36-tCSTRsi SCLn setuptime (8× tCLK )-tSCLri ns19 BeforeSCLn RisingEdge (RE),SeetDHCsi Data Highsetuptime 2 × tCLKp nsFigure36-20 tDLCsi Data Low setuptime BeforeSCLn RE, See Figure36-19 2 × tCLKp ns tSCLri SCLn signalrisetime See Figure36-18 1000 ns tSCLfi SCLn signalfalltime See Figure36-18 300 ns AfterSCLn FallingEdge (FE),SeetSCLlowi SCLn lowtime 16 × tCLKp nsFigure36-21 tSCLhighi SCLn hightime AfterSCLn RE, See Figure36-21 16 × tCLKp ns tSDAri SDAn signalrisetime See Figure36-18 1000 ns tSDAfi SDAn signalfalltime See Figure36-18 300 ns tSDAhi SDAn holdtime AfterSCLn FE, See Figure36-21 0 ns tSDAsi SDAn setuptime BeforeSCLn RE, See Figure36-21 2 × tCLKp ns ACCESS.BUS OUTPUT SIGNALS Bus freetimebetween Stopand StarttBUFo See Figure36-19 tSCLhigho nsCondition (1) Specifiedby design.

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0.7VCC Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. 0.3VCC tSCLf 0.7VCC 0.3VCC tSCLr SDAn 0.7VCC 0.3VCC tSDAf 0.7VCC 0.3VCC tSDAr DS365 CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Table36-7.ACCESS.BUS Timing (continued) DESCRIPTION (1) REFERENCE MIN MAX UNIT BeforeStopCondition,See Figure36-tCSTOso SCLn setuptime tSCLhigho ns19 tCSTRho SCLn holdtime AfterStartCondition,See Figure36-19 tSCLhigho ns BeforeStartCondition,See Figure36-tCSTRso SCLn setuptime tSCLhigho ns20 tDHCso Data Highsetuptime BeforeSCLn RE, See Figure36-20 tSCLhigho -tSDAro ns tDLCso Data Low setuptime BeforeSCLn RE, See Figure36-19 tSCLhigho -tSDAfo ns tSCLfo SCLn signalFalltime See Figure36-18 300(2) ns tSCLro SCLn signalRisetime See Figure36-18 See (3) ns tSCLlowo SCLn lowtime AfterSCLn FE, See Figure36-21 (K × tCLK )-1(4) ns tSCLhigho SCLn hightime AfterSCLn RE, See Figure36-21 (K × tCLK )-1 ns tSDAfo SDAn signalFalltime See Figure36-18 300 ns tSDAro SDAn signalRisetime See Figure36-18 ns tSDAho (5) SDAn holdtime AfterSCLn FE, See Figure36-21 (7× tCLK) -tSCLfo ns (7× tCLK )+tSDAvo SDAn validtime AfterSCLn FE, See Figure36-21 nstRD (2) Assuming signal’s capacitanceup to400 pF. (3) Depends on thesignal’s capacitanceand thepullupvalue.Must be lessthan1 ms. (4) K isas specifiedinACBnCTL2.SCLFRQ ×2.K > 15. (5) Note thatthetransmittermust internallyprovidea holdtimeofatleast300 ns on SDA tobridgetheSCL falltime. Figure36-18.ACB Signals(SDAn and SCLn) Timing Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 387 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. unless the parameter already includes the suffix. DS368 SCLn SDAn tDHCs tCSTRs Start Condition tCSTRh Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. DS367 SCLn SDAn tDLCs tCSTOs tCSTRh Stop Condition Start Condition tBUF Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. DS366 CP3SP33 SNOSCW5 –MAY 2013 www.ti.com Figure36-19.ACB Startand Stop ConditionTiming Figure36-20.ACB StartConditionTiming Figure36-21.ACB Data Timing

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I2SWS, I2SSDI, I2SSDO DS370 tCH tCL T tTH tRS tRH tTD tCR CP3SP33 www.ti.com SNOSCW5 –MAY 2013

36.13 USB PortAC Characteristics

Table36-8.USB PortSignals DESCRIPTION (1) CONDITIONS (2) MIN TYP MAX UNIT TR Risetime C L = 50 pF 4 20 ns TF FallTime C L = 50 pF 4 20 ns TRFM Fall/Risetimematching(TR /TF) C L = 50 pF 90% 110% ZDRV DriverOutputImpedance C L = 50 pF 28 43 Ω (1) Specifiedby design. (2) Waveforms measured at10% to90%.

36.14 I2S InterfaceTiming

Table36-9.I2S InterfaceSignals LOWER LIMIT UPPER LIMIT DESCRIPTION (1) REFERENCE UNIT MIN MAX MIN MAX I2S INTERFACE TRANSMITTER SIGNALS T See Figure36-22 Tt nsI2S clockperiod Tt Minimum transmitterclockperiod T > Tt,See Figure36-22 ns 0.35Tt 0.35TttCH Vih,See Figure36-22 nsI2S clockhigh (master) (slave) 0.35Tt 0.35TttCL Vil,See Figure36-22 nsI2S clocklow (master) (slave) tCR See Figure36-22 0.15Tt nsI2S clockrisetime(slavemode) RisingEdge (RE)on I2S Clock,SeetTD Delay 0.8Tt nsFigure36-22 tTH Holdtime 0 nsRE on I2S Clock,See Figure36-22 I2S INTERFACE RECEIVER SIGNALS T See Figure36-22 Tt nsI2S clockperiod Tr Minimum receiverclockperiod T > Tt,See Figure36-22 ns 0.35Tr 0.35TrtCH Vih,See Figure36-22 nsI2S clockhigh (master) (slave) 0.35Tr 0.35TrtCL Vil,See Figure36-22 nsI2S clocklow (master) (slave) tRS Setuptime 0.2Tr nsRE on I2S Clock tRH Holdtime 0RE on I2S Clock (1) Specifiedby design. Figure36-22.I2S InterfaceTiming Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 389 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

TIOn_y DS482 tT AL/tTBL PCLK TAn/TBn DS481 tT AL/tTBH CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

36.15 Multi-FunctionTimer (MFT) Timing

Table36-10.Multi-FunctionTimer InputSignals DESCRIPTION (1) REFERENCE MIN MAX UNIT tTAH TAn hightime Risingedge (RE)on PCLK clock,See Figure36-23 TCLK + 5 ns tTAL TAn lowtime RE on PCLK clock,See Figure36-23 TCLK + 5 ns tTBH TBn hightime RE on PCLK clock,See Figure36-23 TCLK + 5 ns tTBL TBn lowtime RE on PCLK clock,See Figure36-23 TCLK + 5 ns (1) Specifiedby design. Figure36-23.Multi-FunctionTimer InputTiming

36.16 VersatileTiming Unit(VTU) Timing

Table36-11.VersatileTiming UnitInputSignals DESCRIPTION (1) REFERENCE MIN MAX UNIT tTIOH TIOn_y InputHighTime RisingEdge (RE)on PCLK Clock,See Figure36- 1.5× TCLK + 5 ns tTIOL TIOn_y InputLow Time RE on PCLK Clock,See Figure36-24 1.5× TCLK + 5 ns (1) Specifiedby design. Figure36-24.VersatileTiming UnitInputTiming

36.17 ExternalMemory Interface

Table36-12.ExternalMemory Signals DESCRIPTION (1) REFERENCE MIN MAX UNIT EXTERNAL MEMORY INPUT SIGNALS tDSU Data Bus InputSetup BeforeRisingEdge (RE)on HCLK Clock,See Figure36-25 5 ns tDIH Data Bus InputHold AfterRE on HCLK Clock,See Figure36-25 0 ns EXTERNAL MEMORY OUTPUT SIGNALS tAV AddressBus Valid AfterRE on HCLK Clock,See Figure36-25and Figure36-26 9 ns tAH AddressBus Hold AfterRE on HCLK Clock,See Figure36-25and Figure36-26 0 ns tCSL ChipSelectLow AfterRE on HCLK Clock,See Figure36-25and Figure36-26 9 ns tCSH ChipSelectHold AfterRE on HCLK Clock,See Figure36-25and Figure36-26 0 ns (1) Specifiedby design.

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www.ti.com SNOSCW5 –MAY 2013 Table36-12.ExternalMemory Signals(continued) DESCRIPTION (1) REFERENCE MIN MAX UNIT tBEL ByteEnableLow AfterRE on HCLK Clock,See Figure36-25and Figure36-26 9 ns tBEH ByteEnableHold AfterRE on HCLK Clock,See Figure36-25and Figure36-26 0 ns tOEL OutputEnableLow AfterRE on HCLK Clock,See Figure36-25 9 ns tOEH OutputEnableHold AfterRE on HCLK Clock,See Figure36-25 0 ns tWEL WriteEnableLow AfterRE on HCLK Clock,See Figure36-26 9 ns tWEH WriteEnableHold AfterRE on HCLK Clock,See Figure36-26 0 ns tDOV Data Bus OutputValid AfterRE on HCLK Clock,See Figure36-26 9 ns tDOH Data Bus OutputHold AfterRE on HCLK Clock,See Figure36-26 0 ns Figure36-25.Memory Read Cycle Figure36-26.Memory WriteCycle Copyright© 2013,Texas InstrumentsIncorporated ElectricalSpecifications 391 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

10 11 125 6 7 8 1 2 3 4 13 14 15 B C D E F G H A J K L M N P R CP3SP33 SNOSCW5 –MAY 2013 www.ti.com

37 Pin Assignments

(TOP VIEW) Table37-1.Pin Assignments for224-PinPackage PIN SIGNAL NAME POWER SUPPLY DOMAIN A1 No connect IOVCC A2 PE10 IOVCC A3 PE12 IOVCC A4 PH13 IOVCC A5 PH2 IOVCC A6 PG14 IOVCC A7 IOGND A8 PF1 RFVCC A9 PF5 RFVCC A10 PG8 IOVCC A11 PG4 IOVCC A12 PH12 IOVCC A13 PH10 IOVCC A14 PH8 IOVCC A15 TCRP CODEC OUT B1 PH14 IOVCC B2 PE8 IOVCC B3 PE9 IOVCC B4 PE13 IOVCC B5 PH3 IOVCC B6 PG15 IOVCC B7 PG10 IOVCC B8 PF0 RFVCC

392 PinAssignments Copyright© 2013,Texas InstrumentsIncorporated

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www.ti.com SNOSCW5 –MAY 2013 Table37-1.Pin Assignments for224-PinPackage (continued) PIN SIGNAL NAME POWER SUPPLY DOMAIN B9 PF6 RFVCC B10 IOVCC B11 IOGND B12 PH11 IOVCC B13 PH9 IOVCC B14 PH7 IOVCC B15 TCLP CODEC OUT C1 SDA1 IOVCC C2 PH15 IOVCC C3 PE11 IOVCC C4 IOGND C5 PE15 IOVCC C6 PF11 IOVCC C7 RFCE RFVCC C8 RFDATA RFVCC C9 VCC C10 PG5 IOVCC C11 PG1 IOVCC C12 IOVCC C13 TCDACGND CODEC OUT C14 TCRN CODEC OUT C15 TCLN CODEC OUT D1 IOVCC D2 PE6 IOVCC D3 SCL1 IOVCC D4 PE14 IOVCC D5 PH1 IOVCC D6 PG13 IOVCC D7 PF4 RFVCC D8 RFVCC D9 PG9 IOVCC D10 PG3 IOVCC D11 PF7 IOVCC D12 TCADCVCC CODEC IN D13 TCADCGND CODEC IN D14 TCDACVCC CODEC OUT D15 TCVCM2 CODEC IN E1 DSPTDI IOVCC E2 DSPTMS IOVCC E3 PE4 IOVCC E4 PE7 IOVCC E5 IOVCC E6 PG12 IOVCC E7 PF3 RFVCC E8 RFGND E9 PG6 IOVCC E10 PG0 IOVCC Copyright© 2013,Texas InstrumentsIncorporated PinAssignments 393 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table37-1.Pin Assignments for224-PinPackage (continued) PIN SIGNAL NAME POWER SUPPLY DOMAIN E11 TCMIC1P CODEC IN E12 TCVRFN CODEC IN E13 TCVBUF2 CODEC IN E14 TCMIC2N CODEC IN E15 TCMIC2P CODEC IN F1 XA22 IOVCC F2 XA0 IOVCC F3 IOGND F4 MSEO IOVCC F5 PE5 IOVCC F6 PG11 IOVCC F7 PF2 RFVCC F8 GND F9 PG2 IOVCC F10 ADGND F11 ADVCC F12 TCVCM1 CODEC IN F13 TCMIC1N CODEC IN F14 TCVBUF1 CODEC IN F15 TCVRFP CODEC IN G1 XA20 IOVCC G2 XA2 IOVCC G3 XA21 IOVCC G4 IOVCC G5 DSPTDO IOVCC G6 MCKO IOVCC G7 CLKIN RFVCC G8 PG7 IOVCC G9 ADC6 ADVCC G10 ADC8 ADVCC G11 ADC3 ADVCC G12 ADC2 ADVCC G13 ADC1 ADVCC G14 VREF ADVCC G15 ADC0 ADVCC H1 XA5 IOVCC H2 XA18 IOVCC H3 XA4 IOVCC H4 XA19 IOVCC H5 XA3 IOVCC H6 XA1 IOVCC H7 DSPTCK IOVCC H9 PF14 IOVCC H10 PH0 IOVCC H11 PH6 IOVCC H12 ADC7 ADVCC H13 ADC5 ADVCC

394 PinAssignments Copyright© 2013,Texas InstrumentsIncorporated

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www.ti.com SNOSCW5 –MAY 2013 Table37-1.Pin Assignments for224-PinPackage (continued) PIN SIGNAL NAME POWER SUPPLY DOMAIN H14 ADC4 ADVCC H15 ADC9 ADVCC J1 IOVCC J2 GND J3 XA7 IOVCC J4 XA16 IOVCC J5 XA6 IOVCC J6 XA17 IOVCC J7 IOGND J8 XD6 IOVCC J9 XD9 IOVCC J10 XD13 IOVCC J11 PH5 IOVCC J12 PF15 IOVCC J13 IOGND J14 VCC J15 GND K1 XA8 IOVCC K2 XA14 IOVCC K3 XA9 IOVCC K4 XA15 IOVCC K5 IOGND K6 VCC K7 IOGND K8 IOGND K9 XD21 IOVCC K10 PLLVCC K11 PLLGND K12 RESET IOVCC K13 PH4 IOVCC K14 PF13 IOVCC K15 PF12 IOVCC L1 XA10 IOVCC L2 XA12 IOVCC L3 XA11 IOVCC L4 IOVCC L5 XA13 IOVCC L6 XD3 IOVCC L7 IOVCC L8 XD8 IOVCC L9 XD11 IOVCC L10 XD18 IOVCC L11 XD16 IOVCC L12 PF8 IOVCC L13 X2CK0 PLLVCC L14 X2CKI PLLVCC L15 IOVCC Copyright© 2013,Texas InstrumentsIncorporated PinAssignments 395 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table37-1.Pin Assignments for224-PinPackage (continued) PIN SIGNAL NAME POWER SUPPLY DOMAIN M1 XWE IOVCC M2 XBE1 IOVCC M3 XBE0 IOVCC M4 XOE IOVCC M5 IOVCC M6 XD4 IOVCC M7 XD24 IOVCC M8 XD23 IOVCC M9 XD20 IOVCC M10 IOGND M11 ENV0 IOVCC M12 RDY IOVCC M13 UGND M14 X1CKO PLLVCC M15 X1CKI PLLVCC N1 IOGND N2 XCS1 IOVCC N3 XBE2 IOVCC N4 XD30 IOVCC N5 XD28 IOVCC N6 XD26 IOVCC N7 VCC N8 XD22 IOVCC N9 IOVCC N10 XD17 IOVCC N11 TDI IOVCC N12 TCK IOVCC N13 UVCC N14 VBUS UVCC N15 D+ UVCC P1 XBE3 IOVCC P2 XCS2 IOVCC P3 XD31 IOVCC P4 XD2 IOVCC P5 XD27 IOVCC P6 XD25 IOVCC P7 GND P8 IOGND P9 XD19 IOVCC P10 XD15 IOVCC P11 TDO IOVCC P12 PF10 IOVCC P13 PE1 IOVCC P14 PE0 IOVCC P15 D – UVCC R1 XCS0 IOVCC R2 XD0 IOVCC

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B C D E F G H A J K L M CP3SP33 www.ti.com SNOSCW5 –MAY 2013 Table37-1.Pin Assignments for224-PinPackage (continued) PIN SIGNAL NAME POWER SUPPLY DOMAIN R3 XD1 IOVCC R4 XD29 IOVCC R5 XD5 IOVCC R6 XD7 IOVCC R7 IOVCC R8 XD10 IOVCC R9 XD12 IOVCC R10 XD14 IOVCC R11 ENV1 IOVCC R12 TMS IOVCC R13 PF9 IOVCC R14 PE3 IOVCC R15 PE2 IOVCC FBGA PACKAGE 144-PIN (TOP VIEW) Table37-2.Pin Assignments for144-PinPackage PIN SIGNAL NAME POWER SUPPLY DOMAIN A1 PE9 IOVCC A2 PE10 IOVCC A3 PE13 IOVCC A4 PH3 IOVCC A5 PF11 IOVCC A6 PF3 RFVCC A7 PF2 RFVCC A8 CLKIN RFVCC A9 GND A10 PG1 IOVCC Copyright© 2013,Texas InstrumentsIncorporated PinAssignments 397 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table37-2.Pin Assignments for144-PinPackage (continued) PIN SIGNAL NAME POWER SUPPLY DOMAIN A11 PH9 IOVCC A12 PH8 IOVCC B1 PE5 IOVCC B2 PE7 IOVCC B3 PE8 IOVCC B4 PE12 IOVCC B5 PH2 IOVCC B6 RFCE RFVCC B7 PF0 RFVCC B8 VCC B9 PG0 IOVCC B10 TCRP CODEC OUT B11 TCRN CODEC OUT B12 TCLN CODEC OUT C1 XA2 IOVCC C2 XA0 IOVCC C3 PE6 IOVCC C4 IOGND C5 PE15 IOVCC C6 PF4 RFVCC C7 PF1 RFVCC C8 IOVCC C9 PG2 IOVCC C10 TCDACVCC CODEC OUT C11 TCDACGND CODEC OUT C12 TCLP CODEC OUT D1 XA19 IOVCC D2 XA3 IOVCC D3 XA1 IOVCC D4 PE11 IOVCC D5 PE14 IOVCC D6 IOGND D7 RFDATA RFVCC D8 PG3 IOVCC D9 PH10 IOVCC D10 TCADCGND CODEC IN D11 TCADCVCC CODEC IN D12 TCVBUF2 CODEC IN E1 XA5 IOVCC E2 XA18 IOVCC E3 XA4 IOVCC E4 XA20 IOVCC E5 IOVCC E6 IOVCC E7 RFVCC E8 PH7 IOVCC E9 TCMIC2N CODEC IN

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www.ti.com SNOSCW5 –MAY 2013 Table37-2.Pin Assignments for144-PinPackage (continued) PIN SIGNAL NAME POWER SUPPLY DOMAIN E10 TCMIC2P CODEC IN E11 TCVRFN CODEC IN E12 TCMIC1P CODEC IN F1 XA7 IOVCC F2 XA16 IOVCC F3 XA6 IOVCC F4 XA17 IOVCC F5 IOGND F6 PH1 IOVCC F7 RFGND F8 TCVCM2 CODEC IN F9 TCMIC1N CODEC IN F10 TCVBUF1 CODEC IN F11 TCVRFP CODEC IN F12 TCVCM1 CODEC IN G1 IOVCC G2 GND G3 VCC G4 IOGND G5 XA12 IOVCC G6 GND G7 TDO IOVCC G8 PE3 IOVCC G9 ADC1 ADVCC G10 ADC0 ADVCC G11 ADGND G12 ADVCC H1 XA15 IOVCC H2 XA8 IOVCC H3 XA14 IOVCC H4 XA9 IOVCC H5 XWE IOVCC H6 IOVCC H7 ENV1 IOVCC H8 X2CK0 PLLVCC H9 X2CKI PLLVCC H10 RESET IOVCC H11 VCC H12 GND J1 XA13 IOVCC J2 XA10 IOVCC J3 XOE IOVCC J4 XD2 IOVCC J5 XD5 IOVCC J6 XD9 IOVCC J7 XD15 IOVCC J8 TCK IOVCC Copyright© 2013,Texas InstrumentsIncorporated PinAssignments 399 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

SNOSCW5 –MAY 2013 www.ti.com Table37-2.Pin Assignments for144-PinPackage (continued) PIN SIGNAL NAME POWER SUPPLY DOMAIN J9 X1CKI PLLVCC J10 X1CKO PLLVCC J11 PLLGND J12 PLLVCC K1 XA11 IOVCC K2 XBE0 IOVCC K3 XCS0 IOVCC K4 XD4 IOVCC K5 XD6 IOVCC K6 XD10 IOVCC K7 XD13 IOVCC K8 TMS IOVCC K9 PF10 IOVCC K10 UVCC K11 UGND K12 D+ UVCC L1 XBE1 IOVCC L2 XCS1 IOVCC L3 XD0 IOVCC L4 XD3 IOVCC L5 VCC L6 IOGND L7 XD14 IOVCC L8 TDI IOVCC L9 PF8 IOVCC L10 PE0 IOVCC L11 VBUS UVCC L12 D – UVCC M1 XD1 IOVCC M2 IOVCC M3 IOGND M4 XD7 IOVCC M5 XD8 IOVCC M6 XD11 IOVCC M7 XD12 IOVCC M8 ENV0 IOVCC M9 RDY IOVCC M10 PF9 IOVCC M11 PE2 IOVCC M12 PE1 IOVCC

400 PinAssignments Copyright© 2013,Texas InstrumentsIncorporated

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www.ti.com SNOSCW5 –MAY 2013

37.1 PhysicalDimensions (millimeters)unlessotherwisenoted

Copyright© 2013,Texas InstrumentsIncorporated PinAssignments 401 SubmitDocumentationFeedback ProductFolderLinks:CP3SP33

www.ti.com 8-Oct-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CP3SP33SMS/NOPB ACTIVE NFBGA NZN 224 160 Green (RoHS & no Sb/Br) SNPB Level-3-260C-168 HR -40 to 85 CP3SP33SMS CP3SP33SMSX/NOPB ACTIVE NFBGA NZN 224 1000 Green (RoHS & no Sb/Br) SNPB Level-3-260C-168 HR -40 to 85 CP3SP33SMS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 8-Oct-2015 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CP3SP33SMSX/NOPB NFBGA NZN 224 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 2

www.ti.com SLC224A (Rev A)

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