CP3CN17

CP3CN17 NSC | Alldatasheet

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©2005 National Semiconductor Corporation www.national.com CP3CN17 Reprogrammable Connectivity Processor with CAN Interface FINAL APRIL 2005 CP3CN17 Reprogrammable Connectivity Processor with CAN Interface

1.0 General Description

The CP3CN17 connectivity processor combines a powerful RISC core with on-chip SRAM and Flash memory for high computing bandwidth, hardware communications peripher- als for high I/O bandwidth, and an external bus for system expandability. On-chip communications peripherals include: CAN control- ler, ACCESS.bus, Microwire/Plus, SPI, UART, and Ad- vanced Audio Interface (AAI). Additional on-chip peripherals include DMA controller, CVSD/PCM conversion module, Timing and Watchdog Unit, Versatile Timer Unit, Multi- Function Timer, and Multi-Input Wakeup. The CP3CN17 is backed up by the software resources de- signers need for rapid time-to-market, including an operat- ing system, peripheral drivers, reference designs, and an integrated development environment. National Semiconductor offers a complete and industry- proven application development environment for CP3CN17 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator, Develop- ment Board, and Application Software. Block Diagram CPU Core Bus

12 MHz and 32 kHz

.bus Versatile Timer Unit Muti-Func- tion Timer Multi-Input Wake-UpGPIO Audio Interface Microwire/ SPI UART Clock Generator DS138 TRI-STATE is a registered trademark of National Semiconductor Corporation.

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2.0 Features

„ Fully static RISC processor core, capable of operating from 0 to 24 MHz with zero wait/hold states „ Minimum 41.7 ns instruction cycle time with a 24-MHz in- ternal clock frequency, based on a 12-MHz external input „ 30 independently vectored peripheral interrupts On-Chip Memory „ 256K bytes reprogrammable Flash program memory „ 8K bytes Flash data memory „ 10K bytes of static RAM data memory „ Addresses up to 8 Mbytes of external memory Broad Range of Hardware Communications Peripherals „ Full CAN interface with 15 message buffers conforming to CAN specification 2.0B active „ ACCESS.bus serial bus (compatible with Philips I 2C bus) „ 8/16-bit SPI, Microwire/Plus serial interface „ Universal Asynchronous Receiver/Transmitter (UART) „ Advanced Audio Interface (AAI) to connect to external 8/ 13-bit PCM Codecs as well as to ISDN-Controllers through the IOM-2 interface (slave only) „ CVSD/PCM converter supporting one bidirectional audio connection General-Purpose Hardware Peripherals „ Dual 16-bit Multi-Function Timer „ Versatile Timer Unit with four subsystems (VTU) „ Four channel DMA controller „ Timing and Watchdog Unit Flexible I/O „ Up to 40 general-purpose I/O pins (shared with on-chip peripheral I/O pins) „ Programmable I/O pin characteristics: TRI-STATE out- put, push-pull output, weak pull-up input, high-imped- ance input „ Schmitt triggers on general purpose inputs „ Multi-Input Wakeup Extensive Power and Clock Management Support „ On-chip Phase Locked Loop „ Support for multiple clock options „ Dual clock and reset „ Power-down modes Power Supply „ I/O port operation at 2.5V to 3.3V „ Core logic operation at 2.5V „ On-chip power-on reset Temperature Range „ -40°C to +85°C (Industrial) Packages „ CSP-48, LQFP-100 Complete Development Environment „ Pre-integrated hardware and software support for rapid prototyping and production „ Integrated environment „ Project manager „ Multi-file C source editor CP3CN17 Connectivity Processor Selection Guide NSID Speed (MHz) Temp. Range Program Flash (kBytes) Data Flash (kBytes) SRAM (kBytes) External Address Lines I/Os Package Type Pack Method CP3CN17G38 24 -40° to +85°C 256 8 10 23 40 LQFP-100 Tray CP3CN17G38X 24 -40° to +85°C 256 8 10 23 40 LQFP-100 1000-T&R CP3CN17K38X 24 -40° to +85°C 256 8 10 0 23 CSP-48 2500-T&R CP3CN17K38Y 24 -40° to +85°C 256 8 10 0 23 CSP-48 250-T&R T&R = Tape and Reel

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3.0 Device Overview

The CP3CN17 connectivity processor is a complete micro- computer with all system timi ng, interrupt logic, program memory, data memory, I/O ports included on-chip, making them well-suited to a wide range of embedded applications. The block diagram on page 1 shows the major on-chip com- ponents of the CP3CN17.

3.1 CR16C CPU CORE

The CP3CN17 implements the CR16C CPU core module. The high performance of the CPU core results from the im- plementation of a pipelined architecture with a two-bytes- per-cycle pipelined system bus. As a result, the CPU can support a peak execution rate of one instruction per clock cycle. For more information, please refer to the CR16C Program- mer’s Reference Manual (document number 424521772- 101, which may be downloaded from National’s web site at http://www.national.com).

3.2 MEMORY

The CP3CN17 supports a uniform linear address space of up to 16 megabytes. Three types of on-chip memory occupy specific regions within this address space: „ 256K bytes of Flash program memory „ 8K bytes of Flash data memory „ 10K bytes of static RAM „ Up to 8M bytes of external memory (100-pin devices) The 256K bytes of Flash program memory are used to store the application program and real-time operating system. The Flash memory has security features to prevent uninten- tional programming and to prevent unauthorized access to the program code. This memory can be programmed with an external programming unit or with the device installed in the application system (in-system programming). The 8K bytes of Flash data memory are used for non-vola- tile storage of data entered by the end-user, such as config- uration settings. The 10K bytes of static RAM are used for temporary storage of data and for the program stack and interrupt stack. Read and write operations can be byte-wide or word-wide, de- pending on the instruction executed by the CPU. Up to 8M bytes of external memory can be added on an ex- ternal bus. The external bus is only available on devices in 100-pin packages. For Flash program and data memory, the device internally generates the necessary voltages for programming. No ad- ditional power supply is required.

3.3 INPUT/OUTPUT PORTS

The device has up to 40 software-configurable I/O pins, or- ganized into five 8-pin ports called Port B, Port C, Port G, Port H, and Port I. Each pin can be configured to operate as a general-purpose input or general-purpose output. In addi- tion, many I/O pins can be configured to operate as inputs or outputs for on-chip peripheral modules such as the UART, timers, or Microwire/SPI interface. The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-STATE output, push- pull output, weak pull-up input, or high-impedance input.

3.4 BUS INTERFACE UNIT

The Bus Interface Unit (BIU) controls access to internal/ex- ternal memory and I/O. It determines the configured param- eters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for each requested access. The BIU uses a set of control registers to determine how many wait states and hold states are used when accessing Flash program memory, and the I/O area (Port B and Port C). At start-up, the configuration registers are set for slowest possible memory access. To achieve fastest possible pro- gram execution, appropriate values must be programmed. These settings vary with the clock frequency and the type of off-chip device being accessed.

3.5 INTERRUPT CONTROL UNIT (ICU)

The ICU receives interrupt requests from internal and exter- nal sources and generates interrupts to the CPU. An inter- rupt is an event that temporarily stops the normal flow of program execution and causes a separate interrupt handler to be executed. After the interrupt is serviced, CPU execu- tion continues with the next in struction in the program fol- lowing the point of interruption. Interrupts from the timers, UART, Microwire/SPI interface, and Multi-Input Wake-Up, are all maskable interrupts; they can be enabled or disabled by software. There are 32 of these maskable interrupts, assigned to 32 linear priority lev- els. The highest-priority interrupt is the Non-Maskable Interrupt (NMI ), which is generated by a signal received on the NMI input pin.

3.6 MULTI-INPUT WAKE-UP

The Multi-Input Wake-Up (MIWU) module can be used for either of two purposes: to provide inputs for waking up (ex- iting) from the Halt, Idle, or Power Save mode; or to provide general-purpose edge-triggered maskable interrupts from external sources. This 16-channel module generates four programmable interrupts to the CPU based on the signals received on its 16 input channels. Channels can be individ- ually enabled or disabled, and programmed to respond to positive or negative edges.

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3.7 TRIPLE CLOCK AND RESET

The Triple Clock and Reset module generates a high-speed main System Clock from an external crystal network. It also provides the main system reset signal and a power-on reset function. This module generates a slow System Clock (32.768 kHz) from an optional external crystal network. The Slow Clock is used for operating the device in power-save mode. The 32.768 kHz external crystal network is optional, because the low speed System Clock can be derived from the high- speed clock by a prescaler. Also, two independent clocks divided down from the high speed clock are available on output pins. The Triple Clock and Reset module provides the clock sig- nals required for the operation of the various CP3CN17 on- chip modules. From external crystal networks, it generates the Main Clock, which can be scaled up to 24 MHz from an external 12 MHz input clock, and a 32.768 kHz secondary System Clock. The 12 MHz external clock is primarily used as the reference frequency for the on-chip PLL. Also the clock for modules which require a fixed clock rate (e.g. the CVSD/PCM transcoder) is generated through prescalers from the 12 MHz clock. The PLL may be used to drive the high-speed System Clock through a prescaler. Alternatively, the high speed System Clock can be derived directly from the 12 MHz Main Clock. In addition, this module generates the device reset by using reset input signals coming from an external reset and vari- ous on-chip modules.

3.8 POWER MANAGEMENT

The Power Management Module (PMM) improves the effi- ciency of the device by changing the operating mode and power consumption to match the required level of activity. The device can operate in any of four power modes: „ Active—The device runs at full speed using the high-fre- quency clock. All device functions are fully operational. „ Power Save—The device operates at reduced speed us- ing the Slow Clock. The CPU and some modules can continue to operate at this low speed. „ Idle—The device is inactive except for the Power Man- agement Module and Timing and Watchdog Module, which continue to operate using the Slow Clock. „ Halt—The device is inactive bu t still retains its internal state (RAM and register contents).

3.9 MULTI-FUNCTION TIMER

The Multi-Function Timer (MFT) module contains a pair of 16-bit timer/counter registers. Each timer/counter unit can be configured to operate in any of the following modes: „ Processor-Independent Pulse Width Modulation (PWM) mode—Generates pulses of a specified width and duty cycle and provides a general-purpose timer/counter. „ Dual Input Capture mode —Measures the elapsed time between occurrences of external event and provides a general-purpose timer/counter. „ Dual Independent Timer mode—Generates system tim- ing signals or counts occurrences of external events. „ Single Input Capture and Single Timer mode—Provides one external event counter and one system timer.

3.10 VERSATILE TIMER UNIT

The Versatile Timer Unit (VTU) module contains four inde- pendent timer subsystems, each operating in either dual 8- bit PWM configuration, as a single 16-bit PWM timer, or a 16-bit counter with two input capture channels. Each of the four timer subsystems offer an 8-bit clock prescaler to ac- commodate a wide range of frequencies.

3.11 TIMING AND WATCHDOG MODULE

The Timing and Watchdog Module (TWM) contains a Real- Time timer and a Watchdog unit. The Real-Time Clock Tim- ing function can be used to generate periodic real-time based system interrupt s. The timer output is one of 16 in- puts to the Multi-Input-Wake-Up module which can be used to exit from a power-saving mode. The Watchdog unit is de- signed to detect the application program getting stuck in an infinite loop resulting in loss of program control or “runaway” programs. When the watchdog triggers, it resets the device. The TWM is clocked by the low-speed System Clock.

3.12 UART

The UART supports a wide range of programmable baud rates and data formats, parity generation, and several error detection schemes. The baud rate is generated on-chip, un- der software control. The UART offers a wake-up condition from the power-save mode using the Multi-Input Wake-Up module.

3.13 MICROWIRE/SPI

The Microwire/SPI (MWSPI) interface module supports syn- chronous serial communications with other devices that conform to Microwire or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and 16-bit data transfers. The Microwire interface allows several devices to communi- cate over a single system consisting of four wires: serial in, serial out, shift clock, and slave enable. At any given time, the Microwire interface operates as the master or a slave. The Microwire interface supports the full set of slave select for multi-slave implementation. In master mode, the shift clock is generated on chip under software control. In slave mode, a wake-up out of power- save mode is triggered using the Multi-Input Wake-Up mod- ule.

3.14 CAN INTERFACE

The CAN module contains a Full CAN 2.0B class, CAN se- rial bus interface for applications that require a high-speed (up to 1Mbits per second) or a low-speed interface with CAN bus master capability. The data transfer between CAN and the CPU is established by 15 memory-mapped message buffers, which can be individually configured as receive or transmit buffers. An incoming message is filtered by two masks, one for the first 14 message buffers and another one for the 15th message buffer to provide a basic CAN path. A priority decoder allows any buffer to have the highest or low- est transmit priority. Remote transmission requests can be processed automatically by aut omatic reconfiguration to a receiver after transmission or by automated transmit sched-

www.national.com 6 CP3CN17 uling upon reception. In addition, a time stamp counter (16- bits wide) is provided to support real time applications. The CAN module is a fast core bus peripheral, which allows single cycle byte or word read /write access. A set of diag- nostic features (such as loopback, listen only, and error identification) support the development with the CAN mod- ule and provide a sophisticated error management tool. The CAN receiver can trigger a wake-up condition out of the low-power modes through the Multi-Input Wake-Up module. 3.15 ACCESS.BUS INTERFACE The ACCESS.bus interface module (ACB) is a two-wire se- rial interface with the ACCESS.bus physical layer. It is also compatible with Intel’s System Management Bus (SMBus) and Philips’ I2C bus. The ACB module can be configured as a bus master or slave, and can maintain bidirectional com- munications with both multiple master and slave devices. The ACCESS.bus receiver can trigger a wake-up condition out of the low-power modes using the Multi-Input Wake-Up module.

3.16 DMA CONTROLLER

The Direct Memory Access Co ntroller (DMAC) can speed up data transfer between memory and I/O devices or be- tween two memories, relative to data transfers performed di- rectly by the CPU. A method called cycle-stealing allows the CPU and the DMAC to use the core bus in parallel. The DMAC implements four independent DMA channels. DMA requests from a primary and a secondary source are recog- nized for each DMA channel, as well as a software DMA re- quest issued directly by the CPU. Table 1 shows the DMA channel assignment on the CP3CN17 architecture. The fol- lowing on-chip modules can assert a DMA request to the DMAC: „ CR16C (Software DMA request) „ UART „ Advanced Audio Interface „ CVSD/PCM Converter Table 1 shows how the four DMA channels are assigned to the modules listed above. Table 1 DMA Channel Assignment

3.17 ADVANCED AUDIO INTERFACE

The audio interface provides a serial synchronous, full-du- plex interface to codecs and similar serial devices. Transmit and receive paths operate asynchronously with respect to each other. Each path uses three signals for communica- tion: shift clock, frame synchronization, and data. In case receive and transmit use separate shift clocks and frame sync signals, the interfac e operates in its asynchro- nous mode. Alternatively, the transmit and receive path can share the same shift clock and frame sync signals for syn- chronous mode operation. The interface can handle data words of either 8- or 16-bit length and data frames can consist of up to four slots. In the normal mode of operation, the interface only transfers one word at a periodic rate. In the network mode, the inter- face transfers multiple words at a periodic rate. The periodic rate is also called a data frame and each word within one frame is called a slot. The beginning of each new data frame is marked by the frame sync signal.

3.18 CVSD/PCM CONVERSION MODULE

The CVSD/PCM module performs conversion between CVSD and PCM data, in which the CVSD encoding is as de- fined in the Bluetooth specif ication 1.0 and the PCM data can be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear.

3.19 SERIAL DEBUG INTERFACE

The Serial Debug Interface module (SDI module) provides a JTAG-based serial link to an external debugger, for exam- ple running on a PC. In addition, the SDI module integrates an on-chip debug module, which allows the user to set up to four hardware breakpoints on instruction execution and data transfer. The SDI module can act as a CPU bus master to access all memory mapped resources, such as RAM and peripherals. It also provides fast program download into the on-chip Flash program memory using the JTAG interface. Note: The SDI module may assert Freeze mode to gather information, which may cause periodic fluctuations in re- sponse (bus availability, interrupt latency, etc.). Anomalous behavior often may be traced to SDI activity.

3.20 DEVELOPMENT SUPPORT

The CP3CN17 is backed up by the software resources de- signers need for rapid time-to-market, including an operat- ing system, peripheral drivers, reference designs, and an integrated development environment. National Semiconductor offers a complete and industry- proven application development environment for CP3CN17 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator, Develop- ment Board, and Application Software. See your National Semiconductor sales representative for current information on availability and features of emulation equipment and evaluation boards. Channel Primary/ Secondary Peripheral Transaction Primary Reserved N/A Secondary UART Read Primary UART Write Secondary Unused N/A Primary AAI Read Secondary CVSD/PCM Read Primary AAI Write Secondary CVSD/PCM Write

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4.0 Device Pinouts

Table 2 Pin Assignment s for 100-Pin Package Pin Name Alternate Function(s) Pin Number Type A14 1 O A13 2 O A12 3 O A11 4 O A10 5 O PH6 STD/TIO7 6 GPIO PH7 SRD/TIO8 7 GPIO ENV1 8 I/O A9 9 O A8 10 O A7 11 O A6 12 O A5 13 O X1CKI12 MHz Crystal or Ext. Clock External Bus Interface X1CKO X2CKI32.768 kHz Crystal GPIO X2CKO AVCC IOVCC GND AGND VCC PI0 PI1 PI2/SRCLK CP3CN17 (LQFP-100) SDAACCESS.bus SCL ENV0 Mode Selection ENV1 UART/ MIWU PG0/RXD/WUI10 PG1/TXD/WUI11 PG2/RTS/WUI12 PG3/CTS/WUI13 PI3 PI4 PI5 PI6/WUI9 Power Supply RESETChip Reset PG5/SRFS/NMI MIWU PG4/CKX/TB UART/MFT PI7/TA MFT TMS TCK RDY TDI TDO JTAG I/F to Debugger/ Programmer MICROWIRE/ SPI/ VTU PH0/MSK/TIO1 PH1/MDIDO/TIO2 PH2/MDODI/TIO3 PH3/MWCS/TIO4 AAI/ VTU PH4/SCK/TIO5 PH5/SFS/TIO6 PH6/STD/TIO7 PH7/SRD/TIO8 ENV2 PG6/CANRX/ WUI14CAN/ MIWU PG7/CANTX/ WUI15 PB[7:0] PC[7:0] A[22:0] SEL0 SEL1 SEL2 SELIO WR0 WR1 RD AAI AAI/NMI X1CKI12 MHz Crystal or Ext. Clock CAN/ MIWU X1CKO PG6/CANRX/WUI14 PG7/CANTX/WUI15 ACCESS.busSDA SCL X2CKI32.768 kHz Crystal GPIO X2CKO AVCC IOVCC GND AGND VCC PI0 PI1 PI2/SRCLK CP3CN17 (CSP-48) Mode Selection UART/ MIWU PI3 PI4 PI5 PI6/WUI9 Power Supply Chip Reset MIWU PI7/TA MFT JTAG I/F to Debugger/ Programmer MICROWIRE SPI/ VTU PH0/MSK/TIO1 PH1/MDIDO/TIO2 PH2/MDODI/TIO3 AAI/ VTU PH4/SCK/TIO5 PH5/SFS/TIO6 PH6/STD/TIO7 PH7/SRD/TIO8 ENV0 ENV1 RESET PG5/SRFS/NMI TMS TCK RDY TDI TDO PG0/RXD/WUI10 PG1/TXD/WUI11 PG2/RTS/WUI12 PG3/CTS/WUI13 PH3/MWCS/TIO4 DS140 AAI AAI/NMI

www.national.com 8 CP3CN17 A4 14 O VCC 15 PWR X2CKI 16 I X2CKO 17 O GND 18 PWR AVCC 19 PWR AGND 20 PWR IOVCC 21 PWR X1CKO 22 O X1CKI 23 I GND 24 PWR A3 26 O A2 27 O A1 28 O A0 29 O PI0 30 GPIO PI1 31 GPIO PI2 SRCLK 32 GPIO PB0 D0 33 GPIO PB1 D1 34 GPIO PB2 D2 35 GPIO PB3 D3 36 GPIO PB4 D4 37 GPIO PB5 D5 38 GPIO PB6 D6 39 GPIO PB7 D7 40 GPIO GND 41 PWR IOVCC 42 PWR PI3 43 GPIO PI4 44 GPIO PI5 45 GPIO PI6 WUI9 46 GPIO PI7 TA 47 GPIO PG0 RXD/WUI10 48 GPIO PG1 TXD/WUI11 49 GPIO PC0 D8 50 GPIO PG2 RTS /WUI12 51 GPIO PG3 CTS /WUI13 52 GPIO PC1 D9 53 GPIO PC2 D10 54 GPIO PC3 D11 55 GPIO PC4 D12 56 GPIO PC5 D13 57 GPIO Table 2 Pin Assignment s for 100-Pin Package Pin Name Alternate Function(s) Pin Number Type

9 www.national.com CP3CN17 PC6 D14 58 GPIO PC7 D15 59 GPIO PG5 SRFS/NMI 60 GPIO TMS 61 I TCK 62 I TDI 63 I GND 64 PWR IOVCC 65 PWR ENV2 66 I/O SEL0 67 O PG4 CKX/TB 68 GPIO PG6 CANRX/WUI14 69 GPIO PG7 CANTX/WUI15 70 GPIO SCL 71 I/O SDA 72 I/O TDO 73 O A22 74 O RDY 75 O SEL1 76 O SEL2 77 O SELIO 78 O A21 79 O A20 80 O PH0 MSK/TIO1 81 GPIO PH1 MDIDO/TIO2 82 GPIO PH2 MDODI/TIO3 83 GPIO PH3 MWCS /TIO4 84 GPIO ENV0 85 I/O IOVCC 86 PWR GND 87 PWR VCC 88 PWR GND 89 PWR RESET 90 I RD 91 O WR0 92 O WR1 93 O A19 94 O A18 95 O A17 96 O A16 97 O A15 98 O Table 2 Pin Assignment s for 100-Pin Package Pin Name Alternate Function(s) Pin Number Type

www.national.com 10 CP3CN17 Table 3 Pin Assignments for 48-Pin Package PH4 SCK/TIO5 99 GPIO PH5 SFS/TIO6 100 GPIO Note 1: The ENV0, ENV1, ENV2, TCK, TDI, and TMS pins each have a weak pull-up to keep the input from floating. Note 2: The RESET input has a weak pulldown. Note 3: These functions are always enabled, due to the direct low-impedance path to these pins. Pin Name Alternate Function(s) Pin Number Type PH6 STD/TIO7 1 GPIO PH7 SRD/TIO8 2 GPIO ENV1 3 I/O VCC 4 PWR X2CKI 5 I X2CKO 6 O GND 7 PWR AVCC 8 PWR AGND 9 PWR IOVCC 10 PWR X1CKO 11 O X1CKI 12 I GND 13 PWR PI0 15 GPIO PI1 16 GPIO PI2 SRCLK 17 GPIO PI3 18 GPIO PI4 19 GPIO PI5 20 GPIO PI6 WUI9 21 GPIO PI7 TA 22 GPIO PG0 RXD/WUI10 23 GPIO PG1 TXD/WUI11 24 GPIO PG2 RTS /WUI12 25 GPIO PG3 CTS /WUI13 26 GPIO PG5 SRFS/NMI 27 GPIO TMS 28 I TCK 29 I TDI 30 I GND 31 PWR IOVCC 32 PWR PG6 CANRX/WUI14 33 O, GPIO PG7 CANTX/WUI15 34 O, GPIO SCL 35 I/O SDA 36 PWR, I/O TDO 37 PWR, O Table 2 Pin Assignment s for 100-Pin Package Pin Name Alternate Function(s) Pin Number Type

11 www.national.com CP3CN17 RDY 38 O PH0 MSK/TIO1 39 GPIO PH1 MDIDO/TIO2 40 GPIO PH2 MDODI/TIO3 41 GPIO PH3 MWCS /TIO4 42 GPIO ENV0 43 I/O VCC 44 PWR GND 45 PWR RESET 46 I PH4 SCK/TIO5 47 GPIO PH5 SFS/TIO6 48 GPIO Note 1: The ENV0 and ENV1, TCK, TDI and TMS pins each have a weak pull-up to keep the input from floating. Note 2: The RESET input has a weak pulldown. Note 3: These functions are always enabled, due to the direct low-impedance path to these pins. Pin Name Alternate Function(s) Pin Number Type

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4.1 PIN DESCRIPTION

Some pins may be enabled as general-purpose I/O-port pins or as alternate functions associated with specific pe- ripherals or interfaces. These pins may be individually con- figured as port pins, even when the associated peripheral or interface is enabled. Table 4 lists the device pins. Table 4 Pin Description for the 100-Pin LQFP Package Name Pins I/O Primary Function Alternate Name Alternate Function X1CKI 1 Input 12 MHz Osc illator Input None None X1CKO 1 Output 12 MHz Oscillator Output None None X2CKI 1 Input 32 kHz Oscillator Input None None X2CKO 1 Output 32 kHz Oscillator Output None None AVCC 1 Input PLL Analog Power Supply None None IOVCC 4 Input 2.5V - 3.3V I/O Power Supply None None VCC 2 Input 2.5V Core Logic Power Supply None None GND 6 Input Reference Ground None None AGND 1 Input PLL Analog Ground None None RESET

1 Input Chip general reset None None

TMS 1 Input JTAG Test Mode Select (with internal weak pull-up) None None TDI 1 Input JTAG Test Data Input (with internal weak pull-up) None None TDO 1 Output JTAG Test Data Output None None TCK 1 Input JTAG Test Clock Input (with internal weak pull-up) None None RDY

1 Output NEXUS Ready Output None None

RXD UART Receive Data Input WUI10 Multi-Input Wake-Up Channel 10 PG1 1 I/O Generic I/O TXD UART Transmit Data Output WUI11 Multi-Input Wake-Up Channel 11 PG2 1 I/O Generic I/O RTS UART Ready-To-Send Output WUI12 Multi-Input Wake-Up Channel 12 PG3 1 I/O Generic I/O CTS UART Clear-To-Send Input WUI13 Multi-Input Wake-Up Channel 13 PG4 1 I/O Generic I/O CKX UART Clock Input TB Multi Function Timer Port B PG5 1 I/O Generic I/O SRFS AAI Receive Frame Sync NMI Non-Maskable Interrupt Input PG6 1 I/O Generic I/O CANRX CAN Receive Pin WUI14 Multi-Input Wake-Up Channel 14 PG7 1 I/O Generic I/O CANTX CAN Transmit Pin WUI15 Multi-Input Wake-Up Channel 15

13 www.national.com CP3CN17 PH0 1 I/O Generic I/O MSK SPI Shift Clock TIO1 Versatile Timer Channel 1 PH1 1 I/O Generic I/O MDIDO SPI Master In Slave Out TIO2 Versatile Timer Channel 2 PH2 1 I/O Generic I/O MDODI SPI Master Out Slave In TIO3 Versatile Timer Channel 3 PH3 1 I/O Generic I/O MWCS SPI Slave Select Input TIO4 Versatile Timer Channel 4 PH4 1 I/O Generic I/O SCK AAI Clock TIO5 Versatile Timer Channel 5 PH5 1 I/O Generic I/O SFS AAI Frame Synchronization TIO6 Versatile Timer Channel 6 PH6 1 I/O Generic I/O STD AAI Transmit Data Output TIO7 Versatile Timer Channel 7 PH7 1 I/O Generic I/O SRD AAI Receive Data Input TIO8 Versatile Timer Channel 8 PI0 1 I/O Generic I/O None None PI1 1 I/O Generic I/O None None PI2 1 I/O Generic I/O SRCLK AAI Receive Clock PI3 1 I/O Generic I/O None None PI4 1 I/O Generic I/O None None PI5 1 I/O Generic I/O None None PI6 1 I/O Generic I/O WUI9 Multi-Input Wake-Up Channel 9 PI7 1 I/O Generic I/O TA Multi Function Timer Port A SDA 1 I/O ACCESS.bus Serial Data None None SCL 1 I/O ACCESS.bus Clock None None PB[7:0] 8 I/O Generic I/O D[7:0] External Data Bus Bit 0 to 7 PC[7:0] 8 I/O Generic I/O D[15:8] Ex ternal Data Bus Bit 8 to 15 A[22:0] 23 Output External Address Bus Bit 0 to 22 None None SEL0

1 Output Chip Select for Zone 0 None None

SEL1 1 Output Chip Select for Zone 1 None None SEL2 1 Output Chip Select for Zone 2 None None SELIO 1 Output Chip Select for Zone I/O Zone None None WR0 1 Output External Memory Write Low Byte None None WR1 1 Output External Memory Write High Byte None None RD 1 Output External Memory Read None None ENV0 1 I/O Special mode select input with in- ternal pull-up during reset PLLCLK PLL Clock Output Name Pins I/O Primary Function Alternate Name Alternate Function

www.national.com 14 CP3CN17 Table 5 CP3CN17 Pin Description for the 48-Pin CSP ENV1 1 I/O Special mode select input with in- ternal pull-up during reset CPUCLK CPU Clock Output ENV2 1 I/O Special mode select input with in- ternal pull-up during reset SLOWCLK Slow Clock Output Name Pins I/O Primary Function Alternate Name Alternate Function Name Pins I/O Primary Function Alternate Name Alternate Function X1CKI 1 Input 12 MHz Osc illator Input None None X1CKO 1 Output 12 MHz Oscillator Output None None X2CKI 1 Input 32 kHz Oscillator Input None None X2CKO 1 Output 32 kHz Oscillator Output None None AVCC 1 Input PLL Analog Power Supply None None IOVCC 2 Input 2.5V - 3.3V I/O Power Supply None None VCC 2 Input 2.5V Core Logic Power Supply None None GND 4 Input Reference Ground None None AGND 1 Input PLL Analog Ground None None RESET TMS 1 Input JTAG Test Mode Select (with internal weak pull-up) None None TDI 1 Input JTAG Test Data Input (with internal weak pull-up) None None TDO 1 Output JTAG Test Data Output None None TCK 1 Input JTAG Test Clock Input (with internal weak pull-up) None None RDY RXD UART Receive Data Input WUI10 Multi-Input Wake-Up Channel 10 PG1 1 I/O Generic I/O TXD UART Transmit Data Output WUI11 Multi-Input Wake-Up Channel 11 PG2 1 I/O Generic I/O RTS UART Ready-To-Send Output WUI12 Multi-Input Wake-Up Channel 12 PG3 1 I/O Generic I/O CTS UART Clear-To-Send Input WUI13 Multi-Input Wake-Up Channel 13 PG5 1 I/O Generic I/O SRFS AAI Receive Frame Sync NMI Non-Maskable Interrupt Input PG6 1 I/O Generic I/O CANRX CAN Receive Pin WUI14 Multi-Input Wake-Up Channel 14 PG7 1 I/O Generic I/O CANTX CAN Transmit Pin WUI15 Multi-Input Wake-Up Channel 15

15 www.national.com CP3CN17 PH0 1 I/O Generic I/O MSK SPI Shift Clock TIO1 Versatile Timer Channel 1 PH1 1 I/O Generic I/O MDIDO SPI Master In Slave Out TIO2 Versatile Timer Channel 2 PH2 1 I/O Generic I/O MDODI SPI Master Out Slave In TIO3 Versatile Timer Channel 3 PH3 1 I/O Generic I/O MWCS SPI Slave Select Input TIO4 Versatile Timer Channel 4 PH4 1 I/O Generic I/O SCK AAI Clock TIO5 Versatile Timer Channel 5 PH5 1 I/O Generic I/O SFS AAI Frame Synchronization TIO6 Versatile Timer Channel 6 PH6 1 I/O Generic I/O STD AAI Transmit Data Output TIO7 Versatile Timer Channel 7 PH7 1 I/O Generic I/O SRD AAI Receive Data Input TIO8 Versatile Timer Channel 8 PI0 1 I/O Generic I/O None None PI1 1 I/O Generic I/O None None PI2 1 I/O Generic I/O SRCLK AAI Receive Clock PI3 1 I/O Generic I/O None None PI4 1 I/O Generic I/O None None PI5 1 I/O Generic I/O None None PI6 1 I/O Generic I/O WUI9 Multi-Input Wake-Up Channel 9 PI7 1 I/O Generic I/O TA Multi Function Timer Port A SDA 1 I/O ACCESS.bus Serial Data None None SCL 1 I/O ACCESS.bus Clock None None ENV0 1 I/O Special mode select input with in- ternal pull-up during reset PLLCLK PLL Clock Output ENV1 1 I/O Special mode select input with in- ternal pull-up during reset CPUCLK CPU Clock Output Name Pins I/O Primary Function Alternate Name Alternate Function

5.0 CPU Architecture

Semiconductor web site (http://www.nsc.com). R12, R13, RA, SP , ISP and USP registers are 32 bits wide. Figure 1. CPU Registers

5.1 GENERAL-PURPOSE REGISTERS

of the earlier CR16A/B CPU cores: (R1,R0), (R2,R1) ... dresses greater than 16 bits. addresses used in the index addressing mode. used. The upper word is not referenced or modified.

5.2 DEDICATED ADDRESS REGISTERS

5.2.1 Program Counter (PC) Register

the (R1,R0) general-purpose register pair.

5.2.2 Interrupt Stack Pointer (ISP)

5.2.3 User Stack Pointer (USP)

access, an IAD trap is taken.

17 www.national.com CP3CN17

5.2.4 Interrupt Base Register (INTBASE)

The INTBASE register holds the address of the dispatch ta- ble for exceptions. The dispatch table can be located any- where in the CPU address space. When loading the INTBASE register, bits 31 to 24 and bit 0 must written with 0.

5.3 PROCESSOR STATUS REGISTER (PSR)

The PSR provides state information and controls operating modes for the CPU. The format of the PSR is shown below. C The Carry bit indicates whether a carry or bor- row occurred after addition or subtraction. 0 – No carry or borrow occurred. 1 – Carry or borrow occurred. T The Trace bit enables execution tracing, in which a Trace trap (TRC) is taken after every instruction. Tracing is automatically disabled during the execution of an exception handler. – Tracing disabled. 1 – Tracing enabled. L The Low bit indicates the result of the last comparison operation, with the operands in- terpreted as unsigned integers. – Second operand greater than or equal to first operand. 1 – Second operand less than first operand. U The User Mode bit controls whether the CPU is in user or supervisor mode. In supervisor mode, the SP register is used for stack opera- tions. In user mode, the USP register is used instead. User mode is entered by executing the Jump USR instruction. When an exception is taken, the except ion handler automatically begins execution in supervisor mode. The USP register is accessible using the Load Processor Register (LPR/LPRD) instruction in supervisor mode. In user mode, an attempt to access the USP register generates a UND trap. – CPU is executing in supervisor mode. 1 – CPU is executing in user mode. F The Flag bit is a general condition flag for sig- nalling exception conditions or distinguishing the results of an instruction, among other thing uses. For example, integer arithmetic in- structions use the F bit to indicate an overflow condition after an addition or subtraction oper- ation. Z The Zero bit is used by comparison opera- tions. In a comparison of integers, the Z bit is set if the two operands are equal. If the oper- ands are unequal, the Z bit is cleared. – Source and destination operands un- equal. 1 – Source and destination operands equal. N The Negative bit indicates the result of the last comparison operation, with the operands in- terpreted as signed integers. – Second operand greater than or equal to first operand. 1 – Second operand less than first operand. E The Local Maskable Interrupt Enable bit en- ables or disables maskable interrupts. If this bit and the Global Maskable Interrupt Enable (I) bit are both set, all interrupts are enabled. If either of these bits is clear, only the non- maskable interrupt is enabled. The E bit is set by the Enable Interrupts (EI) instruction and cleared by the Disable Interrupts (DI) instruc- tion. – Maskable interrupts disabled. 1 – Maskable interrupts enabled. P The Trace Trap Pending bit is used together with the Trace (T) bit to prevent a Trace (TRC) trap from occurring more than once for one in- struction. At the beginning of the execution of an instruction, the stat e of the T bit is copied into the P bit. If the P bit remains set at the end of the instruction exec ution, the TRC trap is taken. – No trace trap pending. 1 – Trace trap pending. I The Global Maskable Interrupt Enable bit is used to enable or disable maskable interrupts. If this bit and the Local Maskable Interrupt En- able (E) bit are both set, all maskable inter- rupts are taken. If either bit is clear, only the non-maskable interrupt is taken. Unlike the E bit, the I bit is automatically cleared when an interrupt occurs and automatically set upon completion of an interrupt handler. – Maskable interrupts disabled. 1 – Maskable interrupts enabled. Bits Z, C, L, N, and F of t he PSR are referenced from as- sembly language by the condition code in conditional branch instructions. A condit ional branch instruction may cause a branch in program execution, based on the value of one or more of these PSR bits. For example, one of the Bcond instructions, BEQ (Branch EQual), causes a branch if the PSR.Z bit is set. On reset, bits 0 through 11 of the PSR are cleared, except for the PSR.E bit, which is set. On warm reset, the values of each bit before reset are copied into the R2 general-pur- pose register. Bits 4 and 8 of the PSR have a constant value of 0. Bits 12 through 15 are reserved. In general, status bits are modified only by specific instructions. Otherwise, status bits maintain their values throughout instructions which do not implicitly affect them. 15 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved I P E 0 N Z F 0 U L T C

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5.4 CONFIGURATION REGISTER (CFG)

The CFG register is used to enable or disable various oper- ating modes and to control optional on-chip caches. Be- cause the CP3CN17 does not have cache memory, the cache control bits in the CFG register are reserved. All CFG bits are cleared on reset. ED The Extended Dispatch bit selects whether the size of an entry in the interrupt dispatch ta- ble (IDT) is 16 or 32 bits. Each entry holds the address of the appropriate exception handler. When the IDT has 16-bit entries, and all ex- ception handlers must reside in the first 128K of the address space. The location of the IDT is held in the INTBASE register, which is not affected by the state of the ED bit. – Interrupt dispatch table has 16-bit entries. 1 – Interrupt dispatch table has 32-bit entries. SR The Short Register bit enables a compatibility mode for the CR16B large model. In the CR16C core, registers R12, R13, and RA are extended to 32 bits. In the CR16B large mod- el, only the lower 16 bits of these registers are used, and these “short registers” are paired together for 32-bit operations. In this mode, the (RA, R13) register pair is used as the ex- tended RA register, and address displace- ments relative to a single register are supported with offsets of 0 and 14 bits in place of the index addressing with these displace- ments. – 32-bit registers are used. 1 – 16-bit registers are used (CR16B mode). 15 10 9 8 7 6 5 2 1 0 Reserved SR ED 0 0 Reserved 0 0

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5.5 ADDRESSING MODES

The CR16C CPU core implements a load/store architec- ture, in which arithmetic and logical instructions operate on register operands. Memory operands are made accessible in registers using load and store instructions. For efficient implementation of I/O-intensive embedded applications, the architecture also provides a set of bit operations that oper- ate on memory operands. The load and store instructions support these addressing modes: register/pair, immediate, relative, absolute, and in- dex addressing. When register pairs are used, the lower bits are in the lower index register and the upper bits are in the higher index register. When the CFG.SR bit is clear, the 32- bit registers R12, R13, RA, and SP are also treated as reg- ister pairs. References to register pairs in assembly language use pa- rentheses. With a register pair, the lower numbered register pair must be on the right. For example, jump (r5, r4) load $4(r4,r3), (r6,r5) load $5(r12), (r13) The instruction set supports the following addressing modes: For additional information on the addressing modes, see the CompactRISC CR16C Programmer's Reference Manual. Register/Pair Mode In register/pair mode, the operand is held in a general-purpose register, or in a gen- eral-purpose register pair. For example, the following instruction adds the con- tents of the low byte of register r1 to the contents of the low byte of r2, and places the result in the low byte register r2. The high byte of register r2 is not modified. ADDB R1, R2 Immediate Mode In immediate mode, the operand is a con- stant value which is encoded in the in- struction. For example, the following instruction multiplies the value of r4 by 4 and places the result in r4. MULW $4, R4 Relative Mode In relative mode, the operand is ad- dressed using a relative value (displace- ment) encoded in the instruction. This displacement is relative to the current Program Counter (PC), a general-pur- pose register, or a register pair. In branch instructions, the displacement is always relative to the current value of the PC Register. For example, the follow- ing instruction causes an unconditional branch to an address 10 ahead of the current PC. BR *+10 In another example, the operand resides in memory. Its address is obtained by adding a displacement encoded in the in- struction to the contents of register r5. The address calculation does not modify the contents of register r5. LOADW 12(R5), R6 The following example calculates the ad- dress of a source operand by adding a displacement of 4 to the contents of a register pair (r5, r4) and loads this oper- and into the register pair (r7, r6). r7 re- ceives the high word of the operand, and r6 receives the low word. LOADD 4(r5, r4), (r7, r6) Index Mode In index mode, the operand address is calculated with a base address held in ei- ther R12 or R13. The CFG.SR bit must be clear to use this mode. „ For relative mode operands, the mem- ory address is calculated by adding the value of a register pair and a dis- placement to the base address. The displacement can be a 14 or 20-bit un- signed value, which is encoded in the instruction. „ For absolute mode operands, the memory address is calculated by add- ing a 20-bit absolute address encoded in the instruction to the base address. In the following example, the operand ad- dress is the sum of the displacement 4, the contents of the re gister pair (r5,r4), and the base address held in register r12. The word at this address is loaded into register r6. LOADW [r12]4(r5, r4), r6 Absolute Mode In absolute mode, the operand is located in memory, and its address is encoded in the instruction (normally 20 or 24 bits). For example, the following instruction loads the byte at address 4000 into the lower 8 bits of register r6. LOADB 4000, r6

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5.6 STACKS

A stack is a last-in, first-out data structure for dynamic stor- age of data and addresses. A stack consists of a block of memory used to hold the data and a pointer to the top of the stack. As more data is pushed onto a stack, the stack grows downward in memory. The CR16C supports two types of stacks: the interrupt stack and program stacks.

5.6.1 Interrupt Stack

The processor uses the interrupt stack to save and restore the program state during the exception handling. Hardware automatically pushes this data onto the interrupt stack be- fore entering an exception handler. When the exception handler returns, hardware restores the processor state with data popped from the interrupt stack. The interrupt stack pointer is held in the ISP register.

5.6.2 Program Stack

The program stack is normally used by software to save and restore register values on subroutine entry and exit, hold lo- cal and temporary variables, and hold parameters passed between the calling routine and the subroutine. The only hardware mechanisms which operate on the program stack are the PUSH, POP , and POPRET instructions.

5.6.3 User and Supervisor Stack Pointers

To support multitasking operating systems, support is pro- vided for two program stack pointers: a user stack pointer and a supervisor stack pointer. When the PSR.U bit is clear, the SP register is used for all program stack operations. This is the default mode when the user/supervisor protection mechanism is not used, and it is the supervisor mode when protection is used. When the PSR.U bit is set, the processor is in user mode, and the USP register is used as the program stack pointer. User mode can only be entered using the JUSR instruction, which performs a jump and sets the PSR.U bit. User mode is exited when an exception is taken and re-entered when the exception handler returns. In user mode, the LPRD in- struction cannot be used to change the state of processor registers (such as the PSR).

5.7 INSTRUCTION SET

Table 6 lists the operand specif iers for the instruction set, and Table 7 is a summary of all instructions. For each in- struction, the table shows the mnemonic and a brief de- scription of the operation performed. In the mnemonic column, the lower-case letter “i” is used to indicate the type of integer that the instruction operates on, either “B” for byte or “W” for word. For example, the notation ADDi for the “add” instruction means that there are two forms of this instruction, ADDB and ADDW, which operate on bytes and words, respectively. Similarly, the lower-case string “cond” is used to indicate the type of condition tested by the instruction. For example, the notation Jcond represents a class of conditional jump in- structions: JEQ for Jump on Equal, JNE for Jump on Not Equal, etc. For detailed information on all instructions, see the CompactRISC CR16C Programmer's Reference Manu- al. Table 6 Key to Operand Specifiers Operand Specifier Description abs Absolute address disp Displacement (numeric suffix indicates number of bits) imm Immediate operand (numeric suf- fix indicates number of bits) Iposition Bit position in memory Rbase Base register (relative mode) Rdest Destination register Rindex Index register RPbase, RPbasex Base register pair (relative mode) RPdest Destination register pair RPlink Link register pair Rposition Bit position in register Rproc 16-bit processor register Rprocd 32-bit processor register RPsrc Source register pair RPtarget Target register pair Rsrc, Rsrc1, Rsrc2 Source register

21 www.national.com CP3CN17 Table 7 Instruction Set Summary Mnemonic Operands Description MOVi Rsrc/imm, Rdest Move MOVXB Rsrc, Rdest Move with sign extension MOVZB Rsrc, Rdest Move with zero extension MOVXW Rsrc, RPdest Move with sign extension MOVZW Rsrc, RPdest Move with zero extension MOVD imm, RPdest Move immediate to register-pair RPsrc, RPdest Move between register-pairs ADD[U]i Rsrc/imm, Rdest Add ADDCi Rsrc/imm, Rdest Add with carry ADDD RPsrc/imm, RPdest Add with RP or immediate. MACQWa Rsrc1, Rsrc2, RP dest Multiply signed Q15: RPdest := RPdest + (Rsrc1 × Rsrc2) MACSWa Rsrc1, Rsrc2, RPdest Multiply signed and add result: RPdest := RPdest + (Rsrc1 × Rsrc2) MACUWa Rsrc1, Rsrc2, RPdest Multiply unsigned and add result: RPdest := RPdest + (Rsrc1 × Rsrc2) MULi Rsrc/imm, Rdest Multiply: Rdes t(8) := Rdest(8) × Rsrc(8)/imm Rdest(16) := Rdest(16) × Rsrc(16)/imm MULSB Rsrc, Rdest Multiply: Rdest(16) := Rdest(8) × Rsrc(8) MULSW Rsrc, RPdest Multiply: RPdest := RPdest(16) × Rsrc(16) MULUW Rsrc, RPdest Multiply: RPdest := RPdest(16) × Rsrc(16); SUBi Rsrc/imm, Rdest Subtract: (Rdest := Rdest - Rsrc/imm) SUBD RPsrc/imm, RPdest Subtract: (RPdest := RPdest - RPsrc/imm) SUBCi Rsrc/imm, Rdest Subtract with ca rry: (Rdest := Rdest - Rsrc/imm) CMPi Rsrc/imm, Rdest Compare Rdest - Rsrc/imm CMPD RPsrc/imm, RPdest Com pare RPdest - RPsrc/imm BEQ0i Rsrc, disp Compare Rsrc to 0 and branch if EQUAL BNE0i Rsrc, disp Compare Rsrc to 0 and branch if NOT EQUAL ANDi Rsrc/imm, Rdest Logical AND: Rdest := Rdest & Rsrc/imm ANDD RPsrc/imm, RPdest Logical AND: RPdest := RPsrc & RPsrc/imm ORi Rsrc/imm, Rdest Logical OR: Rdest := Rdest | Rsrc/imm ORD RPsrc/imm, RPdest Logical OR: Rdest := RPdest | RPsrc/imm Scond Rdest Save condition code as boolean XORi Rsrc/imm, Rdest Logical exclusive OR: Rdest := Rdest ^ Rsrc/imm XORD RPsrc/imm, RPdest Logical exclus ive OR: Rdest := RPdest ^ RPsrc/imm ASHUi Rsrc/imm, Rdest Arithmetic left/right shift

www.national.com 22 CP3CN17ASHUD Rsrc/imm, RPdest Arithmetic left/right shift LSHi Rsrc/imm, Rdest Logical left/right shift LSHD Rsrc/imm, RPdest Logical left/right shift SBITi Iposition, disp(Rbase) Set a bit in memory (Because this instruction treats the destination as a read- modify-write operand, it not be used to set bits in write- only registers.) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs CBITi Iposition, disp(Rbase) Clear a bit in memory Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs TBIT TBITi Rposition/imm, Rsrc Test a bit in a register Test a bit in memoryIposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs LPR Rsrc, Rproc Load processor register LPRD RPsrc, Rprocd Load double processor register SPR Rproc, Rdest Store processor register SPRD Rprocd, RPdest Store 32-bit processor register Bcond disp9 Conditional branch disp17 disp24 BAL RPlink, disp24 Branch and link BR disp9 Branch disp17 disp24 EXCP vector Trap (vector) Jcond RPtarget Conditional Jump to a large address JAL RA, RPtarget, Jump and link to a large address RPlink, RPtarget JUMP RPtarget Jump JUSR RPtarget Jump and set PSR.U Table 7 Instruction Set Summary Mnemonic Operands Description

23 www.national.com CP3CN17 RETX Return from exception PUSH imm, Rsrc, RA Push “imm” number of registers on user stack, starting with Rsrc and possibly including RA POP imm, Rdest, RA Restore “imm” number of registers from user stack, starting with Rdest and possibly including RA POPRET imm, Rdest, RA Restore registers (similar to POP) and JUMP RA LOADi disp(Rbase), Rdest Load (register relative) abs, Rdest Load (absolute) (Rindex)abs, Rdest Load (absolute index relative) (Rindex)disp(RPbasex), Rdest Load (register relative index) disp(RPbase), Rdest Load (register pair relative) LOADD disp(Rbase), Rdest Load (register relative) abs, Rdest Load (absolute) (Rindex)abs, Rdest Load (absolute index relative) (Rindex)disp(RPbasex), Rdest Load (register pair relative index) disp(RPbase), Rdest Load (register pair relative) STORi Rsrc, disp(Rbase) Sto re (register relative) Rsrc, disp(RPbase) Store (register pair relative) Rsrc, abs Store (absolute) Rsrc, (Rindex)disp(RPbasex) Store (register pair relative index) Rsrc, (Rindex)abs Store (absolute index) STORD RPsrc, disp(Rbase) Sto re (register relative) RPsrc, disp(RPbase) Store (register pair relative) RPsrc, abs Store (absolute) RPsrc, (Rindex)disp(RPbasex) Store (register pair index relative) RPsrc, (Rindex)abs Store (absolute index relative) STOR IMM imm4, disp(Rbase) Store unsigned 4- bit immediate value extended to operand length in memoryimm4, disp(RPbase) imm4, (Rindex)disp(RPbasex) imm4, abs imm4, (Rindex)abs LOADM imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R0) LOADMP imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R1, R0) STORM STORM imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R2) Table 7 Instruction Set Summary Mnemonic Operands Description

www.national.com 24 CP3CN17STORMP imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R7,R6) DI Disable maskable interrupts EI Enable maskable interrupts EIWAIT Enable maskable interrupts and wait for interrupt NOP No operation WAIT Wait for interrupt Table 7 Instruction Set Summary Mnemonic Operands Description

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6.0 Memory

The CP3CN17 supports a uniform 16M-byte linear address space. Table 8 lists the types of memory and peripherals that occupy this memory space. Unlisted address ranges are reserved and must not be read or written. The BIU zones are regions of the address space that share the same control bits in the Bus Interface Unit (BIU). Table 8 CP3CN17 Memory Map

6.1 OPERATING ENVIRONMENT

The operating environment controls whether external mem- ory is supported and whether the reset vector jumps to a code space intended to support In-System Programming (ISP). Up to 12M of external memory space is available. The operating mode of the device is controlled by the states on the ENV[2:0] pins at reset and the states of the EMPTY bits in the Protection Word, as shown in Table 9. Internal pullups on the ENV[2:0] pins select IRE mode or ISP mode if these pins are allowed to float. When ENV[2:0] = 111b, IRE mode is selected unless the EMPTY bits in the Protection word indicate that the program flash memory is empty (unprogrammed), in which case ISP mode is selected. When ENV[2:0] = 011b, ERE mode is se- lected unless the EMPTY bits indicate that the program flash memory is empty, in which case ISP mode is selected. When ENV[2:0] = 110b, ISP mode is selected without re- gard to the states of the EMPTY bits. See Section 8.4.2 for more details. In the DEV environment, the on-chip flash memory is dis- abled, and the corresponding region of the address space is mapped to external memory. Start Address End Address Size in Bytes Description BIU Zone 00 0000h 03 FFFFh 256K On-chip Flash Program Memory, including Boot Memory Static Zone 0 (mapped internally in IRE and ERE mode; mapped to the external bus in DEV mode) 04 0000h 0D FFFFh 640K Reserved 0E 0000h 0E 1FFFh 8K On-chip Flash Data Memory 0E 2000h 0E 7FFFh 24K Reserved 0E 8000h 0E 91FFh 4.5K Reserved N/A 0E 9200h 0E BFFFh 11.5K Reserved 0E C000h 0E E7FFh 10K System RAM 0E E800h 0E EBFFh 1K Reserved 0E EC00h 0E EFFFh 1K Reserved 0E F000h 0E F13Fh 320 CAN Buffers and Registers 0E F140h 0E F17Fh 64 Reserved 0E F180h 0E F1FFh 128 Reserved 0E F200h 0F FFFFh 67.5K Reserved 10 0000h 3F FFFFh 3072K Reserved 40 0000h 7F FFFFh 4096K External Memory Zone 1 Static Zone 1 80 0000h FE FFFFh 8128K External Memory Zone 2 Static Zone 2 FF 0000h FF FAFFh 64256 BIU Peripherals FF FB00h FF FBFFh 256 I/O Expansion I/O Zone FF FC00h FF FFFFh 1K Peripherals and Other I/O Ports N/A Table 9 Operating Environment Selection ENV[2:0] EMPTY Operating Environment

111 No Internal ROM enabled (IRE) mode

011 No External ROM enabled (ERE) mode

000 N/A Development (DEV) mode

110 N/A In-System-Programming (ISP) mode

111 Y es In-System-Programming (ISP) mode

011 Y es In-System-Programming (ISP) mode

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6.2 BUS INTERFACE UNIT (BIU)

The BIU controls the interface between the CPU core bus and those on-chip modules which are mapped into BIU zones. These on-chip modules are the flash program mem- ory and the I/O zone. The BIU controls the configured pa- rameters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for the requested access.

6.3 BUS CYCLES

There are four types of data transfer bus cycles: „ Normal read „ Fast read „ Early write „ Late write The type of data cycle used in a particular transaction de- pends on the type of CPU operation (a write or a read), the type of memory or I/O being accessed, and the access type programmed into the BIU contro l registers (early/late write or normal/fast read). For read operations, a basic normal read takes two clock cy- cles, and a fast-read bus cycle takes one clock cycle. Nor- mal read bus cycles are enabled by default after reset. For write operations, a basic late-write bus cycle takes two clock cycles, and a basic early-write bus cycle takes three clock cycles. Early-write bus cycles are enabled by default after reset. However, late-w rite bus cycles are needed for ordinary write operations, so this configuration must be changed by software (see Section 6.4.1). In certain cases, one or mo re additional clock cycles are added to a bus access cycle. There are two types of addi- tional clock cycles for ordinary memory accesses, called in- ternal wait cycles (TIW) and hold (Thold) cycles. A wait cycle is inserted in a bus cycle just after the memory address has been placed on the address bus. This gives the accessed memory more time to respond to the transaction request. A hold cycle is inserted at the end of a bus cycle. This holds the data on the data bus for an extended number of clock cy- cles.

6.4 BIU CONTROL REGISTERS

The BIU has a set of control registers that determine how many wait cycles and hold cycles are to be used for access- ing memory. During initialization of the system, these regis- ters should be programmed with appropriate values so that the minimum allowable number of cycles is used. This num- ber varies with the clock frequency. There are five BIU control registers, as listed in Table 10. These registers control the bus cycle configuration used for accessing the various on-chip memory types.

6.4.1 BIU Configuration Register (BCFG)

The BCFG register is a byte-w ide, read/write register that selects early-write or late-write bus cycles. At reset, the reg- ister is initialized to 07h. The register format is shown below. EWR The Early Write bit controls write cycle timing. 0 – Late-write operation (2 clock cycles to write). 1 – Early-write operation. At reset, the BCFG register is initialized to 07h, which se- lects early-write operation. However, late-write operation is required for normal device operation, so software must change the register value to 06h. Bits 1 and 2 of this register must always be set when writing to this register. Table 10 Bus Control Registers Name Address Description BCFG FF F900h BIU Configuration Register IOCFG FF F902h I/O Zone Configuration Register SZCFG0 FF F904h Static Zone 0 Configuration Register SZCFG1 FF F906h Static Zone 1 Configuration Register SZCFG2 FF F908h Static Zone 2 Configuration Register7 3 2 1 0 Reserved 1 1 EWR

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6.4.2 I/O Zone Configur ation Register (IOCFG)

The IOCFG register is a word-wide, read/write register that controls the timing and bus characteristics of accesses to the 256-byte I/O Zone memory space (FF FB00h to FF FBFFh). The registers associated with Port B and Port C re- side in the I/O memory array. At reset, the register is initial- ized to 069Fh. The register format is shown below. WAIT The Memory Wait Cycles field specifies the number of TIW (internal wait state) clock cy- cles added for each memory access, ranging from 000 binary for no additional TIW wait cy- cles to 111 binary for seven additional TIW wait cycles. HOLD The Memory Hold Cycles field specifies the number of T hold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three T hold clock cy- cles. BW The Bus Width bit defines the bus width of the IO Zone. – 8-bit bus width. 1 – 16-bit bus width (default) IPST The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. No idle cycles are required for on-chip accesses. – No idle cycle (recommended). 1 – Idle cycle.

6.4.3 Static Zone 0 Configuration Register (SZCFG0)

The SZCFG0 register is a wo rd-wide, read/write register that controls the timing and bus characteristics of Zone 0 memory accesses. Zone 0 is used for the on-chip flash memory (including the boot area, program memory, and data memory). At reset, the register is initialized to 069Fh. The register for- mat is shown below. WAIT The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG0.FRE bit is set. HOLD The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG0.FRE bit is set. RBE The Read Burst Enab le enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. Because the flash pro- gram memory is required to be 16-bit bus width, the RBE bit is a don’t care bit. This bit is ignored when the SZCFG0.FRE bit is set. – Burst read disabled. 1 – Burst read enabled. WBR The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG0.FRE bit is set or when SZCFG0.RBE is clear. – No TBW on burst read cycles. 1 – One TBW on burst read cycles. BW The Bus Width bit controls the bus width of the zone. The flash program memory must be configured for 16-bit bus width. – 8-bit bus width. 1 – 16-bit bus width (required). FRE The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read op- eration takes one clock cycle. A normal read operation takes at least two clock cycles. – Normal read cycles. 1 – Fast read cycles. IPST The Post Idle bit cont rols whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. No idle cycles are required for on-chip accesses. – No idle cycle (recommended). 1 – Idle cycle inserted. 7 6 5 4 3 2 0 BW Reserved HOLD WAIT 15 10 9 8 Reserved IPST Res. 7 6 5 4 3 2 0 BW WBR RBE HOLD WAIT 15 12 11 10 9 8 Reserved FRE IPRE IPST Res.

www.national.com 28 CP3CN17 IPRE The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a dif- ferent zone. No idle cycles are required for on- chip accesses. – No idle cycle (recommended). 1 – Idle cycle inserted.

6.4.4 Static Zone 1 Configuration Register (SZCFG1)

The SZCFG1 register is a wo rd-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL1 output signal. At reset, the register is initialized to 069Fh. The register for- mat is shown below. WAIT The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG1.FRE bit is set. HOLD The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG1.FRE bit is set. RBE The Read Burst Enab le enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. This bit is ignored when the SZCFG1.FRE bit is set or the SZCFG1.BW is clear. – Burst read disabled. 1 – Burst read enabled. WBR The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG1.FRE bit is set or when SZCFG1.RBE is clear. – No TBW on burst read cycles. 1 – One TBW on burst read cycles. BW The Bus Width bit controls the bus width of the zone. – 8-bit bus width. 1 – 16-bit bus width. FRE The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read op- eration takes one clock cycle. A normal read operation takes at least two clock cycles. – Normal read cycles. 1 – Fast read cycles. IPST The Post Idle bit cont rols whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. 0 – No idle cycle. 1 – Idle cycle inserted. IPRE The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a dif- ferent zone. – No idle cycle. 1 – Idle cycle inserted. 7 6 5 4 3 2 0 BW WBR RBE HOLD WAIT 15 12 11 10 9 8 Reserved FRE IPRE IPST Res.

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6.4.5 Static Zone 2 Config uration Register (SZCFG2)

The SZCFG2 register is a wo rd-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL2 output signal. At reset, the register is initialized to 069Fh. The register for- mat is shown below. WAIT The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG2.FRE bit is set. HOLD The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG2.FRE bit is set. RBE The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. This bit is ignored when the SZCFG2.FRE bit is set or the SZCFG2.BW is clear. – Burst read disabled. 1 – Burst read enabled. WBR The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG2.FRE bit is set or when SZCFG2.RBE is clear. – No TBW on burst read cycles. 1 – One TBW on burst read cycles. BW The Bus Width bit controls the bus width of the zone. – 8-bit bus width. 1 – 16-bit bus width. FRE The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read op- eration takes one clock cycle. A normal read operation takes at least two clock cycles. – Normal read cycles. 1 – Fast read cycles. IPST The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. 0 – No idle cycle. 1 – Idle cycle inserted. IPRE The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a dif- ferent zone. – No idle cycle. 1 – Idle cycle inserted.

6.5 WAIT AND HOLD STATES

The number of wait cycles a nd hold cycles inserted into a bus cycle depends on whether it is a read or write operation, the type of memory or I/O being accessed, and the control register settings.

6.5.1 Flash Prog ram/Data Memory

When the CPU accesses the Flash program and data mem- ory (address ranges 000000h –03FFFFh and 0E0000h – 0E1FFFh), the number of added wait and hold cycles de- pends on the type of access and the BIU register settings. In fast-read mode (SZCFG0.FRE=1), a read operation is a single cycle access. This limi ts the maximum CPU operat- ing frequency to 24 MHz. For a read operation in normal-read mode (SZCFG0.FRE=0), the number of inserted wait cycles is specified in the SZCFG0.WAIT field. The total number of wait cycles is the value in the WAIT field plus 1, so it can range from 1 to 8. The number of inserted hold cycles is specified in the SCCFG0.HOLD field, which can range from 0 to 3. For a write operation in fast read mode (SZCFG0.FRE=1), the number of inserted wait cycles is 1. No hold cycles are used. For a write operation normal read mode (SZCFG0.FRE=0), the number of wait cycles is equal to the value written to the SZCFG0.WAIT field plus 1 (in the late write mode) or 2 (in the early write mode). The number of inserted hold cycles is equal to the value written to the SCCFG0.HOLD field, which can range from 0 to 3.

6.5.2 RAM Memory

Read and write accesses to on-chip RAM is performed with- in a single cycle, without regard to the BIU settings. The RAM address is in the range of 0E 8000h –0E 91FFh and 0E C000h–0E EBFFh.

6.5.3 Access to Peripherals

When the CPU accesses on-chip peripherals in the range of 0E F000h–0E F1FFh and FF 0000h –FF FBFFh, one wait cycle and one preliminary idle cycle is used. No hold cycles are used. The IOCFG register determines the access timing for the address range FF FB00h–FF FBFFh. 7 6 5 4 3 2 0 BW WBR RBE HOLD WAIT 15 12 11 10 9 8 Reserved FRE IPRE IPST Res.

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7.0 System Configuration Registers

The system configuration registers control and provide sta- tus for certain aspects of device setup and operation, such as indicating the states sampled from the ENV[2:0] inputs. The system configuration registers are listed in Table 11.

7.1 MODULE CONFIGURATION REGISTER

(MCFG) The MCFG register is a byte- wide, read/write register that selects the clock output features of the device. The register must be written in active mode only, not in pow- er save, HALT, or IDLE mode. However, the register con- tents are preserved during all power modes. The MCFG register format is shown below. EXIOE The EXIOE bit controls whether the external bus is enabled in the IRE environment for im- plementing the I/O Zone (FF FB00h –FF FBFFh). 0 – External bus disabled. 1 – External bus enabled. PLLCLKOE The PLLCLKOE bit controls whether the PLL clock is driven on the ENV0/PLLCLK pin. – ENV0/PLLCLK pin is high impedance. 1 – PLL clock driven on the ENV0/PLLCLK pin. MCLKOE The MCLKOE bit controls whether the Main Clock is driven on the ENV1/CPUCLK pin. 0 – ENV1/CPUCLK pin is high impedance. 1 – Main Clock is driven on the ENV1/CPU- CLK pin. SCLKOE The SCLKOE bit controls whether the Slow Clock is driven on the ENV2/SLOWCLK pin. 0 – ENV2/SLOWCLK pin is high impedance. 1 – Slow Clock is driven on the ENV2/SLOW- CLK pin. MISC_IO_SPEED The MISC_IO_SPEED bit controls the slew rate of the output dr ivers for the ENV[2:0], RDY, RFDATA, and TDO pins. To minimize noise, the slow slew rate is recommended. 0 – Fast slew rate. 1 – Slow slew rate. MEM_IO_SPEED The MEM_IO_SPEED bit controls the slew rate of the output drivers for the A[22:0], RD , SEL[2:1], and WR[1:0] pins. Memory speeds for the CP3CN17 are characterized with fast slew rate. Slow slew rate reduces the avail- able memory access time by 5 ns. – Fast slew rate. 1 – Slow slew rate.

7.2 MODULE STATUS REGISTER (MSTAT)

The MSTAT register is a byte-wide, read-only register that indicates the general status of the device. The MSTAT reg- ister format is shown below. OENV[2:0] The Operating Envi ronment bits hold the states sampled from the ENV[2:0] input pins at reset. These states are controlled by exter- nal hardware at reset and are held constant in the register until the next reset. PGMBUSY The Flash Programming Busy bit is automati- cally set when either the program memory or the data memory is being programmed or erased. It is clear when neither of the memo- ries is busy. When this bit is set, software must not attempt to program or erase either of these two memories. This bit is a copy of the FMBUSY bit in the FMSTAT register. – Flash memory is not busy. 1 – Flash memory is busy. DPGMBUSY The Data Flash Programming Busy indicates that the flash data memory is being erased or a pipelined programming sequence is current- ly ongoing. Software must not attempt to per- form any write access to the flash program memory at this time, without also polling the FSMSTAT.FMFULL bit in the flash memory in- terface. The DPGMBUSY bit is a copy of the FMBUSY bit in the FSMSTAT register. – Flash data memory is not busy. 1 – Flash data memory is busy. Table 11 System Configuration Registers Name Address Description MCFG FF F910h Module Configuration Register MSTAT FF F914h Module Status Register 7 6 5 4 3 2 1 0 Res. MEM_IO _SPEED MISC_IO _SPEED Reserved SCLK OE MCLK OE PLLCLK OE EXI OE 7 5 4 3 2 1 0 Reserved DPGMBUSY PGMBUSY OENV2 OENV1 OENV0

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8.0 Flash Memory

The flash memory consists of the flash program memory and the flash data memory. The flash program memory is further divided into the Boot Area and the Code Area. A special protection scheme is applied to the lower portion of the flash program memory, called the Boot Area. The Boot Area always starts at address 0 and ranges up to a programmable end address. The maximum boot area ad- dress which can be selected is 00 1BFFh. The intended use of this area is to hold In-System-Programming (ISP) rou- tines or essential application routines. The Boot Area is al- ways protected against CPU write access, to avoid unintended modifications. The Code Area is intended to hold the application code and constant data. The Code Area begins with the next byte af- ter the Boot Area. Table 12 summarizes the properties of the regions of flash memory mapped into the CPU address space. Table 12 Flash Memory Areas

8.1 FLASH MEMORY PROTECTION

The memory protection mechanisms provide both global and section-level protection. Section-level protection against CPU writes is applied to individual 8K-byte sections of the flash program memory and 512-byte sections of the flash data memory. Section-level protection is controlled through read/write registers mapped into the CPU address space. Global write protection is applied at the device level, to disable flash memory writes by the CPU. Global write pro- tection is controlled by the encoding of bits stored in the flash memory array.

8.1.1 Section-Level Protection

Each bit in the Flash Memory Write Enable (FM0WER and FM1WER) registers enables or disables write access to a corresponding section of flash program memory. Write ac- cess to the flash data memory is controlled by the bits in the Flash Slave Memory Write Enable (FSM0WER) register. By default (after reset) all bits in the FM0WER, FM1WER, and FSM0WER registers are cleared, which disables write ac- cess by the CPU to all sections. Write access to a section is enabled by setting the corresponding write enable bit. After completing a programming or erase operation, software should clear all write enable bits to protect the flash program memory against any unintended writes.

8.1.2 Global Protection

The WRPROT field in the Protection Word controls global write protection. The Protection Word is located in a special flash memory outside of the CPU address space. If a major- ity of the bits in the 3-bit WRPROT field are clear, write pro- tection is enabled. Enabling this mode prevents the CPU from writing to flash memory. The RDPROT field in the Protection Word controls global read protection. If a majority of the bits in the 3-bit RDPROT field are clear, read protection is enabled. Enabling this mode prevents reading by an external debugger through the serial debug interface or by an external flash programmer. CPU read access is not affected by the RDPROT bits.

8.2 FLASH MEMORY ORGANIZATION

Each of the flash memories are divided into main blocks and information blocks. The main blocks hold the code or data used by application software. The information blocks hold factory parameters, protection settings, and other device- specific data. The main blocks are mapped into the CPU ad- dress space. The information blocks are accessed indirectly through a register-based interf ace. Separate sets of regis- ters are provided for accessing flash program memory (FM registers) and flash data memory (FSM registers). The flash program memory consists of two main blocks and two data blocks, as shown in Table 13. The flash data memory con- sists of one main block and one information block. Table 13 Flash Memory Blocks

8.2.1 Main Block 0 and 1

Main Block 0 and Main Block 1 hold the 256K-byte program space, which consists of th e Boot Area and Code Area. Area Address Range Read Access Write Access Boot Area 0 –BOOTAREA - 1 Y es No Code Area BOOTAREA–03 FFFFh Ye s Write access only if section write enable bit is set and global write protection is disabled. Data Area 0E 0000h–0E 1FFFh Y es Write access only if section write enable bit is set and global write protection is disabled. Name Address Range Function Main Block 0 00 0000h–01 FFFFh (CPU address space) Flash Program Memory Information Block 0 000h–07Fh (address register) Function Word, Factory Parameters Main Block 1 02 0000h–03 FFFFh (CPU address space) Flash Program Memory Information Block 1 080h–0FFh (address register) Protection Word, User Data Main Block 2 0E 0000h–0E 1FFFh (CPU address space) Flash Data Memory Information Block 2 000h–07Fh (address register) User Data

www.national.com 32 CP3CN17 Each block consists of sixteen 8K-byte sections. Write ac- cess by the CPU to Main Block 0 and Main Block 1 is con- trolled by the corresponding bits in the FM0WER and FM1WER registers, respectively. The least significant bit in each register controls the section at the lowest address.

8.2.2 Information Block 0

Information Block 0 contains 128 bytes, of which one 16-bit word has a dedicated function, called the Function Word. The Function Word resides at address 07Eh. It holds factory parameters. Software only has read access to Information Block 0 through a register-based interface. The Function Word and the factory parameters are pr otected against CPU writes. Table 14 shows the structure of Information Block 0. Table 14 Information Block 0

8.2.3 Information Block 1

Information Block 1 contains 128 bytes, of which one 16-bit word has a dedicated function, called the Protection Word. The Protection Word resides at address 0FEh. It controls the global protection mechanisms and the size of the Boot Area. The Protection Word can be written by the CPU, how- ever the changes only become valid after the next device re- set. The remaining Information Block 1 locations can be used to store other user data . Erasing Information Block 1 also erases Main Block 1. Table 15 shows the structure of the Information Block 1. Table 15 Information Block 1

8.2.4 Main Block 2

Main Block 2 holds the 8K-byte data area, which consists of sixteen 512-byte sections. Write access by the CPU to Main Block 2 is controlled by the corresponding bits in the FSM0WER register. The least significant bit in the register controls the section at the lowest address.

8.2.5 Information Block 2

Information Block 2 contains 128 bytes, which can be used to store user data. The CPU can always read Information Block 2. The CPU can write Information Block 2 only when global write protection is disabled. Erasing Information Block 2 also erases Main Block 2.

8.3 FLASH MEMORY OPERATIONS

Flash memory programming (erasing and writing) can be performed on the flash data memory while the CPU is exe- cuting out of flash program memory. Although the CPU can execute out of flash data memory , it cannot erase or write the flash program memory while executing from flash data memory. To erase or write the flash program memory, the CPU must be executing from the on-chip static RAM or off- chip memory. An erase operation is required before programming. An erase operation sets all of the bits in the erased region. A programming operation clears selected bits. The programming mechanism is pipelined, so that a new write request can be loaded while a previous request is in progress. When the FMFULL bit in the FMSTAT or FSM- STAT register is clear, the pipeline is ready to receive a new request. New requests may be loaded after checking only the FMFULL bit.

8.3.1 Main Block Read

Read accesses from flash program memory can only occur when the flash program memory is not busy from a previous write or erase operation. Read accesses from the flash data memory can only occur when both the flash program mem- ory and the flash data memory are not busy. Both byte and word read operations are supported.

8.3.2 Information Block Read

Information block data is read through the register-based in- terface. Only word read operations are supported and the read address must be word-aligned (LSB = 0). The following steps are used to read from an information block: 1. Load the word address in the Flash Memory Informa- tion Block Address (FMIBAR) or Flash Slave Memory Information Block Address (FSMIBAR) register. 2. Read the data word by reading out the Flash Memory Information Block Data (FMIBDR) or Flash Slave Mem- ory Information Block Data (FSMIBDR) register.

8.3.3 Main Block Page Erase

A flash erase operation sets all of the bits in the erased re- gion. Pages of a main block can be individually erased if their write enable bits are set. This method cannot be used to erase the boot area, if defined. Each page in Main Block 0 and 1 consists of 1024 bytes (512 words). Each page in Main Block 2 consists of 512 bytes (256 words). To erase a page, the following steps are performed: 1. Verify that the Flash Memory Busy (FMBUSY) bit is clear. The FMBUSY bit is in the FMSTAT or FSMSTAT register. 2. Prevent accesses to the flash memory while erasing is in progress. Name Address Range Read Access Write Access Function Word 07Eh –07Fh Ye s N oOther (Used for Factory Parameters) 000h–07Dh Name Address Range Read Access Write Access Protection Word 0FEh–0FFh Ye s Write access only if section write enable bit is set and global write protection is dis- abled. Other (User Data) 080h–0FDh

33 www.national.com CP3CN17 3. Set the Page Erase (PER) bit. The PER bit is in the FM- CTRL or FSMCTRL register. 4. Write to an address within the desired page. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EER R) bit to confirm successful erase of the page. The EERR bit is in the FMSTAT or FSMSTAT register. 7. Repeat steps 4 through 6 to erase additional pages. 8. Clear the PER bit.

8.3.4 Main Block Module Erase

A module erase operation can be used to erase an entire main block. All sections within the block must be enabled for writing. If a boot area is def ined in the block, it cannot be erased. The following steps are performed to erase a main block: 1. Verify that the Flash Memory Busy (FMBUSY) bit is clear. The FMBUSY bit is in the FMSTAT or FSMSTAT register. 2. Prevent accesses to the flash memory while erasing is in progress. 3. Set the Module Erase (MER) bit. The MER bit is in the FMCTRL or FSMCTRL register. 4. Write to any address within the desired main block. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EER R) bit to confirm successful erase of the block. The EERR bit is in the FMSTAT or FSMSTAT register. 7. Clear the MER bit.

8.3.5 Information Block Module Erase

Erasing an information block also erases the corresponding main block. If a boot area is defined in the main block, nei- ther block can be erased. Page erase is not supported for information blocks. The following steps are performed to erase an information block: 1. Verify that the Flash Memory Busy (FMBUSY) bit is clear. The FMBUSY bit is in the FMSTAT or FSMSTAT register. 2. Prevent accesses to the flash memory while erasing is in progress. 3. Set the Module Erase (MER) bit. The MER bit is in the FMCTRL or FSMCTRL register. 4. Load the FMIBAR or FSMIBAR register with any ad- dress within the block, then write any data to the FMIB- DR or FSMIBDR register. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EER R) bit to confirm successful erase of the block. The EERR bit is in the FMSTAT or FSMSTAT register. 7. Clear the MER bit.

8.3.6 Main Block Write

Writing is only allowed when global write protection is dis- abled. Writing by the CPU is only allowed when the write en- able bit is set for the sector which contains the word to be written. The CPU cannot write the Boot Area. Only word- wide write access to word-aligned addresses is supported. The following steps are performed to write a word: 1. Verify that the Flash Memory Busy (FMBUSY) bit is clear. The FMBUSY bit is in the FMSTAT or FSMSTAT register. 2. Prevent accesses to the flash memory while the write is in progress. 3. Set the Program Enable (PE) bit. The PE bit is in the FMCTRL or FSMCTRL register. 4. Write a word to the desired word-aligned address. This starts a new pipelined programming sequence. The FMBUSY bit becomes set while the write operation is in progress. The FMFULL bit in the FMSTAT or FSMSTAT register becomes set if a previous write operation is still in progress. 5. Wait until the FMFULL bit becomes clear. 6. Repeat steps 4 and 5 for additional words. 7. Wait until the FMBUSY bit becomes clear again. 8. Check the programming error (PERR) bit to confirm successful programming. The PERR bit is in the FM- STAT or FSMSTAT register. 9. Clear the Program Enable (PE) bit.

8.3.7 Information Block Write

Writing is only allowed when global write protection is dis- abled. Writing by the CPU is only allowed when the write en- able bit is set for the sector which contains the word to be written. The CPU cannot write Information Block 0. Only word-wide write access to word-aligned addresses is sup- ported. The following steps are performed to write a word: 1. Verify that the Flash Memory Busy (FMBUSY) bit is clear. The FMBUSY bit is in the FMSTAT or FSMSTAT register. 2. Prevent accesses to the flash memory while the write is in progress. 3. Set the Program Enable (PE) bit. The PE bit is in the FMCTRL or FSMCTRL register. 4. Write the desired target address into the FMIBAR or FSMIBAR register. 5. Write the data word into the FMIBDR or FSMIBDR reg- ister. This starts a new pipelined programming se- quence. The FMBUSY bit becomes set while the write operation is in progress. The FMFULL bit in the FM- STAT or FSMSTAT register becomes set if a previous write operation is still in progress. 6. Wait until the FMFULL bit becomes clear. 7. Repeat steps 4 through 6 for additional words. 8. Wait until the FMBUSY bit becomes clear again. 9. Check the programming error (PERR) bit to confirm successful programming. The PERR bit is in the FM- STAT or FSMSTAT register. 10. Clear the Program Enable (PE) bit.

8.4 INFORMATION BLOCK WORDS

Two words in the information blocks are dedicated to hold settings that affect the operation of the system: the Function Word in Information Block 0 and the Protection Word in In- formation Block 1.

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8.4.1 Function Word

The Function Word resides in the Information Block 0 at ad- dress 07Eh. At reset, the Function Word is copied into the FMAR0 register.

8.4.2 Protection Word

The Protection Word resides in Information Block 1 at ad- dress 0FEh. At reset, the Protection Word is copied into the FMAR1 register. BOOTAREA The BOOTAREA field specifies the size of the Boot Area. The Boot Area starts at address 0 and ends at the address specified by this field. The inverted bits of the BOOTAREA field count the number of 1024-byte blocks to be reserved as the Boot Area. The maximum Boot Area size is 7K bytes (address range 0 to 1BFFh). The end of the Boot Area defines the start of the Code Area. If the device starts in ISP mode and there is no Boot Area defined (encoding 111b), the device is kept in reset. Table 16 lists all possible boot area encod- ings. EMPTY The EMPTY field indicates whether the flash program memory has been programmed or should be treated as blank. If a majority of the three EMPTY bits are clear, the flash program memory is treated as programmed. If a major- ity of the EMPTY bits are set, the flash pro- gram memory is treated as empty. If the ENV[1:0] inputs (see Section 6.1) are sam- pled high at reset and the EMPTY bits indicate the flash program memory is empty, the de- vice will begin execution in ISP mode. The de- vice enters ISP mode without regard to the EMPTY status if ENV0 is driven low and ENV1 is driven high. ISPE The ISPE field indicates whether the Boot Area is used to hold In-System-Programming routines or user application routines. If a ma- jority of the three ISPE bits are set, the Boot Area holds ISP routines. If majority of the ISPE bits are clear, the Boot Area holds user application routines. Table 17 summarizes all possible EMPTY , ISPE, and Boot Area set- tings and the corresponding start-up opera- tion for each combination. In DEV mode, the EMPTY bit settings are ignored and the CPU always starts executing from address 0. RDPROT The RDPROT field controls the global read protection mechanism for the on-chip flash program memory. If a ma jority of the three RDPROT bits are clear, the flash program memory is protected against read access from the serial debug interface or an external flash programmer. CPU read access is not af- fected by the RDPROT bits. If a majority of the RDPROT bits are set, read access is allowed. WRPROT The WRPROT field controls the global write protection mechanism for the on-chip flash program memory. If a ma jority of the three WRPROT bits are clear, the flash program memory is protected against write access from any source and read access from the se- rial debug interface. If a majority of the WR- PROT bits are set, write access is allowed. 15 0 Reserved 15 13 12 10 9 7 6 4 3 1 0 WRPROT RDPROT ISPE EMPTY BOOTAREA 1 Table 16 Boot Area Encodings BOOT AREA Size of the Boot Area Code Area Start Address

111 No Boot Area defined 00 0000h

Table 17 CPU Reset Behavior EMPTY ISPE Boot Area Start-Up Operation Not Empty ISP Defined Device starts in IRE/ ERE mode from Code Area start address Not Empty ISP Not Defined Device starts in IRE/ ERE mode from Code Area start address Not Empty No ISP Don’t Care Device starts in IRE/ ERE mode from address 0 Empty ISP Defined Device starts in ISP mode from Code Area start address Empty ISP Not Defined Device starts in ISP mode and is kept in its reset stateEmpty No ISP Don’t Care

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8.5 FLASH MEMORY INTERFACE

There is a separate interface for the program flash and data flash memories. The same set of registers exist in both in- terfaces. In most cases they are independent of each other, but in some cases the program flash interface controls the interface for both memories, as indicated in the following sections. Table 18 lists the registers.

8.5.1 Flash Memory Information Block Address

Register (FMIBAR/FSMIBAR) The FMIBAR register specifies the 8-bit address for read or write access to an information block. Because only word ac- cess to the information blocks is supported, the least signif- icant bit (LSB) of the FMIBAR must be 0 (word-aligned). The hardware automatically clears the LSB, without regard to the value written to the bit. The FMIBAR register is cleared after device reset. The CPU bus master has read/write ac- cess to this register. IBA The Information Block Address field holds the word-aligned address of an information block location accessed during a read or write transaction. The LSB of the IBA field is always clear.

8.5.2 Flash Memory Informati on Block Data Register

(FMIBDR/FSMIBDR) The FMIBDR register holds the 16-bit data for read or write access to an information block. The FMIBDR register is cleared after device reset. The CPU bus master has read/ write access to this register. IBD The Information Block Data field holds the data word for access to an information block. For write operations the IBD field holds the data word to be programmed into the informa- tion block location specified by the IBA ad- dress. During a read operation from an information block, the IBD field receives the data word read from the location specified by the IBA address. Table 18 Flash Memory Interface Registers Program Memory Data Memory Description FMIBAR FF F940h FSMIBAR FF F740h Flash Memory Information Block Address Register FMIBDR FF F942h FSMIBDR FF F742h Flash Memory Information Block Address Register FM0WER FF F944h FSM0WER FF F744h Flash Memory 0 Write Enable Register FM1WER FF F946h N/A Flash Memory 1 Write Enable Register FMCTRL FF F94Ch FSMCTRL FF F74Ch Flash Memory Control Register FMSTAT FF F94Eh FSMSTAT FF F74Eh Flash Memory Status Register FMPSR FF F950h FSMPSR FF F750h Flash Memory Prescaler Register FMSTART FF F952h FSMSTART FF F752h Flash Memory Start Time Reload Register FMTRAN FF F954h FSMTRAN FF F754h Flash Memory Transition Time Reload Register FMPROG FF F956h FSMPROG FF F756h Flash Memory Programming Time Reload Register FMPERASE FF F958h FSMPERASE FF F758h Flash Memory Page Erase Time Reload Register FMMERASE0 FF F95Ah FSMMERASE0 FF F75Ah Flash Memory Module Erase Time Reload Register 0 FMEND FF F95Eh FSMEND FF F75Eh Flash Memory End Time Reload Register FMMEND FF F960h FSMMEND FF F760h Flash Memory Module Erase End Time Reload Register FMRCV FF F962h FSMRCV FF F762h Flash Memory Recovery Time Reload Register FMAR0 FF F964h FSMAR0 FF F764h Flash Memory Auto-Read Register 0 FMAR1 FF F966h FSMAR1 FF F766h Flash Memory Auto-Read Register 1 FMAR2 FF F968h FSMAR2 FF F768h Flash Memory Auto-Read Register 2 15 8 7 0 Reserved IBA 15 0 IBD Table 18 Flash Memory Interface Registers Program Memory Data Memory Description

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8.5.3 Flash Memory 0 Wr ite Enable Register

(FM0WER/FSM0WER) The FM0WER register controls section-level write protec- tion for the first half of the flash program memory. The FMS0WER registers controls section-level write protection for the flash data memory. Each data block is divided into 16 8K-byte sections. Each bit in the FM0WER and FSM0WER registers controls write protection for one of these sections. The FM0WER and FSM0WER registers are cleared after device reset, so the flash memory is write protected after re- set. The CPU bus master has read/write access to this reg- isters. FM0WEn The Flash Memory 0 Write Enable n bits con- trol write protection for a section of a flash memory data block. The address mapping of the register bits is shown below.

8.5.4 Flash Memory 1 Wr ite Enable Register

(FM1WER) The FM1WER register controls write protection for the sec- ond half of the program flash memory. The data block is di- vided into 16 8K-byte sections. Each bit in the FM1WER register controls write protecti on for one of these sections. The FM1WER register is cleared after device reset, so the flash memory is write protected after reset. The CPU bus master has read/write access to this registers. FM1WEn The Flash Memory 1 Write Enable n bits con- trol write protection for a section of a flash memory data block. The address mapping of the register bits is shown below.

8.5.5 Flash Data Memory 0 Write Enable Register

(FSM0WER) The FSM0WER register controls write protection for the flash data memory. The data block is divided into 16 512- byte sections. Each bit in the FSM0WER register controls write protection for one of these sections. The FSM0WER register is cleared after device reset, so the flash memory is write protected after reset. The CPU bus master has read/ write access to this registers. FSM0WEn The Flash Data Memory 0 Write Enable n bits control write protection for a section of a flash memory data block. The address mapping of the register bits is shown below.

8.5.6 Flash Memory Cont rol Register (FMCTRL/

FSMCTRL) This register controls the ba sic functions of the Flash pro- gram memory. The register is clear after device reset. The CPU bus master has read/write access to this register. LOWPRW The Low Power Mode controls whether flash program memory is operated in low-power mode, which draws less current when data is read. This is accomplished be only accessing the flash program memory during the first half of the clock period. The low-power mode must not be used at System Clock frequencies above 25 MHz, otherwise a read access may return undefined data. This bit must not be changed while the flash program memory is busy being programmed or erased. – Normal mode. 1 – Low-power mode. CWD The CPU Write Disable bit controls whether the CPU has write access to flash memory. This bit must not be changed while FMBUSY is set. 0 – The CPU has write access to the flash memory 1 – An external debugging tool is the current “owner” of the flash memory interface, so write accesses by the CPU are inhibited. 15 0 FM0WE Bit Logical Address Range 0 00 0000h –00 1FFFh 1–14 . . . 15 01 E000h –01 FFFFh 15 0 FM1WE Bit Logical Address Range 0 02 0000h –02 1FFFh 1–14 . . . 15 03 E000h –03 FFFFh 15 0 FSM0WE Bit Logical Address Range 0 0E 0000h –0E 01FFh 1–14 . . . 15 0E 1E00h –0E 1FFFh 7 6 5 4 3 2 1 0 MER PER PE IENPROG DISVRF Res. CWD LOWPRW

37 www.national.com CP3CN17 DISVRF The Disable Verify bit controls the automatic verification feature. This bit must not be changed while the flash program memory is busy being programmed or erased. – New flash program memory contents are automatically verified after programming. – Automatic verification is disabled. IENPROG The Interrupt Enable for Program bit is clear after reset. The flash program and data mem- ories share a single interrupt channel but have independent interrupt enable control bits. 0 – No interrupt request is asserted to the ICU when the FMFULL bit is cleared. 1 – An interrupt request is made when the FMFULL bit is cleared and new data can be written into the write buffer. PE The Program Enable bit controls write access of the CPU to the flash program memory. This bit must not be altered while the flash program memory is busy being programmed or erased. The PER and MER bits must be clear when this bit is set. – Programming the flash program memory by the CPU is disabled. 1 – Programming the flash program memory is enabled. PER The Page Erase Enable bit controls whether a a valid write operation triggers an erase oper- ation on a 1024-byte page of flash memory. Page erase operations are only supported for the main blocks, not the information blocks. A page erase operation on an information block is ignored and does not alter the information block. When the PER bit is set, the PE and MER bits must be clear. This bit must not be changed while the flash program memory is busy being programmed or erased. – Page erase mode disabled. Write opera- tions are performed normally. 1 – A valid write operation to a word location in program memory erases the page that contains the word. MER The Module Erase Enable bit controls wheth- er a valid write operation triggers an erase op- eration on an entire block of flash memory. If an information block is written in this mode, both the information block and its correspond- ing main block are erased. When the MER bit is set, the PE and PER bits must be clear. This bit must not be changed while the flash pro- gram memory is busy being programmed or erased. – Module erase mode disabled. Write oper- ations are performed normally. 1 – A valid write operation to a word location in a main block erases the block that con- tains the word. A valid write operation to a word location in an information block erases the block that contains the word and its associated main block.

8.5.7 Flash Memory Stat us Register (FMSTAT/

FSMSTAT) This register reports the currents status of the on-chip Flash memory. The FLSR register is clear after device reset. The CPU bus master has read/write access to this register. EERR The Erase Error bit indicates whether an error has occurred during a page erase or module (block) erase. After an erase error occurs, software can clear the EERR bit by writing a 1 to it. Writing a 0 to the EERR bit has no effect. Software must not change this bit while the flash program memory is busy being pro- grammed or erased. – The erase operation was successful. 1 – An erase error occurred. PERR The Program Error bit indicates whether an error has occurred during programming. After a programming error occurs, software can clear the PERR bit by writing a 1 to it. Writing a 0 to the PERR bit has no effect. Software must not change this bit while the flash pro- gram memory is busy being programmed or erased. – The programming operation was suc- cessful. – A programming error occurred. FMBUSY The Flash Memory Busy bit indicates whether the flash memory (either main block or infor- mation block) is busy being programmed or erased. During that ti me, software must not request any further flash memory operations. If such an attempt is made, the CPU is stopped as long as the FMBUSY bit is active. The CPU must not atte mpt to read from pro- gram memory (including instruction fetches) while it is busy. – Flash memory is ready to receive a new erase or programming request. 1 – Flash memory busy with previous erase or programming operation. FMFULL The Flash Memory Buffer Full bit indicates whether the write buffer for programming is full or not. When the buffer is full, new erase and write requests may not be made. The IENPROG bit can be enabled to trigger an in- terrupt when the buffer is ready to receive a new request. – Buffer is ready to receive new erase or write requests. 1 – Buffer is full. No new erase or write re- quests can be accepted. 7 5 4 3 2 1 0 Reserved DERR FMFULL FMBUSY PERR EERR

www.national.com 38 CP3CN17 DERR The Data Loss Error bit indicates that a buffer overrun has occurred during a programming sequence. After a data loss error occurs, soft- ware can clear the DERR bit by writing a 1 to it. Writing a 0 to the DERR bit has no effect. Software must not change this bit while the flash program memory is busy being pro- grammed or erased. – No data loss error occurred. 1 – Data loss error occurred.

8.5.8 Flash Memory Pres caler Register (FMPSR/

FSMPSR) The FMPSR register is a byte-wide read/write register that selects the prescaler divider ratio. The CPU must not modify this register while an erase or programming operation is in progress (FMBUSY is set). At rese t, this register is initial- ized to 04h if the flash memory is idle. The CPU bus master has read/write access to this register. FTDIV The prescaler divisor scales the frequency of the System Clock by a factor of (FTDIV + 1).

8.5.9 Flash Memory Start Time Reload Register

(FMSTART/FSMSTART) The FMSTART/FSMSTART register is a byte-wide read/ write register that controls the program/erase start delay time. Software must not modify this register while a pro- gram/erase operation is in progress (FMBUSY set). At re- set, this register is initialized to 18h if the flash memory is idle. The CPU bus master has read/write access to this reg- ister. FTSTART The Flash Timing Start Delay Count field gen- erates a delay of (FTSTART + 1) prescaler output clocks.

8.5.10 Flash Memory Tran sition Time Reload

Register (FMTRAN/FSMTRAN) The FMTRAN/FMSTRAN register is a byte-wide read/write register that controls some program/erase transition times. Software must not modify this register while program/erase operation is in progress (FMBUSY set). At reset, this regis- ter is initialized to 30h if the flash memory is idle. The CPU bus master has read/write access to this register. FTTRAN The Flash TIming Transition Count field spec- ifies a delay of (FTTRAN + 1) prescaler output clocks.

8.5.11 Flash Memory Prog ramming Time Reload

Register (FMPROG/FSMPROG) The FMPROG/FSMPROG register is a byte-wide read/write register that controls the programming pulse width. Soft- ware must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this regis- ter is initialized to 16h if the flash memory is idle. The CPU bus master has read/write access to this register. FTPROG The Flash Timing Programming Pulse Width field specifies a programming pulse width of 8 × (FTPROG + 1) prescaler output clocks.

8.5.12 Flash Memory Page Erase Time Reload

Register (FMPERASE/FSMPERASE) The FMPERASE/FSMPERASE regi ster is a byte-wide read/write register that controls the page erase pulse width. Software must not modify this register while a program/ erase operation is in progress (FMBUSY set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master has read/write access to this register. FTPER The Flash Timing Page Erase Pulse Width field specifies a page erase pulse width of 4096 × (FTPER + 1) prescaler output clocks. 75 4 0 Reserved FTDIV FTSTART FTTRAN FTPROG FTPER

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8.5.13 Flash Memory Module Erase Time Reload

Register 0 (FMMERASE0/FSMMERASE0) The FMMERASE0/FSMMERASE0 register is a byte-wide read/write register that c ontrols the module erase pulse width. Software must not modify this register while a pro- gram/erase operation is in progress (FMBUSY set). At re- set, this register is initialized to EAh if the flash memory is idle. The CPU bus master has read/write access to this reg- ister. FTMER The Flash Timing Module Erase Pulse Width field specifies a module erase pulse width of 4096 × (FTMER + 1) prescaler output clocks.

8.5.14 Flash Memory End Time Reload Register

(FMEND/FSMEND) The FMEND/FSMEND register is a byte-wide read/write register that controls the de lay time after a program/erase operation. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 18h when the flash mem- ory on the chip is idle. The CPU bus master has read/write access to this register. FTEND The Flash Timing End Delay Count field spec- ifies a delay of (FTEND + 1) prescaler output clocks.

8.5.15 Flash Memory Module Erase End Time Reload

Register (FMMEND/FSMMEND) The FMMEND/FSMMEND register is a byte-wide read/write register that controls the delay time after a module erase op- eration. Software must not modify this register while a pro- gram/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 3Ch if the flash memory is idle. The CPU bus master has read/write access to this reg- ister. FTMEND The Flash Timing Module Erase End Delay Count field specifies a delay of 8 × (FTMEND + 1) prescaler output clocks.

8.5.16 Flash Memory Recovery Time Reload Register

(FMRCV/FSMRCV) The FMRCV/FSMRCV register is a byte-wide read/write register that controls the recovery delay time between two flash memory accesses. Software must not modify this reg- ister while a program/erase operation is in progress (FM- BUSY set). At reset, this regist er is initialized to 04h if the flash memory is idle. The CP U bus master has read/write access to this register. FTRCV The Flash Timing Recovery Delay Count field specifies a delay of (FTRCV + 1) prescaler output clocks.

8.5.17 Flash Memory Auto-R ead Register 0 (FMAR0/

FSMAR0) The FMAR0/FSMAR0 register contains a copy of the Func- tion Word from Information Block 0

8.5.18 Flash Memory Auto-R ead Register 1 (FMAR1/

FSMAR1) The FMAR1 register contains a copy of the Protection Word from Information Block 1. The Protection Word is sampled at reset. The contents of the FMAR1 register define the cur- rent Flash memory protection settings. The CPU bus mas- ter has read-only access to this register. The FSMAR1 register has the same value as the FMAR1 register. The for- mat is the same as the format of the Protection Word (see Section 8.4.2). FTMER FTEND FTMEND FTRCV 15 0 Reserved 15 13 12 10 9 7 6 4 3 1 0 WRPROT RDPROT ISPE EMPTY BOOTAREA 1

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8.5.19 Flash Memory Auto-R ead Register 2 (FMAR2/

FSMAR2) The FMAR2 register is a word-wide read-only register, which is loaded during reset. It is used to build the Code Area start address. At reset, the CPU executes a branch, using the contents of the FMAR2 register as displacement. The CPU bus master has read-only access to this register. The FSMAR2 register has the same value as the FMAR2 register. CADR8:0 The Code Area Start Address (bits 8:0) con- tains the lower 9 bits of the Code Area start address. The CADR8:0 field has a fixed value of 0. CADR12:9 The Code Area Start Address (bits 12:9) are loaded during reset with the inverted value of BOOTAREA3:0. CADR15:13 The Code Area Start Address (bits 15:13) contains the upper 3 bits of the Code Area start address. The CADR15:13 field has a fixed value of 0. CADR7:0 15 13 12 9 8 CADR15:13 CADR12:8 CADR8

9.0 DMA Controller

1. Arbitrates to become master of the CPU bus.
2. Determines priority among the DMAC channels, one

Channel 0 having the highest priority.

1. Executes data transfer bus cycle(s) selected by the val-

bus cycle that accesses the requesting device.

1. If the transfer of a block is terminated, the DMAC does

Updates the termination bits. Generates an interrupt (if enabled).

1. Returns mastership of the CPU bus to the CPU.

then on the rising edge of every clock cycle.

9.1 CHANNEL ASSIGNMENT

fers, other resources must be disabled.

9.2 TRANSFER TYPES

ry, and when the destination does not support direct mode.

9.2.1 Direct (Flyby) Transfers

anism, as shown in Figure 2. Figure 2. Direct DMA Cycle Followed by a CPU Cycle

www.national.com 42 CP3CN17 ed. The maximum bus throughput in intermittent mode is one transfer for every three System Clock cycles. The max- imum bus throughput in continuous mode is one transfer for every clock cycle. The I/O device which made the DMA request is called the implied I/O device. The other device can be either memory or another I/O device, and is called the addressed device. Because only one address is required in direct mode, this address is taken from the corresponding ADCAn counter. The DMAC channel generates either a read or a write bus cycle, as controlled by the DMACNTLn.DIR bit. When the DMACNTLn.DIR bit is clear, a read bus cycle from the addressed device is performed, and the data is written to the implied I/O device. When the DMACNTLn.DIR bit is set, a write bus cycle to the addressed device is per- formed, and the data is read from the implied I/O device. The configuration of either address freeze or address up- date (increment or decrement) is independent of the num- ber of transferred bytes, transfer direction, or number of bytes in each DMAC transfer cycle. All these can be config- ured for each channel by programming the appropriate con- trol register. Whether 8 or 16 bits are transferred in each cycle is select- ed by the DMACNTLn.TCS register bit. After the data item has been transferred, the BLTCn counter is decremented by one. The ADCAn counter is updated according to the INCA and ADA fields in the DMACNTLn register.

9.2.2 Indirect (Memory-To-Memory) Transfers

In indirect (memory-to-memory ) mode, data transfers use two consecutive bus cycles. The data is first read into a tem- porary register, and then written to the destination in the fol- lowing cycle. This mode is slower than the direct (flyby) mode, but it provides support for different source and desti- nation bus widths. Indirect mode must be used for transfers between memory devices. If an intermittent bus policy is used, the maximum through- put is one transfer for every five clock cycles. If a continuous bus policy is used, maximum throughput is one transfer for every two clock cycles. When the DMACNTLn.DIR bit is 0, the first bus cycle reads data from the source using the ADCAn counter, while the second bus cycle writes the data into the destination using the ADCBn counter. When t he DMACNTLn.DIR bit is set, the first bus cycle reads data from the source using the AD- CBn counter, while the second bus cycle writes the data into the destination addressed by the ADCAn counter. The number of bytes transferred in each cycle is taken from the DMACNTLn.TCS register bit. After the data item has been transferred, the BLTCn counter is decremented by one. The ADCAn and ADCBn counters are updated accord- ing to the INCA, INCB, ADA, and ADB fields in the DMACNTLn register.

9.3 OPERATION MODES

The DMAC operates in three different block transfer modes: single transfer, double buffer, and auto-initialize.

9.3.1 Single Transfer Operation

This mode provides the simplest way to accomplish a single block data transfer. Initialization 1. Write the block transfer addresses and byte count into the corresponding ADCAn, ADCBn, and BLTCn counters. 2. Clear the DMACNTLn.OT bit to select non-auto-initial- ize mode. Clear the DMASTAT.VLD bit by writing a 1 to it. 3. Set the DMACNTLn.CHEN bit to activate the channel and enable it to respond to DMA transfer requests. Termination When the BLTCn counter reaches 0: 1. The transfer operation terminates. 2. The DMASTAT.TC and DMASTAT.OVR bits are set, and the DMASTAT.CHAC bit is cleared. 3. An interrupt is generated if enabled by the DMACNTLn.ETC or DMACNTLn.EOVR bits. The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to avoid prematurely starting a new DMA transfer.

9.3.2 Double Buffer Operation

This mode allows software to set up the next block transfer while the current block transfer proceeds. Initialization 1. Write the block transfer addresses and byte count into the ADCAn, ADCBn, and BLTCn counters. 2. Clear the DMACNTLn.OT bit to select non-auto-initial- ize mode. Clear the DMASTAT.VLD bit by writing a 1 to it. 3. Set the DMACNTLn.CHEN bit. This activates the chan- nel and enables it to respond to DMA transfer requests. 4. While the current block transfer proceeds, write the ad- dresses and byte count for the next block into the ADRAn, ADRBn, and BLTRn registers. The BLTRn reg- ister must be written last, because it sets the DMAS- TAT.VLD bit which indicates that all the parameters for the next transfer have been updated. Continuation/Termination When the BLTCn counter reaches 0: 1. The DMASTAT.TC bit is set. 2. An interrupt is generated if enabled by the DMACNTLn.ETC bit. 3. The DMAC channel checks the value of the VLD bit. If the DMASTAT.VLD bit is set: 1. The channel copies the ADRAn, ADRBn, and BLTRn values into the ADCAn, ADCBn, and BLTCn registers. 2. The DMASTAT.VLD bit is cleared. 3. The next block transfer is started.

43 www.national.com CP3CN17 If the DMASTAT.VLD bit is clear: 1. The transfer operation terminates. 2. The channel sets the DMASTAT.OVR bit. 3. The DMASTAT.CHAC bit is cleared. 4. An interrupt is generated if enabled by the DMACNTLn.EOVR bit. The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to avoid prematurely starting a new DMA transfer. Note: The ADCBn and ADRBn registers are used only in indirect (memory-to-memory ) transfer. In direct (flyby) mode, the DMAC does not use them and therefore does not copy ADRBn into ADCBn.

9.3.3 Auto-Initialize Operation

This mode allows the DMAC to continuously fill the same memory area without software intervention. Initialization 1. Write the block addresses and byte count into the AD- CAn, ADCBn, and BLTCn counters, as well as the ADRAn, ADRBn, and BLTRn registers. 2. Set the DMACNTLn.OT bit to select auto-initialize mode. 3. Set the DMACNTLn.CHEN bit to activate the channel and enable it to respond to DMA transfer requests. Continuation When the BLTCn counter reaches 0: 1. The contents of the ADRAn, ADRBn, and BLTRn regis- ters are copied to the ADCAn, ADCBn, and BLTCn counters. 2. The DMAC channel checks the value of the DMAS- TAT.TC bit. If the DMASTAT.TC bit is set: 1. The DMASTAT.OVR bit is set. 2. A level interrupt is generated if enabled by the DMACNTLn.EOVR bit. 3. The operation is repeated. If the DMASTAT.TC bit is clear: 1. The DMASTAT.TC bit is set. 2. A level interrupt is generated if enabled by the DMACNTLn.ETC bit. 3. The DMAC operation is repeated. Termination The DMA transfer is terminated when the DMACNTLn.CHEN bit is cleared.

9.4 SOFTWARE DMA REQUEST

In addition to the hardware requests from I/O devices, a DMA transfer request can also be initiated by software. A software DMA transfer request must be used for block copy- ing between memory devices. When the DMACNTLn.SWRQ bit is set, the corresponding DMA channel receives a DMA transfer request. When the DMACNTLn.SWRQ bit is clear, the software DMA transfer request of the corresponding channel is inactive. For each channel, use the software DMA transfer request only when the corresponding hardware DMA request is in- active and no terminal count interrupt is pending. Software can poll the DMASTAT.CHAC bit to determine whether the DMA channel is already active. After verifying the DMAS- TATn.CHAC bit is clear (channel inactive), check the DMAS- TATn.TC (terminal count) bit. If the TC bit is clear, then no terminal count condition exists and therefore no terminal count interrupt is pending. If the channel is not active and no terminal count interrupt is pending, software may request a DMA transfer.

9.5 DEBUG MODE

When the FREEZE signal is active, all DMA operations are stopped. They will start again when the FREEZE signal goes inactive. This allows breakpoints to be used in debug systems.

9.6 DMA CONTROLLER REGISTER SET

There are four identical sets of DMA controller registers, as listed in Table 20. Table 20 DMA Controller Registers Name Address Description ADCA0 FF F800h Device A Address Counter Register ADRA0 FF F804h Device A Address Register ADCB0 FF F808h Device B Address Counter Register ADRB0 FF F80Ch Device B Address Register BLTC0 FF F810h Block Length Counter Register BLTR0 FF F814h Block Length Register DMACNTL0 FF F81Ch DMA Control Register DMASTAT0 FF F81Eh DMA Status Register ADCA1 FF F820h Device A Address Counter Register ADRA1 FF F824h Device A Address Register ADCB1 FF F828h Device B Address Counter Register ADRB1 FF F82Ch Device B Address Register BLTC1 FF F830h Block Length Counter Register BLTR1 FF F834h Block Length Register DMACNTL1 FF F83Ch DMA Control Register DMASTAT1 FF F83Eh DMA Status Register

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9.6.1 Device A Address Co unter Register (ADCAn)

The Device A Address Counter register is a 32-bit, read/ write register. It holds the current 24-bit address of either the source data item or the destination location, depending on the state of the DIR bit in the CNTLn register. The ADA bit of DMACNTLn register controls whether to adjust the point- er in the ADCAn register by t he step size specified in the INCA field of DMACNTLn register. The upper 8 bits of the ADCAn register are reserved and always clear.

9.6.2 Device A Address Register (ADRAn)

The Device A Address register is a 32-bit, read/write regis- ter. It holds the 24-bit starting address of either the next source data block, or the next destination data area, according to the DIR bit in the DMACNTLn register. The upper 8 bits of the ADRAn register are reserved and always clear.

9.6.3 Device B Address Co unter Register (ADCBn)

The Device B Address Counter register is a 32-bit, read/ write register. It holds the current 24-bit address of either the source data item, or the destination location, according to the DIR bit in the CNTLn register. The ADCBn register is up- dated after each transfer cycle by INCB field of the DMACNTLn register according to ADB bit of the DMACNTLn register. In direct (flyby) mode, this register is not used. The upper 8 bits of the ADCBn register are re- served and always clear.

9.6.4 Device B Address Register (ADRBn)

The Device B Address register is a 32-bit, read/write regis- ter. It holds the 24-bit starting address of either the next source data block or the next destination data area, accord- ing to the DIR bit in the CNTLn register. In direct (flyby ) mode, this register is not used. The upper 8 bits of the AD- CRBn register are reserved and always clear.

9.6.5 Block Length Coun ter Register (BLTCn)

The Block Length Counter register is a 16-bit, read/write register. It holds the current number of DMA transfers to be executed in the current block. BLTCn is decremented by one after each transfer cycle. A DMA transfer may consist of 1 or 2 bytes, as selected by the DMACNTLn.TCS bit. Note: 0000h is interpreted as 216-1 transfer cycles. ADCA2 FF F840h Device A Address Counter Register ADRA2 FF F844h Device A Address Register ADCB2 FF F848h Device B Address Counter Register ADRB2 FF F84Ch Device B Address Register BLTC2 FF F850h Block Length Counter Register BLTR2 FF F854h Block Length Register DMACNTL2 FF F85Ch DMA Control Register DMASTAT2 FF F85Eh DMA Status Register ADCA3 FF F860h Device A Address Counter Register ADRA3 FF F864h Device A Address Register ADCB3 FF F868h Device B Address Counter Register ADRB3 FF F86Ch Device B Address Register BLTC3 FF F870h Block Length Counter Register BLTR3 FF F874h Block Length Register DMACNTL3 FF F87Ch DMA Control Register DMASTAT3 FF F87Eh DMA Status Register 31 24 23 0 Reserved Device A Address Counter Table 20 DMA Contro ller Registers Name Address Description 31 24 23 0 Reserved Device A Address 31 24 23 0 Reserved Device B Address Counter 31 24 23 0 Reserved Device B Address 15 0 Block Length Counter

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9.6.6 Block Length Register (BLTRn)

The Block Length register is a 16-bit, read/write register. It holds the number of DMA transfers to be performed for the next block. Writing this register automatically sets the DM- ASTAT.VLD bit. Note: 0000h is interpreted as 2 16-1 transfer cycles.

9.6.7 DMA Control Re gister (DMACNTLn)

The DMA Control register n is a word-wide, read/write reg- ister that controls the operation of DMA channel n. This reg- ister is cleared at reset. Reserved bits must be written with CHEN The Channel Enable bit must be set to enable any DMA operation on this channel. Writing a 1 to this bit starts a new DMA transfer even if it is currently a 1. If all DMACNTLn.CHEN bits are clear, the DMA clock is disabled to reduce power. 0 – Channel disabled. 1 – Channel enabled. ETC If the Enable Interrupt on Terminal Count bit is set, it enables an interrupt when the DMAS- TAT.TC bit is set. – Interrupt disabled. 1 – Interrupt enabled. EOVR If the Enable Interrupt on OVR bit is set, it en- ables an interrupt when the DMASTAT.OVR bit is set. – Interrupt disabled. 1 – Interrupt enabled. TCS The Transfer Cycle Size bit specifies the num- ber of bytes transferred in each DMA transfer cycle. In direct (fly-by) mode, undefined re- sults occur if the TCS bit is not equal to the ad- dressed memory bus width. – Byte transfers (8 bits per cycle). 1 – Word transfers (16 bits per cycle). IND The Direct/Indirect Transfer bit specifies the transfer type. 0 – Direct transfer (flyby). 1 – Indirect transfer (memory-to-memory). DIR The Transfer Direction bit specifies the direc- tion of the transfer relative to Device A. – Device A (pointed to by the ADCAn regis- ter) is the source. In Fly-By mode a read transaction is initialized. 1 – Device A (pointed to by the ADCAn regis- ter) is the destination. In Fly-By mode a write transaction is initialized. OT The Operation Type bit specifies the operation mode of the DMA controller. 0 – Single-buffer mode or double-buffer mode enabled. 1 – Auto-Initialize mode enabled. BPC The Bus Policy Control bit specifies the bus policy applied by the DMA controller. The op- eration mode can be either intermittent (cycle stealing) or continuous (burst). – Intermittent operation. The DMAC chan- nel relinquishes the bus after each trans- action, even if the request is still asserted. – Continuous operation. The DMAC chan- nel n uses the bus continuously as long as the request is asserted. This mode can only be used for software DMA requests. For hardware DMA requests, the BPC bit must be clear. SWRQ The Software DMA Request bit is written with a 1 to initiate a software DMA request. Writing a 0 to this bit deactivates the software DMA request. The SWRQ bit must only be written when the DMRQ signal for this channel is in- active (DMASTAT.CHAC = 0). – Software DMA request is inactive. 1 – Software DMA request is active. ADA If the Device A Address Control bit is set, it en- ables updating the Device A address. 0 – ADCAn address unchanged. 1 – ADCAn address incremented or decre- mented, according to INCA field of DMACNTLn register. INCA The Increment/Decrem ent ADCAn field spec- ifies the step size for the Device A address in- crement/decrement. 00 – Increment ADCAn register by 1. 01 – Increment ADCAn register by 2. 10 – Decrement ADCAn register by 1. 11 – Decrement ADCAn register by 2. ADB If the Device B Address Control bit is set, it en- ables updating the Device B Address. – ADCBn address unchanged. 1 – ADCBn address incremented or decre- mented, according to INCB field of DMACNTLn register. INCB The Increment/Decrem ent ADCBn field spec- ifies the step size for the Device B address in- crement/decrement. 00 – Increment ADCBn register by 1. 01 – Increment ADCBn register by 2. 10 – Decrement ADCBn register by 1. 11 – Decrement ADCBn register by 2. 15 0 Block Length 765432 10 BPC OT DIR IND TCS EOVR ETC CHEN 15 14 13 12 11 10 9 8 Res. INCB ADB INCA ADA SWRQ

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9.6.8 DMA Status Register (DMASTAT)

The DMA status register is a byte-wide, read register that holds the status information for the DMA channel n. This register is cleared at reset. The reserved bits always return zero when read. The VLD, OVR and TC bits are sticky (once set by the occurrence of the specific condition, they remain set until explicitly cleared by software). These bits can be in- dividually cleared by writing 1 to the bit positions in the DM- ASTAT register to be cleared. Writing 0 to these bits has no effect TC The Terminal Count bit indicates whether the transfer was completed by a terminal count condition (BLTCn Register reached 0). – Terminal count condition did not occur. 1 – Terminal count condition occurred. OVR The behavior of the Channel Overrun bit de- pends on the operation mode (single buffer, double buffer, or auto-initialize) of the DMA channel. In double-buffered mode (DMACNTLn.OT = 0): The OVR bit is set when the present transfer is completed (BLTCn = 0), but the parameters for the next transfer (address and block length) are not valid (DMASTAT.VLD = 0). In auto-initialize mode (DMACNTLn.OT = 1): The OVR bit is set when the present transfer is completed (BLTCn = 0), and the DMAS- TAT.TC bit is still set. In single-buffer mode: Operates in the same way as double-buffer mode. In single-buffered mode, the DMAS- TAT.VLD bit should always be clear, so it will also be set when the DMASTAT.TC bit is set. Therefore, the OVR bit can be ignored in this mode. CHAC The Channel Active bit continuously indicates the active or inactive status of the channel, and therefore, it is read only. Data written to the CHAC bit is ignored. – Channel inactive. 1 – Indicates that the channel is active (CHEN bit in the CNTLn register is 1 and BLTCn > 0) VLD The Transfer Parameters Valid bit specifies whether the transfer parameters for the next block to be transferred are valid. Writing the BLTRn register automatically sets this bit. The bit is cleared in the following cases:

• The present transfer is completed and the ADRAn, ADRBn (indirect mode only), and BLTR registers are copied to the ADCAn, ADCBn (indirect mode only), and BLTCn registers.  Writing 1 to the VLD bit. 7 4 3 2 1 0 Reserved VLD CHAC OVR TC

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10.0 Interrupts

The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and generates interrupts to the CPU. Interrupts from the timers, UARTs, Microwire/ SPI interface, and Multi-Input Wake-Up are all maskable in- terrupts. The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is triggered by a falling edge received on the NMI input pin. The priorities of the maskable interrupts are hardwired and therefore fixed. The interrupts are named IRQ0 through IRQ31, in which IRQ0 has the lowest priority and IRQ31 has the highest priority.

10.1 NON-MASKABLE INTERRUPTS

The Interrupt Control Unit (ICU) receives the external NMI input and generates the NMI signal driven to the CPU. The NMI input is an asynchronous input with Schmitt trigger characteristics and an internal synchronization circuit, therefore no external synchronizing circuit is needed. The NMI pin triggers an exception on its falling edge.

10.1.1 Non-Maskable Interrupt Processing

The CPU performs an interrupt acknowledge bus cycle when beginning to process a non-maskable interrupt. The address associated with this core bus cycle is within the in- ternal core address space and may be monitored as a Core Bus Monitoring (CBM) clock cycle. At reset, NMI interrupts are disabled and must remain dis- abled until software initializes the interrupt table, interrupt base register (INTBASE), and t he interrupt mode. The ex- ternal NMI interrupt is enabled by setting the EXNMI.EN- LCK bit and will remain enabled until a reset occurs. Alternatively, the external NMI interrupt can be enabled by setting the EXNMI.EN bit and will remain enabled until an in- terrupt event or a reset occurs.

10.2 MASKABLE INTERRUPTS

The ICU receives level-triggered interrupt request signals from 31 internal sources and generates a vectored interrupt to the CPU when required. Priority among the interrupt sources (named IRQ1 through IRQ31) is fixed. The maskable interrupts are globally enabled and disabled by the E bit in the PSR register. The EI and DI instructions are used to set (enable) and clear (disable) this bit. The glo- bal maskable interrupt enable bit (I bit in the PSR) must also be set before any maskable interrupts are taken. Each interrupt source can be individually enabled or dis- abled under software control through the ICU interrupt en- able registers and also through interrupt enable bits in the peripherals that request the interrupts. The CR16C core supports IRQ0, but in the CP3CN17 it is not connected to any interrupt source.

10.2.1 Maskable Interrupt Processing

Interrupt vector numbers are always positive, in the range 10h to 2Fh. The IVCT register contains the interrupt vector of the enabled and pending interrupt with the highest priori- ty. The interrupt vector 10h corresponds to IRQ0 and the lowest priority, while the vector 2Fh corresponds to IRQ31 and the highest priority. The CPU performs an interrupt ac- knowledge bus cycle on receiving a maskable interrupt re- quest from the ICU. During the interrupt acknowledge cycle, a byte is read from address FF FE00h (IVCT register). The byte is used as an index into the Dispatch Table to deter- mine the address of the interrupt handler. Because IRQ0 is not connected to any interrupt source, it would seem that the interrupt vector would never return the value 10h. If it does return a value of 10h, the entry in the dispatch table should point to a default interrupt handler that handles this error condition. One possible condition for this to occur is deassertion of the interrupt before the interrupt acknowledge cycle.

10.3 INTERRUPT CONTROLLER REGISTERS

Table 21 lists the ICU registers.

10.3.1 Non-Maskable Interru pt Status Register

(NMISTAT) The NMISTAT register is a byte-wide read-only register. It holds the status of the current pending Non-Maskable Inter- rupt (NMI) requests. On the CP3CN17, the external NMI in- put is the only source of NMI interrupts. The NMISTAT register is cleared on reset and each time its contents are read. EXT The External NMI request bit indicates wheth- er an external non-maskable interrupt request has occurred. Refer to the description of the EXNMI register below for additional details. – No external NMI request. 1 – External NMI request has occurred. Table 21 Interrupt Controller Registers Name Address Description NMISTAT FF FE02h Non-Maskable Inter- rupt Status Register EXNMI FF FE04h External NMI Trap Control and Status Register IVCT FF FE00h Interrupt Vector Register IENAM0 FF FE0Eh Interrupt Enable and Mask Register 0 IENAM1 FF FE10h Interrupt Enable and Mask Register 1 ISTAT0 FF FE0Ah Interrupt Status Register 0 ISTAT1 FF FE0Ch Interrupt Status Register 1 71 0 Reserved EXT

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10.3.2 External NMI Trap Cont rol and Status Register

(EXNMI) The EXNMI register is a byte-wide read/write register. It in- dicates the current value of the NMI pin and controls the NMI interrupt trap generation based on a falling edge of the NMI pin. TST, EN and ENLCK are cleared on reset. When writing to this register, all reserved bits must be written with 0 for the device to function properly EN The EXNMI trap enable bit is one of two bits that can be used to enable NMI interrupts. The bit is cleared by hardware at reset and whenever the NMI interrupt occurs (EXN- MI.EXT set). It is intended for applications where the NMI input toggles frequently but nested NMI traps are not desired. For these applications, the EN bit needs to be re-en- abled before exiting the trap handler. When used this way, the ENLCK bit should never be set. The EN bit can be set and cleared by soft- ware (software can set this bit only if EXN- MI.EXT is cleared), and should only be set after the interrupt base register and the inter- rupt stack pointer have been set up. – NMI interrupts not enabled by this bit (but may be enabled by the ENLCK bit). – NMI interrupts enabled. PIN The PIN bit indicates the state (non-inverted) on the NMI input pin. This bit is read-only, data written into it is ignored. 0 – NMI pin not asserted. 1 – NMI pin asserted. ENLCK The EXNMI trap enable lock bit is used to per- manently enable NMI interrupts. Only a de- vice reset can clear the ENLCK bit. This allows the external NMI feature to be enabled after the interrupt base register and the inter- rupt stack pointer have been set up. When the ENLCK bit is set, the EN bit is ignored. – NMI interrupts not enabled by this bit (but may be enabled by the EN bit). – NMI interrupts enabled.

10.3.3 Interrupt Vector Register (IVCT)

The IVCT register is a byte-wide read-only register which re- ports the encoded value of the highest priority maskable in- terrupt that is both asserted and enabled. The valid range is from 10h to 2Fh. The register is read by the CPU during an interrupt acknowledge bus cycle, and INTVECT is valid dur- ing that time. It may contain invalid data while INTVECT is updated. INTVECT The Interrupt Vector field indicates the highest priority interrupt which is both asserted and enabled.

10.3.4 Interrupt Enable an d Mask Register 0 (IENAM0)

The IENAM0 register is a wo rd-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ1 through IRQ15. The reg- ister is initialized to FFFFh upon reset. IENA Each Interrupt Enable bit enables or disables the corresponding interrupt request IRQ1 through IRQ15, for example IENA15 controls IRQ15. Because IRQ0 is not used, IENA0 is ignored. – Interrupt is disabled. 1 – Interrupt is enabled.

10.3.5 Interrupt Enable and Mask Register 1 (IENAM1)

The IENAM1 register is a wo rd-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ16 through IRQ31. The reg- ister is initialized to FFFFh at reset. IENA Each Interrupt Enable bit enables or disables the corresponding interrupt request IRQ16 through IRQ31, for example IENA15 controls IRQ31. – Interrupt is disabled. 1 – Interrupt is enabled. 73 2 1 0 Reserved ENLCK PIN EN 7 6 5 0 0 0 INTVECT 15 1 0 IENA Res. 15 0 IENA

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10.3.6 Interrupt Status Register 0 (ISTAT0)

The ISTAT0 register is a word-wide read-only register. It in- dicates which maskable interrupt inputs to the ICU are ac- tive. These bits are not affected by the state of the corresponding IENA bits. IST The Interrupt Status bits indicate if a maskable interrupt source is signalling an in- terrupt request. IST[15:1] correspond to IRQ15 to IRQ1 respectively. Because the IRQ0 interrupt is not used, bit 0 always reads back 0. – Interrupt is not active. 1 – Interrupt is active.

10.3.7 Interrupt Status Register 1 (ISTAT1)

The ISTAT1 register is a word-wide read-only register. It in- dicates which maskable interrupt inputs into the ICU are ac- tive. These bits are not affected by the state of the corresponding IENA bits. IST The Interrupt Status bits indicate if a maskable interrupt source is signalling an in- terrupt request. IST[31:16] correspond to IRQ31 to IRQ16, respectively. – Interrupt is not active. 1 – Interrupt is active.

10.4 MASKABLE INTERRUPT SOURCES

Table 22 shows the interrupts assigned to various on-chip maskable interrupts. The priority of simultaneous maskable interrupts is linear, with IRQ31 having the highest priority. Table 22 Maskable Inte rrupts Assignment 15 1 0 IST Res. 15 0 IST IRQ Number Details IRQ31 TWM (Timer 0) IRQ30 Reserved IRQ29 Reserved IRQ28 Reserved IRQ27 Reserved IRQ26 Reserved IRQ25 Reserved IRQ24 Reserved IRQ23 DMA Channel 0 IRQ22 DMA Channel 1 IRQ21 DMA Channel 2 IRQ20 DMA Channel 3 IRQ19 CAN Interface IRQ18 Advanced Audio Interface IRQ17 UART Rx IRQ16 CVSD/PCM Converter IRQ15 ACCESS.bus Interface IRQ14 TA (Timer input A) IRQ13 TB (Timer input B) IRQ12 VTUA (VTU Interrupt Request 1) IRQ11 VTUB (VTU Interrupt Request 2) IRQ10 VTUC (VTU Interrupt Request 3) IRQ9 VTUD (VTU Interrupt Request 4) IRQ8 Microwire/SPI Rx/Tx IRQ7 UART Tx IRQ6 UART CTS IRQ5 MIWU Interrupt 0 IRQ4 MIWU Interrupt 1 IRQ3 MIWU Interrupt 2 IRQ2 MIWU Interrupt 3 IRQ1 Flash Program/Data Memory IRQ0 Reserved

www.national.com 50 CP3CN17 All reserved or unused interrupt vectors should point to a default or error interrupt handlers.

10.5 NESTED INTERRUPTS

Nested NMI interrupts are always enabled. Nested maskable interrupts are disabled by default, however an in- terrupt handler can allow nested maskable interrupts by set- ting the I bit in the PSR. The LPR instruction is used to set the I bit. Nesting of specific maskable interrupts can be allowed by disabling interrupts from sources for which nesting is not al- lowed, before setting the I bit. Individual maskable interrupt sources can be disabled using the IENAM0 and IENAM1 registers. Any number of levels of nested interrupts are allowed, limit- ed only by the available memory for the interrupt stack.

11.0 Triple Clock and Reset

clocks, and a 32-kHz oscillator start-up delay. Figure 3. Triple Clock and Reset Module

11.1 EXTERNAL CRYSTAL NETWORK

ponents different from the ones specified in this datasheet. X1CKO and optional crystal network at X2CKI/X2CKO. cations for the 32.768 kHz crystal network. Figure 4. External Crystal Network C1 can be trimmed to obtain the desired load capacitance. to minimize power consumption in Power Save mode.

11.2 MAIN CLOCK

Clock signal after a start-up delay of 32,768 clock cycles.

12 MHz ± 20 ppm

53 www.national.com CP3CN17 The Stop Main Osc signal from the Power Management Module stops and starts the high-frequency oscillator. When this signal is asserted, it presets the 14-bit timer to 3FFFh and stops the high-frequ ency oscillator. When the signal goes inactive, the high-frequency oscillator starts and the 14-bit timer counts down from its preset value. When the timer reaches zero, it stops counting and asserts the Good Main Clock signal.

11.3 SLOW CLOCK

The Slow Clock is necessary for operating the device in re- duced power modes and to provide a clock source for mod- ules such as the Timing and Watchdog Module. The Slow Clock operates in a manner similar to the Main Clock. The Stop Slow Osc signal from the Power Manage- ment Module stops and star ts the low-frequency (32.768 kHz) oscillator. When this signal is asserted, it presets a 6- bit timer to 3Fh and disables the low-frequency oscillator. When the signal goes inactive, the low-frequency oscillator starts, and the 6-bit timer counts down from its preset value. When the timer reaches zero, it stops counting and asserts the Good Slow Clock signal, which indicates that the Slow Clock is stable. For systems that do not require a reduced power consump- tion mode, the external crystal network may be omitted for the Slow Clock. In that case, the Slow Clock can be synthe- sized by dividing the Main Clock by a prescaler factor. The prescaler circuit consists of a fixed divide-by-2 counter and a programmable 8-bit prescaler register. This allows a choice of clock divisors ranging from 2 to 512. The resulting Slow Clock frequency must not exceed 100 kHz. A software-programmable mult iplexer selects either the prescaled Main Clock or the 32.768 kHz oscillator as the Slow Clock. At reset, the prescaled Main Clock is selected, ensuring that the Slow Clock is always present initially. Se- lection of the 32.768 kHz oscillator as the Slow Clock dis- ables the clock prescaler, which allows the CLK1 oscillator to be turned off, which reduces power consumption and ra- diated emissions. This can be done only if the module de- tects a toggling low-speed oscillator. If the low-speed oscillator is not operating, the prescaler remains available as the Slow Clock source.

11.4 PLL CLOCK

The PLL Clock is generated by the PLL from the 12 MHz Main Clock by applying a multiplication factor of ×3, ×4, or ×5. To enable the PLL: 1. Set the PLL multiplicati on factor in PRFSC.MODE. 2. Clear the PLL power-down bit CRCTRL.PLLPWD. 3. Clear the high-frequency clock select bit CRC- TRL.FCLK. 4. Read CRCTRL.FCLK, and go back to step 3 if not clear. The CRCTRL.FCLK bit will be clear only after the PLL has stabilized, so software must repeat step 3 until the bit is clear. The clock source can be switched back to the Main Clock by setting the CRCTRL.FCLK bit. The PRSFC register must not be modified while the System Clock is derived from the PLL Clock. The System Clock must be derived from the low-frequency oscillator clock while the MODE field is modified.

11.5 SYSTEM CLOCK

The System Clock drives most of the on-chip modules, in- cluding the CPU. Typically, it is driven by the Main Clock, but it can also be driven by the PLL. In either case, the clock sig- nal is passed through a programmable divider (scale factors from ÷1 to ÷16).

11.6 AUXILIARY CLOCKS

Auxiliary Clock 1 and Auxiliary Clock 2 are generated from Main Clock for use by certain peripherals. Auxiliary Clock 1 is available for the Advanced Audio Interface. Auxiliary Clock 2 is available for the CVSD/PCM transcoder. The Aux- iliary clocks may be configured to keep these peripherals running when the System Clock is slowed down or suspend- ed during low-power modes.

11.7 POWER-ON RESET

The CP3CN17 has specific Power On Reset (POR) timing requirements that must be met to prevent corruption of the on-chip flash program and data memories. This timing se- quence shown in Figure 5. All reset circuits must ensure that this timing sequence is al- ways maintained during power-up and power-down. The design of the power supply also affects how this sequence is implemented. The power-up sequence is: 1. The RESET pin must be held low until both IOVCC and VCC have reached the minimum levels specified in the DC Characteristics section. IOVCC and VCC are al- lowed to reach their nominal levels at the same time which is the best-case scenario. 2. After both of these supply voltage rails have met this condition, then the RESET pin may be driven high. At power-up an internal 14-bit counter is set to 3FFFh and begins counting down to 0 after the crystal oscillator becomes stable. When this counter reaches 0, the on- chip RESET signal is driven high unless the external RESET pin is still being held low. This prevents the CP3CN17 from coming out of reset with an unstable clock source. The power-down sequence is: 1. The RESET pin must be driven low as soon as either the IOVCC or VCC voltage rail reaches the minimum levels specified in the DC Characteristics. 2. The RESET pin must then be held low until the Main Clock is stopped. The Main Clock will decay with the same profile as IOVCC. Meeting the power-down reset conditions ensures that soft- ware will not be executed at voltage levels that may cause incorrect program execution or corruption of the flash mem- ories. This situation must be avoided because the Main Clock decays with the IOVCC supply rather than stopping immediately when IOVCC falls below the minimum specified level.

Figure 5. Power-On Reset Timing

11.7.1 Simple External Reset

Figure 6. Simple External Reset

11.7.2 Manual and SDI External Reset

for a CP3CN17 device operating from an IOVCC at 3.3V. Figure 7. Manual and SDI External Reset plemented, an LM3722 with active pullup may be used.

11.7.3 Fault-Tolerant External Reset

IOVCC supply and an external watchdog timer. Figure 8. Fault-Tolerant External Reset „ Core VCC—the 2.5V power supply rail for the core logic. „ IOVCC—the 2.5–3.3V power supply rail for the I/O logic. LM3710 but without the watchdog timer. —an active-low reset signal to the CP3CN17. to a separate interrupt input. system shutdown functions before being placed into reset.

11.8 CLOCK AND RESET REGISTERS

Table 25 lists the clock and reset registers.

11.8.1 Clock and Reset Control Register (CRCTRL)

source used for the Slow Clock.

12 MHz Main Clock and the PLL as the source

has stabilized. After reset this bit is set.

www.national.com 56 CP3CN17 ACE1 When the Auxiliary Clock Enable bit is set and a stable Main Clock is provided, the Auxiliary Clock 1 prescaler is enabled and generates the first Auxiliary Clock. When the ACE1 bit is clear or the Main Clock is not stable, Auxiliary Clock 1 is stopped. After reset this bit is clear. – Auxiliary Clock 1 is stopped. 1 – Auxiliary Clock 1 is active if the Main Clock is stable. ACE2 When the Auxiliary Clock Enable 2 bit is set and a stable Main Clock is provided, the Aux- iliary Clock 2 prescaler is enabled and gener- ates Auxiliary Clock 2. When the ACE2 bit is clear or the Main Clock is not stable, the Aux- iliary Clock 2 is stopped. Auxiliary Clock 2 is used as the clock input for the CVSD/PCM transcoder. After reset this bit is clear. – Auxiliary Clock 2 is stopped. 1 – Auxiliary Clock 2 is active if the Main Clock is stable. POR Power-On-Reset - The Power-On-Reset bit is set when a power-turn-on condition has been detected. This bit can only be cleared by soft- ware, not set. Writing a 1 to this bit will be ig- nored, and the previous value of the bit will be unchanged. – Software cleared this bit. 1 – Software has not cleared his bit since the last reset.

11.8.2 High Frequency Clock Prescaler Register

(PRSFC) The PRSFC register is a byte -wide read/write register that holds the 4-bit clock divisor used to generate the high-fre- quency clock. In addition, the upper three bits are used to control the operation of the PLL. The register is initialized to 4Fh at reset (except in PROG mode FCDIV The Fast Clock Divis or specifies the divisor used to obtain the high-frequency System Clock from the PLL or Main Clock. The divisor is (FCDIV + 1). MODE The PLL MODE field specifies the operation mode of the on-chip PLL. After reset the MODE bits are initialized to 100b, so the PLL is configured to generate a 48-MHz clock. This register must not be modified when the System Clock is derived from the PLL Clock. The System Clock must be derived from the low-frequency oscillator clock while the MODE field is modified.

11.8.3 Low Frequency Clock Prescaler Register

(PRSSC) The PRSSC register is a byte-wide read/write register that holds the clock divisor used to generate the Slow Clock from the Main Clock. The register is initialized to B6h at reset. SCDIV The Slow Clock Divisor field specifies a divi- sor to be used when generating the Slow Clock from the Main Clock. The Main Clock is divided by a value of (2 × (SCDIV + 1)) to ob- tain the Slow Clock. At reset, the SCDIV reg- ister is initialized to B6h, which generates a Slow Clock rate of 32786.89 Hz. This is about 0.5% faster than a Slow Clock generated from an external 32768 Hz crystal network.

11.8.4 Auxiliary Clock Prescaler Register (PRSAC)

The PRSAC register is a byte- wide read/write register that holds the clock divisor values for prescalers used to gener- ate the two auxiliary clocks from the Main Clock. The regis- ter is initialized to FFh at reset. ACDIV1 The Auxiliary Clock Divisor 1 field specifies the divisor to be used for generating Auxiliary Clock 1 from the Main Clock. The Main Clock is divided by a value of (ACDIV1 + 1). ACDIV2 The Auxiliary Clock Divisor 2 field specifies the divisor to be used for generating Auxiliary Clock 2 from the Main Clock. The Main Clock is divided by a value of (ACDIV2 + 1). 7 6 4 3 0 Res MODE FCDIV MODE2:0 Output Frequency (from 12 MHz input clock)

Description

000 Reserved Reserved

001 Reserved Reserved

010 Reserved Reserved

011 36 MHz 3× Mode 100 48 MHz 4× Mode 101 60 MHz 5× Mode

110 Reserved Reserved

111 Reserved Reserved

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12.0 Power Management

The Power Management Module (PMM) improves the effi- ciency of the CP3CN17 by changing the operating mode (and therefore the power consumption) according to the re- quired level of device activity. The device implements four power modes: „ Active „ Power Save „ Idle „ Halt Table 26 summarizes the differences between power modes: the state of the high-frequency oscillator (on or off), the System Clock source (clo ck used by most modules), and the clock source used by the Timing and Watchdog Module (TWM). The high-frequency oscillator generates the 12-MHz Main Clock, and the low-frequency oscillator gener- ates a 32.768 kHz clock. The Slow Clock can be driven by the 32.768 kHz clock or a scaled version of the Main Clock. The low-frequency oscillator continues to operate in all four modes and power must be provided continuously to the de- vice power supply pins. In Halt mode, however, Slow Clock does not toggle, and as a result, the TWM timer and Watch- dog Module do not operate. In Power Save mode, the high- frequency oscillator can be turned on or off under software control, as long as the low-frequency oscillator is used to drive Slow Clock.

12.1 ACTIVE MODE

In Active mode, the high-frequency oscillator is active and generates the 12-MHz Main Clock. The 32.768 kHz oscilla- tor is active and may be used to generate the Slow Clock. The PLL can be active or inactive, as required. Most on-chip modules are driven by the System Clock. The System Clock can be the PLL Clock after a programmable divider or the 12-MHz Main Clock. The activity of peripheral modules is controlled by their enable bits. Power consumption can be reduced in this mode by selec- tively disabling modules and by executing the WAIT instruc- tion. When the WAIT instruction is executed, the CPU stops executing new instructions until it receives an interrupt sig- nal. After reset, the CP3CN17 is in Active Mode.

12.2 POWER SAVE MODE

In Power Save mode, Slow Clock is used as the System Clock which drives the CPU and most on-chip modules. If Slow Clock is driven by the 32.768 kHz oscillator and no on- chip module currently requires the 12-MHz Main Clock, soft- ware can disable the high-frequency oscillator to further re- duce power consumption. Auxiliary Clocks 1 and 2 can be turned off under software control before switching to a re- duced power mode, or they may remain active as long as Main Clock is also active. If the system does not require the PLL output clock, the PLL can be disabled. Alternatively, the Main Clock and the PLL can also be controlled by the Hard- ware Clock Control function, if enabled. The clock architec- ture is described in Section 11.0. In Power Save mode, some modules are disabled or their operation is restricted. Ot her modules, including the CPU, continue to function normally, but operate at a reduced clock rate. Details of each module’s activity in Power Save mode are described in each module’s descriptions. It is recommended to keep CPU activity at a minimum by ex- ecuting the WAIT instruction to guarantee low power con- sumption in the system.

12.3 IDLE MODE

In Idle mode, the System Clock is disabled and therefore the clock is stopped to most modules of the device. The DHC and DMC bits in the PMMCR register must be set before en- tering this mode to disable the PLL and the high-frequency oscillator. The low-frequency oscillator remains active. The Power Management Module (PMM) and the Timing and Watchdog Module (TWM) continue to operate off the Slow Clock. Idle mode can only be entered from Active mode.

12.4 HALT MODE

In Halt mode, all the device clocks, including the System Clock, Main Clock, and Slow Clock, are disabled. The DHC and DMC bits in the PMMCR register must be set before en- tering this mode. The high-frequency oscillator and PLL are off. The low-frequency oscillator continues to operate, how- ever its circuitry is optimized to guarantee lowest possible power consumption. This mode allows the device to reach the absolute minimum power consumption without losing its state (memory, registers, etc.). Halt mode can only be en- tered from Active mode. Table 26 Power Mode Operating Summary Mode High-Frequency Oscillator System Clock TWM Clock Active On Main Clock Slow Clock Power Save On or Off Slow Clock Slow Clock Idle Off None Slow Clock Halt Off None None

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12.5 CLOCK CONTROL

Altogether, two mechanisms control whether the high-fre- quency oscillator is active, and three mechanisms control whether the PLL is active: „ Disable Bits: The DMC and DHC bits in the PMMCR register may be used to disable the high-frequency oscil- lator and PLL, respectively, in Power Save mode. THese bits must be set in Idle and Halt modes. „ Power Management Mode: Halt mode disables the high-frequency oscillator and PLL. Active Mode enables them. The DMC and DHC bits have no effect in Active or Halt mode. „ PLL Power Down Bit: The PLLPWD bit in the CRCTRL register can be used to disable the PLL in all modes. This bit does not affect the high-frequency oscillator.

12.6 POWER MANAGEMENT REGISTERS

Table 27 lists the power management registers.

12.6.1 Power Management Control Register (PMMCR)

The Power Management Control/Status Register (PMMCR) is a byte-wide, read/write register that controls the operating power mode (Active, Power Save, Idle, or Halt) and enables or disables the high-frequency oscillator and PLL in the Power Save mode. At reset, the non-reserved bits of this register are cleared. The format of the register is shown be- low. PSM If the Power Save Mode bit is clear and the WBPSM bit is clear, writing 1 to the PSM bit causes the device to start the switch to Power Save mode. If the WBPSM bit is set when the PSM bit is written with 1, entry into Power Save mode is delayed until execution of a WAIT instruction. The PSM bit becomes set after the switch to Power Save mode is com- plete. The PSM bit can be cleared by soft- ware, and it can be cleared by hardware when a hardware wake-up event is detected. – Device is not in Power Save mode. 1 – Device is in Power Save mode. IDLE The Idle Mode bit indicates whether the de- vice has entered Idle mode. The WBPSM bit must be set to enter Idle mode. When the IDLE bit is written with 1, the device enters IDLE mode at the execution of the next WAIT instruction. The IDLE bit can be set and cleared by software. It is also cleared by the hardware when a hardware wake-up event is detected. – Device is not in Idle mode. 1 – Device is in Idle mode. HALT The Halt Mode bit indicates whether the de- vice is in Halt mode. Before entering Halt mode, the WBPSM bit must be set. When the HALT bit is written with 1, the device enters the Halt mode at the execution of the next WAIT instruction. When in HALT mode, the PMM stops the System Clock and then turns off the PLL and the high-frequency oscillator. The HALT bit can be set and cleared by soft- ware. The Halt mode is exited by a hardware wake-up event. When this signal is set high, the oscillator is started. After the oscillator has stabilized, the HALT bit is cleared by the hard- ware. – Device is not in Halt mode. 1 – Device is in Halt mode. WBPSM When the Wait Before Power Save Mode bit is clear, a switch from Active mode to Power Save mode only requires setting the PSM bit. When the WBPSM bit is set, a switch from Ac- tive mode to Power Save, Idle, or Halt mode is performed by setting the PSM, IDLE, or HALT bit, respectively, and then executing a WAIT instruction. Also, if t he DMC or DHC bits are set, the high-frequency oscillator and PLL may be disabled only after a WAIT instruction is executed and the Power Save, Idle, or Halt mode is entered. – Mode transitions may occur immediately. 1 – Mode transitions are delayed until the next WAIT instruction is executed. DMC The Disable Main Clock bit may be used to disable the high-frequency oscillator in Power Save mode. In Active mode, the high-frequen- cy oscillator is enabled without regard to the DMC value. The DMC bit is cleared by hard- ware when a hardware wake-up event is de- tected. This bit must be set in Idle and Halt modes. – High-frequency oscillator is not disabled in Power Save mode. 1 – High-frequency oscillator is disabled in Power Save mode. DHC The Disable High-Frequency (PLL) Clock bit and may be used to disable the PLL in Power Save modes. When the DHC bit is clear (and PLLPWD = 0), the PLL is enabled in Power Save mode. If the DHC bit is set, the PLL is disabled in Power Save mode. The DHC bit is cleared by hardware when a hardware wake- Table 27 Power Management Registers Name Address Description PMMCR FF FC60h Power Management Control Register PMMSR FF FC62h Power Management Status Register 7 6 5 4 3 2 1 0 Reserved DHC DMC WBPSM HALT IDLE PSM

– PLL is not disabled in Power Save mode. 1 – PLL is disabled in Power Save mode.

12.6.2 Power Management Status Register (PMMSR)

the register is shown below. not switch to Power Save, Idle, or Halt mode. 1 – Low-frequency oscillator is available. 1 – High-frequency oscillator is available. – PLL is enabled but unstable.

12.7 SWITCHING BETWEEN POWER MODES

Power Management Control/St atus Register (PMMCR). tive mode is usually triggered by a hardware interrupt. events that trigger a transition from one mode to another. Figure 9. Power Mode State Diagram

12.7.1 Active Mode to Power Save Mode

when the transition to the Power Save mode is completed. even before the WAIT instruction is executed.

12.7.2 Entering Idle Mode

www.national.com 60 CP3CN17 tive mode. The DHC and DMC bits must be set when entering Idle mode.

12.7.3 Disabling the Hi gh-Frequency Clock

When the low-frequency oscillator is used to generate the Slow Clock, power consumption can be reduced further in the Power Save mode by disabling the high-frequency oscil- lator. This is accomplished by writing a 1 to the PM- MCR.DHC bit before executing the WAIT instruction that puts the device in the Power Save mode. The high-frequen- cy clock is turned off only after the device enters the Power Save mode. The CPU operates on the low-frequency clock in Power Save mode. It can turn off the high-frequency clock at any time by writing a 1 to the PMMCR.DHC bit. The high-fre- quency oscillator is always enabled in Active mode and al- ways disabled in Halt mode, without regard to the PMMCR.DHC bit setting. Immediately after power-up and entry into Active mode, software must wait for the low-frequency clock to become stable before it can put the device in Power Save mode. It should monitor the PMMSR.OLC bit for this purpose. Once this bit is set, Slow Clock is stable and Power Save mode can be entered.

12.7.4 Entering Halt Mode

Entry into Halt mode is accomplished by writing a 1 to the PMMCR.HALT bit and then executing a WAIT instruction. The PMMCR.WBPSM bit must be set before the WAIT in- struction is executed. Halt m ode can be entered only from Active mode. The DHC and DMC bits must be set when en- tering Idle mode.

12.7.5 Software-Controlled Tr ansition to Active Mode

A transition from Power Save mode to Active mode can be accomplished by either a software command or a hardware wake-up event. The software method is to write a 0 to the PMMCR.PSM bit. The value of the register bit changes only after the transition to the Active mode is completed. If the high-frequency oscillator is disabled for Power Save operation, the oscillator must be enabled and allowed to sta- bilize before the transition to Active mode. To enable the high-frequency oscillator, software writes a 0 to the PM- MCR.DMC bit. Before writin g a 0 to the PMMCR.PSM bit, software must first monitor the PMMSR.OMC bit to deter- mine when the oscillator has stabilized.

12.7.6 Wake-Up Transi tion to Active Mode

A hardware wake-up event switches the device directly from Power Save, Idle, or Halt mode to Active mode. Hardware wake-up events are: „ Non-Maskable Interrupt (NMI) „ Valid wake-up event on a Multi-Input Wake-Up channel When a wake-up event occurs, the on-chip hardware per- forms the following steps: 1. Clears the PMMCR.DMC bit, which enables the high- frequency clock (if it was disabled). 2. Waits for the PMMSR.OMC bit to become set, which in- dicates that the high-frequency clock is operating and is stable. 3. Clears the PMMCR.DHC bit, which enables the PLL. 4. Waits for the PMMSR.OHC bit to become set. 5. Switches the device into Active mode.

12.7.7 Power Mode Switching Protection

The Power Management Module has several mechanisms to protect the device from malfunctions caused by missing or unstable clock signals. The PMMSR.OHC, PMMSR.OM C, and PMMSR.OLC bits indicate the current status of the PLL, high-frequency oscil- lator, and low-frequency oscillator, respectively. Software can check the appropriate bit before switching to a power mode that requires the clock. A set status bit indicates an operating, stable clock. A clear status bit indicates a clock that is disabled, not available, or not yet stable. (Except in the case of the PLL, which has a set status bit when dis- abled.) During a power mode transition, if there is a request to switch to a mode with a clear status bit, the switch is delayed until that bit is set by the hardware. When the system is built without an external crystal network for the low-frequency clock, Main Clock is divided by a pres- caler factor to produce the low-frequency clock. In this situ- ation, Main Clock is disabled only in the Idle and Halt modes, and cannot be disabled for the Power Save mode. Without an external crystal network for the low-frequency clock, the device comes out of Halt or Idle mode and enters Active mode with Main Clock driving Slow Clock. Note: For correct operation in the absence of a low-fre- quency crystal, the X2CKI pin must be tied low (not left float- ing) so that the hardware ca n detect the absence of the crystal.

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13.0 Multi-Input Wake-Up

The Multi-Input Wake-Up Unit (MIWU) monitors its 16 input channels for a software-selectable trigger condition. On de- tection of a trigger condition, the module generates an inter- rupt request and if enabled, a wake-up request. A wake-up request can be used by the power management unit to exit the Halt, Idle, or Power Save mode and return to the active mode. An interrupt request generates an interrupt to the CPU (interrupt IRQ2–IRQ5), which allows an interrupt han- dler to respond to MIWU events. The wake-up event only activates the clocks and CPU, but does not by itself initiate execution of any code. It is the in- terrupt request associated with the MIWU that gets the CPU to start executing code, by jumping to the corresponding in- terrupt handler. Therefore, setting up the MIWU interrupt handler is essential for any wake-up operation. There are four interrupt request s that can be routed to the ICU as shown in Figure 10. Each of the 16 MIWU channels can be programmed to activate one of these four interrupt requests. The MIWU channels are named WUI0 through WUI15, as shown in Table 28. Each channel can be configured to trigger on rising or falling edges, as determined by the setting in the WKEDG register. Each trigger event is latched into the WKPND register. If a trigger event is enabled by its respective bit in the WKENA register, an active wake-up/ interrupt signal is generated. Software can determine which channel has generated the active signal by reading the WKPND register. The MIWU is active at all times, including the Halt mode. All device clocks are stopped in this mode. Therefore, detecting an external trigger condition and the subsequent setting of the pending bit are not synchronous to the System Clock.

13.1 MULTI-INPUT WAKE-UP REGISTERS

Table 29 lists the MIWU unit registers.

13.1.1 Wake-Up Edge Detection Register (WKEDG)

The WKEDG register is a word-wide read/write register that controls the edge sensitivity of the MIWU channels. The WKEDG register is cleared upon reset, which configures all channels to be triggered on rising edges. The register for- mat is shown below. WKED The Wake-Up Edge Detection bits control the edge sensitivity for MIWU channels. The WKED15:0 bits corresp ond to the WUI[15:0] channels, respectively. – Triggered on rising edge (low-to-high transition). – Triggered on falling edge (high-to-low transition). Table 28 MIWU Sources MIWU Channel Source WUI0 TWM-T0OUT WUI1 ACCESS.bus WUI2 CANRX WUI3 MWCS WUI4 CTS WUI5 RXD WUI6 Reserved WUI7 AAI SFS WUI8 Reserved WUI9 PI6 WUI10 PG0 WUI11 PG1 WUI12 PG2 WUI13 PG3 WUI14 PG6 WUI15 PG7 Table 29 Multi-Input Wake-Up Registers Name Address Description WKEDG FF FC80h Wake-Up Edge Detection Register WKENA FF FC82h Wake-Up Enable Register WKIENA FF FC8Ch Wake-Up Interrupt Enable Register WKICTL1 FF FC84h Wake-Up Interrupt Control Register 1 WKICTL2 FF FC86h Wake-Up Interrupt Control Register 2 WKPND FF FC88h Wake-Up Pending Register WKPCL FF FC8Ah Wake-Up Pending Clear Register 15 0 WKED

Figure 10. Multi-Input Wake-Up Module Block Diagram

13.1.2 Wake-Up Enable Register (WKENA)

rupt channels. The register format is shown below. – MIWU channel wake-up events disabled. 1 – MIWU channel wake-up events enabled.

13.1.3 Wake-Up Interrupt Enable Register (WKIENA)

enables and disables interrupts from the MIWU channels. The register format is shown below. whether MIWU channels generate interrupts.

13.1.4 Wake-Up Interrupt Control Register 1

eight channels. The register format is shown below. 00 – Selects MIWU interrupt request 0. 01 – Selects MIWU interrupt request 1. 10 – Selects MIWU interrupt request 2. 11 – Selects MIWU interrupt request 3.

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13.1.5 Wake-Up Interrupt Control Register 2

(WKICTL2) The WKICTL2 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI15 to WUI8. At reset, the WKICTL2 register is cleared, which selects MIWU Interrupt Request 0 for all eight channels. The register format is shown below. WKINTR The Wake-Up Interrupt Request Select fields select which of the four MIWU interrupt re- quests are activated for the corresponding channel. 00 – Selects MIWU interrupt request 0. 01 – Selects MIWU interrupt request 1. 10 – Selects MIWU interrupt request 2. 11 – Selects MIWU interrupt request 3.

13.1.6 Wake-Up Pending Register (WKPND)

The WKPND register is a word-wide read/write register in which the Multi-Input Wake-Up module latches any detect- ed trigger conditions. The CPU can only write a 1 to any bit position in this register. If t he CPU attempts to write a 0, it has no effect on that bit. To clear a bit in this register, the CPU must use the WKPCL register. This implementation prevents a potential hardware-software conflict during a read-modify-write operation on the WKPND register. This register is cleared upon reset. The register format is shown below. WKPD The Wake-Up Pending bits indicate which MIWU channels have been triggered. The WKPD[15:0] bits correspond to the WUI[15:0] channels. Writing 1 to a bit sets it. – Trigger condition did not occur. 1 – Trigger condition occurred.

13.1.7 Wake-Up Pending Clear Register (WKPCL)

The Wake-Up Pending Clear (WKPCL) register is a word- wide write-only register that lets the CPU clear bits in the WKPND register. Writing a 1 to a bit position in the WKPCL register clears the corresponding bit in the WKPND register. Writing a 0 has no effect. Do not modify this register with in- structions that access the regi ster as a read-modify-write operand, such as the bit manipulation instructions. Reading this register location returns undefined data. Therefore, do not use a read-modify-write sequence (such as the SBIT instruction) to set individual bits. Do not attempt to read the register, then perform a logical OR on the regis- ter value. Instead, write the mask directly to the register ad- dress. The register format is shown below. WKCL Writing 1 to a bit clears it. – Writing 0 has no effect. 1 – Writing 1 clears the corresponding bit in the WKPD register.

13.2 PROGRAMMING PROCEDURES

To set up and use the Multi-Input Wake-Up function, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up condition. This same procedure should be used following a reset be- cause the wake-up inputs are le ft floating, resulting in un- known data on the input pins. 1. Clear the WKENA register to disable the MIWU chan- nels. 2. Write the WKEDG register to select the desired type of edge sensitivity (clear for rising edge, set for falling edge). 3. Set all bits in the WKPCL register to clear any pending bits in the WKPND register. 4. Set up the WKICTL1 and WKICTL2 registers to define the interrupt request signal used for each channel. 5. Set the bits in the WKENA register corresponding to the wake-up channels to be activated. To change the edge sensitivity of a wake-up channel, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up/interrupt condition. 1. Clear the WKENA bit associated with the input to be re- programmed. 2. Write the new value to the corresponding bit position in the WKEDG register to reprogram the edge sensitivity of the input. 3. Set the corresponding bit in the WKPCL register to clear the pending bit in the WKPND register. 4. Set the same WKENA bit to re-enable the wake-up function. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKIN TR15 WKIN TR14 WKIN TR13 WKIN TR12 WKIN TR11 WKIN TR10 WKIN TR9 WKIN TR8 15 0 WKPD 15 0 WKCL

14.0 Input/Output Ports

Port C, Port G, Port H, and Port I. I/O pins are shown in Table 2. environments, not by programming the port registers. pull output, weak pull-up inpu t, or high-impedance input. figured to operate in different modes. buffer is a TRI-STATE buffer with weak pull-up capability. to an undefined state when it operates as an input. general-purpose I/O are only enabled when they are read. put and output buffers are described in Section 26.0. Figure 11. I/O Port Pin Logic

14.1 PORT REGISTERS

65 www.national.com CP3CN17 In the descriptions of the ports and port registers, the lower- case letter “x” represents the port designation, either B, C, G, H, or I. For example, “PxDIR register” means any one of the port direction registers: PBDIR, PCDIR, PGDIR, PH- DIR, or PIDIR. All of the port registers are byte-wide read/write registers, except for the port data input registers, which are read-only registers. Each register bit c ontrols the function of the cor- responding port pin. For example, PGDIR.2 (bit 2 of the PGDIR register) controls the direction of port pin PG2. Table 30 Port Registers Name Address Description PBALT FF FB00h Port B Alternate Function Register PBDIR FF FB02h Port B Direction Register PBDIN FF FB04h Port B Data Input Register PBDOUT FF FB06h Port B Data Output Register PBWPU FF FB08h Port B Weak Pull-Up Register PBHDRV FF FB0Ah Port B High Drive Strength Register PBALTS FF FB0Ch Port B Alternate Func- tion Select Register PCALT FF FB10h Port C Alternate Function Register PCDIR FF FB12h Port C Direction Register PCDIN FF FB14h Port C Data Input Register PCDOUT FF FB16h Port C Data Output Register PCWPU FF FB18h Port C Weak Pull-Up Register PCHDRV FF FB1Ah Port C High Drive Strength Register PCALTS FF FB1Ch Port C Alternate Func- tion Select Register PGALT FF FCA0h Port G Alternate Function Register PGDIR FF FCA2h Port G Direction Register PGDIN FF FCA4h Port G Data Input Register PGDOUT FF FCA6h Port G Data Output Register PGWPU FF FCA8h Port G Weak Pull-Up Register PGHDRV FF FCAAh Port G High Drive Strength Register PGALTS FF FCACh Port G Alternate Func- tion Select Register PHALT FF FCC0h Port H Alternate Function Register PHDIR FF FCC2h Port H Direction Register PHDIN FF FCC4h Port H Data Input Register PHDOUT FF FCC6h Port H Data Output Register PHWPU FF FCC8h Port H Weak Pull-Up Register PHHDRV FF FCCAh Port H High Drive Strength Register PHALTS FF FCCCh Port H Alternate Func- tion Select Register PIALT FF FEE0h Port I Alternate Function Register PIDIR FF FEE2h Port I Direction Register PIDIN FF FEE4h Port I Data Input Register PIDOUT FF FEE6h Port I Data Output Register PIWPU FF FEE8h Port I Weak Pull-Up Register PIHDRV FF FEEAh Port I High Drive Strength Register PIALTS FF FEECh Port I Alternate Func- tion Select Register Table 30 Port Registers Name Address Description

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14.1.1 Port Alternate Function Register (PxALT)

The PxALT registers control whether the port pins are used for general-purpose I/O or for their alternate function. Each port pin can be controlled independently. A clear bit in the alternate function register causes the cor- responding pin to be used for general-purpose I/O. In this configuration, the output buffer is controlled by the direction register (PxDIR) and the data output register (PxDOUT). The input buffer is visible to software as the data input reg- ister (PxDIN). A set bit in the alternate function register (PxALT) causes the corresponding pin to be used for its peripheral I/O func- tion. When the alternate func tion is selected, the output buffer data and TRI-STATE configuration are controlled by signals from the on-chip peripheral device. A reset operation clears the port alternate function regis- ters, which initializes the pins as general-purpose I/O ports. This register must be enabled before the corresponding al- ternate function is enabled. PxALT The PxALT bits co ntrol whether the corre- sponding port pins are general-purpose I/O ports or are used for their alternate function by an on-chip peripheral. – General-purpose I/O selected. 1 – Alternate function selected.

14.1.2 Port Direction Register (PxDIR)

The port direction register (PxDIR) determines whether each port pin is used for input or for output. A clear bit in this register causes the corresponding pin to operate as an in- put, which puts the output buffer in the high-impedance state. A set bit causes the pin to operate as an output, which enables the output buffer. A reset operation clears the port direction registers, which initializes the pins as inputs. PxDIR The PxDIR bits select the direction of the cor- responding port pin. – Input. 1 – Output.

14.1.3 Port Data Input Register (PxDIN)

The data input register (PxDIN) is a read-only register that returns the current state on each port pin. The CPU can read this register at any time even when the pin is config- ured as an output. PxDIN The PxDIN bits indicate the state on the cor- responding port pin. – Pin is low. 1 – Pin is high.

14.1.4 Port Data Output Register (PxDOUT)

The data output register (PxDOUT) holds the data to be driven on output port pins. In this configuration, writing to the register changes the output value. Reading the register returns the last value written to the register. A reset operation leaves the register contents unchanged. At power-up, the PxDOUT registers contain unknown val- ues. PxDOUT The PxDOUT bits hold the data to be driven on pins configured as outputs in general-pur- pose I/O mode. 0 – Drive the pin low. 1 – Drive the pin high.

14.1.5 Port Weak Pull-Up Register (PxWPU)

The weak pull-up register (PxWPU) determines whether the port pins have a weak pull-up on the output buffer. The pull- up device, if enabled by the register bit, operates in the gen- eral-purpose I/O mode whenever the port output buffer is disabled. In the alternate function mode, the pull-ups are al- ways disabled. A reset operation clears the port weak pull-up registers, which disables all pull-ups. PxWPU The PxWPU bits control whether the weak pull-up is enabled. – Weak pull-up disabled. 1 – Weak pull-up enabled. 7 0 PxALT 7 0 PxDIR 7 0 PxDIN 7 0 PxDOUT 7 0 PxWPU

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14.1.6 Port High Drive Stre ngth Register (PxHDRV)

The PxHDRV register is a byte-wide, read/write register that controls the slew rate of the corresponding pins. The high drive strength function is enabled when the corresponding bits of the PxHDRV register are set. In both GPIO and alter- nate function modes, the drive strength function is enabled by the PxHDRV registers. At reset, the PxHDRV registers are cleared, making the ports low speed. PxHDRV The PxHDRV bits control whether output pins are driven with slow or fast slew rate. – Slow slew rate. 1 – Fast slew rate.

14.1.7 Port Alternate Func tion Select Register

(PxALTS) The PxALTS register selects which of two alternate func- tions are selected for the port pin. These bits are ignored unless the corresponding PxALT bits are set. Each port pin can be controlled independently. PxALTS The PxALTS bits select among two alternate functions. Table 31 shows the mapping of the PxALTS bits to the alternate functions. Un- used PxALTS bits must be clear.

14.2 OPEN-DRAIN OPERATION

A port pin can be configured to operate as an inverting open-drain output buffer. To do this, the CPU must clear the bit in the data output regist er (PxDOUT) and then use the port direction register (PxDIR) to set the value of the port pin. With the direction register bit set (direction = out), the value zero is forced on the pin. With the direction register bit clear (direction = in), the pin is placed in the TRI-STATE mode. If desired, the internal weak pull-up can be enabled to pull the signal high when the output buffer is in TRI- STATE mode. 7 0 PxHDRV 7 0 PxALTS Table 31 Alternate Function Select Port Pin PxALTS = 0 PxALTS = 1 PG0 RXD WUI10 PG1 TXD WUI11 PG2 RTS WUI12 PG3 CTS WUI13 PG4 CKX TB PG5 SRFS NMI PG6 CANRX WUI14 PG7 CANTX WUI15 PH0 MSK TIO1 PH1 MDIDO TIO2 PH2 MDODI TIO3 PH3 MWCS TIO4 PH4 SCK TIO5 PH5 SFS TIO6 PH6 STD TIO7 PH7 SRD TIO8 PI0 Reserved Reserved PI1 Reserved Reserved PI2 Reserved SRCLK PI3 Reserved Reserved PI4 Reserved Reserved PI5 Reserved Reserved PI6 WUI9 Reserved PI7 TA Reserved

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15.0 CAN Module

The CAN module contains a Full CAN class, CAN (Control- ler Area Network) serial bus interface for low/high speed ap- plications. It supports reception and transmission of extended frames with a 29-bit identifier, standard frames with an 11-bit identifier, applications that require high speed (up to 1 Mbit/s), and a low-speed CAN interface with CAN master capability. Data transfer between the CAN bus and the CPU is handled by 15 message buffers, which can be in- dividually configured as receive or transmit buffers. Every message buffer includes a status/control register which pro- vides information about its current status and capabilities to configure the buffer. All message buffers are able to gener- ate an interrupt on the reception of a valid frame or the suc- cessful transmission of a frame. In addition, an interrupt can be generated on bus errors. An incoming message is only accepted if the message iden- tifier passes one of two acceptance filtering masks. The fil- tering mask can be configured to receive a single message ID for each buffer or a group of IDs for each receive buffer. One of the buffers uses a separate message filtering proce- dure. This provides the capability to establish a BASIC-CAN path. Remote transmission requests can be processed au- tomatically by automatic reconfiguration to a receiver after transmission or by automated transmit scheduling upon re- ception. A priority decoder allows any buffer to have one of 16 transmit priorities including the highest or lowest abso- lute priority, for a total of 240 different transmit priorities. A decided bit time counter (16-bit wide) is provided to sup- port real time applications. The contents of this counter are captured into the message buffer RAM on reception or transmission. The counter can be synchronized through the CAN network. This synchronization feature allows a reset of the counter after the reception or transmission of a mes- sage in buffer 0. The CAN module is a fast CPU bus peripheral which allows single-cycle byte or word read/write access. The CPU con- trols the CAN module by programming the registers in the CAN register block. This incl udes initialization of the CAN baud rate, logic level of the CAN pins, and enable/disable of the CAN module. A set of diagnostic features, such as loop- back, listen only, and error identification, support develop- ment with the CAN module and provide a sophisticated error management tool. The CAN module implements the following features: „ CAN specification 2.0B — Standard data and remote frames — Extended data and remote frames — 0 to 8 bytes data length — Programmable bit rate up to 1 Mbit/s „ 15 message buffers, each configurable as receive or transmit buffers — Message buffers are 16-bit wide dual-port RAM — One buffer may be used as a BASIC-CAN path „ Remote Frame support — Automatic transmission after reception of a Remote Transmission Request (RTR) — Auto receive after transmission of a RTR „ Acceptance filtering — Two filtering capabilities: global acceptance mask and individual buffer identifiers — One of the buffers uses an independent acceptance filtering procedure „ Programmable transmit priority „ Interrupt capability — One interrupt vector for all message buffers (receive/ transmit/error) — Each interrupt source can be enabled/disabled „ 16-bit counter with time st amp capability on successful reception or transmission of a message „ Power Save capabilities with programmable Wake-Up over the CAN bus (alternate source for the Multi-Input Wake-Up module) „ Push-pull capability of the input/output pins „ Diagnostic functions — Error identification — Loopback and listen-only fe atures for test and initial- ization purposes

15.1 FUNCTIONAL DESCRIPTION

As shown in Figure 12, the CAN module consists of three blocks: the CAN core, interface management, and a dual- ported RAM containing the message buffers. There are two dedicated device pins for the CAN interface, CANTX as the transmit output and CANRX as the receive input. The CAN core implements the basic CAN protocol features such as bit-stuffing, CRC calculation/checking, and error management. It controls the transceiver logic and creates error signals according to the bus rules. In addition, it con- verts the data stream from the CPU (parallel data) to the se- rial CAN bus data. The interface management block is divided into the register block and the interface management processor. The regis- ter block provides the CAN interface with control information from the CPU and provides the CPU with status information from the CAN module. Additionally, it generates the interrupt to the CPU. The interface management processor is a state machine ex- ecuting the CPU’s transmission and reception commands and controlling the data transfer between several message buffers and the RX/TX shift registers. 15 message buffers are memory mapped into RAM to trans- mit and receive data through the CAN bus. Eight 16-bit reg- isters belong to each buffer. One of the registers contains control and status information about the message buffer configuration and the current state of the buffer. The other registers are used for the message identifier, a maximum of up to eight data bytes, and the time stamp information. Dur- ing the receive process, the incoming message will be stored in a hidden receive buffer until the message is valid. Then, the buffer contents will be copied into the first mes- sage buffer which accepts the ID of the received message.

Figure 12. CAN Block Diagram

15.2 BASIC CAN CONCEPTS

cepts of the Controller Area Network (CAN). remote frame has been completed. process existing data to perform a new functionality. mation, it can send an overload frame.

and switches to receive mode, as shown in Figure 13. Figure 13. CAN Message Arbitration has canceled the transmit request. message which has the highest internal transmit priority.

15.2.1 CAN Frame Types

i.e., the bus is idle, the bus is kept at the “recessive” level. field, control field, data field (if present), and CRC field. stream for consecutive ones and zeros.

15.2.2 CAN Frame Fields

which starts transmission first. inant” in a data frame and “recessive” in a remote frame.

The DLC field indicates the number of bytes in the data field. It consists of four bits. The data field can be of length zero. cessive” bit is transmitted as the CRC delimiter. bit called the acknowledge delimiter. consists of seven “recessive” bits.

15.2.3 CAN Frame Formats

Figure 14. The structure of an extended data frame is Figure 14. Standard Data Frame Figure 15. Extended Data Frame

Figure 20. Interframe Space

15.2.4 Error Types

slot is not interpreted as a bit error. state change in a message field encoded with bit stuffing. Frame does not constitute a frame error. culation of a received CRC polynomial is non-zero. nant” bit during the ACK frame). Figure 21. Bus States Suspend Transmission is only for error passive nodes.

75 www.national.com CP3CN17 Error Active An error active unit can participate in bus communication and may send an active (“dominant”) error flag. Error Warning The Error Warning state is a sub-state of Error Active to in- dicate a heavily disturbed bus. The CAN module behaves as in Error Active mode. The device is reset into the Error Active mode if the value of both counters is less than 96. Error Passive An error passive unit can participate in bus communication. However, if the unit detects an error it is not allowed to send an active error flag. The unit sends only a passive (“reces- sive”) error flag. A device is error passive when the transmit error counter or the receive error counter is greater than 127. A device becoming error passive will send an active er- ror flag. An error passive device becomes error active again when both transmit and receive error counter are less than 128. Bus Off A unit that is bus off has the output drivers disabled, i.e., it does not participate in any bus activity. A device is bus off when the transmit error counter is greater than 255. A bus off device will become error active again after monitoring 128 × 11 “recessive” bits (including bus idle) on the bus. When the device goes from “bus off“ to “error active“, both error counters will have a value of 0.

15.2.5 Error Counters

There are multiple mechanisms in the CAN protocol to de- tect errors and inhibit erroneous modules from disabling all bus activities. Each CAN module includes two error counters to perform error management. The receive error counter (REC) and the transmit error counter (TEC) are 8- bits wide, located in the 16-bit wide CANEC register. The counters are modified by the CAN module according to the rules listed in Table 32. This table provides an overview of the CAN error conditions and the behavior of the CAN mod- ule; for a detailed description of the error management and fault confinement rules, refer to the CAN Specification 2.0B. If the MSB (bit 7) of the REC is set, the node is error passive and the REC will not increment any further. The Error counters can be read by application software as described under CAN Error Counter Register (CANEC) on page 98. Special error handling for the TEC counter is performed in the following situations: „ A stuff error occurs during arbitration, when a transmitted “recessive” stuff bit is received as a “dominant” bit. This does not lead to an increment of the TEC. „ An ACK-error occurs in an error passive device and no “dominant” bits are detected while sending the passive error flag. This does not lead to an increment of the TEC. „ If only one device is on the bus and this device transmits a message, it will get no acknowledgment. This will be detected as an error and the message will be repeated. When the device goes “error passive” and detects an ac- knowledge error, the TEC counter is not incremented. Therefore the device will not go from ”error passive” to the “bus off” state due to such a condition. Table 32 Error Counter Handling Condition Action Receive Error Counter Conditions A receiver detects a bit error during sending an active error flag. Increment by 8 A receiver detects a “dominant“ bit as the first bit after sending an error flag Increment by 8 After detecting the 14th consecutive “dominant“ bit following an active error flag or overload flag, or after detecting the 8th consecutive “dominant“ bit following a passive error flag. After each sequence of additional 8 consecutive “dominant” bits. Increment by 8 Any other error condition (stuff, frame, CRC, ACK) Increment by 1 A valid reception or transmission Decrement by 1 unless counter is already 0 Transmit Error Counter Conditions A transmitter detects a bit error while sending an active error flag Increment by 8 After detecting the 14th consecutive “dominant“ bit following an active error flag or overload flag or after detecting the 8th consecutive “dominant“ bit following a passive error flag. After each sequence of additional 8 consecutive ‘dominant’ bits. Increment by 8 Any other error condition (stuff, frame, CRC, ACK) Increment by 8 A valid reception or transmission Decrement by 1 unless counter is already 0

15.2.6 Bit Time Logic

Synchronization Jump Width can be configured by software. the various elements of a CAN bit time. positioned at the end of TSEG2. Figure 22. Bit Timing time quanta (tq) is defined by the TSEG2[3:0] bits. within the synchronization segment of each CAN bit time. This segment has the fixed length of one time quantum. either hard or soft synchronization (re-synchronization). frame with the falling edge on the bus while the bus is idle. This is interpreted as the SOF . It restarts the internal logic. chronization jump width (SJW). same effect as hard synchronization.

16 TIme

Figure 23. Resynchronization (e > SJW) Figure 24. Resynchronization (e < -SJW)

15.2.7 Clock Generator

the CKI input clock by the value defined in the CTIM register. the length of one time quantum (tq). a detailed description of the CTIM register. Figure 25. CAN Prescaler

15.3 MESSAGE TRANSFER

bility to establish a BASIC-CAN path. one which matches the received message ID. triggering remote transmission request.

15.4 ACCEPTANCE FILTERING

the mask and the buffers controlled by the masks. Figure 26. Acceptance Filtering into the first buffer with a matching filtering mask. amples illustrate the difference. Figure 27. Acceptance of a Single Identifier Figure 28. Acceptance of a Group of Identifiers “don’t care” bits in the buffer ID). quent messages to be received by this buffer.

buffers use the same acceptance filtering mask). sage. The first incoming frame will be received by buffer 0. Figure 29. Message Storage with BUFFLOCK Enabled

15.5 RECEIVE STRUCTURE

Figure 30. Receive Buffer the different types of frames. ule will not try to match the frame to any subsequent buffer.

swer Remote Frames on page 82.

15.5.1 Receive Timing

Figure 31. Receive Timing immediately after the data bytes are copied into the buffer. resulting update from the CAN module. ing buffer are disabled with the exception of the status field. status is updated by the CAN module as shown in Table 33. states are explained in RX Buffer States on page 81.

15.5.2 Receive Procedure

message buffer for the reception of a CAN message.

1. Configure the receive masks (GMASK or BMASK).
2. Configure the message buffer status as RX_READY .

1 BIT

3 BIT

7 BIT

2 BIT

16 BIT

Figure 32. Buffer R ead Routine (BUFFLOCK Disabled)

1. Read the status (CNSTAT) of the receive buffer. If the

case the procedure described below must be followed.

1. Read the status to determine if a new message has
2. Write RX_READY into CNSTAT.
3. Read the ID/data and object control (DLC/RTR) from
4. Read the buffer status again and check it is not
5. If the buffer status is RX_FULL or RX_OVERRUN, one
6. If status is still RX_READ Y (as set by the CPU at step

2), clear interrupt pending bit and exit. Figure 33. Buffer Read Routine (BUFFLOCK Enabled)

1. Read the ID/data and object control (DLC/RTR) from
2. Write RX_READY into CNSTAT.
3. Clear interrupt pending bit and exit.

15.5.3 RX Buffer States

15.6 TRANSMIT STRUCTURE

the CPU has canceled the transmission request. configured to transmit a remote frame (RTR = 1). write TX_RTR in the status code register again.

15.6.1 Transmit Scheduling

as the transmission of the ne xt frame has not yet started. Figure 34. Data Transmission the TX process is executed again.

15.6.2 Transmit Priority

ber results in the highest transmit priority. with the lower buffer number will have the higher priority.

15.6.3 Transmit Procedure

1. Configure the CNSTAT status field as

mission is aborted by an error.

1. Load buffer identifier and data registers. (For remote
2. Configure the CNSTAT status field to the desired value:

frame to trigger consecutive data frames. transmitted automatically without further CPU activity. Figure 35. Buffer Write Routine

000 H i g h e s t

15.6.4 TX Buffer States

Figure 36. Transmit Buffer States

15.7 INTERRUPTS

rupt process can be initiated from the following sources. ting the flags in the CICLR registers.

15.7.1 Highest Priori ty Interrupt Code

bit in the CAN Interrupt Clear register (CICLR). Figure 37 shows the CAN interrupt management. Figure 37. Interrupt Management bits IRQ and IST3:0 as shown in Table 36.

15.7.2 Usage Hints

terrupt requests according to their priorities.

15.8 TIME STAMP COUNTER

Figure 38. Time Stamp Counter be enabled or disabled using the CGCR.TSTPEN bit.

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15.9 MEMORY ORGANIZATION

The CAN module occupies 144 words in the memory ad- dress space. This space is organized as 15 banks of 8 words per bank (plus one reserved bank) for the message buffers and 14 words (plus 2 reserved words) for control and status.

15.9.1 CPU Access to CAN Registers/Memory

All memory locations occupied by the message buffers are shared by the CPU and CAN module (dual-ported RAM). The CAN module and the CPU normally have single-cycle access to this memory. However, if an access contention oc- curs, the access to the memory is blocked every cycle until the contention is resolved. This internal access arbitration is transparent to software. Both word and byte access to the buffer RAM are allowed. If a buffer is busy during the reception of an object (copy process from the hidden receive buffer) or is scheduled for transmission, the CPU has no write access to the data con- tents of the buffer. Write to the status/control byte and read access to the whole buffer is always enabled. All configuration and status registers can either be access- ed by the CAN module or the CPU only. These registers pro- vide single-cycle word and byte access without any potential wait state. All register descriptions within the next sections have the fol- lowing layout:

15.9.2 Message Buffer Organization

The message buffers are the communication interfaces be- tween CAN and the CPU for the transmission and the re- ception of CAN frames. There are 15 message buffers located at fixed addresses in the RAM location. As shown in Table 37, each buffer consists of two words reserved for the identifiers, 4 words reserved for up to eight CAN data bytes, one word reserved for the time stamp, and one word for data length code, transmit priority code, and the buffer status codes. 15 0 Bit/Field Names Reset Value CPU Access (R = read only, W = write only, R/W = read/write) Table 37 Message Buffer Map Address Buffer Register 1 5 1 4 1 3 1 2 1 1 1 0 98765 4 3210 0E F0XEh ID1 XI[28:18]/ID[10:0] SRR /RTR IDE XI[17:15] 0E F0XCh ID0 XI[14:0] RTR 0E F0XAh DATA0 Data1[7:0] Data2[7:0] 0E F0X8h DATA1 Data3[7:0] Data4[7:0] 0E F0X6h DATA2 Data5[7:0] Data6[7:0] 0E F0X4h DATA3 Data7[7:0] Data8[7:0] 0E F0X2h TSTP TSTP[15:0] 0E F0X0h CNSTAT DLC Reserved PRI ST

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15.10 CAN CONTROLLER REGISTERS

Table 38 lists the CAN module registers.

15.10.1 Buffer Status/Control Register (CNSTAT)

The buffer status (ST), the buffer priority (PRI), and the data length code (DLC) are controlled by manipulating the con- tents of the Buffer Status/Control Register (CNSTAT). The CPU and CAN module have access to this register. ST The Buffer Status field contains the status in- formation of the buffer as shown in Table 39. This field can be modified by the CAN module. The ST0 bits acts as a buffer busy indication. When the BUSY bit is set, any write access to the buffer is disabled with the exception of the lower byte of the CNSTAT register. The CAN module sets this bit if the buffer data is cur- rently copied from the hidden buffer or if a message is scheduled for transmission or is currently transmitting. The CAN module al- ways clears this bit on a status update. Table 38 CAN Controller Registers Name Address Description CNSTAT See Table 37. CAN Buffer Status/ Control Register CGCR 0E F100h CAN Global Configuration Register CTIM 0E F102h CAN Timing Register GMSKX 0E F104h Global Mask Register GMSKB 0E F106h Global Mask Register BMSKX 0E F108h Basic Mask Register BMSKB 0E F10Ah Basic Mask Register CIEN 0E F10Ch CAN Interrupt Enable Register CIPND 0E F10Eh CAN Interrupt Pending Register CICLR 0E F110h CAN Interrupt Clear Register CICEN 0E F112h CAN Interrupt Code Enable Register CSTPND 0E F114h CAN Status Pending Register CANEC 0E F116h CAN Error Counter Register CEDIAG 0E F118h CAN Error Diagnostic Register CTMR 0E F11Ah CAN Timer Register 15 12 11 8 7 4 3 0 DLC Reserved PRI ST R/W

www.national.com 88 CP3CN17 Table 39 Buffer Status Sectio n of the CNSTAT Register ST3 (DIR) ST2 ST1 ST0 (BUSY) Buffer Status 00 0 0 R X _ N O T _ A C T I V E 00 0 1 Reserved for RX_BUSY . (This condition indicates that soft- ware wrote RX_NOT_ACTIVE to a buffer when the data copy process is still active.) 00 1 0 R X _ R E A D Y 00 1 1 RX_BUSY0 (Indicates data is being copied for the first time RX_READY → RX_BUSY0.) 0 1 0 0 RX_FULL 01 0 1 RX_BUSY1 (Indicates data is being copied for the second time RX_FULL → RX_BUSY1.) 0 1 1 0 RX_OVERRUN 01 1 1 RX_BUSY2 (Indicates data is being copied for the third or subsequent times RX_OVERRUN → RX_BUSY2.) 1 0 0 0 TX_NOT_ACTIVE 10 0 1 Reserved for TX_BUSY . (This state indicates that software wrote TX_NOT_ACTIVE to a transmit buffer which is sched- uled for transmission or is currently transmitting.) 11 0 0 T X _ O N C E 11 0 1 TX_BUSY0 (Indicates that a buffer is scheduled for trans- mission or is actively transmitting; it can be due to one of two cases: a message is pending for transmission or is cur- rently transmitting, or an automated answer is pending for transmission or is currently transmitting.) 1 0 1 0 TX_RTR (Automatic response to a remote frame.) 1 0 1 1 Reserved for TX_BUSY1. (This condition does not occur.) 1 1 1 0 TX_ONCE_RTR (Changes to TX_RTR after transmission.) 11 1 1 TX_BUSY2 (Indicates that a buffer is scheduled for trans- mission or is actively transmitting; it can be due to one of two cases: a message is pending for transmission or is cur- rently transmitting, or an automated answer is pending for transmission or is currently transmitting.)

89 www.national.com CP3CN17 PRI The Transmit Priority Code field holds the software-defined transmit priority code for the message buffer. DLC The Data Length Code field determines the number of data bytes within a received/trans- mitted frame. For transmission, these bits need to be set according to the number of data bytes to be transmitted. For reception, these bits indicate the number of valid re- ceived data bytes available in the message buffer. Table 40 shows the possible bit combi- nations for DLC3:0 for data lengths from 0 to 8 bytes. Note: The maximum number of data bytes received/trans- mitted is 8, even if the DLC field is set to a value greater than 8. Therefore, if the data length code is greater or equal to eight bytes, the DLC field is ignored.

15.10.2 Storage of Standard Messages

During the processing of st andard frames, the Extended- Identifier (IDE) bit is clear. T he ID1[3:0] and ID0[15:0] bits are “don’t care” bits. A standard frame with eight data bytes is shown in Table 41. IDE The Identifier Extension bit determines wheth- er the message is a standard frame or an ex- tended frame. 0 – Message is a standard frame using 11 identifier bits. 1 – Message is an extended frame. RTR The Remote Transmission Request bit indi- cates whether the message is a data frame or a remote frame. 0 – Message is a data frame. 1 – Message is a remote frame. ID The ID field is used for the 11 standard frame identifier bits. Table 40 Data Length Coding DLC Number of Data Bytes 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 Table 41 Standard Frame with 8 Data Bytes Address Buffer Register 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0E F0XEh ID1 ID[10:0] RTR IDE Don’t Care 0E F0XCh ID0 Don’t Care 0E F0XAh DATA0 Data1[7:0] Data2[7:0] 0E F0X8h DATA1 Data3[7:0] Data4[7:0] 0E F0X6h DATA2 Data5[7:0] Data6[7:0] 0E F0X4h DATA3 Data7[7:0] Data8[7:0] 0E F0X2h TSTP TSTP[15:0] 0E F0X0h CNSTAT DLC Reserved PRI ST

15.10.3 Storage of Messages with Less Than 8 Data

in these bytes will be overwritten with invalid data.

15.10.4 Storage of Extended Messages

Table 42. The SRR bit is at the bit position of the RTR bit for standard frame and needs to be transmitted as 1. received as monitored on the CAN bus. 1 – Message is an extended frame. 0 – Message is a data frame. 1 – Message is a remote frame.

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15.10.5 Storage of Remote Messages

During remote frame transfer, the buffer registers DATA0– DATA3 are “don’t cares”. If a remote frame is transmitted, the contents of these registers are ignored. If a remote frame is received, the conten ts of these registers will be overwritten with invalid data. The structure of a message buffer set up for a remote frame with extended identifier is shown in Table 43. SRR The Substitute Remote Request bit replaces the RTR bit used in standard frames at this bit position. The SRR bit needs to be set by soft- ware. IDE The Identifier Extension bit determines wheth- er the message is a standard frame or an ex- tended frame. 0 – Message is a standard frame using 11 identifier bits. 1 – Message is an extended frame. RTR The Remote Transmission Request bit indi- cates whether the message is a data frame or a remote frame. 0 – Message is a data frame. 1 – Message is a remote frame. ID The ID field is used to build the 29-bit identifier of an extended frame. The ID[28:18] field is used for the 11 standard frame identifier bits. Table 43 Extended Remote Frame Address Buffer Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0E F0XEh ID1 ID[28:18] SRR IDE ID17:15] 0E F0XCh ID0 ID[14:0] RTR 0E F0XAh DATA0 Don’t Care 0E F0X8h DATA1 0E F0X6h DATA2 0E F0X4h DATA3 0E F0X2h TSTP TSTP 0E F0X0h CNSTAT DLC Reserved PRI ST

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15.10.6 CAN Global Config uration Register (CGCR)

The CAN Global Configuration Register (CGCR) is a 16-bit wide register used to: „ Enable/disable the CAN module. „ Configure the BUFFLOCK function for the message buff- er 0..14. „ Enable/disable the time stamp synchronization. „ Set the logic levels of the CAN Input/Output pins, CAN- RX and CANTX. „ Choose the data storage direction (DDIR). „ Select the error interrupt type (EIT). „ Enable/disable diagnostic functions. CANEN The CAN Enable bit enables/disables the CAN module. When the CAN module is dis- abled, all internal states and the TEC and REC counter registers are cleared. In addition the CAN module clock is disabled. All CAN module control register s and the contents of the object memory are left unchanged. Soft- ware must make sure that no message is pending for transmission before the CAN module is disabled. 0 – CAN module is disabled. 1 – CAN module is enabled. CTX The Control Transmit bit configures the logic level of the CAN transmit pin CANTX. 0 – Dominant state is 0; recessive state is 1. 1 – Dominant state is 1; recessive state is 0. CRX The Control Receive bit configures the logic level of the CAN receive pin CANRX. 0 – Dominant state is 0; recessive state is 1. 1 – Dominant state is 1; recessive state is 0. BUFFLOCK The Buffer Lock bit configures the buffer lock function. If this feature is enabled, a buffer will be locked upon a successful frame reception. The buffer will be unlocked again by writing RX_READY in the buffer status register, i.e., after reading data. 0 – Lock function is disabled for all buffers. 1 – Lock function is enabled for all buffers. TSTPEN The Time Sync Enable bit enables or disables the time stamp synchronization function of the CAN module. 0 – Time synchronization disabled. The Time Stamp counter value is not reset upon re- ception or transmission of a message to/ from buffer 0. 1 – Time synchronization enabled. The Time Stamp counter value is reset upon recep- tion or transmission of a message to/from buffer 0. DDIR The Data Direction bit selects the direction the data bytes are transmitted and received. The CAN module transmits and receives the CAN Data1 byte first and the Data8 byte last (Data1, Data2,...,Data7, Data8). If the DDIR bit is clear, the data contents of a received message is stored with the first byte at the highest data address and the last data at the lowest data address (see Figure 39). The same applies for transmitted data. 0 – First byte at the highest address, subse- quent bytes at lower addresses. 1 – First byte at the lowest address, subse- quent bytes at higher addresses. 7 6 5 4 3 2 1 0 IGNACK LO DDIR TST PEN BUFF LOCK CRX CTX CANEN R/W 15 12 11 10 9 8 Reserved EIT DIAGEN INTERNAL LOOPBACK R/W

www.national.com 94 CP3CN17 INTERNAL If the Internal function is enabled, the CANTX and CANRX pins of the CAN module are inter- nally connected to each other. This feature can be used in conj unction with the LOOP- BACK mode. This means that the CAN mod- ule can receive its own sent messages without connecting an external transceiver chip to the CANTX and CANRX pins; it allows software to run real stand-alone tests without any peripheral devices. 0 – Normal mode. 1 – Internal mode. DIAGEN The Diagnostic Enable bit globally enables or disables the special diagnostic features of the CAN module. This includes the following func- tions:  LO (Listen Only).  IGNACK (Ignore Acknowledge).  LOOPBACK (Loopback).  INTERNAL (Internal Loopback).  Write access to hidden receive buffer. 0 – Normal mode. 1 – Diagnostic features enabled. EIT The Error Interrupt Type bit configures when the Error Interrupt Pending Bit (CIPND.EIP- ND) is set and an error interrupt is generated if enabled by the Error Interrupt Enable (CIEN.EIEN). 0 – The EIPND bit is set on every error on the CAN bus. 1 – The EIPND bit is set only if the error state (CSTPND.NS) changes as a result of in- crementing either the receive or transmit error counter.

15.10.7 CAN Timing Register (CTIM)

The Can Timing Register (CTIM) defines the configuration of the Bit Time Logic (BTL). PSC The Prescaler Configuration field specifies the CAN prescaler. The settings are shown in Table 44 SJW The Synchronization Jump Width field speci- fies the Synchronizatio n Jump Width, which can be programmed between 1 and 4 time quanta (see Table 45). Note: The settings of SJW must be configured to be small- er or equal to TSEG1 and TSEG2 15 9 8 7 6 3 2 0 PSC SJW TSEG1 TSEG2 R/W Table 44 CAN Prescaler Settings PSC6:0 Prescaler 000000 2 000001 3 000010 4 000011 5 000100 6 1111101 127 1111110 128 1111111 128 Table 45 SJW Settings SJW Synchronization Jump Width (SJW) 00 1 time quantum 01 2 time quanta 10 3 time quanta 11 4 time quanta

95 www.national.com CP3CN17 TSEG1 The Time Segment 1 field configures the length of the Time Segment 1 (TSEG1). It is not recommended to configure the time seg- ment 1 to be smaller than 2 time quanta. (see Table 46). TSEG2 The Time Segment 2 field specifies the num- ber of time quanta (tq) for phase segment 2 (see Table 47).

15.10.8 Global Mask Register (GMSKB/GMSKX)

The GMSKB and GMSKX registers allow software to global- ly mask, or “don’t care” the incoming extended/standard identifier bits, RTR/XRTR and IDE. Throughout this docu- ment, the GMSKB and GMSKX 16-bit registers are refer- enced as a 32-bit register GMSK. The following are the bits for the GMSKB register. The following are the bits for the GMSKX register. For all GMSKB and GMSKX regist er bits, the following ap- plies: 0 – The incoming identifier bit must match the correspond- ing bit in the message buffer identifier register. 1 – Accept 1 or 0 (“don’t care”) in the incoming ID bit inde- pendent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the mes- sage buffer will be overwritten by the incoming identifier bits. When an extended frame is received from the CAN bus, all GMSK bits GM[28:0], IDE, RTR, and XRTR are used to mask the incoming message. In this case, the RTR bit in the GMSK register corresponds to the SRR bit in the message. The XRTR bit in the GMSK register corresponds to the RTR bit in the message. During the reception of standard frames only the GMSK bits GM[28:18], RTR, and IDE are used. In this case, the GM[28:18] bits in the GMSK register correspond to the ID[10:0] bits in the message. Table 46 Time Segment 1 Settings TSEG1[3:0] Length of Time (TSEG1)

0000 Not recommended

Table 47 Time Segment 2 Settings TSEG2 Length of TSEG2 000 1 time quantum 001 2 time quanta 010 3 time quanta 011 4 time quanta 100 5 time quanta 101 6 time quanta 110 7 time quanta 111 8 time quanta 15 5 4 3 2 0 GM[28:18] RTR IDE GM[17:15] R/W 15 1 0 GM[14:0] XRTR R/W Global Mask GM[28:18] RTR IDE GM[17:0] XRTR Standard Frame ID[10:0] RTR IDE Unused Extended Frame ID[28:18] SRR IDE ID[17:0] RTR

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15.10.9 Basic Mask Regi ster (BMSKB/BMSKX)

The BMSKB and BMSKX registers allow masking the buffer 14, or “don’t care” the incoming extended/standard identifier bits, RTR/XRTR, and IDE. Throughout this document, the two 16-bit registers BMSKB and BMSKX are referenced to as a 32-bit register BMSK. The following are the bits for the BMSKB register. The following are the bits for the BMSKX register. For all BMSKB and BMSKX regist er bits th e following ap- plies: 0 – The incoming identifier bit must match the correspond- ing bit in the message buffer identifier register. 1 – Accept 1 or 0 (“don’t care”) in the incoming ID bit inde- pendent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the mes- sage buffer will be overwritten by the incoming identifier bits. When an extended frame is received from the CAN bus, all BMSK bits BM[28:0], IDE, RTR, and XRTR are used to mask the incoming message. In this case, the RTR bit in the BMSK register corresponds to the SRR bit in the message. The XRTR bit in the BMSK register corresponds to the RTR bit in the message. During the reception of standard frames, only the BMSK bits BM[28:18], RTR, and IDE are used. In this case, the BM[28:18] bits in the BMSK register correspond to the ID[10:0] bits in the message.

15.10.10 CAN Interrupt Enable Register (CIEN)

The CAN Interrupt Enable (CIEN) register enables the transmit/receive interrupts of the message buffers 0 through 14 as well as the CAN Error Interrupt. EIEN The Error Interrupt Enable bit allows the CAN module to interrupt the CPU if any kind of CAN receive/transmit errors are detected. This causes any error status change in the er- ror counter registers REC/TEC is able to gen- erate an error interrupt. 0 – The error interrupt is disabled and no er- ror interrupt will be generated. 1 – The error interrupt is enabled and a change in REC/TEC will cause an inter- rupt to be generated. IEN The Buffer Interrupt Enable bits allow software to enable/disable the interrupt source for the corresponding message buffer. For example, IEN14 controls interrupts from buffer14, and IEN0 controls interrupts from buffer0. 0 – Buffer as interrupt source disabled. 1 – Buffer as interrupt source enabled.

15.10.11 CAN Interrupt Pending Register (CIPND)

The CIPND register indicate s any CAN Receive/Transmit Interrupt Requests caused by the message buffers 0..14 and CAN error occurrences. EIPND The Error Interrupt Pending field indicates the status change of TEC/ REC and will execute an error interrupt if the EIEN bit is set. Soft- ware has the responsibility to clear the EIPND bit using the CICLR register. 0 – CAN status is not changed. 1 – CAN status is changed. IPND The Buffer Interrupt Pending bits are set by the CAN module following a successful trans- mission or reception of a message to or from the corresponding message buffer. For exam- ple, IPND14 corresponds to buffer14, and IPND0 corresponds to buffer0. 0 – No interrupt pending for the correspond- ing message buffer. 1 – Message buffer has generated an inter- rupt. 15 5 4 3 2 0 BM[28:18] RTR IDE BM[17:15] R/W 15 1 0 BM[14:0] XRTR R/W Basic Mask BM[28:18] RTR IDE BM[17:0] XRTR Standard Frame ID[10:0] RTR IDE Unused Extended Frame ID[28:18] SRR IDE ID[17:0] RTR 15 14 0 EIEN IEN R/W 15 14 0 EIPND IPND R

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15.10.12 CAN Interrupt Clear Register (CICLR)

The CICLR register bits individually clear CAN interrupt pending flags caused by the message buffers and from the Error Management Logic. Do not modify this register with in- structions that access the regi ster as a read-modify-write operand, such as the bit manipulation instructions. EICLR The Error Interrupt Clear bit is used to clear the EIPND bit. 0 – The EIPND bit is unaffected by writing 0. 1 – The EIPND bit is cleared by writing 1. ICLR The Buffer Interrupt Clear bits are used to clear the IPND bits. 0 – The corresponding IPND bit is unaffected by writing 0. 0 – The corresponding IPND bit is cleared by writing 1.

15.10.13 CAN Interrupt Code Enable Register (CICEN)

The CICEN register controls whether the interrupt pending flag in the CIPND register is translated into the Interrupt Code field of the CSTPND register. All interrupt requests, CAN error, and message buffer interrupts can be enabled/ disabled separately for the interrupt code indication field. EICEN The Error Interrupt Code Enable bit controls encoding for error interrupts. 0 – Error interrupt pending is not indicated in the interrupt code. 1 – Error interrupt pending is indicated in the interrupt code. ICEN The Buffer Interrupt Code Enable bits control encoding for message buffer interrupts. 0 – Message buffer interrupt pending is not indicated in the interrupt code. 1 – Message buffer interrupt pending is indi- cated in the interrupt code.

15.10.14 CAN Status Pending Register (CSTPND)

The CSTPND register holds th e status of the CAN Node and the Interrupt Code. NS The CAN Node Status field indicates the sta- tus of the CAN node as shown in Table 48. IRQ/IST The IRQ bit and IST field indicate the interrupt source of the highest priority interrupt current- ly pending and enabled in the CICEN register. Table 49 shows the several interrupt codes when the encoding for all interrupt sources is enabled (CICEN = FFFFh). 15 14 0 EICLR ICLR W 15 14 0 EICEN ICEN R/W 15 8 7 5 4 3 0 Reserved NS IRQ IST R Table 48 CAN Node Status NS Node Status

000 Not Active

010 Error Active

011 Error Warning Level

Table 49 Highest Priority Interrupt Code IRQ IST3:0 CAN Interrupt Request 0 0000 No interrupt request 1 0000 Error interrupt 10 0 0 1 B u f f e r 0 10 0 1 0 B u f f e r 1 10 0 1 1 B u f f e r 2 10 1 0 0 B u f f e r 3 10 1 0 1 B u f f e r 4 10 1 1 0 B u f f e r 5 10 1 1 1 B u f f e r 6 11 0 0 0 B u f f e r 7 11 0 0 1 B u f f e r 8 11 0 1 0 B u f f e r 9 1 1011 Buffer 10 1 1100 Buffer 11 1 1101 Buffer 12 1 1110 Buffer 13 1 1111 Buffer 14

15.10.15 CAN Error Counter Register (CANEC)

Error Counter and the CAN Transmit Error Counter. the value of the receive error counter. the value of the transmit error counter.

15.10.16 CAN Error Diagnostic Register (CEDIAG)

ister, and all bits are cleared on reset. frame field in which the last error occurred. Figure 41. EBID Example 1110b and the EBID field shows 111001b. This means the faulty field was the data field. ter at the time the error occurred.

0000 ERROR

0001 ERROR DEL

0010 ERROR ECHO

0011 BUS IDLE

0100 ACK

0101 EOF

0110 INTERMISSION

0111 SUSPEND

1000 SOF

1001 ARBITRATION

1010 IDE

1011 EXTENDED

1100 R1/R0

1101 DLC

1110 DATA

1111 CRC

ACK and during an active error flag.

15.10.17 CAN Timer Register (CTMR)

Stamp Counter as described in Section 15.8. cleared on a message transfer of the message buffer 0.

15.11 SYSTEM START-UP AND MULTI-INPUT

„ Configure every buffer to its function as receive/transmit. tion Register (CGCR)” on page 92. that no transmission is still pending. can be disabled before entering the reduced-power mode.

15.11.1 External Connection

the functionality described in Table 51. bal Configuration Register (CGCR)” on page 92).

15.11.2 Transceiver Connection

Figure 42. External Transceiver

15.11.3 Timing Requirements

Table 52. These requirements may lead to some restrictions

5 REF

4 RX1 TX

www.national.com 100 CP3CN17 The critical path derives from receiving a remote frame, which triggers the transmission of one or more data frames. There are a minimum of four bit times in-between two con- secutive frames. These bit times start at the validation point of received frame (reception of 6th EOF bit) and end at the earliest possible transmission start of the next frame, which is after the third intermission bit at 100% burst bus load. These four bit times have to be set in perspective with the timing requirements of the CAN module. The minimum duration of the four CAN bit times is deter- mined by the following Bit Time Logic settings: PSC = PSCmin = 2 TSEG1 = TSEG1min = 2 TSEG2 = TSEG2min = 1 Bit time = Sync + Time Segment 1 + Time Segment 2 = (4 tq × PSC) clock cycles = (4 tq × 2) clock cycles = 8 clock cycles For these minimum BTL settings, four CAN bit times take 32 clock cycles. The following is an example that assumes typical case: „ Minimum BTL settings „ Reception and copy of a remote frame „ Update of one buffer from TX_RTR „ Schedule of one buffer from transmit As outlined in Table 52, the copy process, update, and scheduling the next transmission gives a total of 17 + 3 + 2 = 22 clock cycles. Therefore under these conditions there is no timing restriction. The following example assumes the worst case: „ Minimum BTL settings „ Reception and copy of a remote frame „ Update of the 14 remaining buffers from TX_RTR „ Schedule of one buffer for transmit All these actions in total require 17 + (14 × 3) + 2 = 61 clock cycles to be executed by the CAN module. This leads to the limitation of the Bit Time Logic of 61 / 4 = 15.25 clock cycles per CAN bit as a minimum, resulting in the minimum clock frequencies listed below. (The frequency depends on the desired baud rate and assumes the worst case scenario can occur in the application.) Table 53 gives examples for the minimum clock frequency in order to ensure proper functionality at various CAN bus speeds.

15.11.4 Bit Time Logic Calculation Examples

The calculation of the CAN bus clocks using CKI = 16 MHz is shown in the following examples. The desired baud rate for both examples is 1 Mbit/s. Example 1 TSEG1 = TSEG1[3:0] + 1 = 3 + 1 = 4 TSEG2 = TSEG2[2:0] + 1 = 2 + 1 = 3 SJW = TSEG2 = 3 „ Sample point positioned at 62.5% of bit time „ Bit time = 125 ns × (1 + 4 + 3 ± 3) = (1 ± 0.375) µs „ Bus Clock = 16 MHz / (2 × (1 + 4 + 3)) = 1 Mbit/s (nomi- nal) Example 2 TSEG1 = TSEG1[3:0] + 1 = 1 + 1 = 2 TSEG2 = TSEG2[2:0] + 1 = 0 + 1 = 1 SJW = TSEG2 = 1 „ Sample point positioned at 75% of bit time „ Bit time = 250 ns × (1 + 2 + 1 ± 1) = (1 ± 0.25) µs „ Bus Clock = 16 MHz / (2 × (1 + 4 + 3)) = 1Mbit/s (nominal)

15.11.5 Acceptance Filter Considerations

The CAN module provides two acceptance filter masks GMSK and BMSK, as described in “Acceptance Filtering” on page 78, “Global Mask Register (GMSKB/GMSKX)” on page 95, and “Basic Mask Register (BMSKB/BMSKX)” on page 96. These masks allow filtering of up to 32 bits of the message object, which includes the standard identifier, the extended identifier, and the frame control bits RTR, SRR, and IDE.

15.11.6 Remote Frames

Remote frames can be automatically processed by the CAN module. However, to fully enable this feature, the RTR/ XRTR bits (for both standard and extended frames) within the BMSK and/or GMSK register need to be set to “don’t care”. This is because a remote frame with the RTR bit set should trigger the transmission of a data frame with the RTR bit clear and therefore the ID bits of the received message need to pass through the ac ceptance filter. The same ap- plies to transmitting remote frames and switching to receive the corresponding data frames. Table 52 CAN Module Internal Timing Task Cycle Count Occurrence/ Frame Copy hidden buffer to receive message buffer 17 0–1 Update status from TX_RTR to TX_ONCE_RTR 30 – 1 5 Schedule a message for transmission 2 0–1 Table 53 Minimum Clock Frequency Requirements Baud Rate Minimum Clock Frequency 1 Mbit/sec 15.25 MHz 500 kbit/sec 7.625 MHz 250 kbit/sec 3.81 MHz

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15.12 USAGE HINT

Under certain conditions, the CAN module receives a frame sent by itself, even though the loopback feature is disabled. Two conditions must be true to cause this malfunction: „ A transmit buffer and at least one receive buffer are con- figured with the same identifier. Assume this identifier is called ID_RX_TX. With regard to the receive buffer, this means that the buffer identifier and the corresponding fil- ter masks are set up in a way that the buffer is able to re- ceive frames with the identifier ID_RX_TX. „ The following sequence of events occurs: 1. A message with the identifier ID_RX_TX from an- other CAN node is received into the receive buffer. 2. A message with the identifier ID_RX_TX is sent by the CAN module immediately after the reception took place. When these conditions occur, the frame sent by the CAN module will be copied into the next receive buffer available for the identifier ID_RX_TX. If a frame with an identifier different to ID_RX_TX is sent or received in between events 1 and 2, the problem does not occur.

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16.0 Advanced Audio Interface

The Advanced Audio Interface (AAI) provides a serial syn- chronous, full duplex interface to codecs and similar serial devices. The transmit and receive paths may operate asyn- chronously with respect to each other. Each path uses a 3- wire interface consisting of a bit clock, a frame synchroniza- tion signal, and a data signal. The CPU interface can be either interrupt-driven or DMA. If the interface is configured for interrupt-driven I/O, data is buffered in the receive and transmit FIFOs. If the interface is configured for DMA, the data is buffered in registers. The AAI is functionally similar to a Motorola TM Synchronous Serial Interface (SSI). Com pared to a standard SSI imple- mentation, the AAI interface does not support the so-called “On-demand Mode”. It also does not allow gating of the shift clocks, so the receive and transmit shift clocks are always active while the AAI is enabled. The AAI also does not sup- port 12- and 24-bit data word length or more than 4 slots (words) per frame. The reduction of supported modes is ac- ceptable, because the main purpose of the AAI is to connect to audio codecs, rather than to other processors (DSPs). The implementation of a FIFO as a 16-word receive and transmit buffer is an additional feature, which simplifies communication and reduces interrupt load. Independent DMA is provided for each of the four supported audio chan- nels (slots). The AAI also provides special features and op- erating modes to simplify gain control in an external codec and to connect to an ISDN controller through an IOM-2 compatible interface.

16.1 AUDIO INTERFACE SIGNALS

16.1.1 Serial Transmit Data (STD)

The STD pin is used to transmit data from the serial transmit shift register (ATSR). The STD pin is an output when data is being transmitted and is in high-impedance mode when no data is being transmitted. The data on the STD pin changes on the positive edge of the transmit shift clock (SCK). The STD pin goes into high-impedance mode on the negative edge of SCK of the last bit of the data word to be transmit- ted, assuming no other data word follows immediately. If an- other data word follows immediately, the STD pin will not change to the high-impedance mode, instead remaining ac- tive. The data is shifted out with the most significant bit (MSB) first.

16.1.2 Serial Transmit Clock (SCK)

The SCK pin is a bidirectional signal that provides the serial shift clock. In asynchronous mode, this clock is used only by the transmitter to shift out data on the positive edge. The se- rial shift clock may be generated internally or it may be pro- vided by an external clock source. In synchronous mode, the SCK pin is used by both the transmitter and the receiver. Data is shifted out from th e STD pin on the positive edge, and data is sampled on the SRD pin on the negative edge of SCK.

16.1.3 Serial Transmit Frame Sync (SFS)

The SFS pin is a bidirectional signal which provides frame synchronization. In asynchronous mode, this signal is used as frame sync only by the transmitter. In synchronous mode, this signal is used as frame sync by both the transmitter and receiver. The frame sync signal may be generated internally, or it may be provided by an external source.

16.1.4 Serial Receive Data (SRD)

The SRD pin is used as an input when data is shifted into the Audio Receive Shift Register (ARSR). In asynchronous mode, data on the SRD pin is sampled on the negative edge of the serial rece ive shift clock (SRCLK). In synchronous mode, data on the SRD pin is sampled on the negative edge of the serial shift clock (SCK). The data is shifted into ARSR with the most significant bit (MSB) first.

16.1.5 Serial Receive Clock (SRCLK)

The SRCLK pin is a bidirectional signal that provides the re- ceive serial shift clock in asynchronous mode. In this mode, data is sampled on the negative edge of SRCLK. The SR- CLK signal may be generated internally or it may be provid- ed by an external clock source. In synchronous mode, the SCK pin is used as shift clock for both the receiver and transmitter, so the SRCLK pin is available for use as a gen- eral-purpose port pin or an auxiliary frame sync signal to ac- cess multiple slave devices (e .g. codecs) within a network (see Network mode).

16.1.6 Serial Receive Frame Sync (SRFS)

The SRFS pin is a bidirectional signal that provides frame synchronization for the receiver in asynchronous mode. The frame sync signal may be generated internally, or it may be provided by an external source. In synchronous mode, the SFS signal is used as the frame sync signal for both the transmitter and receiver, so the SRFS pin is available for use as a general-purpose port pin or an auxiliary frame sync sig- nal to access multiple slave devices (e.g. codecs) within a network (see Network mode).

16.2 AUDIO INTERFACE MODES

There are two clocking modes: asynchronous mode and synchronous mode. These modes differ in the source and timing of the clock signals used to transfer data. When the AAI is generating the bit shift clock and frame sync signals internally, synchronous mode must be used. In asynchro- nous mode, an external frame sync signal must be used. There are two framing modes: normal mode and network mode. In normal mode, one word is transferred per frame. In network mode, up to four words are transferred per frame. A word may be 8 or 16 bits. The part of the frame which car- ries a word is called a slot. Network mode supports multiple external devices sharing the interface, in which each device is assigned its own slot. Separate frame sync signals are provided, so that each device is triggered to send or receive its data during its assigned slot.

16.2.1 Asynchronous Mode

16.2.2 Synchronous Mode

are derived from the same set of clock prescalers.

16.2.3 Normal Mode

programmed to select slot 0. transmit DMA register 0 (ARDR0/ATDR0). mode with a long frame sync interval. Figure 43. Normal Mode Frame or less than a programmable warning limit. Figure 44. IRQ/DMA Support in Normal Mode In network mode, each frame is composed of multiple slots. up to four slots are supported by this audio interface. to it, in which only that device is allowed to transfer data. frame are reserved for other devices.

Figure 47. Accessing Three Devices in Network Mode

16.3 BIT CLOCK GENERATION

the 12-MHz Aux1 clock and the 48-MHz PLL output clock. BCPRS[7:0] + 1 to generate the bit clock. to minimize the bit clock error, fbit_error. per second. The input clock of the audio interface is 12 MHz.

16.4 FRAME CLOCK GENERATION

used, the frame width must always be at least 16 bits wide. Frame Sync Length field (FSL) in the AGCR register.

16.5 AUDIO INTERFACE OPERATION

16.5.1 Clock Configuration

Aux1 clock by setting the ACE1 bit in the CRCTRL register.

16.5.2 Interrupts

Interrupt Control Unit (ICU). programmed to generate edge-triggered interrupts.

Figure 48 shows the interrupt structure of the AAI. Figure 48. AAI Interrupt Structure

16.5.3 Normal Mode

low byte of each 16-bit FIFO location holds valid data.

16.5.4 Transmit

beginning of a new frame is identified by a frame sync pulse. vious data will be re-transmitted. ed internally, or they can be supplied by an external source.

16.5.5 Receive

SRFS (or SFS in synchronous mode). overwritten with the new data.

107 www.national.com CP3CN17 ated internally, or they can be supplied by an external source.

16.5.6 Network Mode

In network mode, each frame sync signal marks the begin- ning of new frame. Each frame can consist of up to four slots. The audio interface operates in a similar way to nor- mal mode, however, in network mode the transmitter and re- ceiver can be assigned to specific slots within each frame as described below.

16.5.7 Transmit

The transmitter only shifts out data during the assigned slot. During all other slots the STD output is in TRI-STATE mode. DMA Operation When a complete data word has been transmitted through the STD pin, a new data word is reloaded from the corre- sponding transmit DMA register n (ATDRn). A DMA request is asserted when ATDRn is empty. If a new data word must be transmitted in a slot n while ATDRn is still empty, the pre- vious slot n data will be retransmitted. FIFO Operation When a complete data word has been transmitted through the STD pin, a new data word is reloaded from the transmit FIFO from the current location of the Transmit FIFO Read Pointer (TRP). After that, th e TRP is automatically incre- mented by 1. Therefore, the audio data to be transmitted in the next slot of the frame is read from the next FIFO loca- tion. A write to the Audio Transmit FIFO Register (ATFR) results in a write to the transmit FIFO at the current location of the Transmit FIFO Write Pointer (TWP). After every write oper- ation to the transmit FIFO, the TWP is automatically incre- mented by 1. When the TRP is equal to the TWP and the last access to the FIFO was a read operation (transfer to the ATSR), the transmit FIFO is empty. When an additional read operation from the FIFO to the ATSR is performed (while the FIFO is already empty), a transmit FIFO underrun occurs. In this case, the read pointer (TRP) will be decremented by 1 (in- cremented by 15) and the previous data word will be trans- mitted again. A transmit FIFO underrun is indicated by the TXU bit in the Audio Interface Transmit Status and Control Register (ATSCR). No transmit interrupt will be generated (even if enabled). If the current TRP is equal to the TWP and the last access to the FIFO was a write operation (to the ATFR), the FIFO is full. If an additional write to the ATFR is performed, a trans- mit FIFO overrun occurs. This error condition is not prevent- ed by hardware. Software must ensure that no transmit overrun occurs. The transmit frame synchronization pulse on the SFS pin and the transmit shift clock on the SCK pin may be generat- ed internally, or they can be supplied by an external source.

16.5.8 Receive

The receive shift register (ARSR) receives data words of all slots in the frame, regardless of the slot assignment of the interface. However, only those ARSR contents are trans- ferred to the receive FIFO or DMA receive register which were received during the assigned time slots. A receive in- terrupt or DMA request is initiated when this occurs. DMA Operation When a complete data word has been received through the SRD pin in a slot n, the new data word is transferred to the corresponding receive DMA register n (ARDRn). A DMA re- quest is asserted when the ARDRn register is full. If a new slot n data word is received while the ARDRn register is still full, the ARDRn register will be overwritten with the new da- ta. FIFO Operation When a complete word has been received, it is transferred to the receive FIFO at the current location of the Receive FIFO Write Pointer (RWP). After that, the RWP is automati- cally incremented by 1. Therefore, data received in the next slot is copied to the next higher FIFO location. A read from the Audio Receive FIFO Register (ARFR) re- sults in a read from the receive FIFO at the current location of the Receive FIFO Read Pointer (RRP). After every read operation from the receive FIFO, the RRP is automatically incremented by 1. When the RRP is equal to the RWP and the last access to the FIFO was a transfer to the ARFR, the receive FIFO is full. When a new complete data word has been shifted into the ARSR while the receive FIFO was already full, the shift register overruns. In this case, the new data in the ARSR will not be transferred to the FIFO and the RWP will not be in- cremented. A receive FIFO overrun is indicated by the RXO bit in the Audio Interface Receive Status and Control Regis- ter (ARSCR). No receive interrupt will be generated (even if enabled). When the current RWP is equal to the TWP and the last ac- cess to the receive FIFO was a read from ARFR, a receive FIFO underrun has occurred. This error condition is not pre- vented by hardware. Software must ensure that no receive underrun occurs. The receive frame synchronization pulse on the SRFS pin (or SFS in synchronous mode) and the receive shift clock on the SRCLK (or SCK in synchro nous mode) may be gener- ated internally, or they can be supplied by an external source.

16.6 COMMUNICATION OPTIONS

16.6.1 Data Word Length

The word length of the audio data can be selected to be ei- ther 8 or 16 bits. In 16-bit mode, all 16 bits of the transmit and receive shift registers (ATSR and ARSR) are used. In 8- bit mode, only the lower 8 bits of the transmit and receive shift registers (ATSR and ARSR) are used.

16.6.2 Frame Sync Signal

The audio interface can be configured to use either long or short frame sync signals to mark the beginning of a new data frame. If the corresponding Frame Sync Select (FSS) bit in the Audio Control and Status register is clear, the re- ceive and/or transmit path generates or recognizes short frame sync pulses with a length of one bit shift clock period. When these short frame sync pulses are used, the transfer

amples of short and long frame sync pulses. Figure 49. Short and Long Frame Sync Pulses

16.6.3 Audio Control Data

PCM data word plus three audio control bits. Figure 50. Audio Slot with Audio Control Data

16.6.4 IOM-2 Mode

this IOM-2 mode, the AAI can only operate as a slave, i.e. IOM-2 channel 0, but ignores the other two IOM-2 channels. Figure 51 shows the structure of an IOM-2 Frame. Figure 51. IOM-2 Frame Structure (IO Expansion) for controlling the ISDN controller. Figure 52. CP3CN17/ISDN Controller Connections „ The AAI must be in IOM-2 Mode (AGCR.IOM2 = 1). (ACGR.IEFS = 1, ACGR.IEBC = 1). „ The internal frame rate must be 8 ksps (ACCR = 00BE).

16.6.5 Loopback Mode

ample during Built-In-Self-Test (BIST).

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16.6.6 Freeze Mode

The audio interface provides a FREEZE input, which allows to freeze the status of the audio interface while a develop- ment system examines the contents of the FIFOs and reg- isters. When the FREEZE input is asserted, the audio interface be- haves as follows: „ The receive FIFO or receive DMA registers are not up- dated with new data. „ The receive status bits (RXO, RXE, RXF , and RXAF) are not changed, even though t he receive FIFO or receive DMA registers are read. „ The transmit shift register (ATSR) is not updated with new data from the transmit FIFO or transmit DMA regis- ters. „ The transmit status bits (TXU, TXF , TXE, and TXAE) are not changed, even though the transmit FIFO or transmit DMA registers are written. The time at which these registers are frozen will vary be- cause they operate from a different clock than the one used to generate the freeze signal.

16.7 AUDIO INTERFACE REGISTERS

Table 54 Audio Interface Registers Name Address Description ARFR FF FD40h Audio Receive FIFO Register ARDR0 FF FD42h Audio Receive DMA Register 0 ARDR1 FF FD44h Audio Receive DMA Register 1 ARDR2 FF FD46h Audio Receive DMA Register 2 ARDR3 FF FD48h Audio Receive DMA Register 3 ATFR FF FD4Ah Audio Transmit FIFO Register ATDR0 FF FD4Ch Audio Transmit DMA Register 0 ATDR1 FF FD4Eh Audio Transmit DMA Register 1 ATDR2 FF FD50h Audio Transmit DMA Register 2 ATDR3 FF FD52h Audio Transmit DMA Register 3 AGCR FF FD54h Audio Global Configuration Register AISCR FF FD56h Audio Interrupt Status and Control Register ARSCR FF FD58h Audio Receive Status and Control Register ATSCR FF FD5Ah Audio Transmit Status and Control Register ACCR FF FD5Ch Audio Clock Control Register ADMACR FF FD5Eh Audio DMA Control Register

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16.7.1 Audio Receive FI FO Register (ARFR)

The Audio Receive FIFO regi ster shows the receive FIFO location currently addressed by the Receive FIFO Read Pointer (RRP). The receive FIFO receives 8-bit or 16-bit data from the Audio Receive Shift Register (ARSR), when the ARSR is full. In 8-bit mode, only the lower byte of the ARFR is used, and the upper byte contains undefined data. In 16-bit mode, a 16-bit word is copied from ARSR into the receive FIFO. The CPU bus master has read-only access to the receive FIFO, represented by the ARFR register. After reset, the receive FIFO (ARFR) contains undefined data. ARFL The Audio Receive FIFO Low Byte shows the lower byte of the receive FIFO location cur- rently addressed by the Receive FIFO Read Pointer (RRP). ARFH The Audio Receive FIFO High Byte shows the upper byte of the receive FIFO location cur- rently addressed by the Receive FIFO Read Pointer (RRP). In 8-bit mode, ARFH contains undefined data.

16.7.2 Audio Receive DMA Register n (ARDRn)

The ARDRn register contains the data received within slot n, assigned for DMA support. In 8-bit mode, only the lower 8-bit portion of the ARDRn re gister is used, and the upper byte contains undefined data. In 16-bit mode, a 16-bit word is transferred from the Audio Receive Shift Register (ARSR) into the ARDRn register. The CPU bus master, typically a DMA controller, has read-only access to the receive DMA registers. After reset, these registers are clear. ARDL The Audio Receive DMA Low Byte field re- ceives the lower byte of the audio data copied from the ARSR. ARDH In 16-bit mode, the Audio Receive DMA High Byte field receives the upper byte of the audio data word copied from ARSR. In 8-bit mode, the ARDH register holds undefined data.

16.7.3 Audio Transmit FIFO Register (ATFR)

The ATFR register shows the transmit FIFO location cur- rently addressed by the Transmit FIFO Write Pointer (TWP). The Audio Transmit Shift Register (ATSR) receives 8-bit or 16-bit data from the transmit FIFO, when the ATSR is empty. In 8-bit mode, only the lower 8-bit portion of the ATSR is used, and the upper byte is ignored (not transferred into the ATSR). In 16-bit mode, a 16-bit word is copied from the transmit FIFO into the AT SR. The CPU bus master has write-only access to the transmit FIFO, represented by the ATFR register. After reset, the transmit FIFO (ATFR) con- tains undefined data. ATFL The Audio Transmit Low Byte field represents the lower byte of the transmit FIFO location currently addressed by the Transmit FIFO Write Pointer (TWP). ATFH In 16-bit mode, the Audio Transmit FIFO High Byte field represents the upper byte of the transmit FIFO location currently addressed by the Transmit FIFO Write Pointer (TWP). In 8- bit mode, the ATFH field is not used.

16.7.4 Audio Transmit DMA Register n (ATDRn)

The ATDRn register contains the data to be transmitted in slot n, assigned for DMA support. In 8-bit mode, only the lower 8-bit portion of the ATDRn register is used, and the upper byte is ignored (not transferred into the ATSR). In 16- bit mode, the whole 16-bit word is transferred into the ATSR. The CPU bus master, typically a DMA controller, has write- only access to the transmit DMA registers. After reset, these registers are clear. ATDL The Audio Transmit DMA Low Byte field holds the lower byte of the audio data. ATDH In 16-bit mode, the Audio Transmit DMA High Byte field holds the upper byte of the audio data word. In 8-bit mode, the ATDH field is ig- nored. 7 0 ARFL 15 8 ARFH 7 0 ARDL 15 8 ARDH 7 0 ATFL 15 8 ATFH 7 0 ATDL 15 8 ATDH

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16.7.5 Audio Global Config uration Register (AGCR)

The AGCR register controls the basic operation of the inter- face. The CPU bus master has read/write access to the AGCR register. After reset, this register is clear. ASS The Asynchronous/Synchronous Mode Se- lect bit controls whether the audio interface operates in Asynchronous or in Synchronous mode. After reset the ASS bit is clear, so the Synchronous mode is selected by default. 0 – Synchronous mode. 1 – Asynchronous mode. DWL The Data Word Length bit controls whether the transferred data word has a length of 8 or 16 bits. After reset, the DWL bit is clear, so 8- bit data words are used by default. 0 – 8-bit data word length. 1 – 16-bit data word length. LPB The Loop Back bit enables the loop back mode. In this mode, the SRD and STD pins are internally connected. After reset the LPB bit is clear, so by default the loop back mode is disabled. 0 – Loop back mode disabled. 1 – Loop back mode enabled. SCS The Slot Count Select field specifies the num- ber of slots within each frame. If the number of slots per frame is equal to 1, the audio inter- face operates in normal mode. If the number of slots per frame is greater than 1, the inter- face operates in network mode. After reset all SCS bits are cleared, so by default the audio interface operates in normal mode. IEFS The Internal/External Frame Sync bit controls, whether the frame sync signal for the receiver and transmitter are generated internally or provided from an external source. After reset, the IEFS bit is clear, so the frame synchroni- zation signals are generated internally by de- fault. 0 – Internal frame synchronization signal. 1 – External frame synchronization signal. FSS The Frame Sync Select bit controls whether the interface (receiver and transmitter) uses long or short frame synchronization signals. After reset the FSS bit is clear, so short frame synchronization signals are used by default. 0 – Short (bit length) frame synchronization signal. 1 – Long (word length) frame synchronization signal. IEBC The Internal/External Bit Clock bit controls whether the bit clocks for receiver and trans- mitter are generated internally or provided from an external source. After reset, the IEBC bit is clear, so the bit clocks are generated in- ternally by default. 0 – Internal bit clock. 1 – External bit clock. CRF The Clear Receive FIFO bit is used to clear the receive FIFO. When this bit is written with a 1, all pointers of the receive FIFO are set to their reset state. After updating the pointers, the CRF bit will automatically be cleared again. 0 – Writing 0 has no effect. 1 – Writing 1 clears the receive FIFO. CTF The Clear Transmit FIFO bit is used to clear the transmit FIFO. When this bit is written with a 1, all pointers of the transmit FIFO are set to their reset state. After updating the pointers, the CTF bit will automatically be cleared again. 0 – Writing 0 has no effect. 1 – Writing 1 clears the transmit FIFO. FSL The Frame Sync Length field specifies the length of the frame synchronization signal, when a long frame sync signal (FSS = 1) and a 16-bit data word length (DWL = 1) are used. If an 8-bit data word length is used, long frame syncs are always 6 bit clocks in length. IFS The Inverted Frame Sync bit controls the po- larity of the frame sync signal. 0 – Active-high frame sync signal. 1 – Active-low frame sync signal. 7 6 5 4 3 2 1 0 IEBC FSS IEFS SCS LPB DWL ASS 15 14 13 12 11 10 9 8 CLKEN AAIEN IOM2 IFS FSL CTF CRF SCS Number of Slots per Frame Mode 00 1 Normal mode 01 2 Network mode 10 3 Network mode 11 4 Network mode FSL Frame Sync Length 00 13 bit clocks 01 14 bit clocks 10 15 bit clocks 11 16 bit clocks

113 www.national.com CP3CN17 IOM2 The IOM-2 Mode bit selects the normal PCM interface mode or a special IOM-2 mode used to connect to external ISDN controller devic- es. The AAI can only operate as a slave in the IOM-2 mode, i.e. the bit clock and frame sync signals are provided by the ISDN controller. If the IOM2 bit is clear, the AAI operates in the normal PCM interface mode used to connect to external PCM codecs and other PCM audio devices. 0 – IOM-2 mode disabled. 1 – IOM-2 mode enabled. AAIEN The AAI Enable bit co ntrols whether the Ad- vanced Audio Interface is enabled. All AAI registers provide read/write access while (CLKEN = 1) AAIEN is clear. The AAIEN bit is clear after reset. 0 – AAI module disabled. 1 – AAI module enabled. CLKEN The Clock Enable bit controls whether the Ad- vanced Audio Interface clock is enabled. The CLKEN bit must be set to allow access to any AAI register. It must also be set before any other bit of the AGCR can be set. The CLKEN bit is clear after reset. 0 – AAI module clock disabled. 1 – AAI module clock enabled.

16.7.6 Audio Interrupt Stat us and Control Register

(AISCR) The ASCR register is used to specify the source and the conditions, when the audio interface interrupt is asserted to the Interrupt Control Unit. It also holds the interrupt pending bits and the corresponding interrupt clear bits for each audio interface interrupt source. The CPU bus master has read/ write access to the ASCR register. After reset, this register is clear. RXIE The Receive Interrupt Enable bit controls whether receive interrupts are generated. If the RXIE bit is clear, no receive interrupt will be generated. 0 – Receive interrupt disabled. 1 – Receive interrupt enabled. RXEIE The Receive Error Interrupt Enable bit con- trols whether receive error interrupts are gen- erated. Setting this bit enables a receive error interrupt, when the Receive Buffer Overrun (RXOR) bit is set. If the RXEIE bit is clear, no receive error interrupt will be generated. 0 – Receive error interrupt disabled. 1 – Receive error interrupt enabled. TXIE The Transmit Interrupt Enable bit controls whether transmit interrupts are generated. Setting this bit enables a transmit interrupt, when the Transmit Buffer Almost Empty (TX- AE) bit is set. If the TXIE bit is clear, no inter- rupt will be generated. 0 – Transmit interrupt disabled. 1 – Transmit interrupt enabled. TXEIE The Transmit Error Interrupt Enable bit con- trols whether transmit error interrupts are gen- erated. Setting this bit to 1 enables a transmit error interrupt, when the Transmit Buffer Un- derrun (TXUR) bit is set. If the TXEIE bit is clear, no transmit error interrupt will be gener- ated. 0 – Transmit error interrupt disabled. 1 – Transmit error interrupt enabled. RXIP The Receive Interrupt Pending bit indicates that a receive interrupt is currently pending. The RXIP bit is cleared by writing a 1 to the RXIC bit. The RXIP bit provides read-only ac- cess. 0 – No receive interrupt pending. 1 – Receive interrupt pending. RXEIP The Receive Error Interrupt Pending bit indi- cates that a receive error interrupt is currently pending. The RXEIP bit is cleared by writing a 1 to the RXEIC bit. The RXEIP bit provides read-only access. 0 – No receive error interrupt pending. 1 – Receive error interrupt pending. TXIP The Transmit Interrupt Pending bit indicates that a transmit interrupt is currently pending. The TXIP bit is cleared by writing a 1 to the TXIC bit. The TXIP bit provides read-only ac- cess. 0 – No transmit interrupt pending. 1 – Transmit interrupt pending. TXEIP Transmit Error Interrupt Pending. This bit indi- cates that a transmit error interrupt is currently pending. The TXEIP bit is cleared by software by writing a 1 to the TXEIC bit. The TXEIP bit provides read-only access. 0 – No transmit error interrupt pending. 1 – Transmit error interrupt pending. RXIC The Receive Interrupt Clear bit is used to clear the RXIP bit. 0 – Writing a 0 to the RXIC bit is ignored. 1 – Writing a 1 clears the RXIP bit. RXEIC The Receive Error Interrupt Clear bit is used to clear the RXEIP bit. 0 – Writing a 0 to the RXEIC bit is ignored. 1 – Writing a 1 clears the RXEIP bit. TXIC The Transmit Interrupt Clear bit is used to clear the TXIP bit. 0 – Writing a 0 to the TXIC bit is ignored. 1 – Writing a 1 clears the TXIP bit. TXEIC The Transmit Error Interrupt Clear bit is used to clear the TXEIP bit. 0 – Writing a 0 to the TXEIC bit is ignored. 1 – Writing a 1 clears the TXEIP bit. 7 6 5 4 3 2 1 0 TXEIP TXIP RXEIP RXIP TXEIE TXIE RXEIE RXIE 15 12 11 10 9 8 Reserved TXEIC TXIC RXEIC RXIC

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16.7.7 Audio Receive Status and Control Register

(ARSCR) The ARSCR register is used to control the operation of the receiver path of the audio interface. It also holds bits which report the current status of the receive FIFO. The CPU bus master has read/write access to the ASCR register. At re- set, this register is loaded with 0004h. RXAF The Receive Buffer Almo st Full bit is set when the number of data bytes/words in the receive buffer is equal to the specified warning limit. 0 – Receive FIFO below warning limit. 1 – Receive FIFO is almost full. RXF The Receive Buffer Full bit is set when the re- ceive buffer is full. The RXF bit is set when the RWP is equal to the RRP and the last access was a write to the FIFO. 0 – Receive FIFO is not full. 1 – Receive FIFO full. RXE The Receive Buffer Empty bit is set when the the RRP is equal to the RWP and the last ac- cess to the FIFO was a read operation (read from ARDR). 0 – Receive FIFO is not empty. 1 – Receive FIFO is empty. RXO The Receive Overflow bit indicates that a re- ceive shift register has overrun. This occurs, when a completed data word has been shifted into ARSR, while the receive FIFO was al- ready full (the RXF bit was set). In this case, the new data in ARSR will not be copied into the FIFO and the RWP will not be increment- ed. Also, no receive interrupt and DMA re- quest will generated (even if enabled). 0 – No overflow has occurred. 1 – Overflow has occurred. RXSA The Receive Slot Assignment field specifies which slots are recognized by the receiver of the audio interface. Multiple slots may be en- abled. If the frame consists of less than 4 slots, the RXSA bits for unused slots are ig- nored. For example, if a frame only consists of 2 slots, RXSA bits 2 and 3 are ignored. The following table shows the slot assignment scheme. After reset the RXSA field is clear, so software must load the correct slot assignment. RXDSA The Receive DMA Slot Assignment field spec- ifies which slots (audio channels) are support- ed by DMA. If the RXDSA bit is set for an assigned slot n (RXSAn = 1), the data re- ceived within this slot will not be transferred into the receive FIFO, but will instead be writ- ten into the corresponding Receive DMA data register (ARDRn). A DMA request n is assert- ed, when the ARDRn is full and if the RMA bit n is set. If the RXSD bit for a slot is clear, the RXDSA bit is ignored. The following table shows the DMA slot assignment scheme. RXFWL The Receive FIFO Warning Level field speci- fies when a receive interrupt is asserted. A re- ceive interrupt is asserted, when the number of bytes/words in the receive FIFO is greater than the warning level value. An RXFWL value of 0 means that a receive interrupt is asserted if one or more bytes/words are in the RX FIFO. After reset, the RXFWL bit is clear. 7 4 3 2 1 0 RXSA RXO RXE RXF RXAF 15 12 11 8 RXFWL RXDSA RXSA Bit Slots Enabled RXSA0 0 RXSA1 1 RXSA2 2 RXSA3 3 RXDSA Bit Slots Enabled for DMA RXDSA0 0 RXDSA1 1 RXDSA2 2 RXDSA3 3

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16.7.8 Audio Transmit Stat us and Control Register

(ATSCR) The ASCR register controls the basic operation of the inter- face. It also holds bits which report the current status of the audio communication. The CPU bus master has read/write access to the ASCR register. At reset, this register is loaded with F003h. TXAE The Transmit FIFO Almost Empty bit is set when the number of data bytes/words in transmit buffer is equal to the specified warn- ing limit. 0 – Transmit FIFO above warning limit. 1 – Transmit FIFO at or below warning limit. TXE The Transmit FIFO Empty bit is set when the transmit buffer is empty. The TXE bit is set to one every time the TRP is equal to the TWP and the last access to the FIFO was read op- eration (into ATSR). 0 – Transmit FIFO not empty. 1 – Transmit FIFO empty. TXF The Transmit FIFO Full bit is set when the TWP is equal to the TRP and the last access to the FIFO was write operation (write to AT- DR). 0 – Transmit FIFO not full. 1 – Transmit FIFO full. TXU The Transmit Underflow bit indicates that the transmit shift register (ATSR) has underrun. This occurs when the transmit FIFO was al- ready empty and a complete data word has been transferred. In this case, the TRP will be decremented by 1 and the previous data will be retransmitted. No transmit interrupt and no DMA request will be generated (even if en- abled). 0 – Transmit underrun occurred. 1 – Transmit underrun did not occur. TXSA The Transmit Slot Assignment field specifies during which slots the transmitter is active and drives data through the STD pin. The STD pin is in high impedance state during all other slots. If the frame consists of less than 4 slots, the TXSA bits for unused slots are ignored. For example, if a frame only consists of 2 slots, TXSA bits 2 and 3 are ignored. The fol- lowing table shows the slot assignment scheme. After reset, the TXSA field is clear, so soft- ware must load the correct slot assignment. TXDSA The Transmit DMA Slot Assignment field specifies which slots (audio channels) are supported by DMA. If the TXDSA bit is set for an assigned slot n (TXSAn = 1), the data to be transmitted within this slot will not be read from the transmit FIFO, but will instead be read from the corresponding Transmit DMA data register (ATDRn). A DMA request n is as- serted when the ATDRn is empty. If the TSA bit for a slot is clear, the TXDSA bit is ignored. The following table shows the DMA slot as- signment scheme. TFWL The Transmit FIFO Warning Level field speci- fies when a transmit interrupt is asserted. A transmit interrupt is asserted when the num- ber of bytes or words in the transmit FIFO is equal or less than the warning level value. A TXFWL value of Fh means that a transmit in- terrupt is asserted if one or more bytes or words are available in the transmit FIFO. At reset, the TXFWL field is loaded with Fh. 7 4 3 2 1 0 TXSA TXU TXF TXE TXAE 15 12 11 8 TXFWL TXDSA TXSA Bit Slots Enabled TXSA0 0 TXSA1 1 TXSA2 2 TXSA3 3 TXDSA Bit Slots Enabled for DMA TXDSA0 0 TXDSA1 1 TXDSA2 2 TXDSA3 3

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16.7.9 Audio Clock Control Register (ACCR)

The ACCR register is used to control the bit timing of the au- dio interface. After reset, this register is clear. CSS The Clock Source Select bit selects one out of two possible clock sources for the audio inter- face. After reset, the CSS bit is clear. 0 – The Aux1 clock is used to clock the Audio Interface. 1 – The 48-MHz clock is used to clock the Au- dio Interface. FCPRS The Frame Clock Prescaler is used to divide the bit clock to generate the frame clock for the receive and transmit operations. The bit clock is divided by (FCPRS + 1). After reset, the FCPRS field is clear. The maximum al- lowed bit clock rate to achieve an 8 kHz frame clock is 1024 kHz. This value must be set cor- rectly even if the frame sync is generated ex- ternally. BCPRS The Bit Clock Prescaler is used to divide the audio interface clock (selected by the CSS bit) to generate the bit clock for the receive and transmit operations. The audio interface input clock is divided by (BCPRS + 1). After reset, the BCPRS[7:0] bits are clear.

16.7.10 Audio DMA Contro l Register (ADMACR)

The ADMACR register is used to control the DMA support of the audio interface. In addition, it is used to configure the automatic transmission of the audio control bits. After reset, this register is clear. RMD The Receive Master DMA field specify which slots (audio channels) are supported by DMA, i.e. when a DMA request is asserted to the DMA controller. If the RMDn bit is set for an assigned slot n (RXDSAn = 1), a DMA request n is asserted, when the ARDRn is full. If the RXDSAn bit for a slot is clear, the RMDn bit is ignored. The following table shows the receive DMA request scheme. TMD The Transmit Master DMA field specifies which slots (audio channels) are supported by DMA, i.e. when a DMA request is asserted to the DMA controller. If the TMD bit is set for an assigned slot n (TXDSAn = 1), a DMA request n is asserted, when the ATDRn register is empty. If the TXDSA bit for a slot is clear, the TMD bit is ignored. The following table shows the transmit DMA request scheme. ACD The Audio Control Data field is used to fill the remaining bits of a 16-bit slot if only 13, 14, or 15 bits of PCM audio data are transmitted. ACO The Audio Control Output field controls the number of control bits appended to the PCM data word. 00 – No Audio Control bits are appended. 01 – Append ACD0. 10 – Append ACD1:0. 11 – Append ACD2:0.

16.8 USAGE HINTS

When the Advanced Audio Interface is active, it can lock up if the receive FIFO is cleared by writing 1 to the AGCR.CRF bit, the transmit FIFO is cleared by writing 1 to the AGCR.CTF bit, or the module is disabled by clearing the AGCR.AAIEN bit. Follow this procedure to disable the Advanced Audio Inter- face: 1. Clear the ARSCR.RXSA and ATSCR.TXSA fields. 2. Wait at least 10 receive/transmit clock cycles. 3. Clear the AGCR.AAIEN bit. 7 1 0 FCPRS CSS 15 8 BCPRS 7 4 3 0 TMD RMD 15 13 12 11 10 8 Reserved ACO ACD RMD DMA Request Condition

0000 None

0001 ARDR0 full

0010 ARDR1 full

0011 ARDR0 full or ARDR1 full

0001 ATDR0 empty

0010 ATDR1 empty

0011 ATDR0 empty or

17.0 CVSD/PCM Conversion Module

gram of the CVSD to PCM module. Figure 53. CVSD/PCM Converter Block Diagram

17.1 OPERATION

2 MHz input clock based upon the System Clock (usually

either one of the CVSD FIFOs is almost empty or almost full. into an 8 kHz, 16-bit data stream.

17.2 PCM CONVERSIONS

aligned 14-bit linear data format with the two LSBs unused.

2 MHz

www.national.com 118 CP3CN17 If the module is only used for PCM conversions, the CVSD clock can be disabled by clearing the CVSD Clock Enable bit (CLKEN) in the control register.

17.3 CVSD CONVERSION

The CVSD/PCM converter module transforms either 8-bit logarithmic or 13- to 16-bit linear PCM samples at a fixed rate of 8 ksps. The CVSD to PCM conversion format must be specified by the CVSDCONV control bits in the CVSD Control register (CVCTRL). The CVSD algorithm is designed for 2’s complement 16-bit data and is tuned for best performance with typical voice da- ta. Mild distortion will occur for peak signals greater than -6 dB. The Bluetooth CVSD standard is designed for best per- formace with typical voice signals: nominaly -6dB with occa- sional peaks to 0dB rather than full-scale inputs. Distortion of signals greater than -6dB is not considered detrimental to subjective quality tests for voice-band applications and al- lows for greater clarity for signals below -6dB. The gain of the input device should be tuned with this in mind. If required, the RESOLUTION field of the CVCTRL register can be used to optimize the level of the 16-bit linear input data by providing attenuations (right-shifts with sign exten- tion) of 1, 2, or 3 bits. Log data is always 8 bit, but to perform the CVSD conver- sion, the log data is first converted to 16-bit 2’s complement linear data. A-law and u-law conversion can also slightly af- fect the optimum gain of the input data. The CVCTRL.RES- OLUTION field can be used to attenuate the data if required. If the resolution is not set properly, the audio signal may be clipped or have reduced attenuation.

17.4 PCM TO CVSD CONVERSION

The converter core reads out the double-buffered PCMIN register every 125 µs and writes a new 16-bit CVSD data stream into the CVSD Out FIFO every 250 µs. If the PCMIN buffer has not been updated with a new PCM sample be- tween two reads from the CVSD core, the old PCM data is used again to maintain a fixed conversion rate. Once a new 16-bit CVSD data stream has been calculated, it is copied into the 8 × 16-bit wide CVSD Out FIFO. If there are only three empty words (16-bit) left in the FIFO, the nearly full bit (CVNF) is set, and, if enabled (CVSDINT = 1), an interrupt request is asserted. If the CVSD Out FIFO is full, the full bit (CVF) is set, and, if enabled (CVSDERRINT = 1), an interrupt request is assert- ed. In this case, the CVSD Out FIFO remains unchanged. Within the interrupt handler, the CPU can read out the new CVSD data. If the CPU reads from an already empty CVSD Out FIFO, a lockup of the FIFO logic may occur which per- sists until the next reset. Software must check the CVOUTST field of the CVSTAT register to read the number of valid words in the FIFO. Software must not use the CVNF bit as an indication of the number of valid words in the FIFO.

17.5 CVSD TO PCM CONVERSION

The converter core reads from the CVSD In FIFO every 250 µs and writes a new PCM sample into the PCMOUT buffer every 125 µs. If the previous PCM data has not yet been transferred to the audio interface, it will be overwritten with the new PCM sample. If there are only three unread words left, the CVSD In Nearly Empty bit (CVNE) is set and, if enabled (CVSDINT = 1), an interrupt request is generated. If the CVSD In FIFO is empty, the CVSD In Empty bit (CVE) is set and, if enabled (CVSDERRINT = 1), an interrupt re- quest is generated. If the converter core reads from an al- ready empty CVSD In FIFO, the FIFO automatically returns a checkerboard pattern to guarantee a minimum level of dis- tortion of the audio stream.

17.6 INTERRUPT GENERATION

An interrupt is generated in any of the following cases: „ When a new PCM sample has been written into the PCMOUT register and the CVCTRL.PCMINT bit is set. „ When a new PCM sample has been read from the PCMIN register and the CVCTRL.PCMINT bit is set. „ When the CVSD In FIFO is nearly empty (CVSTAT.CVNE = 1) and the CVCTRL.CVSDINT bit is set. „ When the CVSD Out FIFO is nearly full (CVSTAT.CVNF = 1) and the CVCTRL.CVSDINT bit is set. „ When the CVSD In FIFO is empty (CVSTAT.CVE = 1) and the CVCTRL.CVSDERRINT bit is set. „ When the CVSD Out FIFO is full (CVSTAT.CVF = 1) and the CVCTRL.CVSDERRINT bit is set. Both the CVSD In and CVSD Out FIFOs have a size of 8 × 16 bit (8 words). The warning limits for the two FIFOs is set at 5 words. (The CVSD In FIFO interrupt will occur when there are 3 words left in the FIFO, and the CVSD Out FIFO interrupt will occur when there are 3 or less empty words left in the FIFO.) The limit is set to 5 words because Bluetooth audio data is transferred in packages composed of 10 or multiples of 10 bytes.

17.7 DMA SUPPORT

The CVSD module can operate with any of four DMA chan- nels. Four DMA channels are required for processor inde- pendent operation. Both receive and transmit for CVSD data and PCM data can be enabled individually. The CVSD/ PCM module asserts a DMA request to the on-chip DMA controller under the following conditions: „ The DMAPO bit is set and th e PCMOUT register is full, because it has been updated by the converter core with a new PCM sample. (The DMA controller can read out one PCM data word from the PCMOUT register.) „ The DMAPI bit is set and the PCMIN register is empty, because it has been read by the converter core. (The DMA controller can write one new PCM data word into the PCMIN register.) „ The DMACO bit is set and a new 16-bit CVSD data stream has been copied into the CVSD Out FIFO. (The DMA controller can read out one 16-bit CVSD data word from the CVSD Out FIFO.) „ The DMACI bit is set and a 16-bit CVSD data stream has been read from the CVSD In FIFO. (The DMA controller can write one new 16-bit CVSD data word into the CVSD In FIFO.)

119 www.national.com CP3CN17 The CVSD/PCM module only supports indirect DMA trans- fers. Therefore, transferring PCM data between the CVSD/ PCM module and another on-chip module requires two bus cycles. The trigger for DMA may also trigger an interrupt if the cor- responding enable bits in the CVCTRL register is set. Therefore care must be taken when setting the desired in- terrupt and DMA enable bits. The following conditions must be avoided: „ Setting the PCMINT bit an d either of the DMAPO or DMAPI bits. „ Setting the CVSDINT bit and either of the DMACO or DMACI bits.

17.8 FREEZE

The CVSD/PCM module provides support for an In-System- Emulator by means of a special FREEZE input. While FREEZE is asserted the module will exhibit the following be- havior: „ CVSD In FIFO will not have data removed by the con- verter core. „ CVSD Out FIFO will not have data added by the convert- er core. „ PCM Out buffer will not be updated by the converter core. „ The Clear-on-Read function of the following status bits in the CVSTAT register is disabled: „ PCMINT „ CVE „ CVF

17.9 CVSD/PCM CONVERTER REGISTERS

Table 55 lists the CVSD/PCM registers.

17.9.1 CVSD Data Input Register (CVSDIN)

The CVSDIN register is a 16-bit wide, write-only register. It is used to write CVSD data into the CVSD to PCM converter FIFO. The FIFO is 8 words deep. The CVSDIN bit 15 repre- sents the CVSD data bit at t = t 0, CVSDIN bit 0 represents the CVSD data bit at t = t0 - 250 ms.

17.9.2 CVSD Data Output Register (CVSDOUT)

The CVSDOUT register is a 16-bit wide read-only register. It is used to read the CVSD data from the PCM to CVSD converter. The FIFO is 8 words deep. Reading the CVSD- OUT register after reset returns undefined data.

17.9.3 PCM Data Input Register (PCMIN)

The PCMIN register is a 16-bit wide write-only register. It is used to write PCM data to the PCM to CVSD converter via the peripheral bus. It is double-buffered, providing a 125 µs period for an interrupt or DMA request to respond.

17.9.4 PCM Data Output Register (PCMOUT)

The PCMOUT register is a 16-bit wide read-only register. It is used to read PCM data from the CVSD to PCM converter. It is double-buffered, providing a 125 µs period for an inter- rupt or DMA request to respond. After reset the PCMOUT register is clear. Table 55 CVSD/PCM Registers Name Address Description CVSDIN FF FC20h CVSD Data Input Register CVSDOUT FF FC22h CVSD Data Output Register PCMIN FF FC24h PCM Data Input Register PCMOUT FF FC26h PCM Data Output Register LOGIN FF FC28h Logarithmic PCM Data Input Register LOGOUT FF FC2Ah Logarithmic PCM Data Output Register LINEARIN FF FC2Ch Linear PCM Data Input Register LINEAROUT FF FC2Eh Linear PCM Data Output Register CVCTRL FF FC30h CVSD Control Regis- ter CVSTAT FF FC32h CVSD Status Register 15 0 CVSDIN 15 0 CVSDOUT 15 0 PCMIN 15 0 PCMOUT Table 55 CVSD/PCM Registers Name Address Description

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17.9.5 Logarithmic PCM Data Input Register (LOGIN)

The LOGIN register is an 8-bit wide write-only register. It is used to receive 8-bit logarithmic PCM data from the periph- eral bus and convert it into 13-bit linear PCM data.

17.9.6 Logarithmic PCM Data Output Register

(LOGOUT) The LOGOUT register is an 8-bit wide read-only register. It holds logarithmic PCM data that has been converted from linear PCM data. After reset, the LOGOUT register is clear.

17.9.7 Linear PCM Data In put Register (LINEARIN)

The LINEARIN register is a 16-bit wide write-only register. The data is left-aligned. When converting to A-law, bits 2:0 are ignored. When converting to µ-law, bits 1:0 are ignored.

17.9.8 Linear PCM Data Output Register

(LINEAROUT) The LINEAROUT register is a 16-bit wide read-only register. The data is left-aligned. When converting from A-law, bits 2:0 are clear. When converting from µ-law, bits 1:0 are clear. After reset, this register is clear.

17.9.9 CVSD Control Register (CVCTRL)

The CVCTRL register is a 16-b it wide, read/write register that controls the mode of operation and of the module’s in- terrupts. At reset, all implemented bits are cleared. CVEN The Module Enable bit enables or disables the CVSD conversion module interface. When the bit is set, the interface is enabled which allows read and write operations to the rest of the module. When the bit is clear, the module is disabled. When the module is disabled the status register CVSTAT will be cleared to its reset state. 0 – CVSD module enabled. 1 – CVSD module disabled. CLKEN The CVSD Clock Enable bit enables the 2- MHz clock to the filter engine and CVSD en- coders and decoders. 0 – CVSD module clock disabled. 1 – CVSD module clock enabled. PCMINT The PCM Interrupt Enable bit controls gener- ation of the PCM interrupt . If set, this bit en- ables the PCM interrupt. If the PCMINT bit is clear, the PCM interrupt is disabled. After re- set, this bit is clear. 0 – PCM interrupt disabled. 1 – PCM interrupt enabled. CVSDINT The CVSD FIFO Interrupt Enable bit controls generation of the CVSD interrupt. If set, this bit enables the CVSD interrupt that occurs if the CVSD In FIFO is nearly empty or the CVSD Out FIFO is nearly full. If the CVSDINT bit is clear, the CVSD nearly full/nearly empty interrupt is disabled. After reset, this bit is clear. 0 – CVSD interrupt disabled. 1 – CVSD interrupt enabled. CVSDERRINT The CVSD FIFO Error Interrupt Enable bit controls generation of the CVSD error inter- rupt. If set, this bit enables an interrupt to oc- cur when the CVSD Out FIFO is full or the CVSD In FIFO is empty. If the CVSDERROR- INT bit is clear, the CVSD full/empty interrupt is disabled. After reset, this bit is clear. 0 – CVSD error interrupt disabled. 1 – CVSD error interrupt enabled. DMACO The DMA Enable for CVSD Out bit enables hardware DMA control for reading CVSD data from the CVSD Out FIFO. If clear, DMA sup- port is disabled. After reset, this bit is clear. 0 – CVSD output DMA disabled. 1 – CVSD output DMA enabled. DMACI The DMA Enable for CVSD In bit enables hardware DMA control for writing CVSD data into the CVSD In FIFO. If clear, DMA support is disabled. After reset, this bit is clear. 0 – CVSD input DMA disabled. 1 – CVSD input DMA enabled. DMAPO The DMA Enable for PCM Out bit enables hardware DMA control for reading PCM data from the PCMOUT register. If clear, DMA sup- port is disabled. After reset, this bit is clear. 0 – PCM output DMA disabled. 1 – PCM output DMA enabled. LOGIN LOGOUT 15 0 LINEARIN 15 0 LINEAROUT 7 6 5 4 3 2 1 0 DMA PO DMA CI DMA CO CVSD ERR- INT CVSD INT PCM INT CLK EN CVEN 15 14 13 12 11 10 9 8 Res. RESOLUTION PCMCONV CVSDCONV DMAPI

121 www.national.com CP3CN17 DMAPI The DMA Enable for PCM In bit enables hard- ware DMA control for writing PCM data into the PCMIN register. If cleared, DMA support is disabled. After reset, this bit is clear. 0 – PCM input DMA disabled. 1 – PCM input DMA enabled. CVSDCONV The CVSD to PCM Conversion Format field specifies the PCM format for CVSD/PCM con- versions. After reset, this field is clear. 00 – CVSD <-> 8-bit µ-Law PCM. 01 – CVSD <-> 8-bit A-Law PCM. 10 – CVSD <-> Linear PCM. 11 – Reserved. PCMCONV The PCM to PCM Conversion Format bit se- lects the PCM format for PCM/PCM conver- sions. 0 – Linear PCM <-> 8-bit µ-Law PCM 1 – Linear PCM <-> 8-bit A-Law PCM RESOLUTION The Linear PCM Resolution field specifies the attenuation of the PCM data for the linear PCM to CVSD conversions by right shifting and sign extending the data. This affects the log PCM data as well as the linear PCM data. The log data is converted to either left-justified zero-stuffed 13-bit (A-law) or 14-bit (u-law). The RESOLUTION field can be used to com- pensate for any change in average levels re- sulting from this conversion. After reset, these two bits are clear. 00 – No shift. 01 – 1-bit attentuation. 10 – 2-bit attentuation. 11 – 3-bit attentuation.

17.9.10 CVSD Status Register (CVSTAT)

The CVSTAT register is a 16-bit wide, read-only register that holds the status information of the CVSD/PCM module. At reset, and if the CVCTL1.CVEN bit is clear, all implemented bits are cleared. CVNE The CVSD In FIFO Nearly Empty bit indicates when only three CVSD data words are left in the CVSD In FIFO, so new CVSD data should be written into the CVSD In FIFO. If the CVS- DINT bit is set, an interrupt will be asserted when the CVNE bit is set. If the DMACI bit is set, a DMA request will be asserted when this bit is set. The CVNE bit is cleared when the CVSTAT register is read. 0 – CVSD In FIFO is not nearly empty. 1 – CVSD In FIFO is nearly empty. CVNF The CVSD Out FIFO Nearly Full bit indicates when only three empty word locations are left in the CVSD Out FIFO, so the CVSD Out FIFO should be read. If the CVSDINT bit is set, an interrupt will be asserted when the CVNF bit is set. If the DMACO bit is set, a DMA request will be asserted when this bit is set. Software must not rely on the CVNF bit as an indicator of the number of valid words in the FIFO. Software must check the CVOUTST field to read the number of valid words in the FIFO. The CVNF bit is cleared when the CVSTAT register is read. 0 – CVSD Out FIFO is not nearly full. 1 – CVSD Out FIFO is nearly full. PCMINT The PCM Interrupt bi t set indicates that the PCMOUT register is full and needs to be read or the PCMIN register is empty and needs to be loaded with new PCM data. The PCMINT bit is cleared when the CVSTAT register is read, unless the device is in FREEZE mode. 0 – PCM does not require service. 1 – PCM requires loading or unloading. CVE The CVSD In FIFO Empty bit indicates when the CVSD In FIFO has been read by the CVSD converter while the FIFO was already empty. If the CVSDERRORINT bit is set, an interrupt will be asserted when the CVE bit is set. The CVE bit is cleared when the CVSTAT register is read, unless the device is in FREEZE mode. 0 – CVSD In FIFO has not been read while empty. 1 – CVSD In FIFO has been read while emp- ty. CVF The CVSD Out FIFO Full bit set indicates whether the CVSD Out FIFO has been written by the CVSD converter while the FIFO was al- ready full. If the CVSD ERRORINT bit is set, an interrupt will be asserted when the CVF bit is set. The CVF bit is cleared when the CVSTAT register is read, unless the device is in FREEZE mode. 0 – CVSD Out FIFO has not been written while full. 1 – CVSD Out FIFO has been written while full. CVINST The CVSD In FIFO Status field reports the current number of empty 16-bit word locations in the CVSD In FIFO. When the FIFO is emp- ty, the CVINST field will read as 111b. When the FIFO holds 7 or 8 words of data, the CVINST field will read as 000b. CVOUTST CVSD Out FIFO Status field reports the cur- rent number of valid 16-bit CVSD data words in the CVSD Out FIFO. When the FIFO is empty, the CVOUTST field will read as 000b. When the FIFO holds 7 or 8 words of data, the CVOUTST field will read as 111b. 7 5 4 3 2 1 0 CVINST CVF CVE PCMINT CVNF CVNE 15 11 10 8 Reserved CVOUTST

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18.0 UART Module

The UART module is a full-duplex Universal Asynchronous Receiver/Transmitter that supports a wide range of soft- ware-programmable baud rates and data formats. It han- dles automatic parity generation and several error detection schemes. The UART module offers the following features: „ Full-duplex double-buffered receiver/transmitter „ Synchronous or asynchronous operation „ Programmable baud rate „ Programmable framing formats: 7, 8, or 9 data bits; even, odd, or no parity; one or two stop bits (mark or space) „ Hardware parity generation for data transmission and parity check for data reception „ Interrupts on “transmit ready” and “receive ready” condi- tions, separately enabled „ Software-controlled break transmission and detection „ Internal diagnostic capability „ Automatic detection of parity, framing, and overrun errors „ Hardware flow control (CTS and RTS signals) „ DMA capability

18.1 FUNCTIONAL OVERVIEW

Figure 54 is a block diagram of the UART module showing the basic functional units in the UART: „ Transmitter „ Receiver „ Baud Rate Generator „ Control and Error Detection The Transmitter block consists of an 8-bit transmit shift reg- ister and an 8-bit transmit buffer. Data bytes are loaded in parallel from the buffer into the shift register and then shifted out serially on the TXD pin. The Receiver block consists of an 8-bit receive shift register and an 8-bit receive buffer. Data is received serially on the RXD pin and shifted into the shift register. Once eight bits have been received, the contents of the shift register are transferred in parallel to the receive buffer. The Transmitter and Receiver blocks both contain exten- sions for 9-bit data transfers, as required by the 9-bit and loopback operating modes. The Baud Rate Generator generates the clock for the syn- chronous and asynchronous operating modes. It consists of two registers and a two-stage counter. The registers are used to specify a prescaler value and a baud rate divisor. The first stage of the counter divides the UART clock based on the value of the programmed prescaler to create a slower clock. The second stage of the counter creates the baud rate clock by dividing the output of the first stage based on the programmed baud rate divisor. The Control and Error Detection block contains the UART control registers, control logic, error detection circuit, parity generator/checker, and interrupt generation logic. The con- trol registers and control logic determine the data format, mode of operation, clock source, and type of parity used. The error detection circuit generates parity bits and checks for parity, framing, and overrun errors. The Flow Control Logic block provides the capability for hardware handshaking between the UART and a peripheral device. When the peripheral device needs to stop the flow of data from the UART, it de-asserts the clear-to-send (CTS signal which causes the UART to pause after sending the current frame (if any). The UART asserts the ready-to-send (RTS ) signal to the peripheral when it is ready to send a character.

18.2 UART OPERATION

The UART has two basic modes of operation: synchronous and asynchronous. Synchronous mode is only supported on 100-pin devices. In additi on, there are two special-pur- pose modes, called attention and diagnostic. This section describes the operating modes of the UART.

18.2.1 Asynchronous Mode

The asynchronous mode of the UART enables the device to communicate with other devices using just two communica- tion signals: transmit and receive. In asynchronous mode, the transmit shift register (TSFT) and the transmit buffer (UTBUF) double-buffer the data for transmission. To transmit a character, a data byte is loaded in the UTBUF register. The data is then transferred to the TSFT register. While the TSFT register is shifting out the current character (LSB first) on the TXD pin, the UTBUF register is loaded by software with the next byte to be trans- mitted. When TSFT finishes transmission of the last stop bit of the current frame, the contents of UTBUF are transferred to the TSFT register and the Transmit Buffer Empty bit (UT- BE) is set. The UTBE bit is automatically cleared by the UART when software loads a new character into the UTBUF register. During transmission, the UXMIP bit is set high by the UART. This bit is reset only after the UART has sent the last stop bit of the current character and the UTBUF register is empty. The UTBUF register is a read/write register. The TSFT register is not software accessible. In asynchronous mode, the input frequency to the UART is 16 times the baud rate. In other words, there are 16 clock cycles per bit time. In asynchronous mode, the baud rate generator is always the UART clock source. The receive shift register (RSFT) and the receive buffer (URBUF) double buffer the data being received. The UART receiver continuously monitors the signal on the RXD pin for a low level to detect the beginning of a start bit. On sensing this low level, the UART waits for seven input clock cycles and samples again three times. If all three samples still in- dicate a valid low, then the receiver considers this to be a valid start bit, and the remaining bits in the character frame are each sampled three times, around the mid-bit position. For any bit following the start bit, the logic value is found by majority voting, i.e. the two samples with the same value de- fine the value of the data bit. Figure 55 illustrates the pro- cess of start bit detection and bit sampling. Data bits are sensed by taking a majority vote of three sam- ples latched near the midpoint of each baud (bit time). Nor- mally, the position of the samples within the baud is determined automatically, but software can override the au-

18.2.2 Synchronous Mode

are transferred synchronously with the UART clock signal. Figure 56. Data bytes are transmitted and received least significant bit (LSB) first. Figure 56. UART Synchronous Communication and the UTBUF register is empty. on the CKX pin as an output.

18.2.3 Attention Mode

next address character (by setting the UATN bit again). received is read from URB9 in the UART Status Register.

18.2.4 Diagnostic Mode

number of start and stop bits is programmable.

18.2.5 Frame Format Selection

is generated and transmitted following the seven data bits. Figure 57. 7-Bit Data Frame Options

1 Start

Figure 58. 8-Bit Data Frame Options generated or verified in this mode. Figure 59. 9-bit Data Frame Options

18.2.6 Baud Rate Generator

caler (UPSC) and an 11-bit baud rate divisor (UDIV). setting and the prescaler factors is shown in Table 56. UART clock is turned off to reduce power consumption.

18.2.7 Interrupts

00000 No clock

2 Start

3 Start

Figure 60. UART Interrupts bits in the UICTRL register. the UTBUF register (which clears the UTBE bit). (which clears the URBF bit). can be programmed to generate edge-triggered interrupts.

18.2.8 DMA Support

18.2.9 Break Generation and Detection

or longer after a missing stop bit is detected.

18.2.10 Parity Generation and Detection

abled and disabled using the PEN bit in the UFRS register.

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18.3 UART REGISTERS

Software interacts with th e UART by accessing the UART registers. There are eight registers, as listed in Table 57.

18.3.1 UART Receive Data Buffer (URBUF)

The URBUF register is a byte-wide, read/write register used to receive each data byte.

18.3.2 UART Transmit Data Buffer (UTBUF)

The UTBUF register is a byte-wide, read/write register used to transmit each data byte.

18.3.3 UART Baud Rate Prescaler (UPSR)

The UPSR register is a byte-w ide, read/write register that contains the 5-bit clock prescaler and the upper three bits of the baud rate divisor. This register is cleared upon reset. The register format is shown below. UPSC The Prescaler field specifies the prescaler val- ue used for dividing the System Clock in the first stage of the two-stage divider chain. For the prescaler factors corresponding to each 5- bit value, see Table 56. UDIV10:8 The Baud Rate Divisor field holds the three most significant bits (bit s 10, 9, and 8) of the UART baud rate divisor used in the second stage of the two-stage divider chain. The re- maining bits of the baud rate divisor are held in the UBAUD register.

18.3.4 UART Baud Rate Divisor (UBAUD)

The UBAUD register is a byte-wide, read/write register that contains the lower eight bits of the baud rate divisor. The register contents are unknown at power-up and are left un- changed by a reset operation. The register format is shown below. UDIV7:0 The Baud Rate Divisor field holds the eight lowest-order bits of the UART baud rate divi- sor used in the second stage of the two-stage divider chain. The thr ee most significant bits are held in the UPSR register. The divisor val- ue used is (UDIV[10:0] + 1).

18.3.5 UART Frame Select Register (UFRS)

The UFRS register is a byte-w ide, read/write register that controls the frame format, including the number of data bits, number of stop bits, and parity type. This register is cleared upon reset. The register format is shown below. UCHAR The Character Frame Format field selects the number of data bits per frame, not including the parity bit, as follows: 00 – 8 data bits per frame. 01 – 7 data bits per frame. 10 – 9 data bits per frame. 11 – Loop-back mode, 9 data bits per frame. Table 57 UART Registers Name Address Description URBUF FF FE42h UART Receive Data Buffer UTBUF FF FE40h UART Transmit Data Buffer UPSR FF FE4Eh UART Baud Rate Prescaler UBAUD FF FE4Ch UART Baud Rate Divisor UFRS FF FE48h UART Frame Select Register UMDSL1 FF FE4Ah UART Mode Select Register 1 USTAT FF FE46h UART Status Register UICTRL FF FE44h UART Interrupt Control Register UOVR FF FE50h UART Oversample Rate Register UMDSL2 FF FE52h UART Mode Select Register 2 USPOS FF FE54h UART Sample Position Register 7 0 URBUF 7 0 UTBUF 7 3 2 0 UPSC UDIV10:8 7 0 UDIV7:0 7 6 5 4 3 2 1 0 Reserved UPEN UPSEL UXB9 USTP UCHAR

www.national.com 128 CP3CN17 USTP The Stop Bits bit spec ifies the number of stop bits transmitted in each frame. If this bit is 0, one stop bit is transmitted. If this bit is 1, two stop bits are transmitted. 0 – One stop bit per frame. 1 – Two stop bits per frame. UXB9 The Transmit 9th Data Bit holds the value of the ninth data bit, eit her 0 or 1, transmitted when the UART is configured to transmit nine data bits per frame. It has no effect when the UART is configured to transmit seven or eight data bits per frame. UPSEL The Parity Select fiel d selects the treatment of the parity bit. When the UART is configured to transmit nine data bits per frame, the parity bit is omitted and the UPSEL field is ignored. 00 – Odd parity. 01 – Even parity. 10 – No parity, transmit 1 (mark). 11 – No parity, transmit 0 (space). UPEN The Parity Enable bit enables or disables par- ity generation and parity checking. When the UART is configured to transmit nine data bits per frame, there is no parity bit and the UPEN bit is ignored. 0 – Parity generation and checking disabled. 1 – Parity generation and checking enabled.

18.3.6 UART Mode Select Register 1 (UMDSL1)

The UMDSL1 register is a byte-wide, read/write register that selects the clock source, synchronization mode, attention mode, and line break generation. This register is cleared at reset. The register format is shown below. UMOD The Mode bit selects between synchronous and asynchronous mode. 0 – Asynchronous mode. 1 – Synchronous mode. UATN The Attention Mode bit is used to enable At- tention mode. When set, this bit selects the at- tention mode of operation for the UART. When clear, the attention mode is disabled. The hardware clears this bit after an address frame is received. An address frame is a 9-bit character with a 1 in the ninth bit position. 0 – Attention mode disabled. 1 – Attention mode enabled. UBRK The Force Transmission Break bit is used to force the TXD output low. Setting this bit to 1 causes the TXD pin to go low. TXD remains low until the UBRK bit is cleared by software. 0 – Normal operation. 1 – TXD pin forced low. UCKS The Synchronous Clock Source bit controls the clock source when the UART operates in the synchronous mode (UMOD = 1). If the UCKS bit is set, the UART operates from an external clock provided on the CKX pin. If the UCKS bit is clear, the UART operates from the baud rate clock produced by the UART on the CKX pin. This bit is ignored when the UART operates in the asynchronous mode. 0 – Internal baud rate clock is used. 1 – External clock is used. UETD The Enable Transmit DMA bit controls wheth- er DMA is used for UART transmit operations. Enabling transmit DMA automatically disables transmit interrupts, without regard to the state of the UETI bit. 0 – Transmit DMA disabled. 1 – Transmit DMA enabled. UERD The Enable Receive DMA bit controls whether DMA is used for UART receive operations. Enabling receive DMA automatically disables receive interrupts, without regard to the state of the UERI bit. Receive error interrupts are unaffected by the UERD bit. 0 – Receive DMA disabled. 1 – Receive DMA enabled. UFCE The Flow Control Enable bit controls whether flow control interrupts are enabled. 0 – Flow control interrupts disabled. 1 – Flow control interrupts enabled. URTS The Ready To Send bit directly controls the state of the RTS output. 0 – RTS output is high. 1 – RTS output is low.

18.3.7 UART Status Register (USTAT)

The USTAT register is a byte-wide, read-only register that contains the receive and transmit status bits. This register is cleared upon reset. Any attempt by software to write to this register is ignored. The register format is shown below. UPE The Parity Error bit indicates whether a parity error is detected within a received character. This bit is automatically cleared by the hard- ware when the USTAT register is read. 0 – No parity error occurred. 1 – Parity error occurred. UFE The Framing Error bit indicates whether the UART fails to receive a valid stop bit at the end of a frame. This bit is automatically cleared by the hardware when the USTAT register is read. 0 – No framing error occurred. 1 – Framing error occurred. 7 6 5 4 3 2 1 0 URTS UFCE UERD UETD UCKS UBRK UATN UMOD 7 6 5 4 3 2 1 0 Res. UXMIP URB9 UBKD UERR UDOE UFE UPE

129 www.national.com CP3CN17 UDOE The Data Overrun Error bit is set when a new character is received and transferred to the URBUF register before software has read the previous character from the URBUF register. This bit is automatically cleared by the hard- ware when the USTAT register is read. 0 – No receive overrun error occurred. 1 – Receive overrun error occurred. UERR The Error Status bit indicates when a parity, framing, or overrun error occurs (any time that the UPE, UFE, or UDOE bit is set). It is auto- matically cleared by the hardware when the UPE, UFE, and UDOE bits are all 0. 0 – No receive error occurred. 1 – Receive error occurred. UBKD The Break Detect bit indicates when a line break condition occurs. This condition is de- tected if RXD remains low for at least ten bit times after a missing stop bit has been detect- ed at the end of a frame. The hardware auto- matically clears the UBKD bit upon read of the USTAT register, but only if the break condition on RXD no longer exists. If reading the USTAT register does not clear the UBKD bit because the break is still actively driven on the line, the hardware clears the bit as soon as the break condition no longer exists (when the RXD in- put returns to a high level). 0 – No break condition occurred. 1 – Break condition occurred. URB9 The Received 9th Data Bit holds the ninth data bit, when the UART is configured to op- erate in the 9-bit data format. UXMIP The Transmit In Progress bit indicates when the UART is transmitting. The hardware sets this bit when the UART is transmitting data and clears the bit at the end of the last frame bit. 0 – UART is not transmitting. 1 – UART is transmitting.

18.3.8 UART Interrupt Control Register (UICTRL)

The UICTRL register is a byte -wide register that contains the receive and transmit interrupt status bits (read-only bits) and the interrupt enable bits (read/write bits). The register is initialized to 01h at reset. The register format is shown be- low. UTBE The Transmit Buffer Empty bit is set by hard- ware when the UART transfers data from the UTBUF register to the transmit shift register for transmission. It is automatically cleared by the hardware on the next write to the UTBUF register. 0 – Transmit buffer is loaded. 1 – Transmit buffer is empty. URBF The Receive Buffer Full bit is set by hardware when the UART has received a complete data frame and has transferred the data from the receive shift register to the URBUF register. It is automatically cleared by the hardware when the URBUF register is read. 0 – Receive buffer is empty. 1 – Receive buffer is loaded. UDCTS The Delta Clear To Send bit indicates whether the CTS input has changed state since the CPU last read this register. 0 – No change since last read. 1 – State has changed since last read. UCTS The Clear To Send bit indicates the state on the CTS input. 0 – CTS input is high. 1 – CTS input is low. UEFCI The Enable Flow Control Interrupt bit controls whether a flow control interrupt is generated when the UDCTS bit changes from clear to set. 0 – Flow control interrupt disabled. 1 – Flow control interrupt enabled. UETI The Enable Transmitter Interrupt bit, when set, enables generation of an interrupt when the hardware sets the UTBE bit. 0 – Transmit buffer empty interrupt disabled. 1 – Transmit buffer empty interrupt enabled. UERI The Enable Receiver Interrupt bit, when set, enables generation of an interrupt when the hardware sets the URBF bit. 0 – Receive buffer full interrupt disabled. 1 – Receive buffer full interrupt enabled. UEEI The Enable Receive Error Interrupt bit, when set, enables generation of an interrupt when the hardware sets the UERR bit in the USTAT register. 0 – Receive error interrupt disabled. 1 – Receive error interrupt enabled. 7 6 5 4 3 2 1 0 UEEI UERI UETI UEFCI UCTS UDCTS URBF UTBE

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18.3.9 UART Oversample Rate Register (UOVR)

The UOVR register is a byte-wide, read/write register that specifies the oversample rate. At reset, the UOVR register is cleared. The register format is shown below. UOVSR The Oversampling Rate field specifies the oversampling rate, as given in the following ta- ble.

18.3.10 UART Mode Select Register 2 (UMDSL2)

The UMDSL2 register is a byte-wide, read/write register that controls the sample mode used to recover asynchronous data. At reset, the UOVR register is cleared. The register format is shown below. USMD The USMD bit controls the sample mode for asynchronous transmission. 0 – UART determines the sample position au- tomatically. 1 – The USPOS register determines the sam- ple position.

18.3.11 UART Sample Posi tion Register (USPOS)

The USPOS register is a byte-wide, read/write register that specifies the sample position when the USMD bit in the UMDSL2 register is set. At reset, the USPOS register is ini- tialized to 06h. The register format is shown below. USAMP The Sample Position field specifies the over- sample clock period at which to take the first of three samples for sensing the value of data bits. The clocks are numbered starting at 0 and may range up to 15 for 16× oversampling. The maximum value for this field is (oversam- pling rate - 3). The table below shows the clock period at which each of the three sam- ples is taken, when automatic sampling is en- abled (UMDSL2.USMD = 0). The USAMP field may be used to override the automatic selection, to choose any other clock period at which to start taking the three sam- ples. 7 4 3 0 Reserved UOVSR UOVSR3:0 Oversampling Rate 0000–0110 16 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 7 1 0 Reserved USMD 7 4 3 0 Reserved USAMP Oversampling Rate Sample Position 123 72 3 4 82 3 4 93 4 5 10 3 4 5 11 4 5 6 12 4 5 6 13 5 6 7 14 5 6 7 15 6 7 8 16 6 7 8

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18.4 BAUD RATE CALCULATIONS

The UART baud rate is determined by the System Clock fre- quency and the values in the UOVR, UPSR, and UBAUD registers. Unless the System Clock is an exact multiple of the baud rate, there will be a small amount of error in the re- sulting baud rate.

18.4.1 Asynchronous Mode

The equation to calculate the baud rate in asynchronous mode is: where BR is the baud rate, SYS_CLK is the System Clock, O is the oversample rate, N is the baud rate divisor + 1, and P is the prescaler divisor selected by the UPSR register. Assuming a System Clock of 5 MHz, a desired baud rate of 9600, and an oversample rate of 16, the N × P term accord- ing to the equation above is: The N × P term is then divided by each Prescaler Factor from Table 56 to obtain a value closest to an integer. The factor for this example is 6.5. The baud rate register is programmed with a baud rate divi- sor of 4 (N = baud rate divisor + 1). This produces a baud clock of: Note that the percent error is much lower than would be pos- sible without the non-integer prescaler factor. Error greater than 3% is marginal and may result in unreliable operation. Refer to Table 58 below for more examples.

18.4.2 Synchronous Mode

When synchronous mode is selected and the UCKS bit is set, the UART operates from a clock received on the CKX pin. When the UCKS bit is clear, the UART uses the clock from the internal baud rate generator which is also driven on the CKX pin. When the internal baud rate generator is used, the equation for calculating the baud rate is: where BR is the baud rate, SYS_CLK is the System Clock, N is the value of the baud rate divisor + 1, and P is the pres- caler divide factor selected by the value in the UPSR regis- ter. Oversampling is not used in synchronous mode. Use the same procedure to determine the values of N and P as in the asynchronous mode. In this case, however, only integer prescaler values are allowed. BR SYS_CLK NP× 5 6×10() N 32.552 BR 5 6×10() %error 9615.385 9600–() BR SYS_CLK

www.national.com 132 CP3CN17 Table 58 Baud Rate Programming Baud Rate SYS_CLK = 48 MHz SYS_CLK = 24 MHz SYS_CLK = 12 MHz SYS_CLK = 10 MHz O N P %err O N P %err O N P %err O N P %err 1382400 10 1 3.5 0.79 7 1 2.5 0.79 1536000 9 1 3.5 0.79 8 2 1.0 2.34

133 www.national.com CP3CN17 Table 59 Baud Rate Programming Baud Rate SYS_CLK = 8 MHz SYS_CLK = 6 MHz SYS_CLK = 5 MHz SYS_CLK = 4 MHz O N P %err O N P %err O N P %err O N P %err 345600 15 1 1.5 2.88 7 1 2.5 0.79 460800 7 1 2.5 0.79 13 1 1.0 0.16 576000 7 2 1.0 0.79 7 1 1.5 0.79 Baud Rate SYS_CLK = 3 MHz SYS_CLK = 2 MHz SYS_ CLK = 1 MHz SYS_CLK = 500 kHz O N P %err O N P %err O N P %err O N P %err 115200 13 2 1.0 0.16 7 1 2.5 0.79 128000 16 1 1.5 2.34 8 2 1.0 2.34 230400 13 1 1.0 0.16

19.0 Microwire/SPI Interface

communicating with peripherals. Figure 61. Microwire Interface

19.1 MICROWIRE OPERATION

slave mode), and the serial clock (MSK). its own chip select signal (MWCS) for this purpose. serial interface in the device.

Figure 62. Microwire Block Diagram

19.1.1 Shifting

The Microwire interface is a full duplex transmitter/receiver. starting with the most significant bit first.

19.1.2 Reading

is full and a new data transfer sequence starts. read buffer’s higher byte remains unchanged.

19.1.3 Writing

MWDAT register is written to while the BSY bit is set.

19.1.4 Clocking Modes

is sampled on the falling edge of MSK. clock frequencies can be programmed via the MCDV bits.

19.2 MASTER MODE

low, depending on the SCIDL bit. Figure 63. Normal Mode (SCIDL = 0) Figure 64. Normal Mode (SCIDL = 1) Figure 65. Alternate Mode (SCIDL = 0)

Figure 66. Alternate Mode (SCIDL = 1)

19.3 SLAVE MODE

inactive. Data transfer is enabled when MWCS is active. The slave starts driving MDIDO when MWCS is activated. the data transfer is completed. synchronize the bit count between the master and the slave.

19.4 INTERRUPT GENERATION

terrupt for Read” bit is set (EIR = 1). usage is restricted to master mode. Figure 67. MWSPI Interrupts

19.5 MICROWIRE INTERFACE REGISTERS

19.5.1 Microwire Data Register (MWDAT)

Figure 68. MWDAT Register

19.5.2 Microwire Control Register (MWCTL1)

bits are cleared. The register format is shown below. Microwire interface module is enabled. 0 – Microwire module disabled. 1 – Microwire module enabled. set, the device operates as the master. whether or not the data is valid. ceive Overrun Error bit (MWSTAT.OVR) is set. 0 – Disable overrun error interrupts. 1 – Enable overrun error interrupts.

139 www.national.com CP3CN17 EIR The Enable Interrupt for Read bit controls whether an interrupt is generated when the read buffer becomes full. When set, an inter- rupt is generated when the Read Buffer Full bit (MWSTAT.RBF) is set. Otherwise, no inter- rupt is generated when the read buffer is full. 0 – No read buffer full interrupt. 1 – Interrupt when read buffer becomes full. EIW The Enable Interrupt for Write bit controls whether an interrupt is generated when the Busy bit (MWSTAT.BSY) is cleared, which in- dicates that a data transfer sequence has been completed and the read buffer is ready to receive the new data. Otherwise, no inter- rupt is generated when the Busy bit is cleared. 0 – No interrupt on da ta transfer complete. 1 – Interrupt on data transfer complete. SCM The Shift Clock Mode bit selects between the normal clocking mode and the alternate clock- ing mode. In the normal mode, the output data is clocked out on the falling edge of MSK and the input data is sampled on the rising edge of MSK. In the alternate mode, the output data is clocked out on the rising edge of MSK and the input data is sampled on the falling edge of MSK. 0 – Normal clocking mode. 1 – Alternate clocking mode. SCIDL The Shift Clock Idle bit controls the value of the MSK output when the Microwire module is idle. This bit must be changed only when the Microwire module is disabled (MWEN = 0) or when no bus transaction is in progress (MW- STAT.BSY = 0). 0 – MSK is low when idle. 1 – MSK is high when idle SCDV The Shift Clock Divider Value field specifies the divisor used for generating the MSK shift clock from the System Clock. The divisor is 2 × (MCDV[6:0] + 1). Valid values are 0000001b to 1111111b, so the division ratio may range from 3 to 256. This field is ignored in slave mode (MWCTL1.MMNS=0).

19.5.3 Microwire Status Register (MWSTAT)

The MWSTAT register is a word-wide, read-only register that shows the current status of the Microwire interface module. At reset, all non-reserved bits are clear. The regis- ter format is shown below. BSY The Busy bit, when set, indicates that the Mi- crowire shifter is busy. In master mode, the BSY bit is set when the MWDAT register is written. In slave mode, the bit is set on the first leading edge of MSK when MWCS is assert- ed or when the MWDAT register is written, whichever occurs first. In both master and slave modes, this bit is cleared when the Mi- crowire data transfer sequence is completed and the read buffer is ready to receive the new data; in other words, when the previous data held in the read buffer has already been read. If the previous data in the read buffer has not been read and new data has been received into the shift register, the BSY bit will not be cleared, as the transfer could not be complet- ed because the contents of the shift register could not be transferred into the read buffer. 0 – Microwire shifter is not busy. 1 – Microwire shifter is busy. RBF The Read Buffer Full bit, when set, indicates that the Microwire read buffer is full and ready to be read by software. It is set when the shifter loads the read buffer, which occurs upon completion of a transfer sequence if the read buffer is empty. The RBF bit is updated when the MWDAT register is read. At that time, the RBF bit is cleared if the shifter does not contain any new data (in other words, the shifter is not receiving data or has not yet re- ceived a full byte of data). The RBF bit re- mains set if the shifter already holds new data at the time that MWDAT is read. In that case, MWDAT is immediately reloaded with the new data and is ready to be read by software. 0 – Microwire read buffer is not full. 1 – Microwire read buffer is full. OVR The Receive Overrun Error bit, when set in master mode, indicates that a receive overrun error has occurred. This error occurs when the read buffer is full, the 8-bit shifter is full, and a new data transfer sequence starts. This bit is undefined in slave mode. The OVR bit, once set, remains set until cleared by soft- ware. Software clears this bit by writing a 1 to its bit position. Writing a 0 to this bit position has no effect. No other bits in the MWSTAT register are affected by a write operation to the register. 0 – No receive overrun error has occurred. 1 – Receive overrun error has occurred. 15 3 2 1 0 Reserved OVR RBF BSY

with both multiple master and slave devices. its implementation by the module.

20.1 ACB PROTOCOL OVERVIEW

resistors, to keep the signals high when the bus is idle. ceiver (though some peripherals are only receivers).

20.1.1 Data Transactions

sampled during the high phase of the serial clock (SCL). data must be driven during the low phase of the SCL clock. Figure 69. Bit Transfer byte, an Acknowledge signal must follow. by the slave holding SCL low to extend the clock-low period. after each bit, to allow software time to handle this bit. Figure 70. Start and Stop Conditions rection of the data transfer.

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20.2 ACB FUNCTIONAL DESCRIPTION

The ACB module provides the physical layer for an AC- CESS.bus compliant serial interface. The module is config- urable as either a master or slave device. As a slave, the ACB module may issue a request to become the bus mas- ter.

20.2.1 Master Mode

An ACCESS.bus transaction starts with a master device re- questing bus mastership. It sends a Start Condition, fol- lowed by the address of the device it wants to access. If this transaction is successfully completed, software can assume that the device has become the bus master. For a device to become the bus master, software should perform the following steps: 1. Set the ACBCTL1.START bit, and configure the ACBCTL1.INTEN bit to the desired operation mode (Polling or Interrupt). This causes the ACB to issue a Start Condition on the ACCESS.bus, as soon as the ACCESS.bus is free (ACBCST.BB=0). It then stalls the bus by holding SCL low. 2. If a bus conflict is dete cted, (i.e., some other device pulls down the SCL signal before this device does), the ACBST.BER bit is set. 3. If there is no bus conflict, the ACBST.MASTER and ACBST.SDAST bits are set. 4. If the ACBCTL1.INTEN bit is set, and either the ACB- ST.BER bit or the ACBST.SDAST bit is set, an interrupt is sent to the ICU. Sending the Address Byte Once this device is the active master of the ACCESS.bus (ACBST.MASTER = 1), it can send the address on the bus. The address should not be this device’s own address as specified in the ACBADDR.ADDR field if the ACBAD- DR.SAEN bit is set or the ACBADDR2.ADDR field if the ACBADDR2.SAEN bit is set, nor should it be the global call address if the ACBST.GCMTCH bit is set. To send the address byte use the following sequence: 1. Configure the ACBCTL1.INTEN bit according to the de- sired operation mode. For a receive transaction where software wants only one byte of data, it should set the ACBCTL1.ACK bit. If only an address needs to be sent, set the ACBCTL1.STASTRE bit. 2. Write the address byte (7-bit target device address), and the direction bit, to the ACBSDA register. This causes the module to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to the ACBST.NEGACK bit. During the transac- tion, the SDA and SCL signals are continuously checked for conflict with other devices. If a conflict is detected, the transaction is aborted, the ACBST.BER bit is set, and the ACBST.MASTER bit is cleared. 3. If the ACBCTL1.STASTRE bit is set, and the transac- tion was successfully comple ted (i.e., both the ACB- ST.BER and ACBST.NEGACK bits are cleared), the ACBST.STASTR bit is set. In this case, the ACB stalls any further ACCESS.bus operations (i.e., holds SCL low). If the ACBCTL1.INTE bit is set, it also sends an interrupt to the ICU. 4. If the requested direction is transmit, and the start transaction was completed successfully (i.e., neither the ACBST.NEGACK nor ACBST.BER bit is set, and no other master has accessed the device), the ACB- ST.SDAST bit is set to indicate that the module is wait- ing for service. 5. If the requested direction is receive, the start transac- tion was completed successfully, and the ACBCTL1.STASTRE bit is clear, the module starts re- ceiving the first byte automatically. 6. Check that both the ACBST.BER and ACBST.NEGACK bits are clear. If the ACBCTL1.INTEN bit is set, an in- terrupt is generated when either the ACBST.BER or ACBST.NEGACK bit is set. Master Transmit After becoming the bus master, the device can start trans- mitting data on the ACCESS.bus. To transmit a byte, soft- ware must: 1. Check that the BER and NEGACK bits in the ACBST register are clear and the ACBST.SDAST bit is set. Al- so, if the ACBCTL1.STASTRE bit is set, check that the ACBST.STASTR bit is clear. 2. Write the data byte to be transmitted to the ACBSDA register. When the slave responds with a negative acknowledge, the ACBST.NEGACK bit is set and the ACBST.SDAST bit re- mains cleared. In this case, if the ACBCTL1.INTEN bit is set, an interrupt is sent to the core. Master Receive After becoming the bus master, the device can start receiv- ing data on the ACCESS.bus. To receive a byte, software must: 1. Check that the ACBST.SDAST bit is set and the ACB- ST.BER bit is clear. Also, if the ACBCTL1.STASTRE bit is set, check that the ACBST.STASTR bit is clear. 2. Set the ACBCTL1.ACK bit, if the next byte is the last byte that should be read. This causes a negative ac- knowledge to be sent. 3. Read the data byte from the ACBSDA register. Master Stop A Stop Condition may be issued only when this device is the active bus master (ACBST.MASTRER = 1). To end a trans- action, set the ACBCTL1.STOP bit before clearing the cur- rent stall bit (i.e., the ACBST.SDAST, ACBST.NEGACK, or ACBST.STASTR bit). This causes the module to send a Stop Condition immediately, and clear the ACBCTL1.STOP bit. Master Bus Stall The ACB module can stall the ACCESS.bus between trans- fers while waiting for the core’s response. The ACCESS.bus is stalled by holding the SCL signal low after the acknowl- edge cycle. Note that this is interpreted as the beginning of the following bus operation. Software must make sure that the next operation is prepared before the bit that causes the bus stall is cleared.

143 www.national.com CP3CN17 The bits that can cause a stall in master mode are: „ Negative acknowledge after sending a byte (ACBSTNEGACK = 1). „ ACBST.SDAST bit is set. „ If the ACBCTL1.STASTRE bit is set, after a successful start (ACBST.STASTR = 1). Repeated Start A repeated start is performed when this device is already the bus master (ACBST.MASTER = 1). In this case, the AC- CESS.bus is stalled and the ACB waits for the core handling due to: negative acknowledge (ACBST.NEGACK = 1), emp- ty buffer (ACBST.SDAST = 1), or a stop-after-start (ACB- ST.STASTR = 1). For a repeated start: 1. Set the ACBCTL1.START bit. 2. In master receive mode, r ead the last data item from the ACBSDA register. 3. Follow the address send sequence, as described in “Sending the Address Byte” on page 142. 4. If the ACB was waiting for handling due to ACB- ST.STASTR = 1, clear it only after writing the requested address and direction to the ACBSDA register. Master Error Detections The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer, or the ac- knowledge cycle) and a conflict on the data lines of the AC- CESS.bus. If an illegal action is detected, the BER bit is set, and the MASTER mode is exited (the MASTER bit is cleared). Bus Idle Error Recovery When a request to become the active bus master or a re- start operation fails, the ACBST.BER bit is set to indicate the error. In some cases, both this device and the other device may identify the failure and leave the bus idle. In this case, the start sequence may not be completed and the AC- CESS.bus may remain deadlocked. To recover from deadlock, use the following sequence: 1. Clear the ACBST.BER and ACBCST.BB bits. 2. Wait for a time-out period to check that there is no other active master on the bus (i.e., the ACBCST.BB bit re- mains clear). 3. Disable, and re-enable the ACB to put it in the non-ad- dressed slave mode. 4. At this point, some of the slaves may not identify the bus error. To recover, the ACB becomes the bus master by issuing a Start Condition and sends an address field; then issue a Stop Condition to synchronize all the slaves.

20.2.2 Slave Mode

A slave device waits in Idle mode for a master to initiate a bus transaction. Whenever the ACB is enabled, and it is not acting as a master (i.e., ACBST.MASTER = 0), it acts as a slave device. Once a Start Condition on the bus is detected, this device checks whether the address sent by the current master matches either: „ The ACBADDR.ADDR value if the ACBADDR.SAEN bit is set. „ The ACBADDR2.ADDR value if the ACBADDR2.SAEN bit is set. „ The general call address if the ACBCTL1.GCM bit is set. This match is checked even when the ACBST.MASTER bit is set. If a bus conflict (on SDA or SCL) is detected, the ACBST.BER bit is set, the ACBST.MASTER bit is cleared, and this device continues to search the received message for a match. If an address match, or a global match, is de- tected: 1. This device asserts its data pin during the acknowledge cycle. 2. The ACBCST.MATCH, ACBCST.MATCHAF (or ACBCST.GCMTCH if it is a global call address match, or ACBCST.ARPMATCH if it is an ARP address) and ACBST.NMATCH in the ACBCST register are set. If the ACBST.XMIT bit is set (i.e., slave transmit mode), the ACBST.SDAST bit is set to indicate that the buffer is empty. 3. If the ACBCTL1.INTEN bit is set, an interrupt is gener- ated if both the INTEN and NMINTE bits in the ACBCTL1 register are set. 4. Software then reads the ACBST.XMIT bit to identify the direction requested by the master device. It clears the ACBST.NMATCH bit so future byte transfers are identi- fied as data bytes. Slave Receive and Transmit Slave Receive and Transmit are performed after a match is detected and the data transfer direction is identified. After a byte transfer, the ACB extends the acknowledge clock until software reads or writes the ACBSDA register. The receive and transmit sequence are identical to those used in the master routine. Slave Bus Stall When operating as a slave, this device stalls the AC- CESS.bus by extending the first clock cycle of a transaction in the following cases: — The ACBST.SDAST bit is set. — The ACBST.NMATCH, and ACBCTL1.NMINTE bits are set. Slave Error Detections The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition within the data transfer or the acknowledge cycle). When an illegal Start or Stop Condition is detected, the BER bit is set and the MATCH and GMATCH bits are cleared, causing the module to be an unaddressed slave.

www.national.com 144 CP3CN17 Power Down When this device is in Power Save, Idle, or Halt mode, the ACB module is not active but retains its status. If the ACB is enabled (ACBCTL2.ENABLE = 1) on detection of a Start Condition, a wake-up signal is issued to the MIWU module (see Section 13.0). Use this signal to switch this device to Active mode. The ACB module cannot check the address byte for a match following the start condition that caused the wake-up event for this device. The ACB responds with a negative acknowl- edge, and the device should resend both the Start Condition and the address after this device has had time to wake up. Check that the ACBCST.BUSY bit is inactive before entering Power Save, Idle, or Halt mode. This guarantees that the de- vice does not acknowledge an address sent and stop re- sponding later.

20.2.3 SDA and SCL Pins Configuration

The SDA and SCL pins are driven as open-drain signals. For more information, see the I/O configuration section.

20.2.4 ACB Clock Frequency Configuration

The ACB module permits software to set the clock frequen- cy used for the ACCESS.bus clock. The clock is set by the ACBCTL2.SCLFRQ field. This field determines the SCL clock period used by this device. This clock low period may be extended by stall periods initiated by the ACB module or by another ACCESS.bus device. In case of a conflict with another bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved. 20.3 ACCESS.BUS INTERFACE REGISTERS The ACCESS.bus interface uses the registers listed in Table 61.

20.3.1 ACB Serial Data Register (ACBSDA)

The ACBSDA register is a byte-wide, read/write shift regis- ter used to transmit and receive data. The most significant bit is transmitted (received) first and the least significant bit is transmitted (received) last. Reading or writing to the ACB- SDA register is allowed when ACBST.SDAST is set; or for repeated starts after setting the START bit. An attempt to access the register in other cases produces unpredictable results.

20.3.2 ACB Status Register (ACBST)

The ACBST register is a byte-wide, read-only register that maintains current ACB status. At reset, and when the mod- ule is disabled, ACBST is cleared. XMIT The Direction Bit bit is set when the ACB mod- ule is currently in master/slave transmit mode. Otherwise it is cleared. 0 – Receive mode. 1 – Transmit mode. Table 61 ACCESS.bus In terface Registers Name Address Description ACBSDA FF FEC0h ACB Serial Data Register ACBST FF FEC2h ACB Status Register ACBCST FF FEC4h ACB Control Status Register ACBCTL1 FF FEC6h ACB Control Register 1 ACBCTL2 FF FECAh ACB Control Register 2 ACBCTL3 FF FECEh ACB Control Register 3 ACBADDR1 FF FEC8h ACB Own Address Register 1 ACBADDR2 FF FECCh ACB Own Address Register 2 7 0 DATA 7 6 5 4 3 2 1 0 SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT

145 www.national.com CP3CN17 MASTER The Master bit indi cates that the module is currently in master mode. It is set when a re- quest for bus mastership succeeds. It is cleared upon arbitration loss (BER is set) or the recognition of a Stop Condition. 0 – Slave mode. 1 – Master mode. NMATCH The New match bit is set when the address byte following a Start Condition, or repeated starts, causes a match or a global-call match. The NMATCH bit is cleared when written with 1. Writing 0 to NMATCH is ignored. If the ACBCTL1.INTEN bit is set, an interrupt is sent when this bit is set. 0 – No match. 1 – Match or global-call match. STASTR The Stall After Start bit is set by the successful completion of an address sending (i.e., a Start Condition sent without a bus error, or negative acknowledge), if the ACBCTL1.STASTRE bit is set. This bit is ignored in slave mode. When the STASTR bit is set, it stalls the bus by pull- ing down the SCL line, and suspends any oth- er action on the bus (e.g., receives first byte in master receive mode). In addition, if the ACBCTL1.INTEN bit is set, it also sends an interrupt to the ICU. Writing 1 to the STASTR bit clears it. It is also cleared when the module is disabled. Writing 0 to the STASTR bit has no effect. 0 – No stall after start condition. 1 – Stall after successful start. NEGACK The Negative Acknowledge bit is set by hard- ware when a transmission is not acknowl- edged on the ninth clock. (In this case, the SDAST bit is not set.) Writing 1 to NEGACK clears it. It is also cleared when the module is disabled. Writing 0 to the NEGACK bit is ig- nored. 0 – No transmission not acknowledged condi- tion. 1 – Transmission not acknowledged. BER The Bus Error bit is set by the hardware when a Start or Stop Condition is detected during data transfer (i.e., Start or Stop Condition dur- ing the transfer of bits 2 through 8 and ac- knowledge cycle), or when an arbitration problem is detected. Writing 1 to the BER bit clears it. It is also cleared when the module is disabled. Writing 0 to the BER bit is ignored. 0 – No bus error occurred. 1 – Bus error occurred. SDAST The SDA Status bit indicates that the SDA data register is waiting for data (transmit, as master or slave) or holds data that should be read (receive, as master or slave). This bit is cleared when reading from the ACBSDA reg- ister during a receive, or when written to dur- ing a transmit. When the ACBCTL1.START bit is set, reading the ACBSDA register does not clear the SDAST bit. This enables the ACB to send a repeated start in master receive mode. 0 – ACB module is not waiting for data trans- fer. 1 – ACB module is waiting for data to be load- ed or unloaded. SLVSTP The Slave Stop bit indicates that a Stop Con- dition was detected after a slave transfer (i.e., after a slave transfer in which MATCH or GCMATCH is set). Writing 1 to SLVSTP clears it. It is also cleared when the module is dis- abled. Writing 0 to SLVSTP is ignored. 0 – No stop condition after slave transfer oc- curred. 1 – Stop condition after slave transfer oc- curred.

20.3.3 ACB Control Status Register (ACBCST)

The ACBCST register is a byte-wide, read/write register that maintains current ACB status. At reset and when the mod- ule is disabled, the non-reserved bits of ACBCST are cleared. BUSY The BUSY bit indicates that the ACB module is: „ Generating a Start Condition „ In Master mode (ACBST.MASTER is set) „ In Slave mode (ACBCST.MATCH or ACBCST.GCMTCH is set) „ In the period between detecting a Start and completing the reception of the ad- dress byte. After this, the ACB either be- comes not busy or enters slave mode. The BUSY bit is cleared by the completion of any of the above states, and by disabling the module. BUSY is a read only bit. It must al- ways be written with 0. 0 – ACB module is not busy. 1 – ACB module is busy. 7 6 5 4 3 2 1 0 Reserved TGSCL TSDA GCMTCH MATCH BB BUSY

www.national.com 146 CP3CN17 BB The Bus Busy bit indica tes the bus is busy. It is set when the bus is active (i.e., a low level on either SDA or SCL) or by a Start Condition. It is cleared when the module is disabled, on detection of a Stop Condition, or when writing 1 to this bit. See “Usage Hints” on page 148 for a description of the use of this bit. This bit should be set when either the SDA or SCL sig- nals are low. This is done by sampling the SDA and SCL signals continuously and set- ting the bit if one of them is low. The bit re- mains set until cleared by a STOP condition or written with 1. 0 – Bus is not busy. 1 – Bus is busy. MATCH The Address Match bit indicates in slave mode when ACBADDR.SAEN is set and the first seven bits of the address byte (the first byte transferred after a Start Condition) matches the 7-bit address in the ACBADDR register, or when ACBADDR2.SAEN is set and the first seven bits of the address byte matches the 7-bit address in the ACBADDR2 register. It is cleared by Start Condition or re- peated Start and Stop Condition (including il- legal Start or Stop Condition). 0 – No address match occurred. 1 – Address match occurred. GCMTCH The Global Call Match bit is set in slave mode when the ACBCTL1.GCMEN bit is set and the address byte (the first byte transferred after a Start Condition) is 00h. It is cleared by a Start Condition or repeated Start and Stop Condi- tion (including illegal Start or Stop Condition). 0 – No global call match occurred. 1 – Global call match occurred. TSDA The Test SDA bit samples the state of the SDA signal. This bit can be used while recovering from an error condition in which the SDA sig- nal is constantly pulled low by a slave that went out of sync. This bit is a read-only bit. Data written to it is ignored. TGSCL The Toggle SCL bit enables toggling the SCL signal during error recovery. When the SDA signal is low, writing 1 to this bit drives the SCL signal high for one cycle. Writing 1 to TGSCL when the SDA signal is high is ignored. The bit is cleared when the clock toggle is completed. 0 – Writing 0 has no effect. 1 – Writing 1 toggles the SDA signal high for one cycle.

20.3.4 ACB Control Register 1 (ACBCTL1)

The ACBCTL1 register is a byte-wide, read/write register that configures and controls the ACB module. At reset and while the module is disabled (ACBCTL2.ENABLE = 0), the ACBCTL1 register is cleared. START The Start bit is set to generate a Start Condi- tion on the ACCESS.bus. The START bit is cleared when the Start Condition is sent, or upon detection of a Bus Error (ACBST.BER = 1). This bit should be set only when in Master mode, or when requesting Master mode. If this device is not the active master of the bus (ACBST.MASTER = 0), set- ting the START bit generates a Start Condition as soon as the ACCESS.bus is free (ACBCST.BB = 0). An address send se- quence should then be performed. If this de- vice is the active master of the bus (ACBST.MASTER = 1), when the START bit is set, a write to the ACBSDA register generates a Start Condition, then the ACBSDA data is transmitted as the slave’s address and the re- quested transfer direction. This case is a re- peated Start Condition. It may be used to switch the direction of the data flow between the master and the slave, or to choose anoth- er slave device without using a Stop Condition in between. 0 – Writing 0 has no effect. 1 – Writing 1 generates a Start condition. STOP The Stop bit in master mode generates a Stop Condition that completes or aborts the current message transfer. This bit clears itself after the Stop condition is issued. 0 – Writing 0 has no effect. 1 – Writing 1 generates a Stop condition. 7 6 5 4 3 2 1 0 STASTRE NMINTE GCMEN ACK Res. INTEN STOP START

147 www.national.com CP3CN17 INTEN The Interrupt Enable bit controls generating ACB interrupts. When the INTEN bit is cleared ACB interrupt is disabled. When the INTEN bit is set, interrupts are enabled. 0 – ACB interrupts disabled. 1 – ACB interrupts enabled. An interrupt is generated (the interrupt signal to the ICU is high) on any of the following events: „ An address MATCH is detected (ACB- ST.NMATCH = 1) and the NMINTE bit is set. „ A Bus Error occurs (ACBST.BERR = 1). „ Negative acknowledge after sending a byte (ACBST.NEGACK = 1). „ An interrupt is generated on acknowledge of each transaction (same as hardware setting the ACBST.SDAST bit). „ If ACBCTL1.STASTRE = 1, in master mode after a successful start (ACBST.STASTR = 1). „ Detection of a Stop Condition while in slave receive mode (ACBST.SLVSTP = 1). ACK The Acknowledge bit holds the value this de- vice sends in master or slave mode during the next acknowledge cycle. Setting this bit to 1 instructs the transmitting device to stop send- ing data, since the receiver either does not need, or cannot receive, any more data. This bit is cleared after the first acknowledge cycle. This bit is ignored when in transmit mode. GCMEN The Global Call Match Enable bit enables the match of an incoming address byte to the gen- eral call address (Start Condition followed by address byte of 00h) while the ACB is in slave mode. When cleared, the ACB does not re- spond to a global call. 0 – Global call matching disabled. 1 – Global call matching enabled. NMINTE The New Match Interrupt Enable controls whether ACB interrupts are generated on new matches. Set the NMINTE bit to enable the in- terrupt on a new match (i.e., when ACB- ST.NMATCH is set). T he interrupt is issued only if the ACBCTL1.INTEN bit is set. 0 – New match interrupts disabled. 1 – New match interrupts enabled. STASTRE The Stall After Star t Enable bit enables the stall after start mechanism. When enabled, the ACB is stalled after the address byte. When the STASTRE bit is clear, the ACB- ST.STASTR bit is always clear. 0 – No stall after start. 1 – Stall-after-start enabled.

20.3.5 ACB Control Register 2 (ACBCTL2)

The ACBCTL2 register is a byte-wide, read/write register that controls the module and selects the ACB clock rate. At reset, the ACBCTL2 register is cleared. ENABLE The Enable bit controls the ACB module. When this bit is set, the ACB module is en- abled. When the Enable bit is clear, the ACB module is disabled, the ACBCTL1, ACBST, and ACBCST registers are cleared, and the clocks are halted. 0 – ACB module disabled. 1 – ACB module enabled. SCLFRQ The SCL Frequency field specifies the SCL period (low time and high time) in master mode. The clock low time and high time are defined as follows: t SCLl = tSCLh = 2 × SCLFRQ × tCLK Where tCLK is this device’s clock period when in Active mode. The SCLFRQ field may be programmed to values in the range of 0001000b through 1111111b. Using any other value has unpredictable results.

20.3.6 ACB Control Register 3 (ACBCTL3)

The ACBCTL3 register is a byte-wide, read/write register that expands the clock prescaler field and enables ARP matches. At reset, the ACBCTL3 register is cleared. ARPMEN The ARP Match Enable bit enables the matching of an incoming address byte to the SMBus ARP address 110 0001b general call address (Start condition followed by address byte of 00h), while the ACB is in slave mode. 0 – ACB does not respond to ARP address- es. 1 – ARP address matching enabled. SCLFRQ The SCL Frequency field specifies the SCL period (low time and high time) in master mode. The ACBCTL3 register provides a 2-bit expansion of this field, with the remaining 7 bits being held in the ACBCTL2 register. 7 1 0 SCLFRQ6:0 ENABLE 7 3 2 1 0 Reserved ARPMEN SCLFRQ8:7

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20.3.7 ACB Own Address Register 1 (ACBADDR1)

The ACBADDR1 register is a byte-wide, read/write register that holds the module’s first ACCESS.bus address. After re- set, its value is undefined. ADDR The Own Address field holds the first 7-bit AC- CESS.bus address of this device. When in slave mode, the first 7 bits received after a Start Condition are compared to this field (first bit received to bit 6, and the last to bit 0). If the address field matches the received data and the SAEN bit is set, a match is detected. SAEN The Slave Address Enable bit controls wheth- er address matching is performed in slave mode. When set, the SAEN bit indicates that the ADDR field holds a valid address and en- ables the match of ADDR to an incoming ad- dress byte. When cleared, the ACB does not check for an address match. 0 – Address matching disabled. 1 – Address matching enabled.

20.3.8 ACB Own Address Register 2 (ACBADDR2)

The ACBADDR2 register is a byte-wide, read/write register that holds the module’s second ACCESS.bus address. After reset, its value is undefined. ADDR The Own Address field holds the second 7-bit ACCESS.bus address of this device. When in slave mode, the first 7 bits received after a Start Condition are compared to this field (first bit received to bit 6, and the last to bit 0). If the address field matches the received data and the SAEN bit is set, a match is detected. SAEN The Slave Address Enable bit controls wheth- er address matching is performed in slave mode. When set, the SAEN bit indicates that the ADDR field holds a valid address and en- ables the match of ADDR to an incoming ad- dress byte. When cleared, the ACB does not check for an address match. 0 – Address matching disabled. 1 – Address matching enabled.

20.4 USAGE HINTS

„ When the ACB module is disabled, the ACBCST.BB bit is cleared. After enabling the ACB (ACBCTL2.ENABLE = 1) in systems with more than one master, the bus may be in the middle of a transaction with another device, which is not reflected in the BB bit. There is a need to allow the ACB to synchronize to the bus ac- tivity status before issuing a request to become the bus master, to prevent bus errors. Therefore, before issuing a request to become the bus master for the first time, software should check that there is no activity on the bus by checking the BB bit after the bus allowed time-out pe- riod. „ When waking up from power down, before checking the ACBCST.MATCH bit, test the ACBCST.BUSY bit to make sure that the address transaction has finished. „ The BB bit is intended to solve a deadlock in which two, or more, devices detect a usage conflict on the bus and both devices cease being bus masters at the same time. In this situation, the BB bits of both devices are active (because each deduces that there is another master cur- rently performing a transaction, while in fact no device is executing a transaction), and the bus would stay locked until some device sends a ACBCTL1.STOP condition. The ACBCST.BB bit allows software to monitor bus us- age, so it can avoid sending a STOP signal in the middle of the transaction of some other device on the bus. This bit detects whether the bus remains unused over a cer- tain period, while the BB bit is set. „ In some cases, the bus may get stuck with the SCL or SDA lines active. A possible cause is an erroneous Start or Stop Condition that occurs in the middle of a slave re- ceive session. When the SCL signal is stuck active, there is nothing that can be done, and it is the responsibility of the module that holds the bus to release it. When the SDA signal is stuck active, the ACB module enables the release of the bus by using the following sequence. Note that in normal cases, the SCL signal may be toggled only by the bus master. This protocol is a recovery scheme which is an exception that should be used only in the case when there is no other master on the bus. The re- covery scheme is as follows: 1. Disable and re-enable the module to set it into the not addressed slave mode. 2. Set the ACBCTL1.START bit to make an attempt to issue a Start Condition. 3. Check if the SDA signal is active (low) by reading ACBCST.TSDA bit. If it is active, issue a single SCL cycle by writing 1 to ACBCST.TGSCL bit. If the SDA line is not active, continue from step 5. 4. Check if the ACBST.MASTER bit is set, which indi- cates that the Start Condition was sent. If not, repeat step 3 and 4 until the SDA signal is released. 5. Clear the BB bit. This enables the START bit to be ex- ecuted. Continue according to “Bus Idle Error Recov- ery” on page 143. 7 6 0 SAEN ADDR 7 6 0 SAEN ADDR

21.0 Timing and Watchdog Module

locked, only reset can release it.

21.1 TWM STRUCTURE

the Watchdog section on the bottom.

21.2 TIMER T0 OPERATION

Figure 74. Timing and Watchdog Module Block Diagram rupt is also available through this alternative mechanism. cally upon restart of the 16-bit timer. TWW/MT0 Register T0CSR Contrl. Reg.

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21.3 WATCHDOG OPERATION

The Watchdog is an 8-bit down counter that operates on the rising edge of a specified clock source. At reset, the Watch- dog is disabled; it does not count and no Watchdog signal is generated. A write to either the Watchdog Count (WDCNT) register or the Watchdog Service Data Match (WDSDM) register starts the counter . The Watchdog counter counts down from the value programmed in the WDCNT register. Once started, only a reset can stop the Watchdog from op- erating. The Watchdog can be programmed to use either T0OUT or T0IN as its clock source (the output and input of Timer T0, respectively). The TWCFG.WDCT0I bit controls this clock selection. Software must periodically “service” the Watchdog. There are two ways to service the Watchdog, the choice depend- ing on the programmed value of the WDSDME bit in the Timer and Watchdog Configuration (TWCFG) register. If the TWCFG.WDSDME bit is clear, the Watchdog is ser- viced by writing a value to the WDCNT register. The value written to the register is reloaded into the Watchdog counter. The counter then continues counting down from that value. If the TWCFG.WDSDME bit is set, the Watchdog is ser- viced by writing the value 5Ch to the Watchdog Service Data Match (WDSDM) register. This reloads the Watchdog counter with the value previously programmed into the WD- CNT register. The counter then continues counting down from that value. A Watchdog error signal is generated by any of the following events: „ The Watchdog serviced too late. „ The Watchdog serviced too often. „ The WDSDM register is written with a value other than 5Ch when WDSDM type servicing is enabled (TWCFG.WDSDME = 1). A Watchdog error condition resets the device.

21.3.1 Register Locking

The Timer and Watchdog Configuration (TWCFG) register is used to set the Watchdog configuration. It controls the Watchdog clock source (T0IN or T0OUT), the type of Watchdog servicing (using W DCNT or WDSDM), and the locking state of the TWCF G, TWCPR, TIMER0, T0CSR, and WDCNT registers. A regist er that is locked cannot be read or written. A write operation is ignored and a read op- eration returns unpredictable results. If the TWCFG register is itself locked, it remains locked until the device is reset. Any other locked registers also remain locked until the device is reset. This feature prevents a run- away program from tampering with the programmed Watch- dog function.

21.3.2 Power Save Mode Operation

The Timer and Watchdog Module is active in both the Power Save and Idle modes. The clocks and counters continue to operate normally in these modes. The WDSDM register is accessible in the Power Save and Idle modes, but the other TWM registers are accessible only in the Active mode. Therefore, Watchdog servicing must be carried out using the WDSDM register in the Power Save or Idle mode. In the Halt mode, the entire device is frozen, including the Timer and Watchdog Module. On return to Active mode, op- eration of the module resumes at the point at which it was stopped. Note: After a restart or Watchdog service through WDCNT, do not enter Power Save mode for a period equivalent to 5 Slow Clock cycles.

21.4 TWM REGISTERS

The TWM registers controls the operation of the Timing and Watchdog Module. There are six such registers: The WDSDM register is accessible in both Active and Pow- er Save mode. The other TWM registers are accessible only in Active mode. Table 62 TWM Registers Name Address Description TWCFG FF FF20h Timer and Watchdog Configuration Register TWCP FF FF22h Timer and Watchdog Clock Prescaler Register TWMT0 FF FF24h TWM Timer 0 Register T0CSR FF FF26h TWMT0 Control and Status Register WDCNT FF FF28h Watchdog Count Register WDSDM FF FF2Ah Watchdog Service Data Match Register

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21.4.1 Timer and Watchdog Configuration Register

(TWCFG) The TWCFG register is a byte-wide, read/write register that selects the Watchdog clock input and service method, and also allows the Watchdog registers to be selectively locked. A locked register cannot be read or written; a read operation returns unpredictable values and a write operation is ig- nored. Once a lock bit is set, that bit cannot be cleared until the device is reset. At reset, the non-reserved bits of the register are cleared. The register format is shown below. LTWCFG The Lock TWCFG Register bit controls ac- cess to the TWCFG register. When clear, ac- cess to the TWCFG register is allowed. When set, the TWCFG register is locked. 0 – TWCFG register unlocked. 1 – TWCFG register locked. LTWCP The Lock TWCP Regist er bit controls access to the TWCP register. When clear, access to the TWCP register is allowed. When set, the TWCP register is locked. 0 – TWCP register unlocked. 1 – TWCP register locked. LTWMT0 The Lock TWMT0 Register bit controls access to the TWMT0 register. When clear, access to the TWMT0 and T0CSR registers are al- lowed. When set, the TWMT0 and T0CSR registers are locked. 0 – TWMT0 register unlocked. 1 – TWMT0 register locked. LWDCNT The Lock LDWCNT Register bit controls ac- cess to the LDWCNT register. When clear, ac- cess to the LDWCNT register is allowed. When set, the LDWCNT register is locked. 0 – LDWCNT register unlocked. 1 – LDWCNT register locked. WDCT0I The Watchdog Clock from T0IN bit selects the clock source for the Watchdog timer. When clear, the T0OUT signal (the output of Timer T0) is used as the Watchdog clock. When set, the T0IN signal (the prescaled Slow Clock) is used as the Watchdog clock. 0 – Watchdog timer is clocked by T0OUT. 1 – Watchdog timer is clocked by T0IN. WDSDME The Watchdog Service Data Match Enable bit controls which method is used to service the Watchdog timer. When clear, Watchdog ser- vicing is accomplished by writing a count val- ue to the WDCNT register; write operations to the Watchdog Service Data Match (WDSDM) register are ignored. When set, Watchdog servicing is accomplished by writing the value 5Ch to the WDSDM register. 0 – Write a count value to the WDCNT regis- ter to service the Watchdog timer. 1 – Write 5Ch to the WDSDM register to ser- vice the Watchdog timer.

21.4.2 Timer and Watchdog Clock Prescaler Register

(TWCP) The TWCP register is a byte-wide, read/write register that specifies the prescaler value used for dividing the low-fre- quency clock to generate the T0IN clock. At reset, the non- reserved bits of the register are cleared. The register format is shown below. MDIV Main Clock Divide. This 3-bit field defines the prescaler factor used for dividing the low speed device clock to create the T0IN clock. The allowed 3-bit values and the correspond- ing clock divisors and clock rates are listed be- low.

21.4.3 TWM Timer 0 Register (TWMT0)

The TWMT0 register is a word-wide, read/write register that defines the T0OUT interrupt rate. At reset, TWMT0 register is initialized to FFFFh. The register format is shown below. PRESET The Timer T0 Preset field holds the value used to reload Timer T0 on each underflow. Therefore, the frequency of the Timer T0 in- terrupt is the frequency of T0IN divided by (PRESET+1). The allowed values of PRESET are 0001h through FFFFh. 7 6 5 4 3 2 1 0 Res. WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG 7 3 2 0 Reserved MDIV MDIV Clock Divisor (fSCLK = 32.768 kHz) T0IN Frequency 000 1 32.768 kHz 001 2 16.384 kHz 010 4 8.192 kHz 011 8 4.096 kHz 100 16 2.056 kHz 101 32 1.024 kHz Other Reserved N/A 15 0 PRESET

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21.4.4 TWMT0 Control and St atus Register (T0CSR)

The T0CSR register is a byte-wide, read/write register that controls Timer T0 and shows its current status. At reset, the non-reserved bits of the regi ster are cleared. The register format is shown below. RST The Restart bit is used to reset Timer T0. When this bit is set, it forces the timer to re- load the value in the TWMT0 register on the next rising edge of the selected input clock. The RST bit is reset automatically by the hard- ware on the same rising edge of the selected input clock. Writing a 0 to this bit position has no effect. At reset, the non-reserved bits of the register are cleared. 0 – Writing 0 has no effect. 1 – Writing 1 resets Timer T0. TC The Terminal Count bit is set by hardware when the Timer T0 count reaches zero and is cleared when software reads the T0CSR reg- ister. It is a read-only bit. Any data written to this bit position is ignored. The TC bit is not cleared if FREEZE mode is asserted by an ex- ternal debugging system. 0 – Timer T0 did not count down to 0. 1 – Timer T0 counted down to 0. T0INTE The Timer T0 Interrupt Enable bit enables an interrupt to the CPU each time the Timer T0 count reaches zero. When this bit is clear, Timer T0 interrupts are disabled. 0 – Timer T0 interrupts disabled. 1 – Timer T0 interrupts enabled. WDLTD The Watchdog Last Touch Delay bit is set when either WDCNT or WDSDM is written and the data transfer to the Watchdog is in progress (see WDCNT and WDSDM register description). When clear, it is safe to switch to Power Save mode. 0 – No data transfer to the Watchdog is in progress, safe to enter Power Save mode. 1 – Data transfer to the Watchdog in progress. FRZT0E The Freeze Timer0 Enable bit controls wheth- er TImer 0 is stopped in FREEZE mode. If this bit is set, the Timer 0 is frozen (stopped) when the FREEZE input to the TWM is asserted. If the FRZT0E bit is clear, only the Watchdog timer is frozen by asserting the FREEZE input signal. After reset, this bit is clear. 0 – Timer T0 unaffected by FREEZE mode. 1 – Timer T0 stopped in FREEZE mode.

21.4.5 Watchdog Count Register (WDCNT)

The WDCNT register is a byte-wide, write-only register that holds the value that is loaded into the Watchdog counter each time the Watchdog is serviced. The Watchdog is start- ed by the first write to this register. Each successive write to this register restarts the Watchdog count with the written value. At reset, this register is initialized to 0Fh.

21.4.6 Watchdog Service Data Match Register

(WDSDM) The WSDSM register is a byte-wide, write-only register used for servicing the Watchdog. When this type of servic- ing is enabled (TWCFG.WDSDME = 1), the Watchdog is serviced by writing the value 5Ch to the WSDSM register. Each such servicing reloads the Watchdog counter with the value previously written to the WDCNT register. Writing any data other than 5Ch triggers a Watchdog error. Writing to the register more than onc e in one Watchdog clock cycle also triggers a Watchdog error signal. If this type of servic- ing is disabled (TWCFG.WDSDME = 0), any write to the WSDSM register is ignored.

21.5 WATCHDOG PROGRAMMING

The highest level of protection against software errors is achieved by programming and then locking the Watchdog registers and using the WDSDM register for servicing. This is the procedure: 1. Write the desired values into the TWM Clock Prescaler register (TWCP) and the TWM Timer 0 register (TWMT0) to control the T0IN and T0OUT clock rates. The frequency of T0IN can be programmed to any of six frequencies ranging from 1/32 × f SLCLK to f SLCLK. The frequency of T0OUT is equal to the frequency of T0IN divided by (1+ PRESET), in which PRESET is the value written to the TWMT0 register. 2. Configure the Watchdog clock to use either T0IN or T0OUT by setting or clearing the TWCFG.WDCT0I bit. 3. Write the initial value into the WDCNT register. This starts operation of the Watchdog and specifies the maximum allowed number of Watchdog clock cycles between service operations. 4. Set the T0CSR.RST bit to restart the TWMT0 timer. 5. Lock the Watchdog registers and enable the Watchdog Service Data Match Enable function by setting bits 0, 1, 2, 3, and 5 in the TWCFG register. 6. Service the Watchdog by periodically writing the value 5Ch to the WDSDM register at an appropriate rate. Servicing must occur at least once per period pro- grammed into the WDCNT re gister, but no more than once in a single Watchdog input clock cycle. 7 5 4 3 2 1 0 Reserved FRZT0E WDLTD T0INTE TC RST 7 0 PRESET 7 0 RSTDATA

22.0 Multi-Function Timer

also provides a general-purpose timer/counter. timing signals or counts occurrences of external events. vides one external event counter and one system timer.

22.1 TIMER STRUCTURE

Figure 75. Multi-Function Timer Block Diagram

22.1.1 Timer/Counter Block

than one-fourth the speed of the 32.768 kHz System Clock.

22.1.2 Clock Source Block

Clock Source block is shown in Figure 76. Figure 76. Multi-Function Timer Clock Source

counter are both cleared upon reset. the TB pin is used as one of the two capture inputs. the TB pin is used as one of the two capture inputs. Figure 77. Pulse-Accumulate Mode no more than one-fourth the speed of the System Clock. pulses are at least the size of the whole slow-clock period. much slower rate than the original System Clock. System Clock resumes operation. ers stop counting until the System Clock resumes operation.

22.2 TIMER OPERATING MODES

22.2.1 Mode 1: Processor-Independent PWM

general-purpose timer/counter. downward from the loaded value. Figure 78. Processor-I ndependent PWM Mode rupts can be enabled or disabled under software control. the hardware on each occurrence of a timer reload.

22.2.2 Mode 2: Dual Input Capture

TB pin transfers the timer c ontents to the TCRB register. Figure 79. Dual-Input Capture Mode signal with a minimum of CPU overhead. reflect the elapsed time between transitions on the TA pin. equal to or greater than one System Clock cycle. TAIEN, TBIEN, and TCIEN, respectively.

22.2.3 Mode 3: Dual Independent Timer/Counter

clocked by the prescaled System Clock. Figure 80. Dual-Independent Timer/Counter Mode any further action from the CPU.

22.2.4 Mode 4: Input Capture Plus Timer

input rather than two inputs. Figure 81. Input Capture Plus Timer Mode Timer/Counter 1 (TCNT1) operates the same as in Mode 3. further action from the CPU. ther rising or falling edges. register and then the counter is preset to FFFFh. reflect the elapsed time between transitions on the TA pin. greater than one System Clock cycle. events are TBIEN and TDIEN, respectively.

22.3 TIMER INTERRUPTS

bits are named TAPND, TBPND, TCPND, and TDPND. (IRQ14 and IRQ13), respectively. interrupt sources are not used in some operating modes.

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22.4 TIMER I/O FUNCTIONS

The Multi-Function Timer unit uses two I/O pins, called TA and TB. The function of each pin depends on the timer op- erating mode and the TAEN and TBEN enable bits. Table 64 shows the functions of the pins in each operating mode, and for each combination of enable bit settings. When the TA pin is configured to operate as a PWM output (TAEN = 1), the state of the pin is toggled on each underflow of the TCNT1 counter. In this case, the initial value on the pin is determined by the TAOUT bit. For example, to start with TA high, software must set the TAOUT bit before en- abling the timer clock. This option is available only when the timer is configured to operat e in Mode 1, 3, or 4 (in other words, when TCRA is not used in Capture mode). Table 63 Timer Interrupts Overview Sys. Int. Interrupt Pending Bit Mode 1 Mode 2 Mode 3 Mode 4 PWM + Counter Dual Input Capture + Counter Dual Counter Single Capture + Counter Timer Int. 1 (TA Int.) TAPND TCNT1 reload from TCRA Input capture on TA transition TCNT1 reload from TCRA TCNT1 reload from TCRA TBPND TCNT1 reload from TCRB Input Capture on TB transition N/A Input Capture on TB transition TCPND N/A TCNT1 underflow N/A N/A Timer Int. 2 (TB Int.) TDPND TCNT2 underflow TCNT2 underflow TCNT2 reload from TCRB TCNT2 underflow Table 64 Timer I/O Functions I/O TAEN TBEN Mode 1 Mode 2 Mode 3 Mode 4 PWM + Counter Dual Input Capture + counter Dual Counter Single Capture + counter TA TAEN = 0 TBEN = X No Output Capture TCNT1 into TCRA No Output Toggle No Output Toggle TAEN = 1 TBEN = X Toggle Output on Underflow of TCNT1 Capture TCNT1 into TCRA and Preset TCNT1 Toggle Output on Underflow of TCNT1 Toggle Output on Underflow of TCNT1 TB TAEN = X TBEN = 0 Ext. Event or Pulse Accumulate Input Capture TCNT1 into TCRB Ext. Event or Pulse Accumulate Input Capture TCNT2 into TCRB TAEN = X TBEN = 1 Ext. Event or Pulse Accumulate Input Capture TCNT1 into TCRB and Preset TCNT1 Ext. Event or Pulse Accumulate Input Capture TCNT2 into TCRB and Preset TCNT2

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22.5 TIMER REGISTERS

Table 65 lists the CPU-accessible registers used to control the Multi-Function Timers.

22.5.1 Clock Prescaler Register (TPRSC)

The TPRSC register is a byte-wide, read/write register that holds the current value of the 5-bit clock prescaler (CLKPS). This register is cleared on reset. The register format is shown below. CLKPS The Clock Prescaler field specifies the divisor used to generate the Timer Clock from the System Clock. When the timer is configured to use the prescaled clock, the System Clock is divided by (CLKPS + 1) to produce the timer clock. Therefore, the System Clock divisor can range from 1 to 32.

22.5.2 Clock Unit Control Register (TCKC)

The TCKC register is a byte-wide, read/write register that selects the clock source for each timer/counter. Selecting the clock source also starts the counter. This register is cleared on reset, which disables the timer/counters. The register format is shown below. C1CSEL The Counter 1 Clock Select field specifies the clock mode for Timer/Counter 1 as follows: 000 – No clock (Timer/Counter 1 stopped, modes 1, 2, and 3 only). 001 – Prescaled System Clock. 010 – External event on TB (modes 1 and 3 only). 011 – Pulse-accumulate mode based on TB (modes 1 and 3 only). 100 – Slow Clock.* 101 – Reserved. 110 – Reserved. 111 – Reserved. C2CSEL The Counter 2 Clock Select field specifies the clock mode for Timer/Counter 2 as follows: 000 – No clock (Timer/Counter 2 stopped, modes 1, 2, and 3 only). 001 – Prescaled System Clock. 010 – External event on TB (modes 1 and 3 only). 011 – Pulse-accumulate mode based on TB (modes 1 and 3 only). 100 – Slow Clock* 101 – Reserved. 110 – Reserved. 111 – Reserved. * Operation of the Slow Clock is determined by the CRC- TRL.SCLK control bit, as described in Section 11.8.1.

22.5.3 Timer/Counter 1 Register (TCNT1)

The TCNT1 register is a word-wide, read/write register that holds the current count value for Timer/Counter 1. The reg- ister contents are not affected by a reset and are unknown after power-up.

22.5.4 Timer/Counter 2 Register (TCNT2)

The TCNT2 register is a word-wide, read/write register that holds the current count value for Timer/Counter 2. The reg- ister contents are not affected by a reset and are unknown after power-up. Table 65 Multi-Function Timer Registers Name Address Description TPRSC FF FF48h Clock Prescaler Register TCKC FF FF4Ah Clock Unit Control Register TCNT1 FF FF40h Timer/Counter 1 Register TCNT2 FF FF46h Timer/Counter 2 Register TCRA FF FF42h Reload/Capture A Register TCRB FF FF44h Reload/Capture B Register TCTRL FF FF4Ch Timer Mode Control Register TICTL FF FF4Eh Timer Interrupt Control Register TICLR FF FF50h Timer Interrupt Clear Register 7 5 4 0 Reserved CLKPS 7 6 5 3 2 0 Reserved C2CSEL C1CSEL 15 0 TCNT1 15 0 TCNT2

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22.5.5 Reload/Capture A Register (TCRA)

The TCRA register is a word-wide, read/write register that holds the reload or capture value for Timer/Counter 1. The register contents are not affected by a reset and are un- known after power-up.

22.5.6 Reload/Capture B Register (TCRB)

The TCRB register is a word-wide, read/write register that holds the reload or capture value for Timer/Counter 2. The register contents are not affected by a reset and are un- known after power-up.

22.5.7 Timer Mode Control Register (TCTRL)

The TCTRL register is a byte-wide, read/write register that sets the operating mode of the timer/counter and the TA and TB pins. This register is cleared at reset. The register format is shown below. MDSEL The Mode Select field sets the operating mode of the timer/counter as follows: 00 – Mode 1: PWM plus system timer. 01 – Mode 2: Dual-Input Capture plus system timer. 10 – Mode 3: Dual Timer/Counter. 11 – Mode 4: Single-Input Capture and Sin- gle Timer. TAEDG The TA Edge Polarity bit selects the polarity of the edges that trigger the TA input. 0 – TA input is sensitive to falling edges (high to low transitions). 1 – TA input is sensitive to rising edges (low to high transitions). TBEDG The TB Edge Polarity bit selects the polarity of the edges that trigger the TB input. In pulse- accumulate mode, when this bit is set, the counter is enabled only when TB is high; when this bit is clear, the counter is enabled only when TB is low. 0 – TB input is sensitive to falling edges (high to low transitions). 1 – TB input is sensitive to rising edges (low to high transitions). TAEN The TA Enable bit controls whether the TA pin is enabled to operate as a preset input or as a PWM output, depending on the timer operat- ing mode. In Mode 2 (Dual Input Capture), a transition on the TA pin presets the TCNT1 counter to FFFFh. In the other modes, TA functions as a PWM output. When this bit is clear, operation of the pin for the timer/counter is disabled. 0 – TA input disabled. 1 – TA input enabled. TBEN The TB Enable bit controls whether the TB pin in enabled to operate in Mode 2 (Dual Input Capture) or Mode 4 (Single Input Capture and Single Timer). A transition on the TB pin pre- sets the corresponding timer/counter to FFFFh (TCNT1 in Mode 2 or TCNT2 in Mode 4). When this bit is clear, operation of the pin for the timer/counter is disabled. This bit set- ting has no effect in Mode 1 or Mode 3. 0 – TB input disabled. 1 – TB input enabled. TAOUT The TA Output Data bit indicates the current state of the TA pin when the pin is used as a PWM output. The hardware sets and clears this bit, but software can also read or write this bit at any time and therefore control the state of the output pin. In case of conflict, a software write has precedence over a hardware up- date. This bit setting has no effect when the TA pin is used as an input. 0 – TA pin is low. 1 – TA pin is high. TEN The Timer Enable bit controls whether the Multi-Function Timer is enabled. When the module is disabled all clocks to the counter unit are stopped to minimize power consump- tion. For that reason, the timer/counter regis- ters (TCNT1 and TCNT2), the capture/reload registers (TCRA and TCRB), and the interrupt pending bits (TXPND) cannot be written in this mode. Also, the 5-bit clock prescaler and the interrupt pending bits are cleared, and the TA I/O pin becomes an input. 0 – Multi-Function Timer is disabled. 1 – Multi-Function Timer is enabled.

22.5.8 Timer Interrupt Control Register (TICTL)

The TICTL register is a byte-w ide, read/write register that contains the interrupt enable bits and interrupt pending bits for the four timer interrupt sources, designated A, B, C, and D. The condition that causes each type of interrupt depends on the operating mode, as shown in Table 63. This register is cleared upon reset. The register format is shown below. 15 0 TCRA 15 0 TCRB 7 6 5 4 3 2 1 0 TEN TAOUT TBEN TAEN TBEDG TAEDG MDSEL 7 6 5 4 3 2 1 0 TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND

www.national.com 162 CP3CN17 TAPND The Timer Interrupt Source A Pending bit indi- cates that timer interrupt condition A has oc- curred. For an explanation of interrupt conditions A, B, C, and D, see Table 63. This bit can be set by hardware or by software. To clear this bit, software must use the Timer In- terrupt Clear Register (TICLR). Any attempt by software to directly write a 0 to this bit is ig- nored. 0 – Interrupt source A has not triggered. 1 – Interrupt source A has triggered. TBPND The Timer Interrupt Source B Pending bit indi- cates that timer interrupt condition B has oc- curred. For an explanation of interrupt conditions A, B, C, and D, see Table 63. This bit can be set by hardware or by software. To clear this bit, software must use the Timer In- terrupt Clear Register (TICLR). Any attempt by software to directly write a 0 to this bit is ig- nored. 0 – Interrupt source B has not triggered. 1 – Interrupt source B has triggered. TCPND The Timer Interrupt Source C Pending bit in- dicates that timer interrupt condition C has oc- curred. For an explanation of interrupt conditions A, B, C, and D, see Table 63. This bit can be set by hardware or by software. To clear this bit, software must use the Timer In- terrupt Clear Register (TICLR). Any attempt by software to directly write a 0 to this bit is ig- nored. 0 – Interrupt source C has not triggered. 1 – Interrupt source C has triggered. TDPND The Timer Interrupt Source D Pending bit in- dicates that timer interrupt condition D has oc- curred. For an explanation of interrupt conditions A, B, C, and D, see Table 63. This bit can be set by hardware or by software. To clear this bit, software must use the Timer In- terrupt Clear Register (TICLR). Any attempt by software to directly write a 0 to this bit is ig- nored. 0 – Interrupt source D has not triggered. 1 – Interrupt source D has triggered. TAIEN The Timer Interrupt A Enable bit controls whether an interrupt is generated on each oc- currence of interrupt condition A. For an ex- planation of interrupt conditions A, B, C, and D, see Table 63. 0 – Condition A interrupts disabled. 1 – Condition A interrupts enabled. TBIEN The Timer Interrupt B Enable bit controls whether an interrupt is generated on each oc- currence of interrupt condition B. For an ex- planation of interrupt conditions A, B, C, and D, see Table 63. 0 – Condition B interrupts disabled. 1 – Condition B interrupts enabled. TCIEN The Timer Interrupt C Enable bit controls whether an interrupt is generated on each oc- currence of interrupt condition C. For an ex- planation of interrupt conditions A, B, C, and D, see Table 63. 0 – Condition C interrupts disabled. 1 – Condition C interrupts enabled. TDIEN The Timer Interrupt D Enable bit controls whether an interrupt is generated on each oc- currence of interrupt condition D. For an ex- planation of interrupt conditions A, B, C, and D, see Table 63. 0 – Condition D interrupts disabled. 1 – Condition D interrupts enabled.

22.5.9 Timer Interrupt Clear Register (TICLR)

The TICLR register is a byte-wide, write-only register that al- lows software to clear the TAPND, TBPND, TCPND, and TDPND bits in the Timer Inte rrupt Control (TICTRL) regis- ter. Do not modify this register with instructions that access the register as a read-modify-write operand, such as the bit manipulation instructions. The register reads as FFh. The register format is shown below. TACLR The Timer Pending A Clear bit is used to clear the Timer Interrupt Source A Pending bit (TAPND) in the Timer Interrupt Control regis- ter (TICTL). 0 – Writing a 0 has no effect. 1 – Writing a 1 clears the TAPND bit. TBCLR The Timer Pending A Clear bit is used to clear the Timer Interrupt Source B Pending bit (TB- PND) in the Timer Interrupt Control register (TICTL). 0 – Writing a 0 has no effect. 1 – Writing a 1 clears the TBPND bit. TCCLR The Timer Pending C Clear bit is used to clear the Timer Interrupt Source C Pending bit (TCPND) in the Timer Interrupt Control regis- ter (TICTL). 0 – Writing a 0 has no effect. 1 – Writing a 1 clears the TCPND bit. TDCLR The Timer Pending D Clear bit is used to clear the Timer Interrupt Source D Pending bit (TD- PND) in the Timer Interrupt Control register (TICTL). 0 – Writing a 0 has no effect. 1 – Writing a 1 clears the TDPND bit. 7 4 3 2 1 0 Reserved TDCLR TCCLR TBCLR TACLR

23.0 Versatile Timer Unit (VTU)

wide range of system frequencies.

23.1 VTU FUNCTIONAL DESCRIPTION

or capture inputs depending on the mode of operation. a 16-bit PWM timer, or as a dual 16-bit capture timer. Figure 82 shows the main elements of the VTU. Figure 82. Versatile Time r Unit Block Diagram

23.1.1 Dual 8-bit PWM Mode

ments at the rate determined by the clock prescaler. counter increment. Figure 83 illustrates this concept. Figure 83. VTU PWM Generation duty cycle to be programmed in a range from 0% to 100%. turn the most recent value written to it. the counter value and the PERCAPx register value occurs. The counter will then be cleared and continue counting up. case the counter will count up to FFh, then roll over to 00h. 00h to 01h transition of the counter. counter register while either timer is running will be ignored.

as independent PWM outputs in the dual 8-bit PWM mode. defined by the IOxCTL.PxPOL bit. „ The counter will stop and will retain its last value. MODE.TxRUN bits are cleared. the other three timer subsystems. Figure 84. VTU Dual 8-Bit PWM Mode nated to form a single 16-bit counter. the other three timer subsystems. Figure 85. VTU 16-bit PWM Mode

23.1.3 Dual 16-Bit Capture Mode

duty cycle of external signals. Starting the counter is identical to the 16-bit PWM mode, i.e. event inputs are enabled once the MODE.TxRUN bit is set. ative transition or both a positive and a negative transition. duty cycle measurement of an external signal.

the other three timer subsystems. Figure 86. VTU Dual 16-bit Capture Mode

23.1.4 Low Power Mode

registers of a timer subsystem while it is in low-power mode. All registers can be read at any time.

23.1.5 Interrupts

Figure 87. VTU Interrupt Request Structure which cause an interrupt pending bit to be set.

23.1.6 ISE Mode operation

ture input events are re-enabled.

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23.2 VTU REGISTERS

The VTU contains a total of 19 user accessible registers, as listed in Table 67. All registers are word-wide and are initial- ized to a known value upon reset. All software accesses to the VTU registers must be word accesses.

23.2.1 Mode Control Register (MODE)

The MODE register is a word-wide read/write register which controls the mode selection of all four timer subsystems. The register is clear after reset. TxRUN The Timer Run bit controls whether the corre- sponding timer is stopped or running. If set, the associated counter and clock prescaler is started depending on the mode of operation. Once set, the clock to the clock prescaler and the counter are enabled and the counter will increment each time the clock prescaler counter value matches the value defined in the associated clock prescaler field (CxPR- SC). 0 – Timer stopped. 1 – Timer running. TMODx The Timer System Operating Mode field en- ables or disables the Timer Subsystem and defines its operating mode. 00 – Low-Power Mode. All clocks to the counter subsystem are stopped. The counter is stopped regardless of the val- ue of the TxRUN bits. Read operations to the Timer Subsystem will return the last value; software must not perform any write operations to the Timer Sub- system while it is disabled since those will be ignored. 01 – Dual 8-bit PWM mode. Each 8-bit counter may individually be started or stopped via its associated TxRUN bit. The TIOx pins will function as PWM out- puts. 10 – 16-bit PWM mode. The two 8-bit counters are concatenated to form a sin- gle 16-bit counter. The counter may be started or stopped with the lower of the two TxRUN bits, i.e. T1RUN, T3RUN, T5RUN, and T7RUN. The TIOx pins will function as PWM outputs. 11 – Capture Mode. Both 8-bit counters are concatenated and operate as a single 16-bit counter. The counter may be start- ed or stopped with the lower of the two TxRUN bits, i.e., T1RUN, T3RUN, T5RUN, and T7RUN. The TIOx pins will function as capture inputs. Table 67 VTU Registers Name Address Description MODE FF FF80h Mode Control Register IO1CTL FF FF82h I/O Control Register 1 IO2CTL FF FF84h I/O Control Register 2 INTCTL FF FF86h Interrupt Control Register INTPND FF FF88h Interrupt Pending Register CLK1PS FF FF8Ah Clock Prescaler Register 1 CLK2PS FF FF98h Clock Prescaler Register 2 COUNT1 FF FF8Ch Counter 1 Register PERCAP1 FF FF8Eh Period/Capture 1 Register DTYCAP1 FF FF90h Duty Cycle/Capture 1 Register COUNT2 FF FF92h Counter 2 Register PERCAP2 FF FF94h Period/Capture 2 Register DTYCAP2 FF FF96h Duty Cycle/Capture 2 Register COUNT3 FF FF9Ah Counter 3 Register PERCAP3 FF FF9Ch Period/Capture 3 Register DTYCAP3 FF FF9Eh Duty Cycle/Capture 3 Register COUNT4 FF FFA0h Counter 4 Register PERCAP4 FF FFA2h Period/Capture 4 Register DTYCAP4 FF FFA4h Duty Cycle/Capture 4 Register 7 6 5 4 3 2 1 0 TMOD2 T4RUN T3RUN TMOD1 T2RUN T1RUN 15 14 13 12 11 10 9 8 TMOD4 T8RUN T7RUN TMOD3 T6RUN T5RUN

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23.2.2 I/O Control Register 1 (IO1CTL)

The I/O Control Register 1 (IO1CTL) is a word-wide read/ write register. The r egister controls the function of the I/O pins TIO1 through TIO4 depending on the selected mode of operation. The register is clear after reset. CxEDG The Capture Edge Control field specifies the polarity of a capture event and the reset of the counter. The value of this three bit field has no effect while operating in PWM mode. PxPOL The PWM Polarity bit selects the output polar- ity. While operating in PWM mode the bit specifies the polarity of the corresponding PWM output (TIOx). Once a counter is stopped, the output will assume the value of PxPOL, i.e., its initial value. The PxPOL bit has no effect while operating in capture mode. 0 – The PWM output goes high at the 00h to 01h transition of the counter and will go low once the counter value matches the duty cycle value. 1 – The PWM output goes low at the 00h to 01h transition of the counter and will go high once the counter value matches the duty cycle value.

23.2.3 I/O Control Register 2 (IO2CTL)

The IO2CTL register is a word-wide read/write register. The register controls the functi onality of the I/O pins TIO5 through TIO8 depending on the selected mode of operation. The register is cleared at reset. The functionality of the bit fields of the IO2CTL register is identical to the ones described in the IO1CTL register sec- tion.

23.2.4 Interrupt Control Register (INTCTL)

The INTCTL register is a word-wide read/write register. It contains the interrupt enable bits for all 16 interrupt sources of the VTU. Each interrupt enable bit corresponds to an in- terrupt pending bit located in the Interrupt Pending Register (INTPND). All INTCTL register bits are solely under soft- ware control. The register is clear after reset. IxAEN The Timer x Interrupt A Enable bit controls in- terrupt requests triggered on the correspond- ing IxAPD bit being set. The associated IxAPD bit will be updated regardless of the value of the IxAEN bit. 0 – Disable system interrupt request for the IxAPD pending bit. 1 – Enable system interrupt request for the Ix- APD pending bit. IxBEN The Timer x Interrupt B Enable bit controls in- terrupt requests triggered on the correspond- ing IxBPD bit being set. The associated IxBPD bit will be updated regardless of the value of the IxBEN bit. 0 – Disable system interrupt request for the IxBPD pending bit. 1 – Enable system interrupt request for the Ix- BPD pending bit. 7 6 4 3 2 0 P2POL C2EDG P1POL C1EDG 15 14 12 11 10 8 P4POL C4EDG P3POL C3EDG CxEDG Capture Counter Reset

000 Rising edge No

001 Falling edge No

010 Rising edge Ye s

011 Falling edge Ye s

100 Both edges No

101 Both edges Rising edge

110 Both edges Falling edge

111 Both edges Both edges

I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN 15 14 13 12 11 10 9 8 I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN

169 www.national.com CP3CN17 IxCEN The Timer x Interrupt C Enable bit controls in- terrupt requests triggered on the correspond- ing IxCPD bit being set. The associated IxCPD bit will be updated regardless of the value of the IxCEN bit. 0 – Disable system interrupt request for the IxCPD pending bit. 1 – Enable system interrupt request for the Ix- CPD pending bit. IxDEN Timer x Interrupt D Enable bit controls inter- rupt requests triggered on the corresponding IxDPD bit being set. The associated IxDPD bit will be updated regardless of the value of the IxDEN bit. 0 – Disable system interrupt request for the IxDPD pending bit. 1 – Enable system interrupt request for the IxDPD pending bit.

23.2.5 Interrupt Pendin g Register (INTPND)

The INTPND register is a wo rd-wide read/write register which contains all 16 interrupt pending bits. There are four interrupt pending bits called IxAPD through IxDPD for each timer subsystem. Each interrupt pending bit is set by a hard- ware event and can be cleared if software writes a 1 to the bit position. The value will remain unchanged if a 0 is written to the bit position. All interrupt pending bits are cleared (0) upon reset. IxAPD The Timer x Interrupt A Pending bit indicates that an interrupt condition for the related timer subsystem has occurred. Table 66 on page 166 lists the hardware condition which causes this bit to be set. 0 – No interrupt pending. 1 – Timer interrupt condition occurred. IxBPD The Timer x Interrupt B Pending bit indicates that an interrupt condition for the related timer subsystem has occurred. Table 66 on page 166 lists the hardware condition which causes this bit to be set. 0 – No interrupt pending. 1 – Timer interrupt condition occurred. IxCPD The Timer x Interrupt C Pending bit indicates that an interrupt condition for the related timer subsystem has occurred. Table 66 on page 166 lists the hardware condition which causes this bit to be set. 0 – No interrupt pending. 1 – Timer interrupt condition occurred. IxDPD The Timer x Interrupt D Pending bit indicates that an interrupt condition for the related timer subsystem has occurred. Table 66 on page 166 lists the hardware condition which causes this bit to be set. 0 – No interrupt pending. 1 – Timer interrupt condition occurred.

23.2.6 Clock Prescaler Register 1 (CLK1PS)

The CLK1PS register is a word-wide read/write register. The register is split into two 8-bit fields called C1PRSC and C2PRSC. Each field holds the 8-bit clock prescaler com- pare value for timer subsystems 1 and 2 respectively. The register is cleared at reset. C1PRSC The Clock Prescaler 1 Compare Value field holds the 8-bit prescaler value for timer sub- system 1. The counter of timer subsystem is incremented each time when the clock pres- caler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C1PRSC + 1). For example, 00h is a ratio of 1, and FFh is a ratio of 256. C2PRSC The Clock Prescaler 2 Compare Value field holds the 8-bit prescaler value for timer sub- system 2. The counter of timer subsystem is incremented each time when the clock pres- caler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C2PRSC + 1).

23.2.7 Clock Prescaler Register 2 (CLK2PS)

The Clock Prescaler Register 2 (CLK2PS) is a word-wide read/write register. The register is split into two 8-bit fields called C3PRSC and C4PRSC. Each field holds the 8-bit clock prescaler compare value for timer subsystems 3 and 4 respectively. The register is cleared at reset. C3PRSC The Clock Prescaler 3 Compare Value field holds the 8-bit prescaler value for timer sub- system 3. The counter of timer subsystem is incremented each time when the clock pres- caler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C3PRSC + 1). C4PRSC The Clock Prescaler 4 Compare Value field holds the 8-bit prescaler value for timer sub- system 4. The counter of timer subsystem is incremented each time when the clock pres- caler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C4PRSC + 1). 7 6 5 4 3 2 1 0 I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD 15 14 13 12 11 10 9 8 I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD 15 8 7 0 C2PRSC C1PRSC 15 8 7 0 C4PRSC C3PRSC

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23.2.8 Counter Regi ster n (COUNTx)

The Counter (COUNTx) registers are word-wide read/write registers. There are a total of four registers called COUNT1 through COUNT4, one for eac h of the four timer sub- systems. Software may read the registers at any time. Reading the register will return the current value of the counter. The register may only be written if the counter is stopped (i.e. if both TxRUN bits associated with a timer sub- system are clear). The registers are cleared at reset.

23.2.9 Period/Capture Register n (PERCAPx)

The PERCAPx registers are word-wide read/write registers. There are a total of four registers called PERCAP1 through PERCAP4, one for each timer subsystem. The registers hold the period compare value in PWM mode of the counter value at the time the last associated capture event occurred. In PWM mode the register is double buffered. If a new peri- od compare value is written while the counter is running, the write will not take effect until counter value matches the pre- vious period compare value or until the counter is stopped. Reading may take place at any time and will return the most recent value which was written. The PERCAPx registers are cleared at reset.

23.2.10 Duty Cycle/Capture Register n (DTYCAPx)

The Duty Cycle/Capture (DTYCAPx) registers are word- wide read/write registers. There are a total of four registers called DTYCAP1 through DTYCAP4, one for each timer subsystem. The registers hold the period compare value in PWM mode or the counter value at the time the last associ- ated capture event occurred. In PWM mode, the register is double buffered. If a new duty cycle compare value is written while the counter is running, the write will not take effect un- til the counter value matches the previous period compare value or until the counter is stopped. The update takes effect on period boundaries only. Reading may take place at any time and will return the most recent value which was written. The DTYCAPx registers are cleared at reset. 15 0 CNTx 15 0 PCAPx 15 0 DCAPx

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24.0 Register Map

Table 68 is a detailed memory map showing the specific memory address of the memory, I/O ports, and registers. The table shows the starting address, the size, and a brief description of each memory block and register. For detailed information on using these memory locations, see the appli- cable sections in the data sheet. All addresses not listed in the table are reserved and must not be read or written. An attempt to access an unlisted ad- dress will have unpredictable results. Each byte-wide register occupies a single address and can be accessed only in a byte-wide transaction. Each word- wide register occupies two consecutive memory addresses and can be accessed only in a word-wide transaction. Both the byte-wide and word-wide registers reside at word boundaries (even addresses). Therefore, each byte-wide register uses only the lowest eight bits of the internal data bus. Most device registers are read/write registers. However, some registers are read-only or write-only, as indicated in the table. An attempt to read a write-only register or to write a read-only register will have unpredictable results. When software writes to a register in which one or more bits are reserved, it must write a zero to each reserved bit unless indicated otherwise in the description of the register. Read- ing a reserved bit returns an undefined value. Table 68 Detailed Device Mapping Register Name Size Address Access Type Value After Reset Comments CAN Module Message Buffers CMB0_CNSTAT Word 0E F000h Read/Write XXXXh CMB0_TSTP Word 0E F002h Read/Write XXXXh CMB0_DATA3 Word 0E F004h Read/Write XXXXh CMB0_DATA2 Word 0E F006h Read/Write XXXXh CMB0_DATA1 Word 0E F008h Read/Write XXXXh CMB0_DATA0 Word 0E F00Ah Read/Write XXXXh CMB0_ID0 Word 0E F00Ch Read/Write XXXXh CMB0_ID1 Word 0E F00Eh Read/Write XXXXh CMB1 8-word 0E F010h– 0E F01Fh Read/Write XXXXh Same register layout as CMB0. CMB2 8-word 0E F020h– 0E F02Fh Read/Write XXXXh Same register layout as CMB0. CMB3 8-word 0E F030h– 0E F03Fh Read/Write XXXXh Same register layout as CMB0. CMB4 8-word 0E F040h– 0E F04Fh Read/Write XXXXh Same register layout as CMB0. CMB5 8-word 0E F050h– 0E F05Fh Read/Write XXXXh Same register layout as CMB0. CMB6 8-word 0E F060h– 0E F06Fh Read/Write XXXXh Same register layout as CMB0. CMB7 8-word 0E F070h– 0E F07Fh Read/Write XXXXh Same register layout as CMB0. CMB8 8-word 0E F080h– 0E F08Fh Read/Write XXXXh Same register layout as CMB0. CMB9 8-word 0E F090h– 0E F09Fh Read/Write XXXXh Same register layout as CMB0.

www.national.com 172 CP3CN17CMB10 8-word 0E F0A0h– 0E F0AFh Read/Write XXXXh Same register layout as CMB0. CMB11 8-word 0E F0B0h– 0E F0BFh Read/Write XXXXh Same register layout as CMB0. CMB12 8-word 0E F0C0h– 0E F0CFh Read/Write XXXXh Same register layout as CMB0. CMB13 8-word 0E F0D0h– 0E F0DFh Read/Write XXXXh Same register layout as CMB0. CMB14 8-word 0E F0E0h– 0E F0EFh Read/Write XXXXh Same register layout as CMB0. CAN Registers CGCR Word 0E F100h Read/Write 0000h CTIM Word 0E F102h Read/Write 0000h GMSKX Word 0E F104h Read/Write 0000h GMSKB Word 0E F106h Read/Write 0000h BMSKX Word 0E F108h Read/Write 0000h BMSKB Word 0E F10Ah Read/Write 0000h CIEN Word 0E F10Ch Read/Write 0000h CIPND Word 0E F10Eh Read Only 0000h CICLR Word 0E F110h Write Only 0000h CICEN Word 0E F112h Read/Write 0000h CSTPND Word 0E F114h Read Only 0000h CANEC Word 0E F116h Read Only 0000h CEDIAG Word 0E F118h Read Only 0000h CTMR Word 0E F11Ah Read Only 0000h DMA Controller ADCA0 Double Word FF F800h Read/Write 0000 0000h ADRA0 Double Word FF F804h Read/Write 0000 0000h ADCB0 Double Word FF F808h Read/Write 0000 0000h ADRB0 Double Word FF F80Ch Read/Write 0000 0000h BLTC0 Word FF F810h Read/Write 0000h BLTR0 Word FF F814h Read/Write 0000h DMACNTL0 Word FF F81Ch Read/Write 0000h Register Name Size Address Access Type Value After Reset Comments

173 www.national.com CP3CN17 DMASTAT0 Byte FF F81Eh Read/Write 00h ADCA1 Double Word FF F820h Read/Write 0000 0000h ADRA1 Double Word FF F824h Read/Write 0000 0000h ADCB1 Double Word FF F828h Read/Write 0000 0000h ADRB1 Double Word FF F82Ch Read/Write 0000 0000h BLTC1 Word FF F830h Read/Write 0000h BLTR1 Word FF F834h Read/Write 0000h DMACNTL1 Word FF F83Ch Read/Write 0000h DMASTAT1 Byte FF F83Eh Read/Write 00h ADCA2 Double Word FF F840h Read/Write 0000 0000h ADRA2 Double Word FF F844h Read/Write 0000 0000h ADCB2 Double Word FF F848h Read/Write 0000 0000h ADRB2 Double Word FF F84Ch Read/Write 0000 0000h BLTC2 Word FF F850h Read/Write 0000h BLTR2 Word FF F854h Read/Write 0000h DMACNTL2 Word FF F85Ch Read/Write 0000h DMASTAT2 Byte FF F85Eh Read/Write 00h ADCA3 Double Word FF F860h Read/Write 0000 0000h ADRA3 Double Word FF F864h Read/Write 0000 0000h ADCB3 Double Word FF F868h Read/Write 0000 0000h ADRB3 Double Word FF F86Ch Read/Write 0000 0000h BLTC3 Word FF F870h Read/Write 0000h BLTR3 Word FF F874h Read/Write 0000h DMACNTL3 Word FF F87Ch Read/Write 0000h DMASTAT3 Byte FF F87Eh Read/Write 00h Register Name Size Address Access Type Value After Reset Comments

www.national.com 174 CP3CN17 Bus Interface Unit BCFG Byte FF F900h Read/Write 07h IOCFG Word FF F902h Read/Write 069Fh SZCFG0 Word FF F904h Read/Write 069Fh SZCFG1 Word FF F906h Read/Write 069Fh SZCFG2 Word FF F908h Read/Write 069Fh System Configuration MCFG Byte FF F910h Read/Write 00h DBGCFG Byte FF F912h Read/Write 00h MSTAT Byte FF F914h Read Only ENV2:0 pins Flash Program Memory Interface FMIBAR Word FF F940h Read/Write 0000h FMIBDR Word FF F942h Read/Write 0000h FM0WER Word FF F944h Read/Write 0000h FM1WER Word FF F946h Read/Write 0000h FMCTRL Word FF F94Ch Read/Write 0000h FMSTAT Word FF F94Eh Read/Write 0000h FMPSR Byte FF F950h Read/Write 04h FMSTART Byte FF F952h Read/Write 18h FMTRAN Byte FF F954h Read/Write 30h FMPROG Byte FF F956h Read/Write 16h FMPERASE Byte FF F958h Read/Write 04h FMMERASE0 Byte FF F95Ah Read/Write EAh FMEND Byte FF F95Eh Read/Write 18h FMMEND Byte FF F960h Read/Write 3Ch FMRCV Byte FF F962h Read/Write 04h FMAR0 Word FF F964h Read Only FMAR1 Word FF F966h Read Only FMAR2 Word FF F968h Read Only Register Name Size Address Access Type Value After Reset Comments

175 www.national.com CP3CN17 Flash Data Memory Interface FSMIBAR Word FF F740h Read/Write 0000h FSMIBDR Word FF F742h Read/Write 0000h FSM0WER Word FF F744h Read/Write 0000h FSMCTRL Word FF F74Ch Read/Write 0000h FSMSTAT Word FF F74Eh Read/Write 0000h FSMPSR Byte FF F750h Read/Write 04h FSMSTART Byte FF F752h Read/Write 18h FSMTRAN Byte FF F754h Read/Write 30h FSMPROG Byte FF F756h Read/Write 16h FSMPERASE Byte FF F758h Read/Write 04h FSMMERASE0 Byte FF F75Ah Read/Write EAh FSMEND Byte FF F75Eh Read/Write 18h FSMMEND Byte FF F760h Read/Write 3Ch FSMRCV Byte FF F762h Read/Write 04h FSMAR0 Word FF F764h Read Only FSMAR1 Word FF F766h Read Only FSMAR2 Word FF F768h Read Only CVSD/PCM Converter CVSDIN Word FF FC20h Write Only 0000h CVSDOUT Word FF FC22h Read Only 0000h PCMIN Word FF FC24h Write Only 0000h PCMOUT Word FF FC26h Read Only 0000h LOGIN Byte FF FC28h Write Only 0000h LOGOUT Byte FF FC2Ah Read Only 0000h LINEARIN Word FF FC2Ch Write Only 0000h LINEAROUT Word FF FC2Eh Read Only 0000h CVCTRL Word FF FC30h Read/Write 0000h CVSTAT Word FF FC32h Read Only 0000h CVTEST Word FF FC34h Read/Write 0000h CVRADD Word FF FC36h Read/Write 0000h CVRDAT Word FF FC38h Read/Write 0000h CVDECOUT Word FF FC3Ah Read Only 0000h Register Name Size Address Access Type Value After Reset Comments

www.national.com 176 CP3CN17CVENCIN Word FF FC3Ch Read Only 0000h CVENCPR Word FF FC3Eh Read Only 0000h Triple Clock + Reset CRCTRL Byte FF FC40h Read/Write 00X0 0110b PRSFC Byte FF FC42h Read/Write 4Fh PRSSC Byte FF FC44h Read/Write B6h PRSAC Byte FF FC46h Read/Write FFh Power Management PMMCR Byte FF FC60h Read/Write 00h PMMSR Byte FF FC62h Read/Write 0000 0XXXb Multi-Input Wake-Up WKEDG Word FF FC80h Read/Write 00h WKENA Word FF FC82h Read/Write 00h WKICTL1 Word FF FC84h Read/Write 00h WKICTL2 Word FF FC86h Read/Write 00h WKPND Word FF FC88h Read/Write 00h Bits may only be set; writing 0 has no effect. WKPCL Word FF FC8Ah Write Only XXh WKIENA Word FF FC8Ch Read/Write 00h General-Purpose I/O ports PBALT Byte FF FB00h Read/Write 00h PBDIR Byte FF FB02h Read/Write 00h PBDIN Byte FF FB04h Read Only XXh PBDOUT Byte FF FB06h Read/Write XXh PBWPU Byte FF FB08h Read/Write 00h PBHDRV Byte FF FB0Ah Read/Write 00h PBALTS Byte FF FB0Ch Read/Write 00h PCALT Byte FF FB10h Read/Write 00h PCDIR Byte FF FB12h Read Only 00h PCDIN Byte FF FB14h Read/Write XXh PCDOUT Byte FF FB16h Read/Write XXh Register Name Size Address Access Type Value After Reset Comments

177 www.national.com CP3CN17 PCWPU Byte FF FB18h Read/Write 00h PCHDRV Byte FF FB1Ah Read/Write 00h PCALTS Byte FF FB1Ch Read/Write 00h I/O ports with Alternate Functions PGALT Byte FF FCA0h Read/Write 00h PGDIR Byte FF FCA2h Read/Write 00h PGDIN Byte FF FCA4h Read Only XXh PGDOUT Byte FF FCA6h Read/Write XXh PGWPU Byte FF FCA8h Read/Write 00h PGHDRV Byte FF FCAAh Read/Write 00h PGALTS Byte FF FCACh Read/Write 00h PHALT Byte FF FCC0h Read/Write 00h PHDIR Byte FF FCC2h Read/Write 00h PHDIN Byte FF FCC4h Read Only XXh PHDOUT Byte FF FCC6h Read/Write XXh PHWPU Byte FF FCC8h Read/Write 00h PHHDRV Byte FF FCCAh Read/Write 00h PHALTS Byte FF FCCCh Read/Write 00h PIALT Byte FF FEE0h Read/Write 00h PIDIR Byte FF FEE2h Read/Write 00h PIDIN Byte FF FEE4h Read Only XXh PIDOUT Byte FF FEE6h Read/Write XXh PIWPU Byte FF FEE8h Read/Write 00h PIHDRV Byte FF FEEAh Read/Write 00h PIALTS Byte FF FEECh Read/Write 00h Advanced Audio Interface ARFR Word FF FD40h Read Only 0000h ARDR0 Word FF FD42h Read Only 0000h ARDR1 Word FF FD44h Read Only 0000h ARDR2 Word FF FD46h Read Only 0000h ARDR3 Word FF FD48h Read Only 0000h ATFR Word FF FD4Ah Write Only XXXXh ATDR0 Word FF FD4Ch Write Only 0000h Register Name Size Address Access Type Value After Reset Comments

www.national.com 178 CP3CN17ATDR1 Word FF FD4Eh Write Only 0000h ATDR2 Word FF FD50h Write Only 0000h ATDR3 Word FF FD52h Write Only 0000h AGCR Word FF FD54h Read/Write 0000h AISCR Word FF FD56h Read/Write 0000h ARSCR Word FF FD58h Read/Write 0004h ATSCR Word FF FD5Ah Read/Write F003h ACCR Word FF FD5Ch Read/Write 0000h ADMACR Word FF FD5Eh Read/Write 0000h Interrupt Control Unit IVCT Byte FF FE00h Read Only 10h Fixed Addr. NMISTAT Byte FF FE02h Read Only 00h EXNMI Byte FF FE04h Read/Write XXXX 00X0b ISTAT0 Word FF FE0Ah Read Only 0000h ISTAT1 Word FF FE0Ch Read Only 0000h IENAM0 Word FF FE0Eh Read/Write 0000h IENAM1 Word FF FE10h Read/Write 0000h UART UTBUF Byte FF FE40h Read/Write XXh URBUF Byte FF FE42h Read Only XXh UICTRL Byte FF FE44h Read/Writ e 01h Bits 0:1 read only USTAT Byte FF FE46h Read only 00h UFRS Byte FF FE48h Read/Write 00h UMDSL1 Byte FF FE4Ah Read/Write 00h UBAUD Byte FF FE4Ch Read/Write 00h UPSR Byte FF FE4Eh Read/Write 00h UOVR Byte FF FE50h Read/Write 00h UMDSL2 Byte FF FE52h Read/Write 00h USPOS Byte FF FE54h Read/Write 06h Microwire/SPI interface MWDAT Word FF FE60h Read/Write XXXXh MWCTL1 Word FF FE62h Read/Write 0000h Register Name Size Address Access Type Value After Reset Comments

179 www.national.com CP3CN17 MWSTAT Word FF FE64h Read Only All imple- mented bits are 0 ACCESS.bus ACBSDA Byte FF FEC0h Read/Write XXh ACBST Byte FF FEC2h Read/Write 00h ACBCST Byte FF FEC4h Read/Write 00h ACBCTL1 Byte FF FEC6h Read/Write 00h ACBADDR Byte FF FEC8h Read/Write XXh ACBCTL2 Byte FF FECAh Read/Write 00h ACBADDR2 Byte FF FECCh Read/Write XXh ACBCTL3 Byte FF FECEh Read/Write 00h Timing and Watchdog TWCFG Byte FF FF20h Read/Write 00h TWCP Byte FF FF22h Read/Write 00h TWMT0 Word FF FF24h Read/Write FFFFh T0CSR Byte FF FF26h Read/Write 00h WDCNT Byte FF FF28h Write Only 0Fh WDSDM Byte FF FF2Ah Write Only 5Fh Multi-Function Timer TCNT1 Word FF FF40h Read/Write XXh TCRA Word FF FF42h Read/Write XXh TCRB Word FF FF44h Read/Write XXh TCNT2 Word FF FF46h Read/Write XXh TPRSC Byte FF FF48h Read/Write 00h TCKC Byte FF FF4Ah Read/Write 00h TCTRL Byte FF FF4Ch Read/Write 00h TICTL Byte FF FF4Eh Read/Write 00h TICLR Byte FF FF50h Read/Write 00h Register Name Size Address Access Type Value After Reset Comments

www.national.com 180 CP3CN17 Versatile Timer Unit MODE Word FF FF80h Read/Write 0000h IO1CTL Word FF FF82h Read/Write 0000h IO2CTL Word FF FF84h Read/Write 0000h INTCTL Word FF FF86h Read/Write 0000h INTPND Word FF FF88h Read/Write 0000h CLK1PS Word FF FF8Ah Read/Write 0000h COUNT1 Word FF FF8Ch Read/Write 0000h PERCAP1 Word FF FF8Eh Read/Write 0000h DTYCAP1 Word FF FF90h Read/Write 0000h COUNT2 Word FF FF92h Read/Write 0000h PERCAP2 Word FF FF94h Read/Write 0000h DTYCAP2 Word FF FF96h Read/Write 0000h CLK2PS Word FF FF98h Read/Write 0000h COUNT3 Word FF FF9Ah Read/Write 0000h PERCAP3 Word FF FF9Ch Read/Write 0000h DTYCAP3 Word FF FF9Eh Read/Write 0000h COUNT4 Word FF FFA0h Read/Write 0000h PERCAP4 Word FF FFA2h Read/Write 0000h DTYCAP4 Word FF FFA4h Read/Write 0000h Register Name Size Address Access Type Value After Reset Comments

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25.0 Register Bit Fields

The following tables show the functions of the bit fields of the device registers. For more information on using these regis- ters, see the detailed description of the applicable function elsewhere in this data sheet. CAN Control/ Status 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 CGCR Reserved EIT DIAG EN INTE RNAL LOOP BACK IGN ACK LO DD IR TST PEN BUFF LOCK CRX CTX CAN EN CTIM PSC[6:0] SJW[1:0] TSEG1[3:0] TSEG2[2:0] GMSKB GM[28:18] RTR IDE GM[17:15] GMSKX GM[14:0] XRTR BMSKB BM[28:18] RTR IDE BM[17:15] BMSKX BM[14:0] XRTR CIEN EI EN IEN[14:0] CIPND EI PND IPND[14:0] CICLR EI CLR ICLR[14:0] CICEN EI CEN ICEN[14:0] CSTPND Reserved NS[2:0] IRQ IST[3:0] CANEC REC[7:0] TEC[7:0] CEDIAG Res. DRI VE MON CRC STU FF TXE EBID[5:0] EFID[3:0] CTMR CTMR[15:0]

www.national.com 182 CP3CN17 CAN Memory Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMBn.ID1 XI28 ID10 XI27 ID9 XI26 ID8 XI25 ID7 XI24 ID6 XI23 ID5 XI22 ID4 XI21 ID3 XI20 ID2 XI19 ID1 XI18 ID0 SRR RTR IDE XI17 XI16 XI15 CMBn.ID0 XI14 XI13 XI12 XI11 XI10 XI9 X I8 XI7 XI6 XI5 XI4 XI3 XI2 XI1 XI0 RTR CMBn.DATA0 Data 1.7 Data 1.6 Data 1.5 Data 1.4 Data 1.3 Data 1.2 Data 1.1 Data 1.0 Data 2.7 Data 2.6 Data 2.5 Data 2.4 Data 2.3 Data 2.2 Data 2.1 Data 2.0 CMBn.DATA1 Data 3.7 Data 3.6 Data 3.5 Data 3.4 Data 3.3 Data 3.2 Data 3.1 Data 3.0 Data 4.7 Data 4.6 Data 4.5 Data 4.4 Data 4.3 Data 4.2 Data 4.1 Data 4.0 CMBn.DATA2 Data 5.7 Data 5.6 Data 5.5 Data 5.4 Data 5.3 Data 5.2 Data 5.1 Data 5.0 Data 6.7 Data 6.6 Data 6.5 Data 6.4 Data 6.3 Data 6.2 Data 6.1 Data 6.0 CMBn.DATA3 Data 7.7 Data 7.6 Data 7.5 Data 7.4 Data 7.3 Data 7.2 Data 7.1 Data 7.0 Data 8.7 Data 8.6 Data 8.5 Data 8.4 Data 8.3 Data 8.2 Data 8.1 Data 8.0 CMBn.TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP TSTP CMBn.CNSTAT DLC3 DLC2 DLC1 DLC0 Reserved PRI3 PRI2 PRI1 PRI0 ST3 ST2 ST1 ST0 DMAC Registers 2 0 . . 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 ADCA Device A Address Counter ADRA Device A Address ADCB Device B Address Counter ADRB Device B Address BLTC N/A Block Length Counter BLTR N/A Block Length DMACNTL N/A Res. INCB ADB INCA ADA SW RQ Res. OT DIR IND TCS EO VR ETC CH EN DMASTAT N/A Reserved VLD CH AC OVR TC System Configuration Registers 7 6 5 43210 MCFG Reserved MEM_IO_ SPEED MISC_IO_ SPEED Reserved SCLKOE MCLKOE PLLCLKOE EXIOE DBGCFG Reserved FREEZE ON MSTAT Reserved DPGM BUSY PGMBUSY OENV2 OENV1 OENV0

183 www.national.com CP3CN17 BIU Registers 1 5 1 2 1 1 1 0 9876543210 BCFG Reserved EWR IOCFG Reserved IPST Res. BW Reserved HOLD WAIT SZCFG0 Reserved FRE IPRE IPST Res. BW WBR RBE HOLD WAIT SZCFG1 Reserved FRE IPRE IPST Res. BW WBR RBE HOLD WAIT SZCFG2 Reserved FRE IPRE IPST Res. BW WBR RBE HOLD WAIT T B I R e g i s t e r 76543210 TMODE Reserved TSTEN ENMEM TMSEL Flash Program Memory Interface Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMIBAR Reserved IBA FMIBDR IBD FM0WER FM0WE[15:0] FM1WER FM1WE[15:0] FM2WER FM2WE[15:0] FM3WER FM3WE[15:0] FMCTRL Reserved MER PER PE IENP ROG DIS VRF Res. CWD LOW PRW FMSTAT Reserved DE RR FM FULL FM BUSY PERR EERR FMPSR Reserved FTDIV[4:0] FMSTART Reserved FTSTART[7:0] FMTRAN Reserved FTTRAN[7:0] FMPROG Reserved FTPROG[7:0] FMPERASE Reserved FTPER[7:0] FMMERASE0 Reserved FTMER[7:0] FMEND Reserved FTEND[7:0] FMMEND Reserved FTMEND[7:0] FMRCV Reserved FTRCV[7:0]

www.national.com 184 CP3CN17 FMAR0 Reserved Res. FMAR1 WRPROT RDPROT ISPE EMPTY BOOTAREA FMAR2 CADR15:0 Flash Program Memory Interface Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Flash Data Memory Interface Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSMIBAR Reserved IBA FSMIBDR IBD FSM0WER FM0WE[15:0] FSM1WER FM1WE[15:0] FSM2WER FM2WE[15:0] FSM3WER FM3WE[15:0] FSMCTRL Reserved MER PER PE IENP ROG DIS VRF Res. CWD LOW PRW FSMSTAT Reserved DE RR FM FULL FM BUSY PE RR EE RR FSMPSR Reserved FTDIV[3:0] FSMSTART Reserved FTSTART[7:0] FSMTRAN Reserved FTTRAN[7:0] FSMPROG Reserved FTPROG[7:0] FSMPERASE Reserved FTPER[7:0] FSMMERASE0 Reserved FTMER[7:0] FSMEND Reserved FTEND[7:0] FSMMEND Reserved FTMEND[7:0] FSMRCV Reserved FTRCV[7:0] FSMAR0 Reserved Res. FSMAR1 WRPROT RDPROT ISPE EMPTY BOOTAREA FSMAR2 CADR15:0

185 www.national.com CP3CN17 CVSD/PCM Registers 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 CVSDIN CVSDIN CVSDOUT CVSDOUT PCMIN PCMIN PCMOUT PCMOUT LOGIN Reserved LOGIN LOGOUT Reserved LOGOUT LINEARIN LINEARIN LINEAROUT LINEAROUT CVCTRL Reserved PCM CO NV CVSD CONV DMA PI DMA PO DMA CI DMA CO CVS DER RINT CVS DINT PCM INT CLK EN CV EN CVSTAT Reserved CVOUTST CVINST CVF CVE PCM INT CVN F CV NE CVTEST Reserved TEST _VAL ENC _IN DEC _EN RT TB CVRADD Reserved CVRADD[6:0] CVRDAT CVRDAT[15:0] CVDECOUT CVDECOUT[15:0] CVENCIN CVENCIN[15:0] CVENCPR CVENCPRT[15:0] CLK3RES Registers 76543210 CRCTRL Reserved POR ACE2 ACE1 PLLPWD FCLK SCLK PRSFC Reserved MODE FCDIV PRSSC SCDIV PRSAC ACDIV2 ACDIV1 P M M R e g i s t e r 76543210 PMMCR HCCH HCCM DHC DMC WBPSM HALT IDLE PSM PMMSR Reserved OHC OMC OLC

www.national.com 186 CP3CN17 MIWU16 Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEDG WKED WKENA WKEN WKICTL1 WKINTR7 WKINTR6 WKINTR5 WKIN TR4 WKINTR3 WKINTR2 WKINTR1 WKINTR0 WKICTL2 WKINTR15 WKINTR14 WKINTR13 WKINT R12 WKINTR11 WKINTR10 WKINTR9 WKINTR8 WKPND WKPD WKPCL WKCL WKIENA WKIEN GPIO Registers 7 6 5 4 3 2 1 0 PxALT Px Pins Alternate Function Enable PxDIR Px Port Direction PxDIN Px Port Output Data PxDOUT Px Port Input Data PxWPU Px Port Weak Pull-Up Enable PxHDRV Px Port High Drive Strength Enable PxALTS Px Pins Alternate F unction Source Selection AAI Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARSR ARSH ARSL ATSR ATSH ATSL ARFR ARFH ARFL ARDR0 ARDH ARDL ARDR1 ARDH ARDL ARDR2 ARDH ARDL ARDR3 ARDH ARDL ATFR ATFH ARFL ATDR0 ATDH ATDL ATDR1 ATDH ATDL ATDR2 ATDH ATDL ATDR3 ATDH ATDL AGCR CLK EN AAI EN IOM2 IFS FSL[1:0] CTF CRF IEBC FSS IEFS SCS[1:0] LPB DWL ASS

187 www.national.com CP3CN17 AISCR Reserved TX EIC TX IC RX EIC RX IC TX EIP TX IP RX EIP RX IP TX EIE TX IE RX EIE RX IE ARSCR RXFWM[3:0] RXDSA[3: 0] RXSA[3:0] RXO RXE RXF RX AF ATSCR TXFWM[3:0] TXDSA[3:0] TXSA[3:0] TXU TXF TXE TXAE ACCR BCPRS[7:0] FCPRS[6:0] CSS ADMACR Reserved ACO[1:0] A CD{2:0] TMD[3:0] RMD[3:0] AAI Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IVCT Reserved 0 0 INTVECT[5:0] ISTAT0 IST(15:0) ISTAT1 IST(31:16) IENAM0 IENA(15:0) IENAM1 IENA(31:16) UART Registers 76543210 UTBUF UTBUF URBUF URBUF UICTRL UEEI UERI UETI UEFCI UCTS UDCTS URBF UTBE USTAT Reserved UXMIP URB9 UBKD UERR UDOE UFE UPE UFRS Reserved UPEN UPSEL UXB9 USTP UCHAR UMDSL1 URTS UFCE UERD UETD UCKS UBRK UATN UMOD UBAUD UDIV[7:0] UPSR UPSC[4:0] UDIV[10:8] UOVR Reserved UOVSR[3:0] UMDSL2 Reserved USMD USPOS Reserved USAMP[3:0] MWSPI16 Registers 1 5 . . . 9876543210 MWDAT MWDAT MWCTL1 SCDV SCIDL SCM EIW EIR EIO ECHO MOD MNS MWEN MWSTAT Reserved OVR RBF BSY

www.national.com 188 CP3CN17 A C B R e g i s t e r s 76543210 ACBSDA DATA ACBST SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT ACBCST ARPMATCH MATCHAF TGSCL TSDA GMATCH MATCH BB BUSY ACBCTL1 STASTRE NMINTE GCMEN ACK Reserved INTEN STOP START ACBADDR SAEN ADDR ACBCTL2 SCLFRQ[6:0] ENABLE ACBADDR2 SAEN ADDR ACBCTL3 Reserved ARPEN SCLFRQ[8:7] T W M R e g i s t e r s 1 5 . . . 8 76543210 TWCFG Reserved Reserved WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG TWCP Reserved Reserved MDIV TWMT0 PRESET T0CSR Reserved Reserved FRZT0E WDTLD T0INTE TC RST WDCNT Reserved PRESET WDSDM Reserved RSTDATA MFT16 Registers 1 5 . . . 8 76543210 TCNT1 TCNT1 TCRA TCRA TCRB TCRB TCNT2 TCNT2 TPRSC Reserved Reserved CLKPS TCKC Reserved Reserved C2CSEL C1CSEL TCTRL Reserved TEN TAOUT TBEN TAEN TBEDG TAEDG TMDSEL TICTL Reserved TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND TICLR Reserved Reserved TDCLR TCCLR TBCLR TACLR

189 www.national.com CP3CN17 VTU Registers 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 MODE TMOD4 T8 RUN RUN TMOD3 T6 RUN RUN TMOD2 T4 RUN RUN TMOD1 T2 RUN RUN IO1CTL P4 POL C4EDG P3 POL C3EDG P2 POL C2EDG P1 POL C1EDG IO2CTL P7 POL C7EDG P6 POL C6EDG P5 POL C5EDG P5 POL C5EDG INTCTL I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN INTPND I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD CLK1PS C2PRSC C1PRSC COUNT1 CNT1 PERCAP1 PCAP1 DTYCAP1 DCAP1 COUNT2 CNT2 PERCAP2 PCAP2 DTYCAP2 DCAP2 CLK2PS C4PRSC C3PRSC COUNT3 CNT3 PERCAP3 PCAP3 DTYCAP3 DCAP3 COUNT4 CNT4 PERCAP4 PCAP4 DTYCAP4 DCAP4

www.national.com 190 CP3CN17

26.0 Electrical Characteristics

26.1 ABSOLUTE MAXIMUM RATINGS

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distribu- tors for availability and specifications. Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings. *The latch-up tolerance on ACCESS.bus pins exceeds 150 mA.

26.2 DC ELECTRICAL CHARACTERISTICS (Temperature: -40°C ≤ TA ≤ +85°C)

Supply voltage (VCC) 3.6V All input and output voltages with re- spect to GND* -0.5V to IOVCC + 0.5V ESD protection level 2 kV (Human Body Model) Allowable sink/source current per signal pin ±10 mA Total current into IOVCC pins 200 mA Total current into VCC pins (source) 200 mA Total current out of GND pins (sink) 200 mA Latch-up immunity ±200 mA Storage temperature range -65°C to +150°C Symbol Parameter Conditions Min Max Units Vcc Digital Logic Supply Voltage 2.25 2.75 V IOVcc I/O Supply Voltage 2.25 3.63 V AVcc Analog PLL Supply Voltage 2.25 2.75 V V IL Logical 0 Input Voltage (except X2CKI) -0.5 a 0.3 Vcc V VIH Logical 1 Input Voltage (except X2CKI) 0.7 IOVcc IOVcc + 0.5 a V Vxl1 X1CKI Low Level Input Voltage External X1 clock -0.5 a 0.3 Vcc V Vxh1 X1CKI High Level Input Voltage OSC External X1 clock 0.7 Vcc Vcc + 0.5 V Vxl2 X2CKI Logical 0 Input Voltage External X2 clock -0.5 a 0.6 V Vxh2 X2CKI Logical 1 Input Voltage External X2 clock 0.7 Vcc Vcc + 0.5 V Vhys Hysteresis Loop Width a 0.1 IOVcc V IOH Logical 1 Output Current V OH = 1.8V, IOVcc = 2.25V -1.6 mA IOL Logical 0 Output Current V OL = 0.45V, IOVcc = 2.25V 1.6 mA IOLACB SDA, SCL Logical 0 Output Current V OL = 0.4V, IOVcc = 2.25V 3.0 mA IOHW Weak Pull-up Current V OH = 1.8V, IOVcc =2.25V -10 µA IIL RESET pin Weak Pull-down Current V IL = 0.45V, IOVcc = 2.25V 0.4 µA IL High Impedance Input Leakage Current 0V ≤ Vin ≤ IOVcc -2.0 2.0 µA IO(Off) Output Leakage Current (I/O pins in input mode) 0V ≤ Vout ≤ Vcc -2.0 2.0 µA Icca1 Digital Supply Current Active Mode b Vcc = 2.75V, IOVcc = 3.63V 12 mA Icca2 Digital Supply Current Active Mode c Vcc = 2.75V, IOVcc = 3.63V 8m A Iccprog Digital Supply Current Active Mode d Vcc = 2.75V, IOVcc = 3.63V 15 mA

191 www.national.com CP3CN17 Iccps Digital Supply Current Power Save Mode e Vcc = 2.75V, IOVcc = 3.63V 4.0 mA Iccid Digital Supply Current Idle Mode f Vcc = 2.75V, IOVcc = 3.63V 950 µA Iccq Digital Supply Current Halt Mode f,g Vcc = 2.75V, IOVcc = 3.63V 700 µA a. Guaranteed by design b. Test code executing from internal RAM. No peripheral blocks other than PLL and Auxiliary Clock enabled. X1CLKI is 24 MHz. Not programming Flash memory. Typical applications will show 16 mA (Icca1 + 4 mA) at 24 MHz executing code from flash memory. c. Waiting for interrupt on executing WAIT instruction, Iout = 0 mA, X1CKI = 12 MHz, PLL enabled (4×), internal system clock is 24 MHz, not programming Flash memory d. Same conditions as Icca1, but programming or erasing Flash memory page e. Running from internal memory (RAM), Iout = 0 mA , XCKI1 = 12 MHz, PLL disabled, X2CKI = 32.768 kHz, device put in power-save mode, Slow Clock derived from XCKI1 f. Iout = 0 mA, XCKI1 = off, X2CKI = 32.768 kHz g. Halt current approximately doubles for every 20°C. Symbol Parameter Conditions Min Max Units

www.national.com 192 CP3CN17

26.3 FLASH MEMORY ON-CHIP PROGRAMMING

Symbol Parameter Conditions Min Max Units tSTART Program/Erase to NVSTR Setup Timea (NVSTR = Non-Volatile Storage a. Program/erase to NVSTR Setup Time is determined by the following equation: tSTART = Tclk × (FTDIV + 1) × (FTSTART + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTSTART is the contents of the FMSTART or FSMSTART register 5- µ s tTRAN NVSTR to Program Setup Timeb b. NVSTR to Program Setup Time is determined by the following equation: tTRAN = Tclk × (FTDIV + 1) × (FTTRAN + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTTRAN is the contents of the FMTRAN or FSMTRAN register 10 - µs tPROG Programming Pulse Widthc c. Programming Pulse Width is determined by the following equation: tPROG = Tclk × (FTDIV + 1) × 8 × (FTPROG + 1), where Tclk is the System Clock period, FTDIV is the con- tents of the FMPSR or FSMPSR register, and FTPROG is the contents of the FMPROG or FSMPROG regis- ter 20 40 µs tPERASE Page Erase Pulse Widthd d. Page Erase Pulse Width is determined by the following equation: tPERASE = Tclk × (FTDIV + 1) × 4096 × (FTPER + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTPER is the contents of the FMPERASE or FSMPER- ASE register 20 - ms tMERASE Module Erase Pulse Widthe e. Module Erase Pulse Width is determined by the following equation: tMERASE = Tclk × (FTDIV + 1) × 4096 × (FTMER + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTMER is the contents of the FMMERASE0 or FSMMERASE0 register 200 - ms tEND NVSTR Hold Timef f. NVSTR Hold Time is determined by the following equation: tEND = Tclk × (FTDIV + 1) × (FTEND + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTEND is the contents of the FMEND or FSMEND register 5- µ s tMEND NVSTR Hold Time (Module Erase)g g. NVSTR Hold Time (Module Erase) is determined by the following equation: tMEND = Tclk × (FTDIV + 1) × 8 × (FTMEND + 1), where Tclk is the System Clock period, FTDIV is the con- tents of the FMPSR or FSMPSR register, and FTMEND is the contents of the FMMEND or FSMMEND regis- ter 100 - µs tRCV Recovery Timeh h. Recovery Time is determined by the following equation: tRCV = Tclk × (FTDIV + 1) × (FTRCV + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTRCV is the contents of the FMRCV or FSMRCV register 1- µ s tHV Cumulative Program High Voltage Period For Each Row After Erasei i. Cumulative program high voltage period for each row after erase t HV is the accumulated duration a flash cell is exposed to the programming voltage after the last erase cycle. 128K program blocks - 8 ms tHV 8K data block - 4 ms Write/Erase Endurance 20,000 - cycles Data Retention 25 °C1 0 0 - y e a r s

193 www.national.com CP3CN17

26.4 OUTPUT SIGNAL LEVELS

All output signals are powered by the digital supply (VCC). Table 69 summarizes the states of the output signals during the reset state (when VCC power exists in the reset state) and during the Power Save mode. The RESET and NMI input pins are active during the Power Save mode. In order to guarantee that the Power Save cur- rent not exceed 1 mA, these inputs must be driven to a volt- age lower than 0.5V or higher than VCC - 0.5V. An input voltage between 0.5V and (VCC - 0.5V) may result in power consumption exceeding 1 mA.

26.5 CLOCK AND RESET TIMING

Table 69 Output Pins Duri ng Reset and Power-Save Signals on a Pin Reset State (with Vcc) Power Save Mode Comments PB7:0 TRI-STATE Previous state I/O ports will maintain their values when entering power-save modePC7:0 TRI-STATE Previous state PG7:0 TRI-STATE Previous state PH7:0 TRI-STATE Previous state PI7:0 TRI-STATE Previous state Table 70 Clock and Reset Signals Symbol Figure Description Referenc e Min (ns) Max (ns) Clock Input Signals tX1p 88 X1 period Rising Edge (RE) on X1 to next RE on X1 83.33 83.33 tX1h 88 X1 high time, external clock At 2V level (Both Edges) (0.5 Tclk) - 5 tX1l 88 X1 low time, external clock At 0.8V level (Both Edges) (0.5 Tclk) - 5 tX2p 88 X2 period a RE on X2 to next RE on X2 10,000 tX2h 88 X2 high time, external clock At 2V level (both edges) (0.5 Tclk) - 500 tX2l 88 X2 low time, external clock At 0.8V level (both edges) (0.5 Tclk) - 500 tIH 89 Input hold time (NMI , RXD1, RXD2) After RE on CLK 0 Reset and NMI Input Signals tIW 89 NMI Pulse Width NMI Falling Edge (FE) to RE 20 tRST 90 RESET Pulse Width RESET FE to RE 100 tR 90 Vcc Rise Time 0.1 Vcc to 0.9 Vcc a. Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be used between X2CKI and X2CKO. If Slow Clock is internally generated from Main Clock, it may not exceed this given limit.

Figure 88. Clock Timing Figure 89. NMI Signal Timing Figure 90. Non-Power-On Reset Figure 91. Power-On Reset

0.9 VCC

0.1 VCC

26.6 UART TIMING

Figure 92. UART Synchronous Mode Timing

26.7 I/O PORT TIMING

Figure 93. I/O Port Timing

26.8 ADVANCED AUDIO INTERFACE (AAI) TIMING

Figure 94. Receive Timi ng, Short Frame Sync

199 www.national.com CP3CN17

26.9 MICROWIRE/SPI TIMING

Table 74 Microwir e/SPI Signals Symbol Figure Description Referenc e Min (ns) Max (ns) Microwire/SPI Input Signals tMSKh 98 Microwire Clock High At 2.0V (both edges) 80 - tMSKl 98 Microwire Clock Low At 0.8V (both edges) 80 - tMSKp Microwire Clock Period SCIDL bit = 0; Rising Edge (RE) MSK to next RE MSK 200

99 SCIDL bit = 1; Falling Edge

(FE) MSK to next FE MSK - tMSKh 98 MSK Hold (slave only) After MWCS goes inactive 40 - tMSKs 98 MSK Setup (slave only) Before MWCS goes active 80 - tMCSh MWCS Hold (slave only) SCIDL bit = 0: After FE MSK

99 SCIDL bit = 1: After RE

MWCS Setup (slave only) SCIDL bit = 0: Before RE MSK

99 SCIDL bit = 1: Before FE

Microwire Data In Hold (master) Normal Mode: After RE MSK

100 Alternate Mode: After FE

Microwire Data In Hold (slave) Normal Mode: After RE MSK Normal Mode: Before RE MSK

100 Alternate Mode: Before FE

Microwire/SPI Output Signals tMSKh 98 Microwire Clock High At 2.0V (both edges) 40 - tMSKl 98 Microwire Clock Low At 0.8V (both edges) 40 - tMSKp Microwire Clock Period SCIDL bit = 0: Rising Edge (RE) MSK to next RE MSK 100

99 SCIDL bit = 1: Falling Edge

(FE) MSK to next FE MSK - tMSKd 98 MSK Leading Edge Delayed (master only) Data Out Bit #7 Valid 0.5 tMSK 1.5 tMSK tMDOf 98 Microwire Data Float b (slave only) After RE on MCSn -2 5 tMDOh Microwire Data Out Hold Normal Mode: After FE MSK 0.0

99 Alternate Mode: After RE

tMDOnf 102 Microwire Data No Float (slave only) After FE on MWCS 02 5

Figure 98. Microwire Transaction Timing, Normal Mode, SCIDL = 0

Figure 99. Microwire Transaction Timing, Normal Mode, SCIDL = 1

Figure 100. Microwire Transaction Ti ming, Alternate Mode, SCIDL = 0

www.national.com 204 CP3CN17 26.10 ACCESS.BUS TIMING Table 75 ACCESS.bus Signals Symbol Figure Description Referenc e Min (ns) Max (ns) ACCESS.bus Input Signals tBUFi 104 Bus free time between Stop and Start Condition tSCLhigho - tCSTOsi 104 SCL setup time Before Stop Condition (8 × t CLK) - tSCLri - tCSTRhi 104 SCL hold time After Start Condition (8 × t CLK) - tSCLri - tCSTRsi 104 SCL setup time Before Start Condition (8 × t CLK) - tSCLri - tDHCsi 105 Data High setup time Before SCL Rising Edge (RE) 2 × t CLK - tDLCsi 104 Data Low setup time Before SCL RE 2 × t CLK - tSCLfi 103 SCL signal Rise time - 300 tSCLri 103 SCL signal Fall time - 1000 tSCLlowi 106 SCL low time After SCL Falling Edge (FE) 16 × t CLK - tSCLhighi 106 SCL high time After SCL RE 16 × t CLK - tSDAfl 103 SDA signal Fall time - 300 tSDAri 103 SDA signal Rise time - 1000 tSDAhi 106 SDA hold time After SCL FE 0 - tSDAsi 106 SDA setup time Before SCL RE 2 × t CLK - ACCESS.bus Output Signals tBUFo 104 Bus free time between Stop and Start Condition tSCLhigho - tCSTOso 104 SCL setup time Before Stop Condition t SCLhigho - tCSTRho 104 SCL hold time After Start Condition t SCLhigho - tCSTRso 105 SCL setup time Before Start Condition t SCLhigho - tDHCso 105 Data High setup time Before SCL R.E. t SCLhigho -tSDAro - tDLCso 104 Data Low setup time Before SCL R.E. t SCLhigho -tSDAfo - tSCLfo 103 SCL signal Fall time - 300 c tSCLro 103 SCL signal Rise time - - d tSCLlowo 106 SCL low time After SCL F .E. (K × t CLK) -1e - tSCLhigh o 106 SCL high time After SCL R.E. (K × t CLK) -1e tSDAfo 103 SDA signal Fall time - 300 tSDAro 103 SDA signal Rise time -- tSDAho 106 SDA hold time After SCL F .E. (7 × t CLK) - t SCLfo - tSDAvo 106 SDA valid time After SCL F .E. - (7 × t CLK) + t RD

Figure 106. ACB Data Timing and "i" for input signal timing. unless the parameter already includes the suffix.

26.11 MULTI-FUNCTION TIMER (MFT) TIMING

Figure 107. Multi-Function Timer Input Timing

26.12 VERSATILE TIMI NG UNIT (VTU) TIMING

Figure 108. Versatile Timing Unit Input Timing

209 www.national.com CP3CN17

26.13 EXTERNAL BUS TIMING

Table 78 External Bus Signals Symbol Figure Description Referenc e Min (ns) Max (ns) External Bus Input Signals 109, 111, 112, 113 Input Setup Time D[15:0] Before Rising Edge (RE) on CLK 8 - 109, 111, 112, 113 Output Hold Time D[15:0] After RE on CLK 0 - External Bus Output Signals 109, 110 Output Valid Time D[15:0] After RE on CLK - 8 109, 110, 111, 112, 113 Output Valid Time A[21:0] (CP3BT10) A[22:0] (CP3BT13) After RE on CLK - 8 t 109, 110, 111, 112, 113 Output Active/Inactive Time RD SEL[1:0] SELIO After RE on CLK - 8 109, 110 Output Active/Inactive Time WR[1:0] After RE on CLK - 0.5 Tclk + 8 t7 111 Minimum Inactive Time RD At 2.0V Tclk - 4 - t8 109 Output Float Time D[15:0] After RE on CLK - 8 t9 109 Minimum Delay Time From RD Trailing Edge (TE) to D[15:0] driven Tclk - 4 - t10 109,

110 Minimum Delay Time From RD TE to SELn

Leading Edge (LE) 0 - t11 110 Minimum Delay Time From SELx TE to SELy LE 0 - t12 109, 110, 111, 112, 113 Output Hold Time A22 (CP3BT13 only) A[21:0] D[15:0] RD SEL[2:0] SELIO After RE on CLK 0 - t13 109, 110 Output Hold Time WR[1:0] After RE on CLK 0.5 Tclk - 3 -

Figure 109. Early Write Between Normal Read Cycles (No Wait States)

Figure 110. Late Write Between Normal Read Cycles (No Wait States)

Figure 111. Consecutive Normal Read Cycles (Burst, No Wait States)

Figure 112. Normal Read Cycle (Wai t Cycle Followed by Hold Cycle)

Figure 113. Early Write Between Fast Read Cycles

27.0 Pin Assignments

Figure 114. CP3CN17 in the 100- pin LQFP Package (Top View)

Figure 115. CP3CN17 in the 48-pin CSP Package (Top View)

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28.0 Revision History

Date Major Changes From Previous Version 10/14/02 Original release of full CP3CN17 datasheet. 10/16/02 Corrections to flash memory programming sequence and MFT block diagrams. 11/11/02 Numerous minor corrections. Added more description to AAI section. Added external reset circuit. Fixed problems with figures. 11/21/02 Converted to new format. 1/13/03 Removed erroneous warning to always write the IOCFG register with bit 1 set. Alternate clock source for Advanced Audio Interface changed to Aux1 clock. Changed warning about clock glitches to say Microwire interface must be disabled when modifying bits in MWCTL1 register. Changed bit settings which occur in step 2 of the sequence of ACCESS.bus slave mode address match or global match. Timer Mode Control Register bit 7 is the TEN bit (a bit description has been added). Polarity of all of the bits in the INTCTL register has been inverted. 5/20/03 Updated DC specifications. Fixed errors in Microwire bit and pin names. Changed UART pin names to TXD and RXD. Added Section 11.6 “Auxiliary Clocks”. Changed diagram of I/O Port Pin Logic (Section 14). 11/14/03 Defined valid range of SCDV field in Microwire/SPI module. Noted default PRSSC register value generates a Slow Clock frequency slightly higher than 32768 Hz. Clarified usage of CVSTAT register bits and fields in CVSD/PCM module. Added usage hint for avoiding ACCESS.bus module bus error. Added usage hint for avoiding CAN unexpected loopback condition. 2/28/04 Added entry for CTIM register in CAN section register list. Changed CVSD Conversion section. Changed definition of the RESOLUTION field of the CVSD Control register (CVCTRL). Changed DC specification for Vxl2. 3/16/04 Updated DC specifications Iccid and Iccq. 6/23/04 Moved revision history in front of physical dimensions. Changed back page disclaimers. Changed absolute maximum supply voltage to 3.6V. Changed processor selection guide table. 7/3/04 Changed footnote b in DC specs. Changed product selection guide table. 7/16/04 Changed product selection guide table. 8/24/04 Added AC timing specifications for GPIO and UART. 9/7/04 In Section 17.2, added sentence that an external frame sync must be used in asynchronous mode. In Section 12, in several places noted that Idle and Halt modes may only be entered from Active mode, and the DHC and DMC bits must be set when entering Idle and Halt modes. Added usage hints Section 16.8. Removed Section 20.4.1. 4/4/05 Added new reset circuits. Added note about fluctuations in response due to SDI activity. New back page. Table 79 Revision History (Continued) Date Major Changes From Previous Version

29.0 Physical Dimensions (millimeters) unless otherwise noted

Figure 116. 100-Pin LQFP Package Figure 117. 48-Pin CSP Package

219 www.national.com CP3CN17 Notes

CP3CN17 Reprogrammable Connectivity Processor with CAN Interface National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTE N APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any co mponent of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to af- fect its safety or effectiveness. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materi als meet the provisions of t he Customer Products Stewardsh ip Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no “Banned Substances” as defined in CSP-9-111S2.