DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 27

Technical content

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

11 Configurable GPIO Pins with Alternate Functions

Figure 1. Example System Diagram

48 MHz

12 Mbps

348 Byte PROM

2 Rev. 0.7

Rev. 0.7 3 TABLE OF C ONTENTS Section Page

4 Rev. 0.7 1. System Overview The CP2130 is a highly-integrated USB-to-SPI bridge controller providing a simple solution for bridging a Universal Serial Bus (USB) host to a Serial Peripheral Interfac e (SPI) bus using a minimum of components and PCB space. The CP2130 includes a USB 2. 0 full-speed controller, USB transceiver, oscillator, one-time programmable (OTP) ROM, and a SPI controller in a compact 4 x 4 mm QFN24 package (sometimes called “MLF” or “MLP”). The on-chip, OTP ROM provides the option to custom ize the USB Vendor ID, Product ID, Manufacturer String, Product Description String, Power Descriptor, Device Release Number, Device Serial Number, and GPIO configuration as desired for OEM applications. The CP2130 uses a Silicon Labs vendor-specific USB protocol using control and bulk transfers which is supported by most operating systems through the use of generic USB drivers and interface libraries. A custom driver typically does not need to be developed for th is device. Windows applications co mmunicate with the CP2130 through a Windows DLL which is provided by Silicon Labs that communicates with the Microsoft WinUSB driver via a WinUSB DLL. The interface specification for the CP2130 is also available to enable development of an API for any operating system that supports control and bulk transfers over USB. The CP2130 SPI implements the standard signals, including SCK, MISO, MOSI, CS , as well as a ready-to-read (RTR) hardware handshaking input, so existing syst em firmware does not need to be modified. The SPI capabilities of the CP2130 include fix ed SPI clock rates ranging from 93.75 kHz to 12 MH z, configurable clock phase, configurable clock polarity, adjustable SPI delays, and up to 11 configurable chip select signals. Any of the multi-purpose pins not used as chip select signals may instead be used as GPIO signals that are user- defined. The GPIO signals may also be configured to init iate a USB remote wakeup event on GPIO state change, which allows the CP2130 to wake a USB host from sleep mode. Eight of the GPIO signals support alternate features including ready-to-read (RTR) handshaking, a co nfigurable event counter, a configurable clock output (93.75 kHz to 24 MHz), SPI activity LED toggle, and USB suspend indicators. Support for I/O interface voltages down to 1.8 V is provided via a V IO pin. An evaluation kit for the CP2130 (Part Number: CP2130EK) is available. It includes a CP2130-based USB-to-SPI evaluation board with SPI sl ave devices such as an EEPROM and ADC as well as connections for an external CP2400 LCD controller EVB and SPI monitor. The kit also includes a Windows DLL a nd test application, USB cables, and full documentation. See www.silabs.com for the latest application notes and product support information for the CP2130. C ontact a Silicon Labs sales representatives or go to www.silabs.com to order the CP2130 Evaluation Kit.

  1. Electrical Characteristics

Table 1. Global DC Electrical Characteristics VDD = 3.0 to 3.6 V, –40 to +85 °C unless otherwise specified.

  1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
  2. USB Pull-up current should be added for total supply current. USB normal and suspended supply current is current

flowing into VREGIN. USB normal and suspended supply current is guaranteed by characterization.

  1. The USB Pull-up supply current values are calculated values based on USB specifications. USB Pull-up supply current

is current flowing from VDD to GND through USB pull-down/pull-up resistors on D+ and D-.

Table 2. SPI, Port I/O, and Suspend I/O DC Electrical Characteristics VIO = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Table 3. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Table 4. Voltage Regulator Electrical Specifications –40 to +85 °C unless otherwise specified.

  1. Input range specified for regulation. When the internal regulator is not used, should be tied to VDD.
  2. The maximum regulator supply current is 100 mA. This includes the supply current of the CP2130.

Table 5. GPIO Output Specifications –40 to +85 °C unless otherwise specified. *Note: The clock output frequency is configurable from 93.75 kHz to 24 MHz. Table 6. USB Transceiver Electrical Characteristics* VDD = 3.0 V to 3.6 V, –40 to +85 °C unless otherwise specified. *Note: Refer to the USB Specification for timing diagrams and symbol definitions. Table 7. OTP ROM Electrical Characteristics –40 to +85 °C unless otherwise specified.

Table 8. Thermal Characteristics *Note: Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad. Table 9. Absolute Maximum Ratings* operation of the devices at or exceeding the conditions in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Rev. 0.7 9 3. USB Function Controller and Transceiver The Universal Serial Bus (USB) function controller in the CP2130 is a USB 2.0-compliant, full-speed device with integrated transceiver and on-chip matching and pullup re sistors. The USB function controller manages all data transfers between the USB and the SPI bus as well as command requests generated by the USB host and commands for controlling the function of the SPI and GPIO pins. The USB Suspend and Resume modes are supported for power management of both the CP2130 device as well as external circuitry. The CP2130 enters Suspend mo de when Suspend signaling is detected on the bus. Upon entering Suspend mode, the Suspend signals are asserted. The Suspend signals are also asserted after a CP2130 reset until device configuration and U SB Enumeration is comple te. SUSPEND is logic high when the device is in the Suspend state, and logic low when th e device is in normal mode. The SUSPEND pin has the opposite logic value of the SUSPEND pin. The CP2130 exits Suspend mode when any of the following occur: Resume signaling is detected or generated, a USB Reset signal is detected, the configured GPIO wakeup sources do not match the configured latch value, or a device reset occurs . SUSPEND and SUSPEND are weakly pulled to VIO in a high impedance state during a CP2130 reset. If this behavior is undesirable, a strong pulldown (10 k) can be used to ensure SUSPEND remains low during reset. The CP2130 can be configured to use any of the GPIO pi ns as a remote wakeup source. While suspended, if any of the pins configured as a wakeup source does not ma tch the configured wakeup match value, then the CP2130 will send remote wakeup signaling to the USB host. If the host has conf igured the CP2130 to enable remote wakeup, then the host will send resume signaling to the CP2130 and the device will exit Suspend mode. The logic level and output mode (push-pull or open-drain) of various pins during USB Suspend is configurable in the OTP ROM. See Section 6 for more information.

the double-buffered endpoint is used for OUT transfers and the single-buffered endpoint is used for IN transfers. transfers and the single-buffered endpoint is used for OUT transfers. same clock phase and polarity. The clock and data line relationships are shown in Figure 4. frequency is restricted to discrete values between 93.8 kHz and 12 MHz. Figure 4. Data/Clock Timing Table 10. Typical SPI Throughput

Figure 7. SPI Delays (CPHA = Leading Edge) Figure 8. SPI Delays (CPHA = Trailing Edge) Table 11. SPI Timing Parameters1

12 MHz

1.5 MHz

  1. N = user-specified delay values, where {0 ≤ N ≤ 65535}.
  • SCK is shown for CPOL = Active High. SCK is the opposite polarity for CPOL = Active Low.
  • SCK is shown for CPOL = Active High. SCK is the opposite polarity for CPOL = Active Low.

Customization Guide” available on the Silicon Labs website. programmable for each device. See Section 6 for more information about programming the GPIO pin functionality. voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V. The speed of reading and writing the GPIO pins is subjec t to the timing of the USB interface and host computer. GPIO pins configured as inputs or outputs are not recommended for real-time signaling. The following paragraphs describe the alternate functions available on the corresponding GPIO pin. Table 12. GPIO Pin Alternate Functions Table 13. GPIO Pin Default Configuration

will only read SPI data when the RTR pin is asserted. the device must be configured to use RTR flow control to use this pin. Figure 9. Hardware Flow Control Typical Connection Diagram

pin is connected to an LED to indicate data transfer. Figure 10. SPI Activity Toggle Typical Connection Diagram SUSPEND pin has the opposite logic value of the SUSPEND pin. may respond by resuming the CP2130. Match Mask and Wakeup Match Value are shown in Table 15. revert to the previous function configurations and modes.

  1. One-Time Programmable ROM

been customized, the default configuration data shown in Table 14 and Table 15 is used. multiple CP2130 devices to be connected to the same PC. programming one of the items in the group prevents further programming of any of the other items in the group. and VIO must remain at 3.3 V or higher to successfully write to the configuration OTP ROM. Table 14. Default USB Configuration Data Table 15. Default GPIO, UART, and Suspend Configuration Data

device will be operated in either of the self-powered modes. required to meet the absolute maximum voltage on VBUS specification in Table 9. Figure 11. Typical Bus-Powered Connection Diagram

  1. VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface voltage.
  2. USB connector shield decoupling capacitors and re sistor are not required, but ca n be added for noise immunity.
  3. Avalanche transient vo ltage suppression diodes compatible with Full-speed USB should be added at the

connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.

  1. An external pull-up is not required, but can be added for noise immunity.
  2. If programming the configuration ROM via USB, add a 4.7 F capacitor between VPP and ground.

During a programming operation, do not connect the VPP pin to other circuitry, and ensure that VIO is at least 3.3 V .

3.45 V Power

bypassed is shown in Figure 12. Figure 12. Typical Self-Powered Connection Diagram (Regulator Bypass)

  1. VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface voltage.
  2. USB connector shield decoupling capacitors and resistor are not required, but can be added for noise immunity.
  3. Avalanche transient voltage suppression diodes compatible with Full-speed USB should be added at the

connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.

  1. An external pull-up is not required, but can be added for noise immunity.
  2. If programming the configuration ROM via USB, add a 4.7 F capacitor between VPP and ground.

During a programming operation, do not connect the VPP pin to other circuitry, and ensure that VIO is at least 3.3 V.

  1. For self-powered systems where VDD and VIO may be unpowered when VBUS is connected to 5 V, a resistor

specification in the Electrical Characteristics section.

20 Rev. 0.7 8. CP2130 Interface Specification and Windows Interface DLL The CP2130 is a Bulk Mode USB device and requires a ge neric USB driver such as Microsoft’s WinUSB driver or the open-source LibUSB driver. The CP2130 uses a vendor-specific interface protocol, and so the host application or library must comply with the CP2130 Interface Specification to communicate with the device. The low-level USB specification for the CP2130 is prov ided in application note, “AN792: CP 2130 Interface Specification.” This document describes all of the basic functions for opening, reading from, writing to, and closing the device as well as the OTP ROM programming functions. Silicon Labs also provides an interf ace library that encapsulate s the CP2130 interface an d also adds higher level features such as read/write time-outs. This library is the recommended interface for the CP2130. The interface library is provided as a Windows DLL. Documentation for the interface library API is included in the installation package. AN792: CP2130 Interface Specification and the library are available in the CP2130EK CD as well as online at: www.silabs.com. 9. Relevant Application Notes The following application notes are applicable to the CP21 30. The latest versions of these application notes and their accompanying software are available at http://www.silabs.com/products/Interface/Pages/interface-application-notes.aspx.  AN721: CP21xx Device Customization Guide. This application note describes how to use the AN721 software, CP21xx Customization Utility, to configure the USB parameters on CP2130 devices.  AN792: CP2130 Interface Specification. This application note describes how to interface to the CP2130 using the low-level, USB bulk and control mode Interface.

Figure 13. QFN-24 Pinout Diagram (Top View)

Table 16. CP2130 Pin Definitions

1 SCK D Out SPI clock output

2 GND Ground. Must be tied to ground. IO Power In I/O Supply Voltage Input. Voltage Regulator Output. See Section 7. 7 REGIN Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator. 10* N/C No connect. This pin should be left unconnected or tied to V IO. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. In USB suspend mode, this pin is Low when in USB suspend mode. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. In USB suspend mode, this pin is High when in USB suspend mode. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. In SPI activity mode, this pin toggles to indicate SPI activity. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. programming via the USB interface. *Note: Pin can be left unconnected when not in use.

In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. In clock output mode, this pin outputs a configurable frequency clock signal. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. In event counter mode, this pin is an event counter input. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. In Ready-to-Read mode, this pin is a SPI read flow control input. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output. In GPIO mode, this pin is a user-configurable input or output. In chip select mode, this pin is a SPI chip select output.

23 MOSI D Out SPI master output/slave input

24 MISO D In SPI master input/slave output

Table 16. CP2130 Pin Definitions (Continued) *Note: Pin can be left unconnected when not in use.

  1. QFN-24 Package Specifications

Figure 14. QFN-24 Package Drawing Table 17. QFN-24 Package Dimensions

  1. All dimensions shown are in millimeters (mm) unless otherwise noted.
  2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
  3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for

custom features D2, E2, Z, Y , and L which are toleranced per supplier designation.

  1. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Figure 15. QFN-24 Recommended PCB Land Pattern Table 18. QFN-24 PCB Land Pattern Dimensions

  1. All dimensions shown are in millimeters (mm) unless otherwise noted.
  2. This Land Pattern Design is based on the IPC-7351 guidelines.
  3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 µm minimum, all the way around the pad.

  1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used

to assure good solder paste release.

  1. The stencil thickness should be 0.125 mm (5 mils).
  2. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
  3. A 2 x 2 array of 1.10 x 1.10 mm openings on a 1.30 mm pitch should be used for the center
  4. A No-Clean, Type-3 solder paste is recommended.
  5. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small

26 Rev. 0.7 DOCUMENT CHANGE LIST Revision 0.5 to Revision 0.6  Updated pin configuration functions for GPIO.6 and GPIO.7. Revision 0.6 to Revision 0.7  Moved VBUS to a separate row and updated the specification in Table 9, “Absolute Maximum Ratings*,” on page 8.  Added VPP Voltage specification to Table 7, “OTP  Updated "7. Voltage Regulator" on page 18 to add absolute maximum voltage on VBUS requirements in self-powered systems.  Updated measured throughput numbers in Table 10, “Typical SPI Throughput,” on page 11.

Rev. 0.7 27 CONTACT INFORMATION Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog- intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea- tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran- ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend- ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.