CP2120

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Technical content

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Figure 1. Block Diagram

2 Rev. 0.4

Rev. 0.4 3 TABLE OF CONTENTS Section Page

a command set that governs all CP2120 configuration and operation.

1. Global DC Electrical Characteristics

Table 1. Absolute Maximum Ratings Table 2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified.

Rev. 0.4 5 4. Pinout And Package Definition 4.1. Pin Out Chart Name Pin # Type Description VDD 3 Power Supply Pin GND 2 Ground RST 4 Digital I/O Device Reset. Open -drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. SCLK 1 Digital In SPI Clock Input MISO 20 Digital Out SPI Slave Output MOSI 19 Digital In SPI Slave Input CS 18 Digital In SPI Slave Select SDA 17 Digital I/O I 2C Data Input/Output SCL 16 Digital I/O I 2C Clock Input/Output GPIO 0 5 Digital I/O General Purpose Configurable Digital Input/Output GPIO 1 12 Digital I/O General Purpose Configurable Digital Input/Output GPIO 2 11 Digital I/O General Purpose Configurable Digital Input/Output GPIO 3 10 Digital I/O General Purpose Configurable Digital Input/Output GPIO 4 9 Digital I/O General Purpose Configurable Digital Input/Output GPIO 5 8 Digital I/O General Purpose Configurable Digital Input/Output GPIO 6 7 Digital I/O General Purpose Configurable Digital Input/Output GPIO 7 6 Digital I/O General Purpose Configurable Digital Input/Output EINT 13 Digital I/O Edge-Triggered Interrupt Source INT 14 Digital Out CP2120 Interrupt Indicator NC 15 Digital Out Not connected, leave floating

6 Rev. 0.4 4.2. QFN-20 Pinout Diagram (Top View) SCLK GND VDD RST GPIO 0 GPIO 7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 EINT INT NC SCL SDA CS MOSI MISO CP2120 GND

Rev. 0.4 7 4.3. QFN-20 Pinout Diagram (Bottom View) Table 4.1. QFN-20 Package Dimensions MM MIN TYP MAX A 0.80 0.90 1.00 A1 0 0.02 0.05 A2 0 0.65 1.00 A3 — 0.25 — b 0.18 0.23 0.30 D— 4 . 0 0 — D2 2.00 2.15 2.25 E— 4 . 0 0 — E2 2.00 2.15 2.25 e— 0 . 5 — L 0.45 0.55 0.65 N— 2 0 — ND — 5 — NE — 5 — R0 . 0 9 — — AA — 0.435 — BB — 0.435 — CC — 0.18 — DD — 0.18 —

8 Rev. 0.4 4.4. QFN-20 Solder Paste Recommendations

transactions, while other commands modify or monitor CP2120 operation and events. be issued at any time, even while an I2C transaction is in progress, as they do not initiate any I2C bus transactions. Table 3 shows a list of all internal registers. Table 3. Internal Register Addresses

care" byte, the internal register value is transmitted across the MISO line. The SPI Configuration command configures the bit orientation of transfers across the SPI bus to one of two states. of the values shown in the following table. Any values other than those listed in the table are ignored. Figure 4. SPI Slave Timing

CP2120 will not ACK the address defined in the I2CADR Internal Register. Table 4. SPI Slave Timing Parameters *Note: TSYSCLK equals 24.5 MHz.

Figure 5. Typical I2C Bus* *Note: VDD is defined in Table 1, “Absolute Maximum Ratings,” on page 4. For Rpu values, please see “6.1. Determining Pull-Up Register Values” . those devices’ datasheets. The maximum capacitance allowed before the bus violates I2C specification is 400 pF. frequency. The maximum rise time allowed by the I2C specification is 1000 ns. due to conditions on the bus, such as a slave device extending the SCL low time.

14 Rev. 0.4 Internal Register Definition 1. I2CCLOCK: I2C Clock Frequency Configuration The transaction time-out counter, which terminates an I2C transaction after a set period of time has passed, can be configured through the I2CTO Internal Register. If the time-out counter is not enabled, the CP2120 will make only one attempt at executing an I2C transaction and abort if that transaction attempt fails. Equation 2. CTO Time-Out Frequency Internal Register Definition 2. I2CTO: I2C Time Out The SPI Master can assign an I 2C address to the CP2120 by writing to the I2CADR Internal Register. Setting this address is not necessary for device operation. If set, the CP2120 w ill ACK this address when another I 2C Master on the bus attempts to communicate with it. The CP2120 will NACK all attempts at data transfer when responding as an I2C slave. Internal Register Definition 3. I2CADR: I2C Address Internal Register Address: 0x02 Reset Value: 0xA0 Bit 7-0: I2CCK7-0: I 2C Clock Frequency Configuration value (minimum register value = 5, maximum register value = 255) R/W R/W R/W R/W R/W R/W R/W R/W I2CCK7 I2CCK6 I2CCK5 I2CCK4 I2CCK3 I2CCK2 I2CCK1 I2CCK0 Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 Time-out Frequency TO Internal Register Address: 0x03 Reset Value: 0x00 Bit 7-1: TO6-0: Time Out Value Bit 0: TEN:Time Out Enable Bit. 0: Disable Timer. 1: Enable Timer. R/W R/W R/W R/W R/W R/W R/W R/W TO6 TO5 TO4 TO3 TO2 TO1 TO0 TEN Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 Internal Register Address: 0x05 Reset Value: 0x00 Bit 7-Bit 0: I2CAD7-0: I 2C Address Sets I2C bus address. R/W R/W R/W R/W R/W R/W R/W R/W I2CAD7 I2CAD6 I2CAD5 I2CAD4 I2CAD3 I2CAD2 I2CAD1 I2CAD0 Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0

Rev. 0.4 15 The SPI2I2C provides additional SMBus-related timers to enable I 2C protocol compatibility. Setting the I 2C Bus Free Detect enables the device to poll the SMBus lines and determine when a transfer can begin. Setting the SCL Low Time Out detect will cause an SMBus transaction to abor t if the SCL line has been held low by a device for a period of approximately 25 ms. Internal Register Definition 4. I2CTO2: Additional I2C Time Outs 6.3. I2C Status The CP2120 maintains an Internal Register, I2CSTAT, which describes the current status of the I2C Interface. The I2CSTAT register can be read at any time. The CP2120 updates I2CSTAT when an I 2C transaction begins, when an I2C transaction completes (successfully or unsuccessfully), and when a received SPI command contains errors. It is not recommended that an SPI master poll the CP2120's I2CSTAT Internal Register to determine when an I 2C transaction has completed. The SPI master should instead watch for the INT pin to drop low, and then read the I2CSTAT register to determine the I2C transaction results. Internal Register Address: 0x09 Reset Value: 0x00 Bit 1: I 2C Bus Free Detect 0: Bus Free Detect Disabled 1: Bus Free Detect Enabled Bit 0: I 2C SCL Low Time Out Detect 0: SCL Low Time Out Detect disable 1: SCL Low Time Out Detect enable R/W R/W R/W R/W R/W R/W R/W R/W Reserved Reserved Reserved Rese rved Reserved Reserved FREN LWEN B i t 7B i t 6B i t 5B i t 4 B i t 3 B i t 2B i t 1B i t 0

16 Rev. 0.4 Internal Register Definition 5. I2CSTAT: I2C Status Register Internal Register Address: 0x04 Reset Value: 0x00 RRRRRRRR I2ST7 I2ST6 I2ST5 I2ST4 I2ST3 I2ST2 I2ST1 I2ST0 Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 Bit 7–0 I2ST: I2C Status I2C Status Value Status Description 0xF0 I 2C transaction completed successfully. 0xF1 Slave address NACKed. 0xF2 Slave data NACKed. 0xF3 I 2C transaction in progress. 0xF8 I 2C transaction timed out due to timer configured in I2CTO. 0xF9 Command’s Bytes to Transmit Byte and Data Buffer Size do not match, or Read Buffer read number of bytes greater than buffer count. 0xFA I 2C SCL Low time-out, using timer configured in I2CTO2. 0xFB I 2C bus free detect has been disabled, and the bus is not free.

Rev. 0.4 17 6.4. I2C Receive Buffer Size Bytes received from I 2C transactions are stored in the 255-byte data buffer. The number of bytes currently stored inside this buffer is saved in the RXBUFF Internal Register. Internal Register Definition 6. RXBUFF: Receive Buffer Size Register 6.5. I2C Commands SPI commands initiate all I 2C transactions. The CP2120 executes I 2C transactions only after every byte of the command has been successfully received across the SPI bus. Once the CP2120 has completed the I 2C transaction prompted by th e command, the INT pin will be pulled low to indicate that command execution has completed. If an I 2C command is issued while an I 2C command is in progress, the second I 2C command will be ignored. 6.5.1. Write Bytes to I2C This command transmits data to an I 2C slave device. The command begins with the command byte (0x00), followed by the number of bytes to be transmitted across I 2C, which can range from 1 to 255, and the address of the I2C Slave. The SPI master then sends the data to be transmitted across I2C. Sending more or fewer bytes than was indicated by the second byte of th e command will result in an error condition, and the I2C transaction will not be initiated. Once the I2C transaction completes, the CP2120 pulls the INT pin low and sets the internal register according to the results of the transaction. 6.5.2. Read Bytes from I2C This command attempts to retrieve bytes from an I2C Slave device. The command begins with the command byte, 0x01, followed by the number of bytes to read (1 to 255) and the address of the I2C slave device. Once the I2C transaction completes, the CP2120 pulls the INT pin low and sets I2CSTAT according to the results of the transaction. The CP2120 saves the number of bytes st ored in the buffer in the internal register named RXBUFF. A Read Buffer command can be issued to retrieve the bytes from the buffer. Note that if the SPI Master issues a second Read Bytes from I 2C command before issuing a Read Buffer command, the bytes stored in the CP2120's buffer will be overwritten. Internal Register Address: 0x06 Reset Value: 0x00 Bit 7-0: RXB7-0: Receive Buffer Size Indicates the number of bytes received during the last I2C read transaction. RRRRRRRR RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 DATA BYTE1 DATA BYTE N NUMBER OF BYTES COMMAND 0x00 SLAVE ADDRESS +W ... SPI Master NUMBER OF BYTES COMMAND 0x01 SLAVE ADDRESS +RSPI Master

18 Rev. 0.4 6.5.3. Read Buffer The Read Buffer command retrieves bytes from the CP2120's data buffer. The command begins with the command byte, 0x06. After the command byte, the SPI Master must transmit a single byte of data, which is ignored by the CP2120. After receiving the ignored byte of data, the CP2120 transmits data bytes across the MISO pin. It is recommended that the SPI Master read the RXBUFF Internal Register to determine how many bytes are stored in the CP2120's buffer before issuing a Read Buffer command. If the SPI Master attempts to retrieve more bytes than the buffer contains, the CP212 0 will signal the error in I2CSTAT. If an SPI Master atte mpts to retrieve fewer bytes than are stored in the data buffer, all bytes left in the buffer will be deleted when the Read Buffer command terminates. 6.5.4. Read After Write The Read After Write command writes bytes to one I 2C slave and then reads bytes from another I 2C slave. The SPI Master calls this command by first sending the comma nd byte, 0x02, then the number of bytes to write (1 to 255) and bytes to read (1 to 255). These bytes are followed by the address of the I 2C slave to which the CP2120 will attempt to write bytes, followed by the data bytes to write. The la st byte of the command is the I 2C slave from which the CP2120 will attempt to read bytes. 6.5.5. Write After Write The Write After Write command writes to an I 2C slave device and then issues another write to a second I 2C slave device. The command begins with the command byte, 0x08, followed by the number of bytes to write to the first I2C device and the bytes to write to the second I 2C device. The SPI master sends the slave address of the first I 2C device and the data bytes to write to the first I2C slave. The SPI Master then sends the slave address of the second I2C slave device followed by the data bytes to transmit to that slave device. 6.5.6. Write To Multiple Slaves The Write to Multiple Slaves command allows an SPI Master to write the same data buffer to multiple I 2C slaves. The command begins with the command byte, 0x09, followed by the size of the data buffer (0 to 255), followed by the number of slaves (0 to 254). Next, the list of slave addresses is transmitted. Following that, the data buffer to write to each slave is transmitted. The combined size of the slave address list and the data buffer should not exceed 255 bytes. The I2CSTAT Internal Register shows the results from the last I 2C transaction of the command. COMMAND 0x06 Don’t Care Data Byte 0 Data Byte N... SPI Master CP2120 NUMBER OF WRITE BYTES 0x02 COMMAND SLAVE ADDRESS+W ... NUMBER OF READ BYTES DATA WRITE BYTE 0 DATA WRITE BYTE N SLAVE ADDRESS+R SPI Master NUMBER OF BYTES 1 0x03 COMMAND SLAVE 1 ADDRESS +W ... NUMBER OF BYTES 2 DATA BYTE 1 DATA BYTE N SLAVE 2 ADDRESS +W DATA BYTE 1 ... DATA BYTE NSPI Master Num Bytes0x 09

Rev. 0.4 19 7. Port I/O The CP2120 offers eight general-purpose port pins that c an be configured as output, i nput, or quasi-bidirectional output by writing to the internal regi sters, IOCONFIG and IOCONFIG2. Pin state can be updated by writing to the internal register, IOSTATE. Reading the IOSTATE Internal Register will return the current values of each port pin. The port pin, EINT, can be configured as an edge-triggered interrupt source by writing to the EDGEINT Internal Register. The EIT bit sets the interrupt to trigger upon a 0 to 1 or a 1 to 0 logic change on the pin. The bit, EIE, enables the pin as an interrupt source. Once the interrupt has been configured and enabled, the CP2120 will pull the INT pin low when the port pin's logic value switches to “1'” or “0”, depending on the interrupt configuration specified in the EIT bit. When an interrupt is triggered, EIF in the EDGEINT Internal Register is set. Reading from EDGEINT will clear the EIF bit. Internal Register Definition 7. IOCONFIG: Port I/O Configuration Internal Register Address: 0x00 Reset Value: 0x00 Bit 7-6: PCIO3.1-PCIO3.0: Port Configuration for GPIO Pin 3 Bit 5-4: PCIO2.1-PCIO2.0: Port Configuration for GPIO Pin 2 Bit 3-2: PCIO1.1-PCIO1.0: Port Configuration for GPIO Pin 1 Bit 1-0: PCIO0.1-PCIO0.0: Port Configuration for GPIO Pin 0 These bits select the port state for GPIO pins 3 through 0. R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 PCIOx.1 PCIOx.0 GPIO Pin x Mode 0 0 Open Drain Output 0 1 Input Only 1 0 Push-Pull Output 1 1 Input Only

20 Rev. 0.4 Internal Register Definition 8. IOCONFIG2: Port I/O Configuration 2 Internal Register Definition 9. IOSTATE: Port I/O State Internal Register Address: 0x07 Reset Value: 0x00 Bit 7-6: PCIO7.1-PCIO7.0: Port Configuration for GPIO Pin 7 Bit 5-4: PCIO6.1-PCIO6.0: Port Configuration for GPIO Pin 6 Bit 3-2: PCIO5.1-PCIO5.0: Port Configuration for GPIO Pin 5 Bit 1-0: PCIO4.1-PCIO4.0: Port Configuration for GPIO Pin 4 These bits select the port state for GPIO pins 7 through 4. R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 PCIOx.1 PCIOx.0 GPIO Pin x Mode 0 0 Open Drain Output 0 1 Input Only 1 0 Push-Pull Output 1 1 Input Only Internal Register Address: 0x01 Reset Value: 0x00 Bit 7-0: GPIO7-0: General Purpose Input/Output State Write - Output appears on output pins. 0: GPIOx set to logic low output. 1: GPIO set to logic high output. Read - Reads port state. 0: GPIOx is logic low. 1: GPIOx is logic high. R/W R/W R/W R/W R/W R/W R/W R/W GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0

Rev. 0.4 21 Internal Register Definition 10. EDGEINT: Edge Triggered Interrupt Enable Internal Register Address: 0x08 Reset Value: 0x00 Bit 7: EIF: Edge Triggered Interrupt Flag 0: No edge triggered event has occurred on the EI_INT pin. 1: Edge-triggered event has occurred on the EI_INT pin. Bit 6: EIE: Edge Tri ggered Interrupt Enable 0: Edge Triggered interrupts disabled. 1: Edge Triggered interrupts enabled. Bit 5: EIT: Edge Triggered Interrupt Trigger 0: Interrupt triggered on negative-to-positive digital transition on the EI_INT port pin. 1: Interrupt triggered on positive-to-negative digital transition on the EI_INT port pin. Bit 4–Bit 0: Not used. R/W R/W R/W R/W R/W R/W R/W R/W EIF EIE EIT Rsvd Rsvd Rsvd Rsvd Rsvd Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0

22 Rev. 0.4 8. CP2120 Revision Number The CP2120 revision number can be retrieved by first sending the Revision Number command byte of 0x40 and then transmitting one “don’t care” transitional byte. The CP2120 then transmits the two-byte revision number, most significant byte first, in BCD format. For example, a tran smitted byte sequence of “0x01 0x44” would indicate that the CP2120’s revision number is equal to 1.44. 0x40 COMMAND Don’t Care Rev Num Byte 1 Rev Num Byte 2 SPI Master CP2120

Rev. 0.4 23 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2  Various small text changes.  Updated 4.1 Pin Out Chart.  Updated 4.2 Pin Out Diagram.  Updated Figure 2. SPI Bus Typical Connections.  Added Table 3. Internal Register Addresses.  Updated all CP2120 command drawings.  Added section 6.1 Determining Pull-Up Register Values.  Changed appearance of all Internal Register Definition charts.  Changed contents of Section 8. CP2120 Revision Number. Revision 0.2 to Revision 0.3  Removed references to power down mode.  Corrected Equation 1, “I2C Clock Frequency,” on page 13.  In Internal Register 4, “I2CTO2: Additional I2C Time Outs,” on page 15, changed Internal Register Address to “0x09”.  In Internal Register 5, “I2CSTAT: I2C Status Register,” on page 16, changed all bits to “R” instead of “R/W”  In Internal Register 6, “RXBUFF: Receive Buffer Size Register,” on page 17, changed all bits to “R” instead of “R/W”. Revision 0.3 to Revision 0.4  Updated Figure 1.  Updated Digital Supply Voltage in Table 2.  Updated Figure 3.

24 Rev. 0.4 CONTACT INFORMATION Silicon Laboratories Inc.

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