CP1158 ETC | Alldatasheet
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Technical content
8-port Ethernet Over SDH Mapping Device Copyright ©2006 Chiphomer Technology Limited Page 1 of 3 OVERVIEW The CP1158 is one of the OPTRANS series chips designed by Chiphomer Technology Limited. It is a highly integrated EOS device that provides for mapping of 10/100/1000 Mbit/s Ethernet into SDH STM-1 Transport pay loads. The device supports connection for up to eight 10/100 Mbit/s Ethernet ports, using SMII or SS-SMII interface, or one 1000 Mbit/s Ethernet port, using GMII interface. Ethernet frames are encapsulated using either GFP or HDLC-like prot ocol. The encapsulated Ethernet frames are then mapped into virtually concatenated VC-12, VC-3 or VC-4 payloads. Link Capacity Adjustment Scheme (LCAS) for VC-12/VC-3/VC-4 virtual concatenation is provided to enable hitless addition and removal of bandwidth under the control of a network management system. The VC-12, VC-3 and VC-4 POH generation and termination are performed. A byte-wide 19.44MHz Telecom Bus interface is provided for the SDH interface.
FEATURES
z Supports up to eight ports of full-duplex10/100 Mbit/s Ethernet or a single port of full-duplex 1000 Mbit/s Ethernet with standards-compliant flow control supported: 10/100 Mbit/s Ethernet interf ace supports SMII and SS-SMII 1000 Mbit/s Ethernet interface supports GMII CP1158 IPBC (Ingress Packet Buffer Control) External DDR SDRAM DDR_CTL (DDR SDRAM controlller) MAC RDEC (Receive GFP/HDLC-like Decapsulation) TENC (Transmit GFP/HDLC-like Encapsulation) TVCP (Transmit Virtual Concatenation and LCAS Processing) RVCP (Receive Virtual Concatenation and LCAS Processing) EPBC (Egress Packet Buffer Control ) VC-12 POH Insertion VC-3 /VC-4 POH Insertion VC-12 POH Extraction VC-3/VC-4 POH Extraction Telecom Bus Interface 8 x 10/100 or 1 x 1000 Output bus Input bus Ethernet Line Side Telecom Bus Side MDIO POH (SDH LO/HO Path Overhead Processor) MP (Microprocess Interface) PBGA352 -40 ~ 85 ℃ PBGA352
8-port Ethernet Over SDH Mapping Device Copyright ©2006 Chiphomer Technology Limited Page 2 of 3 z Ethernet Management interface (MDIO) for control and configuration of external connected PHYs z Provides IEEE 802.3 Management Statistics (RMON) z Supports multiple virtual concatenation groups from one Ethernet port based on VLAN tag identification z Supports multiple virtual concatenation groups to one Ethernet port based on the user’s configuration z Supports up to 16 virtual concatenation groups z Supports up to four priority queues, enabling time-sensitive data to have access to the network with minimal delay z Provides RED algorithm for buffer management z Provides per-priority scheduling using Round Robin mechanism z Supports the following encapsulation/decapsulation protocols on a per port basis: ITU-T G.7041, Generic Framing Procedure (GFP) HDLC-like Framing, includi ng the following protocols: ITU-T X.86/X.85, Link Access Procedure SDH (LAPS) RFC1662, Point-to-Point Protocol (PPP) RFC3518, PPP Bridging Control Protocol (BCP) z Supports the following SDH mapping formats: C-12/VC-12/TU-12/TUG-2/TUG-3/VC-4/AU-4/STM-1 C-3/VC-3/TU-3/TUG-3/VC-4/AU-4/STM-1 C-4/VC-4/AU-4/STM-1 z Supports selection of VC-4, VC-3 or VC-12 virtual concatenation on a per virtual concatenation group basis z Supports hitless Link Capacity Adjustment Scheme (LCAS) (ITU-T G.7042) z Supports up to 240ms (VC-12)/254ms (VC-3) of differential delay compensation z Supports TU-12/TU-3 pointer interpretation z Supports VC-12, VC-3 and VC-4 POH generation and termination z Full access VC-12, VC-3 and VC-4 POH through external serial interface z Provides byte-wide 19.44MHz Telecom Bus interface z Controlled High-Z output on Output Telecom Bus z Provides three bus timing modes for Output Telecom Bus z Supports per-port Ethernet side and SDH system side loopbacks for system level diagnostics z Provides 16-bit Intel/Motorola microprocessor interface z Provides an IEEE 1149.1 compliant JTAG test port for boundary scan z Operating Industrial temperature range: -40℃ ~ 85℃ z Low power 1.8V core with 3.3V LVTTL I/O, LVPECL I/O and 2.5V SSTL_2 digital I/O z The maximum power consumption is 2.3W z 27x27mm PBGA 352 package
APPLICATIONS
z SDH Add/Drop Multiplexers SDH Terminal Multiplexers z Multi-service Access Platform (MSAP) Cust omer Premises Equipment (CPE) platform z Test Equipment
8-port Ethernet Over SDH Mapping Device Copyright ©2006 Chiphomer Technology Limited Page 3 of 3 TYPICAL APPLICATION Add Bus Drop Bus 10/100 Mbit/s SMII/SS-SMII Interface ... ...
1000 Mbit/s
19.44MHz Telecom Bus CP1158 CP1158 Ethernet PHY or Switch Ethernet PHY or Switch
RELATED PRODUCTS
z CP1154: 4-port Ethernet over SDH Mapping device z CP1122A: STM-1 Single Chip Add/ Drop Multiplexer System device z CP1121A: STM-1/4 Single Chip Add/Drop Multiplexer System device z CP1181: 21 Channel Dual Bus E1/T1 Mapper z CP1130: SDH/SONET 155/622 Bu s Converter and Aggregator z CP1125: Dual 622/155 SDH/SONET Framer with LOPP and Cross Connect Chiphomer Technology Limited Add: 4F, Building D, 1618 Yishan Road, Shanghai, P.R.C. Tel: +86-(0)21-64058488, 64014543 Email: sales@chiphomer.com Web: www.chiphomer.com