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BQ24152 TI | Alldatasheet

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LO 1.0 H/c109 10 nF CBOOT PACK- PACK+ 1/c109F CAUXPWR SCL SDA CSOUT CSIN PGND SW I2C□BUS bq24152 10□k/c87 VAUX HOST SCL SDA STAT VREF STAT PMID VBUS CIN VBUS CIN

1 F/c109

4.7 F/c109

0.1/c109F 10□k/c87 10□k/c87 10□k/c87 bq24152 www.ti.com SLUS847 JUNE 2008 Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support Charge Faster than Linear Chargers Output Voltage for VBUS: 5.05 V High-Accuracy Voltage and Current Regulation 1.976 x 1.924mm 20-Pin WCSP Package Input Current Regulation Accuracy: (100 mA and 500 mA) Mobile and Smart Phones Charge Voltage Regulation Accuracy: MP3 Players 0.5% (25 C), C-125 Handheld Devices Charge Current Regulation Accuracy: High-Efficiency Mini-USB/AC Battery Charger for Single-Cell Li-Ion and Li-Polymer Battery The bq24152 is a compact, flexible, high-efficiency, Packs USB-friendly switch-mode charge management 20-V Absolute Maximum Input Voltage Rating device for single-cell Li-ion and Li-polymer batteries 6-V Maximum Operating Input Voltage used in a wide range of portable applications. The Built-In Input Current Sensing and Limiting charge parameters can be programmed through an I C interface. The bq24152 integrates a synchronous Integrated Power FETs for Up To 1.25-A PWM controller, power MOSFETs, input current Charge Rate sensing, high-accuracy current and voltage Programmable Charge Parameters through regulation, and charge termination, into a small I C Interface (up to 3.4 Mbps): WCSP package. Input Current The bq24152 charges the battery in three phases: Fast-Charge/Termination Current conditioning, constant current and constant voltage. The input current is automatically limited to the value Charge Voltage (3.5 V to 4.44 set by the host. Charge is terminated based on Safety Timer user-selectable minimum current level. A safety timer Termination Enable with reset control provides a safety backup for I C interface. During normal operation, bq24152 Synchronous Fixed-Frequency PWM automatically restarts the charge cycle if the battery Controller Operating at MHz with to voltage falls below an internal threshold and 99.5% Duty Cycle automatically enters sleep mode or high impedance Automatic High Impedance Mode for Low mode when the input supply is removed. The charge Power Consumption status is reported to the host using the I C interface. Safety Timer with Reset Control Typical Application Circuit Reverse Leakage Protection Prevents Battery Drainage Thermal Regulation and Protection Input/Output Overvoltage Protection Status Output for Charging and Faults USB Friendly Boot-Up Sequence Automatic Charging Power up System without Battery Boost Mode Operation for USB OTG: Input Voltage Range (from Battery): 2.5 V to 4.5 V Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. I2C is a trademark of Philips Electronics. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. During the charging process, the bq24152 monitors its junction temperature J and reduces the charge current once T J increases to approximately 125 To support USB OTG device, bq24152 provides VBUS (approximately 5.05V) by boosting the battery voltage. The bq24152 is available in 20-pin WCSP package. WCSP PACKAGE (Top View) TERMINAL FUNCTIONS TERMINAL I/O NO. Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 µ to CSOUT I PGND if there are long inductive leads to battery. VBUS A1, I Charger input voltage. Bypass it with a µ F ceramic capacitor from VBUS to PGND. Connection point between reverse blocking MOSFET and high-side switching MOSFET. Bypass it PMID B1, B2, O with a minimum of 3.3- µ F capacitor from PMID to PGND. SW C1, C2, O Internal switch to output inductor connection. Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 10-nF ceramic capacitor BOOT O (voltage rating above from BOOT pin to SW pin. PGND D1, D2, Power ground Charge current-sense input. Battery current is sensed via the voltage drop across an external sense CSIN I resistor. A 0.1- µ F ceramic capacitor to PGND is required. SCL I I C interface clock. Open drain output, connect a 10-k Ω pullup resistor SDA I/O I C interface data. Open drain output, connect a 10-k Ω pullup resistor Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a STAT O 128 µ S pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or communicate with a host processor. Internal bias regulator voltage. Connect a µ F ceramic capacitor from this output to PGND. External VREF O load on VREF is not allowed. Auxiliary power supply, connected to the battery pack to provide power in high-impedance mode. AUXPWR I Bypass it with a µ F ceramic capacitor from this pin to PGND. Boost mode enable control or input current limiting selection pin. When OTG is in active status, bq24152 is forced to operate in boost mode. It has higher priority over I C control and can be disabled OTG I through control register. The logic voltage level at OTG active status can also be controlled. At POR, the OTG pin is default to be used as the input current limiting selection pin. When OTG High, Iin limit 500 mA and when OTG Low, Iin limit 100 mA, see the Control Register for details. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

(1) ABSOLUTE MAXIMUM RATINGS (1) bq24152 www.ti.com SLUS847 JUNE 2008 ORDERING INFORMATION (1) Part NO. MARKING MEDIUM QUANTITY bq24152YFFR bq24152 Tape and Reel 3000 bq24152YFFT bq24152 Tape and Reel 250 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. T A C DERATING FACTOR PACKAGE R θ JA R θ JC POWER RATING T A C WSCP-20 (1) 185 C/W (2) 1.57 C/W 0.54 W 0.0054 C (1) Maximum power dissipation is a function of T J (max), R θ JA and T A The maximum allowable power dissipation at any allowable ambient temperature is P D J (max)-T A R θ JA (2) For PCB board with only top trace layer. For PCB board with four layers (top trace layer, buried ground layer, buried signal layer and bottom layer), R θ JA drops to 75.96 C/W over operating free-air temperature range (unless otherwise noted) VALUE UNIT Supply voltage range (with V SS VBUS 0.3 to V respect to PGND) Input voltage range (with V I SCL, SDA, OTG, CSIN, CSOUT, AUXPWR 0.3 to V respect to and PGND) PMID, STAT 0.3 to V Output voltage range (with V O VREF 6.5 V respect to and PGND) SW, BOOT 0.7 to V Voltage difference between CSIN and CSOUT inputs (CSIN) (CSOUT) V Output sink STAT mA I O Output current (average) SW 1.25 A T A Operating free-air temperature range to C T J Junction temperature to 150 C T stg Storage temperature to 150 C ESD Human body model at VBUS, PMID, STAT (2) (3) 800 V Rating (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. (2) The human body model is a 100-pF capacitor discharged through a 1.5-k Ω resistor into each pin. (3) Other pins pass kV for human body model. All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

www.ti.com MIN NOM MAX UNIT V BUS Supply voltage, VBUS (1) V T J Operating junction temperature range +125 C (1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight layout minimizes switching noise. Circuit of Figure VBUS HZ_MODE OPA_MODE (charger mode operation), T J C to 125 T J C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENTS VBUS VBUS(min), PWM switching mA VBUS VBUS(min), PWM NOT switching C T J VBUS HZ_MODE V (AUXPWR) V (LOWV) SCL, SDA, OTG V or µ A I (VBUS) VBUS supply current control 1.8 V C T J VBUS HZ_MODE V (AUXPWR) V (LOWV) S mode, SCL, SDA, OTG µ A V or 1.8 V Leakage current from battery to C T J V (AUXPWR) 4.2 High I lkg µ A VBUS pin impedance mode Battery discharge current in High C T J V (AUXPWR) 4.2 High Impedance mode, (CSIN, impedance mode µ A CSOUT, AUXPWR, SW pins) SCL, SDA, OTG V or 1.8 V VOLTAGE REGULATION V (OREG) Output charge voltage Operating in voltage regulation, programmable 3.5 4.44 V T A C 0.5% 0.5% Voltage regulation accuracy CURRENT REGULATION (FAST CHARGE) V (LOWV) V (AUXPWR) V (OREG) VBUS V (SLP) 550 I O(CHARGE) Output charge current 1250 mA R (SNS) m Ω Programmable Regulation accuracy for charge mV V (IREG) mV current across R (SNS) mV V (IREG) V (IREG) I O(CHARGE) R (SNS) WEAK BATTERY DETECTION V (LOWV) Weak battery voltage threshold Programmable 3.4 3.7 V Weak battery voltage accuracy Hysteresis for V (LOWV) Battery voltage falling 100 mV Deglitch time for weak battery Rising voltage, mV overdrive, t RISE 100 ns ms threshold OTG PIN LOGIC LEVEL V IL Input low threshold level 0.4 V V IH Input high threshold level 1.3 V CHARGE TERMINATION DETECTION Termination charge current V (AUXPWR) V (OREG) V (RCH) mA I (TERM) 400 VBUS V (SLP) R (SNS) m Ω Programmable Deglitch time for charge Both rising and falling, mV overdrive, t RISE t FALL ms termination 100 ns Voltage regulation accuracy for mV V (IREG_TERM) mV 25% 25% termination current across R (SNS) mV V (IREG_TERM) mV V (IREG_TERM) I O(TERM) R (SNS) INPUT POWER SOURCE DETECTION Input voltage lower limit Input power source detection 3.6 3.8 V Deglitch time for VBUS rising ms V IN (min) Rising voltage, mV overdrive, t RISE 100 ns above V IN (min) Hysteresis for V IN (min) Input voltage rising 100 200 mV t INT Detection Interval Input power source detection S Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

www.ti.com SLUS847 JUNE 2008 ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure VBUS HZ_MODE OPA_MODE (charger mode operation), T J C to 125 T J C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENT LIMITING I IN 100 mA mA I IN Input current limiting threshold USB charge mode I IN 500 mA 450 475 500 VREF BIAS REGULATOR VBUS V IN (min) or V (AUXPWR) V (BAT) min, V V ref Internal bias regulator voltage 6.5 I(VREF) mA, C(VREF) µ F V ref output short current limit mA Voltage from BOOT pin to SW V During charge or boost operation 6.5 pin BATTERY RECHARGE THRESHOLD V (RCH) Recharge threshold voltage Below V (OREG) 100 120 150 mV V (AUXPWR) decreasing below threshold, Deglitch time 130 ms t FALL 100ns, mV overdrive STAT OUTPUTS Low-level output saturation I O mA, sink current 0.4 V voltage, STAT V OL(STAT) High-level leakage current for Voltage on STAT pin is V µ A STAT I C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS V OL Output low threshold level I O mA, sink current 0.4 V V IL Input low threshold level 0.4 V V IH Input high threshold level 1.2 V I (BIAS) Input bias current V (pull-up) 1.8 SDA and SCL µ A f (SCL) SCL clock frequency 3.4 MHz BATTERY DETECTION Battery detection current before Begins after termination detected, 0.45 mA charge done (sink current) (1) V (AUXPWR) V (OREG) I (DETECT) Battery detection time 262 ms SLEEP COMPARATOR Sleep-mode entry threshold, V (SLP) 2.3 V V (AUXPWR) V (OREG) V BUS falling +0.0 +0.04 +0.1 V V BUS V AUXPWR Sleep-mode exit hysteresis 2.3 V V (AUXPWR) V (OREG) 100 160 mV V (SLP_EXIT) Deglitch time for VBUS rising Rising voltage, 2-mV overdrive, t RISE 100ns ms above V (SLP) V (SLP_EXIT) UNDERVOLTAGE LOCKOUT UVLO IC active threshold voltage VBUS rising 3.05 3.3 3.55 V UVLO (HYS) IC active hysteresis VBUS falling from above UVLO 120 150 mV PWM Internal top reverse blocking I IN(LIMIT) 500 mA, Measured from VBUS to 180 250 MOSFET on-resistance PMID Internal top N-channel Switching Measured from PMID to SW 120 250 m Ω MOSFET on-resistance Internal bottom N-channel Measured from SW to PGND 150 200 MOSFET on-resistance f (OSC) Oscillator frequency MHz Frequency accuracy 10% 10% D (MAX) Maximum duty cycle 99.5% D (MIN) Minimum duty cycle Synchronous mode to non-synchronous mode transition Low side MOSFET cycle by cycle current sensing 100 mA current threshold (2) (1) Negative charge current means the charge current flows from the battery to charger (discharging battery). (2) Bottom N-channel MOSFET always turns on for ns and then turns off if current is too low. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

www.ti.com ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure VBUS HZ_MODE OPA_MODE (charger mode operation), T J C to 125 T J C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BOOST MODE OPERATION FOR VBUS (OPA_MODE HZ_MODE Boost output voltage (to pin V (BUS_B) 2.5 V V (AUXPWR) 4.5 Open loop 5.05 V VBUS) Boost output voltage accuracy Including line and load regulation Maximum output current for I (BO) V (BUS_B) 5.05 2.5 V V (AUXPWR) 4.5 V 200 mA boost Cycle by cycle current limit for I (BLIMIT) V (BUS_B) 5.05 2.5 V V (AUXPWR) 4.5 V A boost Overvoltage protection threshold Threshold over VBUS to turn off converter during 5.8 6.2 V for boost (VBUS pin) boost VBUS (OVP) VBUS (OVP) hysteresis VBUS falling from above VBUS (OVP) 125 mV Maximum battery voltage for V (CSOUT) rising edge during boost 4.75 4.9 5.05 V boost (CSOUT pin) V (BAT) MAX V (BAT) MAX hysteresis V (CSOUT) falling from above VBATMAX 200 mV During boosting 2.5 V Minimum battery voltage for V (BAT) MIN boost (AUXPWR pin) Before boost starts 2.9 3.05 V Boost output resistance at high-impedance mode (From HZ_MODE 165 k Ω VBUS to PGND) PROTECTION Input VBUS OVP threshold Threshold over VBUS to turn off converter during 6.3 6.5 6.7 V voltage charge V (OVP-IN) V (OVP_IN) hysteresis VBUS falling from above V (OVP_IN) 140 mV V (CSOUT) threshold over V (OREG) to turn off charger Battery OVP threshold voltage 110 117 121 (ORE during charge V (OVP) V (OVP) hysteresis Lower limit for V (CSOUT) falling from above V (OVP) Cycle-by-cycle current limit for I (LIMIT) Charge mode operation 1.5 2.3 A charge Short-circuit voltage threshold V (AUXPWR) falling 1.9 2.1 V V (SHORT) V (SHORT) hysteresis V (AUXPWR) rising from below V (SHORT) 100 mV I (SHORT) Short-circuit current V (AUXPWR) V (SHORT) mA T (SHTDWN) Thermal trip 165 Thermal hysteresis C T (CF) Thermal regulation threshold (3) Charge current begins to reduce 120 Time constant for the second T (32S) Second mode s timer (3) Verified by design Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

I2C□BUS VAUX HOST SCL SDA STAT VREF STAT PMID VBUS CIN VBUS CIN BOOT OTG AUXPWR OTG CO RSNS CCSIN VBAT 10□k/c87 10□k/c8710□k/c8710□k/c87 10□k/c87 L 1.0 HO /c109 68□m/c87

10 F/c109

0.1 F/c109

I2C□BUS VAUX HOST SCL SDA STAT VREF STAT PMID VBUS CIN VBUS CIN 68□m/c87 VOUT 10□k/c87 10□k/c8710□k/c87 10□k/c87 10□k/c87 LO□□□1.0 H/c109 www.ti.com SLUS847 JUNE 2008 VBUS I (IN_LIMIT) 500 mA, I (CHARGE) 750 mA, VBAT 3.5 V to 4.44 V (adjustable), Safety Timer minutes or seconds. Figure I C Controlled 1-Cell Charger Application Circuit VBUS I (IN_LIMIT) 500 mA, V OUT 3.5 V to 4.44 V (adjustable), Safety Timer minutes or seconds. Figure I C Controlled 1-Cell Pre-Regulator Application Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

2□V/div I

0.5 A/div

500 S/div/c109

5□V/div VBAT 2□V/div VSW 5□V/div I 32S□Mode VSW 2□V/div IL 100□nS/div VBUS 2□V/div VSW 5□V/div I

0.1 A/div

2□mS/div V 5□V/div BUS V 1□V/div BAT OTG 5□V/div I 50□mA/div BAT 20□mS/div V =□0-5□V, No□Battery, C =□100 F, R =□5□k IN OUT LOAD /c109 /c87 VSW 2□V/div I L

2 S/div/c109

www.ti.com Using circuit shown in Figure T A unless otherwise specified. ADAPTER INSERTION BATTERY INSERTION/REMOVAL Figure Figure PWM CHARGING WAVEFORMS POOR SOURCE DETECTION Figure Figure BATTERY DETECTION AT POWER UP CYCLE BY CYCLE CURRENT LIMIT IN CHARGE MODE Figure Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

5□V/div I

0.2 A/div

0.5□S/div (OTG□Control,□32□Minute□Mode), Iin_limit□=□100□mA (I C□Control,□32□Second□Mode) 32□Minute Mode 32□Second Mode 0 100 200 300 400 500 600 700 800 900 10001100 12001300 Charge□Current□-□mA Efficiency□-□% Vbat□=□4□V Vbat□=□3□V Vbat□=□3.6□V V =□5□VBUS VBUS□100□mV/div,□5.06□V□Offset VBAT 100□mV/div,□3.5□V□Offset VSW 2□V/div IL

5 S/div/c109

VBUS□10□mV/div,□5.08□V□Offset VBAT 10□mV/div,□3.52□V□Offset VSW 2□V/div IL 100□nS/div VBUS 2□V/div VSW 5□V/div I 5□mS/div VPMID 200□mV/div, 5.02□V□Offset VBUS 100□mV/div, 5.06□V□Offset VSW 5□V/div I

100 S/div/c109

0.2□V/div, 3.8□V□Offset bq24152 www.ti.com SLUS847 JUNE 2008 TYPICAL CHARACTERISTICS (continued) INPUT CURRENT CONTROL CHARGER EFFICIENCY Figure Figure 10. BOOST WAVEFORM (PWM MODE) BOOST WAVEFORM (PFM MODE) Figure 11. Figure 12. VBUS OVERLOAD WAVEFORMS (BOOST MODE) LOAD STEP UP RESPONSE (BOOST MODE) Figure 13. Figure 14. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

100□mV/div, 5.06□V□Offset VSW 5□V/div I

0.2 A/div,

3.8□V□Offset BAT VSW 2□V/div IL overload□operation 200□nS/div VBUS 0.5□V/div, 4.5□V□Offset VSW 5□V/div OTG 2□V/div IL 0.5□mS/div Vbus□=□4.5□V,□(Charge□Mode)/5.1□V□(Boost□Mode), 0 50 100 150 200 Load□Current□at□VBUS□-□mA Efficiency□-□% VBAT =□2.5□V VBAT =□3.6□V VBAT =□4□V 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 5.09 5.1 0 50 100 150 200 Load□Current□at□VBUS□-□mA VBUS□-□V VBAT =□2.5□V VBAT =□3.6□V VBAT =□4□V 4.99 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 5.09 5.1 VBAT□-□V VBUS□-□V IBUS□=□50□mA IBUS□=□100□mA IBUS□=□200□mA bq24152 SLUS847 JUNE 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) LOAD STEP DOWN RESPONSE (BOOST MODE) CYCLE BY CYCLE CURRENT LIMITING IN BOOST MODE Figure 15. Figure 16. BOOST TO CHARGE MODE TRANSITION (OTG CONTROL) BOOST EFFICIENCY Figure 17. Figure 18. LINE REGULATION FOR BOOST LOAD REGULATION FOR BOOST Figure 19. Figure 20. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

CHARGE□CONTROL , TIMER□and□DISPLAY LOGIC * Sleep CSOUT CSIN STAT PGND SW PGND SCL NMOS NMOS NMOS PMID SDA (I2C□Control) Decoder DAC Q2 Q3 VREF PMID BOOTREFERNCES & BIAS PMID VBUS SW VPMID PGND VBUS VPMID OTG AUXPWR ISHORT VREF LINEAR _CHG TJ TCF IOCHARGE VOREG VREF Charge Pump VREF 1 IIN_LIMIT OSC -VOVP_IN VBUS VBUS -VUVLO VBUS VIN(MIN) VBUS TJ TSHTDWN CBC Current LimitingPWM Controller ILIMIT VBAT VBUS VBAT VOUT VCSIN * Battery□OVP+ VOUT VOVP VBUS□UVLO Poor□Input VBUS□OVP Thermal Shutdown * Recharge+ -VOUT VOREG-VRCH * Signal□Deglitched VOUT VCSIN ITERM PWM _CHG * PWM□Charge Mode VBAT VSHORT Termination bq24152 www.ti.com SLUS847 JUNE 2008 FUNCTIONAL BLOCK DIAGRAM (Charge Mode) Figure 21. Function Block Diagram of bq24152 in Charge Mode Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

CHARGE□CONTROL , TIMER□and□DISPLAY LOGIC * Low□Battery CSOUT CSIN STAT PGND SW PGND SCL NMOS NMOS NMOS PMID SDA (I2C□Control) Decoder DAC VREF PMID BOOTREFERNCES & BIAS PMID VBUS SW VPMID PGND VBUS VPMID OTG AUXPWR VBUS_FB VREF Charge Pump VREF1 VREF1 IBO OSC -VBUSOVP VBUS VBUS TJ TSHTDWN CBC Current LimitingPWM Controller IBLIMIT VBAT VBATMIN VBAT Battery□OVP+ VOUT VBATMAX VBUS□OVP Thermal Shutdown * Signal□Deglitched PWM_BOOST 75mA PFM□Mode VBUS_FB bq24152 SLUS847 JUNE 2008 www.ti.com FUNCTIONAL BLOCK DIAGRAM (Boost Mode) Figure 22. Function Block Diagram of bq24152 in Boost Mode Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

VAUXPWR<VSHORT? Yes No 32-Minute Timer□Expired ? No Enable□ISHORT Indicate□Charge -In- Progress Regulate Input□Current , Charge Current□or□Voltage High□Impedance□Modeor□Host Controlled□Operation□Mode Termination□Enable d ITERM detected and□VAUXPWR>VOREG-VRCH Yes VAUXPWR < VOREG - VRCH? VAUXPWR<VSHORT? No No Yes Yes Yes /CE=HIGH Turn□Off□Charge Indicate□Fault Indicate□Short Circuit□condition 32-Minute Timer Expired? No Yes Yes Indicate□DONE Charge□Complete VBUS<VIN(MIN)? Yes No Indicate□Power not□Good Disable□Charge Wait□Mode Delay TINT VBUS<VIN(MIN)? No Yes VAUXPWR < VOREG - VRCH? Enable□IDETECT for tDETECT Turn□Off□Charge No No Reset□Charge Parameters Battery□Removed Wait□Mode Delay TINT Yes VAUXPWR<VLOWV and bq24152? Power□Up VBUS>VUVLO No Yes Any Charge State/CE=HIGHCharge□Configure Mode Disable□Charge /CE=LOW 32-Minute Timer Active? No Yes High□Impedance Mode Charge□Complete Reset□and□Start 32-Minute Timer POR Load□I2C□Registers with□Default□Value bq24152 www.ti.com SLUS847 JUNE 2008 OPERATIONAL FLOW CHART Figure 23. Operational Flow Chart of bq24152 in Charge Mode Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

www.ti.com For a current limited power source, such as a USB host or hub, the high efficiency converter is critical in fully using the input power capacity and charging the battery. Due to the high efficiency in a wide range of the input voltage and battery voltage, the switching mode charger is a good choice for high speed charging with less power loss and better thermal management. The bq24152 is a highly integrated synchronous switch-mode charger with reverse boost function for USB OTG support, featuring integrated MOSFETs and small external components, targeted at extremely space-limited portable pack. The bq24152 usually has three operation modes: charge mode, boost mode, and high impedance mode. In charge mode, the bq24152 supports a precision Li-ion or Li-polymer charging system for single-cell applications. In boost mode, bq24152 boosts the battery voltage to VBUS for powering attached OTG devices. In high impedance mode, the bq24152 stops charging or boosting and operates in a mode with low current from VBUS or battery, to effectively reduce the power consumption when the portable device in standby mode. Through the proper control, bq24152 can achieve the smooth transition among different operation modes. Charge Profile In charge mode, bq24152 has four control loops to regulate input current, charge current, charge voltage and device junction temperature, as shown in Figure During the charging process, all four loops are enabled and the one that is dominant will take over the control. The bq24152 supports a precision Li-ion or Li-polymer charging system for single-cell applications. Figure (a) indicates a typical charge profile without input current regulation loop and it is similar to the traditional CC/CV charge curve, while Figure (b) shows a typical charge profile when input current limiting loop is dominant during the constant current mode, and in this case the charge current is higher than the input current so the charge process is faster than the linear chargers. For bq24152, the input current limits, the charge current, termination current, and charge voltage are all programmable using I C interface. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

(Linear□Charge ) Fast□Charge (PWM□Charge) I SHORT Termination VSHORT Regulation Current Regulation Voltage Precharge Phase Current□Regulation Phase Voltage□Regulation Phase Charge□Current Charge□Voltage Precharge (Linear□Charge ) Fast□Charge (PWM□Charge) ISHORT Termination VSHORT Regulation voltage Precharge Phase Current□Regulation Phase Voltage□Regulation Phase Charge□Current Charge□Voltage (a) (b) bq24152 www.ti.com SLUS847 JUNE 2008 Figure 24. Typical Charging Profile of bq24152 for (a) without Input Current Limit, and (b) with Input Current Limit Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

www.ti.com The bq24152 provides an integrated, fixed 3-MHz frequency voltage-mode controller with Feed-Forward function to regulate charge current or voltage. This type of controller is used to help improve line transient response, thereby, simplifying the compensation network used for both continuous and discontinuous current conduction operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with low ESR. There is a 0.5-V offset on the bottom of the PWM ramp to allow the device to operate between to 99.5% duty cycles. The bq24152 has two back to back common-drain N-channel MOSFETs at the high side and one N-channel MOSFET at low side. An input N-MOSFET (Q1) prevents battery discharge when VBUS is lower than VAUXPWR. The second high-side N-MOSFET (Q2) behaves as the switching control switch (see Figure A charge pump circuit is used to provide gate drive for Q1, while a boot strap circuit with external boot-strap capacitor is used to boost up the gate drive voltage for Q2. Cycle-by-cycle current limit is sensed through the internal sense MOSFETs for and Q3. The threshold for is set to a nominal 1.9-A peak current. The low-side MOSFET (Q3) also has a current limit that decides if the PWM Controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side N-channel MOSFET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used when the current of the low-side MOSFET is greater than 100mA to minimize power losses. At the beginning of precharge, while battery voltage is below the V (SHORT) threshold, the bq24152 applies a short-circuit current, I (SHORT) to the battery. When the battery voltage is above V (SHORT) and below V (OREG) the charge current ramps up to fast charge current, I O(CHARGE) or a charge current that corresponds to the input current of I (IN_LIMIT) The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient. Both the input current limit (default at 100 mA), IIN_LIMIT, and fast charge current, I O(CHARGE) can be set by the host. Once the battery voltage is close to the regulation voltage, V (OREG) the charge current is tapered down as shown in Figure The voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins. bq24152 is a fixed single-cell voltage version, with adjustable regulation voltage (3.5 V to 4.44 programmed through I C interface. The bq24152 monitors the charging current during the voltage regulation phase. Once the termination threshold, ITERM, is detected and the battery voltage is above the recharge threshold, the bq24152 terminates charge. The termination current level is programmable. To disable the charge current termination, the host can set the charge termination bit (I_Term) of charge control register to see the I C section for details. A new charge cycle is initiated when one of the following conditions is detected: The battery voltage falls below the V (OREG) V (RCH) threshold. VBUS Power-on reset (POR), if battery voltage is below the V (LOWV) threshold. CE bit toggle or RESET bit is set (host controlled) At the beginning of charging process, the bq24152 starts a 32-minute timer (T32min) that can be stopped by any write-action performed by host through I C interface. Once the 32-minute timer is stopped, a 32-second timer (T32sec) is automatically started. The 32-second timer can be reset by host using I C interface. Writing "1" to reset bit of TMR_RST in control register resets the 32-second timer and TMR_RST is automatically set to "0" after the 32-second timer is reset. If the 32-second timer expires, the charge is terminated and charge parameters are reset to default values. Then the 32-minute timer starts and the charge resumes. During normal charging process, the bq24152 is normally in 32-second mode with host control, and 32-minute mode without host control using I C interface. The process repeats until the battery is fully charged. If the 32-minute timer expires, bq24152 turns off the charger and enunciates FAULT on the STATx bits of status register. This function prevents battery over charge if the host fails to reset the safety timer. The safety timer flow chart is shown in Figure Fault condition is cleared by POR and fault status bits can only be updated after the status bits are read out by the host. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

T32min Active? Yes No Charge Host□Should□Reset T32sec Timer T32min Expired? Start T32min Timer Charge□Start No Timer□Fault Yes T32sec□Expired? Yes No Reset□Charge Parameters Any□I2C□Write- Action? Yes Start T32sec Stop T32min No USB Friendly Boot-Up Sequence Input Current Limiting Thermal Regulation and Protection bq24152 www.ti.com SLUS847 JUNE 2008 Figure 25. Timer Flow Chart for bq24152 in Charge Mode At power on reset (POR) of VBUS, if the battery voltage is above the weak battery threshold, V LOWV bq24152 will operate in a mode dictated by the I C control registers. On the other hand, if the battery voltage is below V LOWV and the host control through I C interface is lost (32 minute mode), bq24152 will reset all I C registers with default values and enable the charger with an input current limit dictated by the OTG pin voltage level until the host programs the I C registers. During this period, the input current limit is 100 mA when the voltage level of OTG pin is Low; while the input current limit is 500 mA when the voltage level of OTG pin is high. This feature could quickly revive the deeply discharged cell. The charge process continues even the battery is charged to the regulation voltage (default at 3.54 since termination is disabled by default. In another case, if the battery voltage is below V LOWV but the host control using I C interface is available (32 second mode), bq24152 will operate in a mode dictated by control registers. To maximize the charge rate of bq24152 without overloading the USB port, the input current for bq24152 can be limited to 100mA or 500mA which is programmed in the control register or OTG pin. Once the input current reaches the input current limiting threshold, the charge current is reduced to keep the input current from exceeding the programmed threshold. For bq14150, the default input current limit is controlled by the OTG pin at VBUS power on reset when V (AUXPWR) is lower than V (LOWV) The input current sensing resistor and control loop are integrated into bq24152. The input current limit can also be disabled using I C control, see the definition of control register (01H) for details. To prevent overheating the chip during the charging process, the bq24152 monitors the junction temperature, T J of the die and begins to taper down the charge current once T J reaches the thermal regulation threshold, T CF The charge current is reduced to zero when the junction temperature increases approximately C above T CF At any state, if T J exceeds T SHTDWN bq24152 suspends charging. At thermal shutdown mode, PWM is turned off and all timers are frozen. Charging resumes when T J falls below T SHTDWN by approximately Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

www.ti.com Sleep Mode The bq24152 enters the low-power sleep mode if the voltage on VBUS pin falls below sleep-mode entry threshold, V AUXPWR V SLP and VBUS is still higher than the poor source detection threshold, V IN (min). This feature prevents draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking switch and PWM are turned off. Input Source Detection During the charging process, bq24152 continuously monitors the input voltage, VBUS. If VBUS falls to the low input voltage threshold, V IN (min), poor input power source is detected. Under this condition, bq24152 terminates the charge process, waits for a delay time of T INT and repeats the charging process, as indicated in Figure This unique function provides intelligence to bq24152 and so prevents USB power bus collapsing and oscillation when connecting to a suspended USB port, or a USB-OTG device with low current capability. Input Overvoltage Protection The bq24152 provides a built-in input over-voltage protection to protect the device and other components against damages if the input voltage (Voltage from VBUS to PGND) goes too high. When an input overvoltage condition is detected, bq24152 turns off the PWM converter, sets fault status bits, and sends out fault pulse in STAT pin. Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and charge process resumes. Output Overvoltage Protection The bq24152 provides a built-in overvoltage protection to protect the device and other components against damage if the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage condition is detected, bq24152 turns off the PWM converter, sets fault status bits and sends out fault pulse in STAT pin. Once V (CSOUT) drops to the battery overvoltage exit threshold, the fault is cleared and charge process back to normal. Battery Detection During Normal Charging For packs, the bq24152 provides a battery absent detection scheme to reliably detect insertion or removal of battery packs. During normal charging process with host control, once the voltage at the AUXPWR pin is above the battery recharge threshold, V (OREG) V (RCH) and the termination charge current is detected, bq24152 turns off the charge and enables a discharge current, I (DETECT) for a period of t DETECT then checks the battery voltage. If the battery voltage is still above recharge threshold, the battery is present and the charge done is detected. However, if the battery voltage is below battery recharge threshold, the battery is absent. Under this condition, the charge parameters (such as input current limit) are reset to the default values and charge resumes after a delay of T INT as shown in Figure This function ensures that the charge parameters are reset whenever the battery is replaced. Power Up Without Battery When no battery is present, at VBUS power up, bq24152 will charge the output capacitor in short circuit mode (when V AUXPWR V SHORT or PWM mode (when V AUXPWR SHORT Once the output voltage at CSOUT pin is charged to the default regulation voltage (3.54V), the voltage is kept constant until the 32-minute timer expires or the host takes over the control through I C interface. This unique feature makes bq24152 capable of starting the system without battery. Battery Short Protection During the normal charging process, if the battery voltage is lower than the short-circuit threshold, V (SHORT) the charger operates in short circuit mode with a lower charge rate of I (SHORT) as shown in Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

Output, STAT Pin Control Bits in Charge Mode Boost Mode Operation bq24152 www.ti.com SLUS847 JUNE 2008 The STAT pin is used to indicate operation conditions for bq24152. STAT is pulled low during charging and EN_STAT bit in control register (00H) is set to "1". Under other conditions, the STAT pin acts as a high impedance (open-drain) output. Under fault conditions, a 128- µ s pulse is sent out to notify the host. The status of STAT pin at different operation conditions is summarized in Table The STAT pin can be used to drive an LED or communicate to the host processor. Table STAT Pin Summary Charge State STAT Charge in progress and EN_STAT Low Other normal conditions Open-drain Charge mode faults: Timer fault, sleep mode, VBUS 128- µ s pulse, then open-drain or battery overvoltage, poor input source, VBUS UVLO, no battery, thermal shutdown Boost mode faults: Timer fault, over load, VBUS or 128- µ s pulse, then open-drain battery overvoltage, low battery voltage, thermal shutdown CE Bit (Charge Mode) The bit of CE in control register is used to disable or enable the charge process. A low logic level (0) on this bit enables the charge and a high logic level (1) disables the charge. RESET Bit The bit of RESET in control register is used to reset all the charge parameters. Writing '1" to RESET bit resets all the charge parameters to default values and RESET bit is automatically cleared to zero once the charge parameters are reset. It is designed for charge parameter reset before charge starts, and it is not recommended to set the RESET bit when charging or boosting in progress. OPA_Mode Bit OPA_MODE is the operation mode control bit. When OPA_MODE the bq24152 charges the related operation modes if HZ_MODE is set to "0", refer to Table for detail. Table Operation Mode Summary OPA_MODE HZ_MODE OPERATION MODE Charge (no fault) Charge configure (fault, V bus V UVLO High impedance bus V UVLO Boost (no faults) Any fault go to charge configure mode X High impedance In second mode, when the OTG pin is in active status or the bit of operation mode (OPA_MODE) at control register is set to the bq24152 operates in boost mode and delivers the power to VBUS from the battery. At normal boost mode, bq24152 converts the battery voltage (2.5 V to 4.5 to VBUS-B (about 5.05V) and delivers a current as much as I (BO) (approximately 200 mA) to support other USB OTG devices connected to the USB connector. PWM Controller in Boost Mode Similar to charge mode operation, in boost mode, the bq24152 provides an integrated, fixed MHz frequency voltage-mode controller to regulate output voltage at PMID pin (VPMID), as shown in Figure The voltage control loop is internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation with a wide load range and battery voltage range Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

www.ti.com In boost mode, the input N-MOSFET (Q1) prevents battery discharge when VBUS pin is overloaded. Cycle-by-cycle current limit is sensed through the internal sense MOSFET for Q3. The threshold for is set to a nominal 1-A peak current. The upper-side MOSFET (Q2) also has a current limit that decides if the PWM Controller will operate in synchronous or non-synchronous mode. This threshold is set to mA and it turns off the high-side N-channel MOSFET (Q2) before the current reverses, preventing the battery from charging. Synchronous operation is used when the current of the high-side MOSFET is greater than mA to minimize power losses. Boost Start Up To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start up. PFM Mode at Light Load In boost mode, the bq24152 operates in pulse skipping mode (PFM mode) to reduce the power loss and improve the converter efficiency at light load condition. During boosting, the PWM converter is turned off once the inductor current is less than mA; and the PWM is turned back on only when the voltage at PMID pin drops to about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between PWM and PFM mode. Safety Timer in Boost Mode At the beginning of boost operation, the bq24152 starts a 32-second timer that can be reset by host through I C interface. Writing "1" to reset bit of TMR_RST in the control register resets the 32-second timer and TMR_RST is automatically set to "0" after the 32-second timer is reset. To keep in boost mode, the host must reset the 32-second timer repeatedly. Once the 32-second timer expires, the bq24152 turns off the boost converter, enunciate the fault pulse in STAT pin and set fault status bits in status register. Fault condition is cleared by POR or host control. Protection in Boost Mode Output Overvoltage Protection The bq24152 provides a built-in overvoltage protection to protect the device and other components against damage if the VBUS voltage goes too high. When an overvoltage condition is detected, the bq24152 turns off the PWM converter, reset OPA_MODE bit to sets fault status bits, and sends out fault pulse in STAT pin. Once VBUS drops to the normal level, the boost starts after host sets OPA_MODE to "1", or the OTG pin remains in active status. Output Overload Protection The bq24152 provides a built-in overload protection to prevent the device and battery from damage when VBUS is over loaded. Once over load condition is detected, operates in linear mode to limit the output current while VPMID keeps in voltage regulation. If the overload condition lasts for more than 30ms, the overload fault is detected. When an overload condition is detected, the bq24152 turns off the PWM converter, reset OPA_MODE bit to sets fault status bits, and sends out fault pulse in STAT pin. The boost will not start until the host clears the fault register. Battery Voltage Protection During boosting, when battery voltage is above the battery overvoltage threshold, V (BATMX) or below the minimum battery voltage threshold, V (BAT) min, the bq24152 turns off the PWM converter, reset OPA_MODE bit to sets fault status bits, and sends out fault pulse in STAT pin. Once battery voltage goes back to the normal level, the boost starts after host sets OPA_MODE to "1", or the OTG pin remains in active status. During normal boosting process, the STAT pin behaves as a high impedance (open-drain) output. Under fault conditions, a 128- µ s pulse is sent out to notify the host. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

1=o 2 L C f /c112 /c180 /c180 (1) Pre-Regulator Application State Machine Table and State Diagram bq24152 www.ti.com SLUS847 JUNE 2008 When control bit of HZ-MODE is set to "1" and the OTG pin is not in active status, the bq24152 operates in high impedance mode, with the impedance in VBUS pin higher than 165 k Ω In high impedance mode, a crude 32-second timer is enabled when the battery voltage is below V (LOWV) to monitor the host control is available or not. If the crude second timer expires, the bq24152 operates in minute mode and the crude second timer is disabled. In minute mode, when VBUS is below UVLO, the bq24152 operates in high impedance mode regardless of the setting of the HZ_MODE bit. The bq24152 provides internal loop compensation. With this scheme, the best stability occurs when the LC resonant frequency, ƒ o is approximately kHz (20 kHz to kHz). Equation is used to calculate the value of the output inductor, L OUT and output capacitor, C OUT To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 µ F and µ F is recommended for C OUT see the application section for components selection. Figure shows a typical pre-regulator application that the bq24152 operates as a DC/DC converter, with the termination disabled. The robust internal compensation design ensures the stable operation when the host-controlled switch is turned off. With the input overvoltage protection, output current regulation and high efficiency power conversion, the bq24152 is an ideal choice for pre-regulator used in pulse charging applications. Based on the previously-described operation modes, the definitions of all operation states are shown in Table and Table whereas the relationship among different states is shown in Figure Table State Machine Table of bq24152 MODE POWER DOWN CHARGE CONFIGURE SHORT CIRCUIT PWM CHARGE OPA_MODE OPA_MODE OPA_MODE HZ_MODE HZ_MODE HZ_MODE OTG Inactive OTGIinactive OTG Inactive VBUS UVLO VBUS VBUS(MIN) VBUS VBUS(MIN) VBUS UVLO IN Condition VBUS VBUS(MIN) VBUS V (SLP_ENT) VBUS V (SLP_ENT) V (AUXPWR) V (SHORT) or (SLP_EXIT) (SLP_EXIT) VBUS V (SLP_ENT) V (AUXPWR) V (SHORT) V (AUXPWR) V (SHORT) or CE Low CE Low CE HIGH No Faults No Faults OPA_MODE OPA_MODE OPA_MODE or HZ_MODE or HZ_MODE or HZ_MODE VBUS VBUS(MIN) VBUS VBUS(MIN) or VBUS V (SLP_ENT) VBUS V (SLP_ENT) VBUS UVLO VBUS VBUS(MIN) OUT Condition or or V (AUXPWR) V (SHORT) VBUS V (SLP_ENT) V (AUXPWR) V (SHORT) V (AUXPWR) V (SHORT) V (SLP_EXIT) CE HIGH CE HIGH or VBUS UVLO or Faults or Faults OTG Active or OTG Active or OTG Active I C Off On On On Buck Off Off Off On I (SHORT) Off Off On Off Boost Off Off Off Off Off On/Off On On Note POR when out Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

POWER□DOWN CHARGE CONFIGURE BOOST CONFIGURE BOOST HIGH IMPEDANCE SHORT CIRCUIT PWM□CHARGE VBUS>VUVLO VAUXPWR<VLOWV VAUXPWR>VSHORT, VBUS>VBUS(MIN) VBUS>VSLP_ENT+VSLP_EXIT NO□FAULTS HZ_MODE=1 OPA_MODE=1 HZ_MODE=0 VAUXPWR<VSHORT or□VBUS<VBUS(MIN) or□FAULTS VAUXPWR>VSHORT or□VBUS<VBUS(MIN) or□FAULTS VAUXPWR>VPOR VBUS>POR START UP No□FAULTS HZ_MODE=1 Or VAUXPWR<VLOWV OPA_MODE=0 or□FAULTS OPA_MODE=1 HZ_MODE=0 VAUXPWR>VLOWV HZ_MODE=1 or VAUXPWR<VBATMIN OPA_MODE=1 HZ_MODE=0 HZ_MODE=1 or□VBUS<VUVLO, VAUXPWR>VSHORT VBUS>VUVLO HZ_MODE=0, OPA_MODE=0 VAUXPWR<VSHORT VBUS>VBUS(MIN) VBUS>VSLP_ENT+VSLP_EXIT NO□FAULTS OPA_MODE=0 ANY STATE VBUS<VUVLO VAUXPWR<VSHORT bq24152 SLUS847 JUNE 2008 www.ti.com Table State Machine Table of bq24152 MODE HIGH IMPEDANCE BOOST CONFIGURE BOOST OPA_MODE OPA_MODE OPA_MODE or OTG inactive or HZ_MODE HZ_MODE VBUS UVLO, V (AUXPWR) V (SHORT) or OTG active or OTG active IN Condition or Boost Configure, V (AUXPWR) V (LOWV) V (AUXPWR) V (BAT) MIN V (AUXPWR) V (LOWV) Ready To Start Up Start Up Finished or Boost, V (AUXPWR) (BAT) MIN or Faults During Boost or No Faults HZ_MODE OPA_MODE OPA_MODE OPA_MODE VBUS UVLO OTG Inactive OTG Inactive or HZ_MODE OPA_MODE OUT Condition or HZ_MODE or HZ_MODE V (AUXPWR) V (LOWV) or V (AUXPWR) V (LOWV) or V (AUXPWR) V (BAT) MIN or V (AUXPWR) (SHORT) Boost Start Up Finished or Faults or OTG Active On On On Off Off Off Off Off Off Off Off On Off On/Off (1) On (1) is OFF when VBUS is shorted to ground. Figure 26. State Diagram for bq24152 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

START□Condition DATA CLK STOP Condition S P DATA CLK Data□Line Stable; Data□Valid Change of□Data Allowed bq24152 www.ti.com SLUS847 JUNE 2008 I C is a 2-wire serial interface developed by Philips Semiconductor (see I C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I C compatible devices connect to the I C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The bq24152 device works as a slave and supports the following data transfer modes, as defined in the I C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register

2.2 V (typical). The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as the HS-mode. The bq24152 device only supports 7-bit addressing. The device 7-bit address is defined as 1101011 (6BH). The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure All I C-compatible devices should recognize a start condition. Figure 27. START and STOP Condition The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. Figure 28. Bit Transfer on the Serial Interface The master generates further SCL cycles to either transmit data to the slave (R/W bit or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

Data□Output by□Transmitter Data□Output by□Receiver SCL From Master Not Acknowledge Acknowledge Clock□Pulse□for Acknowledgement 1 2 8 9 START Condition SDA SCL Recognize□START□or REPRATED□START Condition Recognize□STOP or REPRATED□START Condition Generate ACKNOWLEDGE Signal Acknowledgement Signal□From□Slave MSB Address R/W ACK Clock□Line□Held□Low□While Interrupts□are□Serviced S or Sr Sr or P P Sr ACK H/S Mode Protocol bq24152 SLUS847 JUNE 2008 www.ti.com acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure This releases the bus and stops the communication link with the addressed slave. All I C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the slave I C logic from remaining in a bad state. Attempting to read data from register addresses not listed in this section will result in FFh being read out. Figure 29. Acknowledge on the I C Bus Figure 30. Bus Protocol When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing HS master code '00001XXX'. This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

I C Update Sequence S SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A P Data Transferred ‘0’ (Write) (n Bytes□+ Acknowledge) From□master□to bq24152 A = Acknowledge□(SDA LOW) A = Not□acknowledge□(SDA HIGH) From bq24152□to□master S =□START□condition Sr =□Repeated□START□condition P =□STOP condition (a) F/S-Mode F/S-Mode HS-Mode S HS-MASTER□CODE A Sr SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A P Data Transferred ‘0’ (write) (n Bytes□+ Acknowledge) Sr Slave A. (b)□HS- Mode F/S-Mode HS-Mode Continues Slave Address Byte bq24152 www.ti.com SLUS847 JUNE 2008 The master then generates a repeated start condition repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the internal settings of the slave devices to support the F/S mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS mode. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the slave I C logic from remaining in a bad state. Attempting to read data from register addresses not listed in this section results in FFh being read out. The bq24152 requires a start condition, a valid I C address, a register address byte, and a data byte for a single update. After the receipt of each byte, bq24152 device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I C address selects the bq24152. The bq24152 performs an update on the falling edge of the acknowledge signal that follows the LSB byte. For the first update, bq24152 requires a start condition, a valid I C address, a register address byte, a data byte. For all consecutive updates, bq24152 needs a register address byte, and a data byte. Once a stop condition is received, the bq24152 releases the I C bus, and awaits a new start conditions. Figure 31. Data Transfer Format in F/S Mode and H/S Mode MSB LSB X Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

I C INTERFACE TIMING CHARACTERISTICS bq24152 SLUS847 JUNE 2008 www.ti.com The slave address byte is the first byte received following the START condition from the master device. The address bits are factory preset to 1101011 MSB LSB Following the successful acknowledgment of the slave address, the bus master will send a byte to the bq24152, which contains the address of the register to be accessed. The bq24152 contains five 8-bit registers accessible via a bidirectional I C-bus interface. Among them, four internal registers have read and write access; and one has only read access. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Standard mode 100 kHz Fast mode 400 kHz High-speed mode (write operation) 3.4 CB 100 pF max High-speed mode (read operation) f SCL SCL clock frequency CB 100 pF max MHz High-speed mode (write operation) 1.7 CB 400 pF max High-speed mode (read operation) CB 400 pF max Standard mode 4.7 Bus free time between a STOP and t BUF µ s START condition Fast mode 1.3 Standard mode µ s Hold time (repeated) START t HD t STA Fast mode 600 condition ns High-speed mode 160 Standard mode 4.7 µ s Fast mode 1.3 t LOW LOW period of the SCL clock High-speed mode, C B 100 pF max 160 ns High-speed mode, C B 400 pF max 320 Standard mode µ s Fast mode 600 t HIGH HIGH period of the SCL clock High-speed mode, C B 100 pF max ns High-speed mode, C B 400 pF max 120 Standard mode 4.7 µ s Setup time for a repeated START t SU t STA Fast mode 600 condition ns High-speed mode 160 Standard mode 250 t SU t DAT Data setup time Fast mode 100 ns High-speed mode Standard mode 3.45 µ s Fast mode 0.9 t HD t DAT Data hold time High-speed mode, C B 100 pF max ns High-speed mode, C B 400 pF max 150 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

I C Timing Diagrams SDA SCL tf tLOW tHD;ST A tr tHD;DA T tHIGH tSU;ST A tSU;DA T tf S Sr tHD;ST A tSU;STO tSP tr tBUF P S bq24152 www.ti.com SLUS847 JUNE 2008 SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Standard mode 20+0.1C B 1000 Fast mode 20+0.1C B 300 t RCL Rise time of SCL signal ns High-speed mode, C B 100 pF max High-speed mode, C B 400 pF max Standard mode 20+0.1C B 1000 Rise time of SCL signal after a Fast mode 20+0.1C B 300 t RCL1 repeated START condition and after ns High-speed mode, C B 100 pF max an acknowledge bit High-speed mode, C B 400 pF max 160 Standard mode 20+0.1C B 300 Fast mode 20+0.1C B 300 t FCL Fall time of SCL signal ns High-speed mode, C B 100 pF max High-speed mode, C B 400 pF max Standard mode 20+0.1C B 1000 Fast mode 20+0.1C B 300 t RDA Rise time of SDA signal ns High-speed mode, C B 100 pF max High-speed mode, C B 400 pF max 160 Standard mode 20+0.1C B 300 Fast mode 20+0.1C B 300 t FDA Fall time of SDA signal ns High-speed mode, C B 100 pF max High-speed mode, C B 400 pF max 160 Standard mode µ s t SU t STO Setup time for STOP condition Fast mode 600 ns High-speed mode 160 C B Capacitive load for SDA and SCL 400 pF Figure 32. Serial Interface Timing for FS Mode Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO trCL1 tHIGH tLOW tLOW tHIGH tfCL1 trCL1 trCL1(1) (1) =□MCS□current□source□pull-up =□R resister□pull-upP REGISTER www.ti.com Figure 33. Serial Interface Timing for HS Mode Table Status/Control Register (Read/Write) Memory Location: 00, Reset State: x1xx 0xxx BIT NAME READ/WRITE FUNCTION Write: TMR_RST function, write "1" to reset the safety timer (auto clear) (MSB) TMR_RST/OTG Read/Write Read: OTG pin status, 0-OTG pin at Low level, 1-OTG pin at High level EN_STAT Read/Write 0-Disable STAT pin function, 1-Enable STAT pin function (default STAT2 Read Only 00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault STAT1 Read Only BOOST Read Only 1-Boost mode, 0-Not in boost mode FAULT_3 Read Only Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Poor input source or VBUS UVLO, 100-Battery OVP, 101-Thermal shutdown, 110-Timer FAULT_2 Read Only fault, 111-No battery Boost mode: 000-Normal, 001-VBUS OVP, 010-Over load, 011-Battery voltage (LSB) FAULT_1 Read Only is too low, 100-Battery OVP, 101-Thermal shutdown, 110-Timer fault, 111-NA Table Control Register (Read/Write) Memory Location: 01, Reset State: 0011 0000 (30H) BIT NAME READ/WRITE FUNCTION (MSB) Iin_Limit_2 Read/Write 00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit, 10-USB host/charger with 800-mA current limit, 11-No input current limit Iin_Limit_1 Read/Write (default 00) VLOWV_2 (1) Read/Write 200-mV weak battery voltage threshold (default VLOWV_1 (1) Read/Write 100-mV weak battery voltage threshold (default 1-Enable charge current termination, 0-Disable charge current termination TE Read/Write (default CE Read/Write 1-Charger is disabled, 0-Charger enabled (default HZ_MODE Read/Write 1-High impedance mode, 0-Not high impedance mode (default (1) The range of the weak battery voltage threshold (LOWV) is 3.4 V to 3.7 V and step of 100 mV (default of 3.7 V). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

I(TERM0) O(TERM_STEP) (SNS) V I = R (2) bq24152 www.ti.com SLUS847 JUNE 2008 Table Control Register (Read/Write) Memory Location: 01, Reset State: 0011 0000 (30H) (continued) BIT NAME READ/WRITE FUNCTION (LSB) OPA_MODE Read/Write 1-Boost mode, 0-Charger mode (default Table Control/Battery Voltage Register (Read/Write) Memory Location: 02, Reset State: 0000 1010 (0AH) BIT NAME READ/WRITE FUNCTION (MSB) V O(REG5) Read/Write Battery regulation voltage: 640mV (default V O(REG4) Read/Write Battery regulation voltage: 320mV (default V O(REG3) Read/Write Battery regulation voltage: 160mV (default V O(REG2) Read/Write Battery regulation voltage: 80mV (default V O(REG1) Read/Write Battery regulation voltage: 40mV (default V O(REG0) Read/Write Battery regulation voltage: 20mV (default OTG_PL Read/Write 1-Active at High level, 0-Active at Low level (default (LSB) OTG_EN Read/Write 1-Enable OTG Pin, 0-Disable OTG pin (default Charge voltage range is 3.5 V to 4.44 V with the offset of 3.5 V and step of mV (default is 3.54 V). Table Vender/Part/Revision Register (Read only) Memory Location: 03, Reset State: 0100 x001 BIT NAME READ/WRITE FUNCTION (MSB) Vender2 Read Only Vender Code: bit (default Vender1 Read Only Vender Code: bit (default Vender0 Read Only Vender Code: bit (default PN1 Read Only Part Number Code: bit (default PN0 Read Only Part Number Code: bit (default for bq24151, default for bq24152) Revision2 Read Only 000: Revision 1.0; 001: Revision 1.1; Revision1 Read Only 010: Revision 1.2; (LSB) Revision0 Read Only 011-111: Future Revisions Table Battery Termination/Fast Charge Current Register (Read/Write) Memory Location: 04, Reset State: 1000 1001 (89H) BIT NAME READ/WRITE FUNCTION Write: 1-Charger in reset mode, 0-No effect (MSB) Reset Read/Write Read: always get "1" V I(CHRG2) Read/Write Charge current sense voltage: 27.2mV (default V I(CHRG1) Read/Write Charge current sense voltage: 13.6mV(default V I(CHRG0) Read/Write Charge current sense voltage: 6.8mV (default NA Read/Write NA V I(TERM2) Read/Write Termination current sense voltage: 13.6mV (default V I(TERM1) Read/Write Termination current sense voltage: 6.8mV (default (LSB) V I(TERM0) Read/Write Termination current sense voltage: 3.4mV (default Default charge current is 0mA and default termination current is 100 mA, if a 68-m Ω sensing resistor is used. Both the termination current range and charge current range are depending on the sensing resistor R (SNS) The termination current step O(TERM_STEP) is calculated using Equation Table shows the termination current settings with two sensing resistors. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

I(CHRG0) O(CHARGE_STEP) (SNS) V I = R (3) DESIGN EXAMPLE FOR TYPICAL APPLICATION CIRCUITS /c180 /c180 /c180 /c68O UT L VBAT (VBUS - VBAT )L = VBUS I f the worst case is when battery voltage is as close as to half of the input OUT 6 2.5 (5 - 2.5)L = 5 (3 10 ) 1.25 0.3 /c180 /c180 /c180 /c180 /c180 /c180/c68 /c180 /c180L OUT VBAT (VBUS - VBAT)I = VBUS L f L -6 /c180/c68 /c180 /c180 /c180 /c180 bq24152 SLUS847 JUNE 2008 www.ti.com Table 10. Termination Current Settings for 68-m Ω and 100-m Ω Sense Resistors I (TERM) (mA) I (TERM) (mA) BIT V I(TERM) (mV) R (SNS) 68m Ω R (SNS) 100m Ω V I(TERM2) 13.6 200 136 V I(TERM1) 6.8 100 V I(TERM0) 3.4 Offset 3.4 The charge current step O(CHARGE_STEP) is calculated using Equation Table shows the charge current settings with two sensing resistors. Table 11. Charge Current Settings for 68-m Ω and 100-m Ω Sense Resistors I O(CHARGE) (mA) I O(CHARGE) (mA) BIT V I(REG) (mV) R (SNS) 68m Ω R (SNS) 100m Ω V I(CHRG2) 27.2 400 272 V I(CHRG1) 13.6 200 136 V I(CHRG0) 6.8 100 Offset 37.4 550 374 Systems Design Specifications: VBUS V V (BAT) 4.2 V (1-Cell) I (charge) 1.25 A Inductor ripple current 30% of fast charge current Determine the inductor value OUT for the specified charge current ripple: voltage. L OUT 1.11 µ H Select the output inductor to standard µ Calculate the total ripple current with using the µ H inductor: Δ I L 0.42 A Calculate the maximum output current: Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

/c68/c61 /c43 LP K 0.42I 1.25 2/c61 /c43 OUT OUT 1=o 2 L C f /c112 /c180 /c180 2 2OUT OUT

4 L 0f

/c61 /c112 /c180 /c180 2 3 2 -6OUT 4 (40 10 ) (1 10 ) /c61 /c112 /c180 /c180 /c180 /c180 (RSNS) (SNS) (CHARGE) V R I/c61 (SNS) 85mVR 1.25A/c61 bq24152 www.ti.com SLUS847 JUNE 2008 I LPK 1.46 A Select 2.5mm by 2.0mm µ H 1.5-A surface mount multi-layer inductor. The suggested inductor part numbers are shown as following. Table 12. Inductor Part Numbers PART NUMBER INDUCTANCE SIZE MANUFACTURER LQM2HPN1R0MJ0 µ H 2.5 x 2.0 mm muRata MIPS2520D1R0 µ H 2.5 x 2.0 mm FDK MDT2520-CN1R0M µ H 2.5 x 2.0 mm TOKO CP1008 µ H 2.5 x 2.0 mm Inter-Technical Determine the output capacitor value C OUT using kHz as the resonant frequency: C OUT 15.8 µ F Select two 0603 X5R 6.3V 10- µ F ceramic capacitors in parallel i.e., muRata GRM188R60J106M. Determine the sense resistor using the following equation: The maximum sense voltage across sense resistor is mV. In order to get a better current regulation accuracy, V (RSNS) should equal mV, and calculate the value for the sense resistor. R (SNS) m Ω This is a standard value. If it is not a standard value, then choose the next close value and calculate the real charge current. Calculate the power dissipation on the sense resistor: P (RSNS) I (CHARGE) R (SNS) P (RSNS) 125 0.068 P (RSNS) 0.106 W Select 0402 0.125-W 68-m Ω sense resistor, i.e. Panasonic ERJ2BWGR068. Measured efficiency and total power loss for different inductors are shown in Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

Battery□Charge□Efficiency 500 600 700 800 900 1000 1100 1200 1300 Charge□Current□-□mA Efficiency□-□% TOKO FDK muRata Inter-Technical Battery□Charge□Loss 100 200 300 400 500 600 700 800 500 600 700 800 900 1000 1100 1200 1300 Loss□-□mW Charge□Current□-□mA T =25°C, VBUS□=□5□V, VBAT□=□3□V A T =25°C, VBUS□=□5□V, VBAT□=□3□V A TOKO FDK muRata Inter-Technical PCB LAYOUT CONSIDERATION High Frequency Current Path L1 R1 C3C1 VBUS PMID PGND SW V BA T BA TVIN bq24152 SLUS847 JUNE 2008 www.ti.com Figure 34. Measured Efficiency and Power Loss It is important to pay special attention to the PCB layout. The following provides some guidelines: To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed as close as possible to the bq24152. The output inductor should be placed close to the IC and the output capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation problems, proper layout to minimize high frequency current path loop is critical (see Figure The sense resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other on adjacent layers (do not route the sense leads through a high-current path, see Figure Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place components such that routing interrupts power stage currents). All small control signals should be routed away from the high current paths. The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for small-signal components). A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is no ground-bounce issue, and having the components segregated minimizes coupling between signals. The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET. Figure 35. High Frequency Current Path Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): bq24152

Charge□Current□Direction To□CSIN□and□CSOUT□pin R SNS To□Inductor To□Capacitor□and□battery Current□Sensing□Direction PACKAGE SUMMARY A1 A2 A3 A4 E1 E2 E3 E4 D E WCSP PACKAGE (Top□View) CHIP SCALE□PACKAGE (Top□Side□Symbol□For□bq24152) TIYMLLLLS bq24152 0-Pin A1□Marker,□TI-TI□Letters, YM- Year□Month Date□Code,□LLLL-Lot□Trace□Code,□S-Assembly Site□Code CHIP SCALE□PACKAGING□DIMENSIONS The□bq24152□device□is□available□in□a□20-bump□chip□scale□package□(YFF,□NanoFree ). The□package dimensions□are TM /c183 /c183 D□=□1.976 0.05□mm E /c177 bq24152 www.ti.com SLUS847 JUNE 2008 Figure 36. Sensing Resistor PCB Layout Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24152

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) BQ24152YFFR ACTIVE DSBGA YFF 20 3000 Green (RoHS & no Sb/Br) SnAgCu Level-1-260C-UNLIM BQ24152YFFT ACTIVE DSBGA YFF 20 250 Green (RoHS & no Sb/Br) SnAgCu Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Jun-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24152YFFR DSBGA YFF 20 3000 217.0 193.0 35.0 BQ24152YFFT DSBGA YFF 20 250 217.0 193.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2008 Pack Materials-Page 2

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Summary

Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support

Description