CN7221 CONEXANT | Alldatasheet
Document overview
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- PDF pages: 18
Technical content
Features
- Supports the HomePNA 1.0 specification for a home phoneline network
- 1 Mbps data rate
- Integrated Analog Front End
- Configurable transmit power level; high- and low-power
- Configurable transmit data rate; low- and high-speed
- 32-pin TQFP package HomePNA 1.0 Specification
- Meets HomePNA certification test requirements
- Uses existing phonelines, no new wires required
- Compatible with existing services – Internet access, voice services, and home network coexist on the same wire
- Robust protocol assures performance over poor wiring infrastructure
- FCC Part 15- and Part 68-compliant
Ordering Information
Product Package Device Number CN7221 HomePNA 1.0 Physical Layer with Integrated Analog Front End 32-pin TQFP 11625-11
Related Products
Multifunction PCI/CardBus Ethernet and HomeLAN Controller with Integrated HomePNA 1.0 Physical Layer and 56 Kbps HCF/HSF Modem Interface 176-pin TQFP 11623-14 RS7112-LAN Multifunction PCI/CardBus Ethernet and HomeLAN Controller with Integrated HomePNA 1.0 Physical Layer Only 176-pin TQFP 11623-12 RS7111A Multifunction PCI/CardBus Ethernet and HomeLAN Controller with V.90 HCF Modem Interface 176-pin TQFP 11617-14 RS7111A-LAN Multifunction PCI/CardBus Ethernet and HomeLAN Controller Only 176-pin TQFP 11617-12 RS7220 HomePNA 1.0 Physical Layer device 64-pin TQFP R8293-11 Information provided by Conexant Systems, Inc. is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. Conexant, “What’s Next in Communications Technologies,” and LANfinity are registered trademarks of Conexant Systems, Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. 1999, Conexant Systems, Inc. All Rights Reserved
Home Networking PHY with Integrated AFE LANfinity CN7221 LAN-056, Rev. A Conexant 3 PROPRIETARY INFORMATION Typical Application RS7112 Multifunction Controller (Ethernet MAC/V.90 Modem Combination) P C I V.90 DSP (optional) V.90 CODEC DAA RJ-11 CN7221 Home Networkin g PHY with Integrated AFE 7-Wire Serial I/F (7WS) Ethernet 10 Mbps or
100 Mbps PHY/
(MII) RJ-45 LAN-056_CN7221_f1 Figure 1. Typical Application
Description
The typical application shown in Figure 1 displays a multifunction PCI Network Interface Card (NIC). The NIC incorporates the RS7112 Home Networking Controller, the CN7221 Home Networking PHY with Integrated AFE, and a V.90 56 Kbps host-controlled modem. The RS7112’s 7- wire serial interface (7WS) is used to support the CN7221. Home Networking The home phoneline network is an Ethernet-compatible LAN running over the random-tree wiring found in nearly all homes. It does not require any hubs, routers, splitters, filters or terminations. Initial products are PC network interface cards, which will interface home computers directly to the network via an in-home telephone jack. Home phoneline networking will also work with current Internet access technologies, such as cable modems, V.90 and ADSL.
Figure 2. CN7221 Device Block Diagram the interface to the RS7112 is referred to as the back end. wire serial interface itself (page 5). HLAN_RX_CLK. All signals are active high. in a manner guaranteed to be glitch-free.
device. They are shown in Table 1. The HLAN_OSC pin is the 60 MHz clock input pin. Table 1. System Signals HLAN_RX_CLK, HLAN_CRS, HLAN_RXD, and HLAN_COL.
- Idle (no activity in either direction)
- RxPKT (receiving data)
- TxPKT (transmitting data). The subsequent subsections analyze each 7WS-related state of the PHY in detail.
Table 2. 7WS Interface Signals
LANfinity CN7221 Home Networking PHY with Integrated AFE 6 Conexant LAN-056, Rev. A PROPRIETARY INFORMATION RxPKT Carrier Sense Asserted HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_RX_CLK becomes disabled (and left in the high state) as soon as HLAN_CRS is asserted. HLAN_CRS may be asserted at re-enabled about 135 uS into the packet. RxPKT HLAN_RX_CLK Active and HLAN_CRS Cleared HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_RX_CLK and HLAN_TX_CLK are unrelated to each other during this time. When a symbol has been received and decoded, HLAN_RX_CLK toggles at a rate of 233.3ns (full period, 50% duty cycle) in order to shift out the three to six bits encoded in the symbol. The middle portion of this diagram shows the end of the preamble, followed by an SFD and the beginning of the datagram. HLAN_CRS will fall approximately 16us after the last received symbol. Once HLAN_CRS falls, HLAN_RX_CLK and HLAN_TX_CLK are toggled continuously at 233.3ns for 97 cycles, after which the PHY returns to the Idle state. TxPKT HLAN_TX_EN Asserted HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL Once HLAN_TX_EN is asserted, the PHY stops HLAN_RX_CLK, asserts HLAN_CRS, and toggles HLAN_TX_CLK at 233.3ns.
Home Networking PHY with Integrated AFE LANfinity CN7221 LAN-056, Rev. A Conexant 7 PROPRIETARY INFORMATION TxPKT HLAN_RX_CLK Active HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_TX_CLK continues to toggle at 233.3ns until the SFD is observed, as shown in the first section of the above diagram. At this point, HLAN_TX_CLK is disabled (high) until the AID header has been transmitted on the wire (or until a HLAN_COL has been detected). This takes about 120us, at which time HLAN_RX_CLK starts toggling, thereby shifting 32 bits of preamble and SFD back to the MAC. Sometime later, the HLAN_TX_CLK restarts as symbols get sent onto the wire in an analogous manner as HLAN_RX_CLK during packet reception. TxPKT HLAN_TX_EN Cleared HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL Once HLAN_TX_EN is cleared, the last symbol gets encoded and transmitted, the looped-back data is presented back to the MAC, and about 22us later, HLAN_CRS falls. Once HLAN_CRS falls, HLAN_TX_CLK and HLAN_RX_CLK toggle with a period of 233.3ns for 97 clocks, after which the system returns to the Idle state.
LANfinity CN7221 Home Networking PHY with Integrated AFE 8 Conexant LAN-056, Rev. A PROPRIETARY INFORMATION TxPKT HLAN_COL Asserted HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_COL will be asserted some time after the preamble and SFD have been clocked in. HLAN_TX_CLK and HLAN_RX_CLK are then clocked with a period of 233.3ns until HLAN_CRS drops. HLAN_TX_EN drops about 32 clocks after HLAN_COL was asserted. HLAN_CRS and HLAN_COL are dropped together after more than 500 clocks (about 120us). HLAN_TX_CLK and HLAN_RX_CLK keep toggling at 233.3ns period for roughly another 100 clock cycles, when the system returns to the idle state. RxPKT HLAN_COL Asserted HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_COL may be asserted up to 120us after HLAN_CRS has been asserted. Once HLAN_COL has been asserted, HLAN_TX_CLK and HLAN_RX_CLK run at a period of 233.3ns per cycle until 97 cycles after HLAN_COL and HLAN_CRS are cleared. It can take up to about 60us for HLAN_CRS to clear.
HLAN_SPI_DOUT, HLAN_SPI_DIN, and HLAN_SPI_CS#. and disables all write operations when in that state. Table 3. SPI Signals Table 4. SPI Timing Figure 3. SPI Timing
9), and the HLAN_IRQ# signal. All SPI registers in the system are readable and writable. of those pins will update the CONTROL register bits. Table 5. RS7112 Interface Signals be cleared and bit 0 of the ISTAT register will be set.
Figure 4. CN7221 32-pin TQFP Pinout Diagram
Table 6. CN7221 32-pin TQFP Pin Designations by Number
1 HLAN_OSC 17 AFE_TX_MINUS
2 HLAN_SPI_DOUT 18 AFE_TX_PLUS
3 HLAN_SPI_CS# 19 VDD
4 HLAN_SPI_CLK 20 SCAN_ENABLE
5 HLAN_RESET# 21 SCAN_MODE
6 VSS 22 HLAN_IRQ#
7 AFE_REF_NOISE 23 HLAN_RXD
8 AFE_REF_PEAK 24 HLAN_RX_CLK
9 AFE_REF_DATA 25 HLAN_COL
10 AFE_VDD_RX 26 HLAN_CRS
11 AFE_VSS_RX 27 HLAN_TX_EN
12 AFE_RBIAS 28 VSS
13 AFE_VC 29 VDD
14 AFE_VSS_TX 30 HLAN_TXD
15 AFE_RX_MINUS 31 HLAN_TX_CLK
16 AFE_RX_PLUS 32 HLAN_SPI_DIN
Table 7. Pin Designations by Group uF Cap for data CT comparator.
LANfinity CN7221 Home Networking PHY with Integrated AFE 14 Conexant LAN-056, Rev. A PROPRIETARY INFORMATION Test Signals Pin Name Type Schmitt Resistive Drive Description Pin Number(s) SCAN_MODE I /G38 ↓ Selects different scan modes 21 SCAN_ENABLE I /G38 ↓ Scan enable (1 = enable scan) 20 Power Pins Pin Name Type Characteristic Description Pin Number(s) VDD P 5 pins +3.3V Power 19, 29 VSS G 7 pins Ground 6, 28
Home Networking PHY with Integrated AFE LANfinity CN7221 LAN-056, Rev. A Conexant 15 PROPRIETARY INFORMATION
Electrical Characteristics
Table 8.Absolute Maximum Ratings Parameter Symbol Min Typ Max Units Supply Voltage V DD V Input Voltage V IN V Operating Temperature Range T o C Storage Temperature T stg oC Voltage Applied to Outputs in High Z state V hz V DC Input Clamp Current I lk mA DC Input Clamp Current I ok mA Static Discharge Voltage (25 oC) ESD V Latch-up Current I trig mA Table 9. DC Electrical Characteristics Table 10. AC Electrical Characteristics conform to the PCI Bus Timing Specification.
Table 11. Current and Power Characteristics
1.6 MAX
1.4 REF
7.0 REF
5.6 REF
1.0 REF
0.80 BSC
0.10 MAX
0.0630 MAX
0.0551 REF
0.2756 REF
0.2205 REF
0.0394 REF
0.0315 BSC
0.004 MAX
Figure 5. 32-pin TQFP Package Dimensions
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