CMV1030

CMV1030 CALMIRCO | Alldatasheet

Document overview

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Technical content

Features

• Tiny SOT23-5 Package  Guaranteed specs at 1.8V, 2.2V, 2.7V , 3V and 5V  Very Low Supply current typically 150µA @3V  Rail-to-Rail Output  Typical Total Harmonic Distortion of 0.02% at 3V  2.7MHz Typical Gain Bandwidth Product  2V/µs Typical Slew Rate Product Description The CMV1030 is a high performance CMOS operational amplifier available in a small SOT23-5 package. Operat- ing with very low supply current, it is ideal for battery operated applications where power, space and weight are critical. With 2.7MHz Gain Bandwidth Product, 2V/µs Slew Rate, and a typical current consumption of only 150µA, the

Applications

 Mobile Communications  Cellular Phones  Portable Equipment  Notebooks and PDAs C0940500 PIN DIAGRAM CMV1030 provides excellent power-performance ratio for power sensitive applications. Ideal for use in personal electronics such as cellular handsets, pagers, cordless telephones and other products with limited space and battery power. NON-INV INPUT OUTPUT 5-Pin SOT23-5 + V+ INV INPUT NOITAMROFNIGNIREDROTRAPDRADNATS egakcaP rebmuNtraPgniredrO sniPe lytSl eeR&epaTg nikraMtraP 55 -32TOSR /Y0301VMC0 301

©2000 California Micro Devices Corp. All rights reserved. 10/19/2000 215 Topaz Street, Milpitas, California 95035 /G20 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CMV1030 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating conditions indicate ratings fo r which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and th e test conditions, see the Electrical Operating Characteristics. Note 2: Human Body Model, 1.5KΩ in series with 100pF . Note 3: Applies to both single-supply and split-supply operation. Continuous short ckt operation at elevated ambient temperatures can result in exceeding the maximum allowed junction temperature of 150 °C. Note 4: The maximum power dissipation is a function of TJ (MAX), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ (MAX) - TA)/θJA . All numbers apply for packages soldered directly to a PC board. )1ETON(SGNITARMUMIXAMETULOSBA retemaraPg nitaRt inU )2etoN,MBH(noitcetorPDSE0 002V egatloVtupnIlaitnereffiD/ + − egatloVylppuSV niPtuptuo/tupnitaegatloVV (,3.0+)+V( −) − 3.0V egarotS:erutarepmeT )4etoN(noitcnuJgnitarepO )s01,gniredloS(daeL − 051ot56 521 062 Vot+V(egatloVylppuS −)5 .7V niPtupnItatnerruC5 A m )3etoN(niPtuptuOtatnerruC5 1A m sniPylppuSrewoPtatnerruC5 1A m )esiwrehtodeificepssselnu(SNOITIDNOCGNITAREPO retemaraPg nitaRt inU egatloVylppuS7 ot8.1V erutarepmeTnoitcnuJ − 58ot04 C° ecnatsiseRlamrehT5 23W /C°

© 2000 California Micro Devices Corp. All rights reserved. 10/19/2000 3 215 Topaz Street, Milpitas, California 95035 /G20 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CMV1030 SCITSIRETCARAHCGNITAREPOLACIRTCELEV8.1 M1>LR,V0=-V,V8.1=+V,C°52=jTdeificepsesiwrehtosselnU( ΩΩΩΩΩ) lobmySr etemaraPs noitidnoCp yTt imiLt inU V SO egatloVtesffOtupnIV TUO V9.0=9 V m IB tnerruCsaiBtupnI 1A p I SO tnerruCtesffOtupnI 5.0A p R NI ecnatsiseRtupnI 1T Ω IS tnerruCylppuS 0210 42A µ WBGt cudorPhtdiwdnaBniaG 2z HM AV niaGegatloVlangiSegraLV TUO V6.1otV2.0=0 80 6B d RSe taRwelSA V = − K001=LR,14 .15 3.0V / sµ RRSPo itaRnoitcejeRylppuSrewoPV 2.1ptV9.0=+V V− = 9.0− otV 2.1− V V0=MCV 070 5B d RRMCn oitcejeRedoMnommoC oitaR V8.1<MCV<V00 60 4B d V MC egnaRtupnIedoMnommoC 0 1.1 V DHTn oitrotsiDcinomraHlatoTA V = − V,zHK1=f,1 TUO p-pV1= K001=LR 620.0% I CS tnerruCtiucriCtrohStuptuOk niS/ecruoS5 A m VO liarrehtiemorfgniwStuptuOK 01=LR0 20 51V m 2S CITSIRETCARAHCGNITAREPOLACIRTCELEV2. M1>LR,V0=-V,V2.2=+V,C°52=jTdeificepsesiwrehtosselnU( ΩΩΩΩΩ) lobmySr etemaraPs noitidnoCp yTt imiLt inU V SO egatloVtesffOtupnIV TUO V1.1=9 V m IB tnerruCsaiBtupnI 1A p I SO tnerruCtesffOtupnI 5.0A p R NI ecnatsiseRtupnI 1T Ω IS tnerruCylppuS 5310 72A µ WBGt cudorPhtdiwdnaBniaG 4.2z HM AV niaGegatloVlangiSegraLV TUO V2otV2.0=0 80 6B d RSe taRwelSA V = − K001=LR,18 .15 4.0V / sµ RRSPo itaRnoitcejeRylppuSrewoPV 4.1ptV1.1=+V V− = − otV1.1 − V4.1 V0=MCV 070 5B d RRMCn oitcejeRedoMnommoC oitaR V2.1<MCV<V00 60 4B d V MC egnaRtupnIedoMnommoC 0 5.1 V DHTn oitrotsiDcinomraHlatoTA V = − V,zHK1=f,1 TUO p-pV4.1= K001=LR 20.0% I CS tnerruCtiucriCtrohStuptuOk niS/ecruoS7 A m VO liarrehtiemorfgniwStuptuOK 01=LR0 20 51V m

©2000 California Micro Devices Corp. All rights reserved. 10/19/2000 215 Topaz Street, Milpitas, California 95035 /G20 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CMV1030 SCITSIRETCARAHCGNITAREPOLACIRTCELEV3 M1>LR,V0=-V,V3=+V,C°52=jTdeificepsesiwrehtosselnU( ΩΩΩΩΩ) lobmySr etemaraPs noitidnoCp yTt imiLt inU V SO egatloVtesffOtupnIV TUO V5.1=5 V m IB tnerruCsaiBtupnI 1A p I SO tnerruCtesffOtupnI 5.0A p R NI ecnatsiseRtupnI 1T Ω IS tnerruCylppuS 0510 03A µ WBGt cudorPhtdiwdnaBniaG 7.2z HM AV niaGegatloVlangiSegraLV TUO V8.2otV2.0=5 85 6B d RSe taRwelSA V = − K001=LR,12 5 .0s µ/V RRSPo itaRnoitcejeRylppuSrewoPV 8.1otV5.1=+V V− = − otV5.1 − V8.1 V0=MCV 085 5B d RRMCo itaRnoitcejeRedoMnommoCV 2<MCV<V00 70 5B d V MC egnaRtupnIedoMnommoC 0 3.2 V DHTn oitrotsiDcinomraHlatoTA V = − V,zHK1=f,1 TUO p-pV2= K001=LR 20.0% I CS tnerruCtiucriCtrohStuptuOk niS/ecruoS5 1A m VO liarrehtiemorfgniwStuptuOK 01=LR0 20 51V m SCITSIRETCARAHCGNITAREPOLACIRTCELEV7.2 M1>LR,V0=-V,V7.2=+V,C°52=jTdeificepsesiwrehtosselnU( ΩΩΩΩΩ) lobmySr etemaraPs noitidnoCp yTt imiLt inU V SO egatloVtesffOtupnIV TUO V53.1=6 V m IB tnerruCsaiBtupnI 1A p I SO tnerruCtesffOtupnI 5.0A p R NI ecnatsiseRtupnI 1T Ω IS tnerruCylppuS 0510 03A µ WBGt cudorPhtdiwdnaBniaG 7.2z HM AV niaGegatloVlangiSegraLV TUO V5.2otV2.0=5 85 6B d RSe taRwelSA V = − K001=LR,12 5 .0s µ/V RRSPo itaRnoitcejeRylppuSrewoPV 56.1otV53.1=+V V− = − V56.1otV53.1 V0=MCV 070 5B d RRMCo itaRnoitcejeRedoMnommoCV 7.1<MCV<V00 65 4B d V MC egnaRtupnIedoMnommoC 0 2 V DHTn oitrotsiDcinomraHlatoTA V = − V,zHK1=f,1 TUO p-pV9.1= K001=LR 20.0% I CS tnerruCtiucriCtrohStuptuOk niS/ecruoS2 1A m VO liarrehtiemorfgniwStuptuOK 01=LR0 20 51V m

© 2000 California Micro Devices Corp. All rights reserved. 10/19/2000 5 215 Topaz Street, Milpitas, California 95035 /G20 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CMV1030 SCITSIRETCARAHCGNITAREPOLACIRTCELEV5 M1>LR,V0=-V,V5=+V,C°52=jTdeificepsesiwrehtosselnU( ΩΩΩΩΩ) lobmySr etemaraPs noitidnoCp yTt imiLt inU V SO egatloVtesffOtupnIV TUO V5.1=5 V m IB tnerruCsaiBtupnI 1A p I SO tnerruCtesffOtupnI 5.0A p R NI ecnatsiseRtupnI 1T Ω IS tnerruCylppuS 0010 02A µ WBGt cudorPhtdiwdnaBniaG 9.2z HM AV niaGegatloVlangiSegraLV TUO V8.4otV2.0=0 90 7B d RSe taRwelSA V = − K001=LR,13 .25 75.0s µ/V RRSPo itaRnoitcejeRylppuSrewoPV 8.2otV5.2=+V V− = 2− otV5. 2− V8. V0=MCV 085 5B d RRMCo itaRnoitcejeRedoMnommoCV 4<MCV<V00 70 5B d V MC egnaRtupnIedoMnommoC 0 3.4 V DHTn oitrotsiDcinomraHlatoTA V = − V,zHK1=f,1 TUO p-pV4= K001=LR 20.0% I CS tnerruCtiucriCtrohStuptuOk niS/ecruoS5 2A m VO liarrehtiemorfgniwStuptuOK 01=LR0 20 51V m

©2000 California Micro Devices Corp. All rights reserved. 10/19/2000 215 Topaz Street, Milpitas, California 95035 /G20 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CMV1030 RL = 1MEG RL = 100K RL = 10K V+ = 5V V- = 0V TA = 25°C Open Loop Voltage Gain Response Frequency(Hz) AVOL (dB) V+ = 5V V- = 0V T A = 25°C RL = 1MEG RL = 100K RL = 10K Open Loop Phase Response Frequency(Hz) Phase (º) V+ = 5V V- = 0V RL = 100KΩ TA = 25°C Large Signal Pulse Response Time(µs) VOUT (V) Supply Current Versus Supply Voltage TA = 85ºC TA = 25ºC TA = -40ºC Supply Voltage(V) Supply Current (µA) Non Inverting Small Signal Response V+ = 5V V- = 0V TA = 25°C RL = 100K RL = 10K Time(µs) VOUT (V) Inverting Small Signal Response V+ = 5V V- = 0V TA = 25°C RL = 100K RL = 10K Time(µs) VOUT (V)

© 2000 California Micro Devices Corp. All rights reserved. 10/19/2000 7 215 Topaz Street, Milpitas, California 95035 /G20 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CMV1030 VS = ±2.5V -2.5V < Vin < 2V TA = 25°C Common Mode Rejection Ratio Vin(V) VOS (mV) V+ = 5V V- = 0V TA = 25°C VOUT is referenced to V+ Current Sourcing Versus VOUT VOUT(V) IOUT V+ = 5V V- = 0V TA = 25°C VOUT is referenced to V- Current Sinking Versus VOUT VOUT(V) IOUT

©2000 California Micro Devices Corp. All rights reserved. 10/19/2000 215 Topaz Street, Milpitas, California 95035 /G20 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CMV1030 Applications Information 1. Input Common Mode Range and Output Voltage Considerations The CMV1030 is capable of accommodating an input common mode voltage equal to one volt below the positive rail and all the way to the negative rail. It is also capable of output voltages equal to both power supply rails. Voltages that exceed the supply voltages will not cause phase inversion of the output, however, ESD diode clamps are provided at the inputs that can be damaged if static currents in excess of ±5mA are allowed to flow in them. This can occur when the magnitude of input voltage exceeds the rail by more than 0.3 volt. To preclude damage, an applications resistor, Rs, in series with the input is recommended as illustrated in Figure 1 whose value for Rs is given by: V IN - (V+ + 0.3 V) 5mA For V+ (or V-) equal to 2.2 volts and VIN equal to 10 volts, RS should be chosen for a value of 2.5K Ω or greater. Figure 1. 2. Output Current and Power Dissipation Considerations The CMV1030 is capable of sinking and sourcing output currents in excess of 7mA at voltages very nearly equal to the rails. As such, it does not have any internal short circuit protection (which would in any event detract from its rail to rail capability). Although the power dissipation and junction temperature rise are small, a short analysis is worth investigating. Obviously, the worst case from a power dissipation point of view is when the output is shorted to either ground in a single rail application or to the opposite supply voltage in split rail applications. Since device only draws 60 µA supply current (100 µA maximum), its contribution to the junction temperature, T J, is negligible. As an example, let us analyze a situation in which the CMV1030 is oper- ated from a 5 volt supply and ground, the output is "programmed" to positive saturation, and the output pin is indefinitely shorted to ground. In general: P DISS = (V+ –VOUT)*IOUT + IS*V+ Where: PDISS = Power dissipated by the chip V+ = Supply voltage V OUT = The output voltage IS = Supply Current The contribution to power dissipation due to supply current is 200µW and is indeed negligible as stated above. The primary contribution to power dissipation occurs in the output stage. V+ – VOUT would equal 5V – 0V = 5 V, and power dissipation would be equal to 35mW. TJ = TA + θJA* PDISS Where: TA = The ambient temperature θJA = The thermal impedance of the package junction to ambient The SOT23 exhibits a θJA equal to 325°C/W. Thus for our example the junction rise would be about 11.4 which is clearly not a destructive situation even under an ambient temperature of 85°C. 3. Input Impedance Considerations The CMV1030 exhibits an input impedance typically in excess of 1 Tera Ω (1 X 10 12 ohms) making it very appropriate for applications involving high source impedance such as photodiodes and high output impedance transducers or long time constant integra- tors. High source impedances usually dictate large feedback resistors. But, the output capacitance of the source in parallel with the input capacitance of the CMV1030 (which is typically 3pF) create a parasitic pole with the feedback resistor which erodes the phase margin of the amplifier. The usual fix is to bypass, R F, as shown in Figure 2 with a small capacitor to cancel the input pole. The usual formula for calculating C F always results in a value larger than that is required: 1 1 2Π RS CS 2Π RF CF Since the parasitic capacitance can change between the breadboard and the production printed circuit board, we favor the use of a "gimmick", a technique perfected by TV technicians in the 1950 ’s. A gimmick is made by taking two lengths (typically about a foot) of small gauge wire such as AWG 24, twisting them together, and then after baring all ends soldering the gimmick across R With the circuit operating, C F is "adjusted" by clipping short lengths of the gimmick off until the compensation is nominal. Then simply remove the gimmick, take it to an impedance bridge, and select the capacitor accord-

©2000 California Micro Devices Corp. All rights reserved. 10/19/2000 215 Topaz Street, Milpitas, California 95035 /G20 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CMV1030 Figure 5