CMT60N03 ETC | Alldatasheet

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N-CHANNEL Logic Level Power M OSFET 2004/05/24 Preliminary Champion Microelectronic Corporation Page 1 APPLICATION

FEATURES

‹ Buck Converter High Side Switch ‹ Other Applications VDSS R DS(ON) Typ. I D 30V 10.8m Ω 50A ‹ Low ON Resistance ‹ Low Gate Charge ‹ Peak Current vs Pulse Width Curve ‹ Inductive Switching Curves ‹ Improved UIS Ruggedness PIN CONFIGURATION SYMBOL TO-252 TO-263 F r o n t V i e w F r o n t V i e w 1 23 GATE DRAIN SOURCE 2 31 GS D D S G N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Drain to Source Voltage (Note 1) V DSS 30 V Drain to Current － Continuous Tc = 25 ℃, VGS@10V (Note 2) － Continuous Tc = 100 ℃, VGS@10V (Note 2) － Pulsed Tc = 25 ℃, VGS@10V (Note 3) ID ID IDM Fig.3 Fig.6 A Gate-to-Source Voltage － Continue V GS ±20 V Total Power Dissipation Derating Factor above 25 ℃ PD 52 0.5 W W/℃ Peak Diode Recovery dv/dt (Note 4) dv/dt 3.0 V/ns Operating Junction and Storage Temperature Range T J, TSTG -55 to 150 ℃ Single Pulse Avalanche Energy L=1.1mH,ID=30 Amps E AS 500 mJ Maximum Lead Temperature for Soldering Purposes T L 300 ℃ Maximum Package Body for 10 seconds T PKG 260 ℃ Pulsed Avalanche Rating I AS Fig.8 THERMAL RESISTANCE Symbol Parameter Min Typ Max Units Test Conditions RθJC Junction-to-case 2.4 ℃/W Water cooled heatsink, P D adjusted for a peak junction temperature of +150℃ RθJA Junction-to-ambient (PCB Mount) 50 ℃/W Minimum pad area, 2-oz copper, FR-4 circuit board, double sided RθJA Junction-to-ambient 62 ℃/W 1 cubic foot chamber, free air

N-CHANNEL Logic Level Power M OSFET 2004/05/24 Preliminary Champion Microelectronic Corporation Page 2

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, TJ = 25℃. CMT60N03 Characteristic Symbol Min Typ Max Units OFF Characteristics Drain-to-Source Breakdown Voltage ( V GS = 0 V, ID = 250 μA) VDSS 30 V Breakdown Voltage Temperature Coefficient, Fig.11 (Reference to 25℃, ID = 250 μA) ΔVDSS/∆TJ 27 mV/ ℃ Drain-to-Source Leakage Current (VDS = 24 V, VGS = 0 V, TJ = 25℃) (VDS = 24 V, VGS = 0 V, TJ = 125℃) IDSS µA Gate-to-Source Forward Leakage ( V GS = 20 V) IGSS 100 nA Gate-to-Source Reverse Leakage ( V GS = -20 V) IGSS -100 nA ON Characteristics Gate Threshold Voltage,Fig.12 ( V DS = VGS, ID = 250 μA) VGS(th) 1.0 3.0 V Static Drain-to-Source On-Resistance, Fig.9,10 (Note 5) ( V GS = 10 V, ID = 15A) ( V GS = 4.5 V, ID = 12A) RDS(on) 10.8 15.4 12.5 mΩ Forward Transconductance (VDS = 15 V, ID = 12A) (Note 5) g FS 28 S Dynamic Characteristics Input Capacitance C iss 1520 pF Output Capacitance C oss 314 pF Reverse Transfer Capacitance (VDS = 15 V, VGS = 0 V, f = 1.0 MHz) Fig.14 Crss 152 pF Total Gate Charge (VGS = 10 V) Q g 27.9 35 nC Total Gate Charge (VGS = 4.5 V) Q g 14 19 nC Gate-to-Source Charge Q gs 4.9 nC Gate-to-Drain Charge (VDS = 15 V, ID = 12 A) (Note 6) Fig.15 Qgd 4.3 nC Resistive Switching Characteristics Turn-On Delay Time t d(on) 10 ns Rise Time tr 3.4 ns Turn-Off Delay Time t d(off) 36 ns Fall Time (VDD = 15 V, ID = 12 A, VGS = 10 V, RG = 1.0Ω) (Note 6) tf 6.0 ns Turn-On Delay Time t d(on) 16 ns Rise Time tr 7.2 ns Turn-Off Delay Time t d(off) 34 ns Fall Time (VDD = 15 V, ID = 12 A, VGS = 4.5V, RG = 1.0Ω) (Note 6) tf 14 ns Source-Drain Diode Characteristics Continuous Source Current (Body Diode Fig.16) IS 50 A Pulse Source Current (Body Diode) Integral pn-diode in MOSFET ISM Fig.6 A Forward On-Voltage (I S = 12 A, VGS = 0 V) V SD 1.0 V Forward Turn-On Time t rr 25 38 ns Reverse Recovery Charge (IF = 12 A, VGS = 0 V, di/dt = 100A/µs) Qrr 31 46 nC

N-CHANNEL Logic Level Power M OSFET 2004/05/24 Preliminary Champion Microelectronic Corporation Page 3 Note 1: TJ = +25℃ to 150 ℃ Note 2: Current is calculated based upon maximum allowable junction temperature. Package current limitation is 30A. Note 3: Repetitive rating; pulse width limited by maximum junction temperature. Note 4: ISD = 12.0A, di/dt ≤100A/µs, VDD ≤ BVDSS, TJ = +150℃ Note 5: Pulse width ≤ 250µs; duty cycle ≤ 2% Note 6: Essentially independent of operating temerpature.

N-CHANNEL Logic Level Power M OSFET 2004/05/24 Preliminary Champion Microelectronic Corporation Page 7 PACKAGE DIMENSION TO-252 12 3 L E C A V J U H D R B SK G PIN 1: GATE PIN 2: DRAIN PIN 3: SOURCE TO-263 B S G E C A V J K HD PIN 1: GATE PIN 2: DRAIN PIN 3: SOURCE 1 2 3

N-CHANNEL Logic Level Power M OSFET 2004/05/24 Preliminary Champion Microelectronic Corporation Page 8 IMPORTANT NOTICE Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. A few applications using integrated circuit products may involv e potential risks of death, personal injury, or severe property or environmental damage. CMC integrated ci rcuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Us e of CMC products in such applications is understood to be fully at the risk of the cust omer. In order to minimize risks associated with the customer’s applications, th e customer should provide adequate design and operating safeguards. HsinChu Headquarter Sales & Marketing 5F-1, No. 11, Park Avenue II, Science-Based Industrial Park, HsinChu City, Taiwan 11F, No. 306-3, SEC. 1, Ta Tung Road, Hsichih, Taipei Hsien 221, Taiwan T E L : +886-3-567 9979 T E L : +886-2-8692 1591 FAX: +886-3-567 9909 FAX: +886-2-8692 1596