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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 26
Technical content
Features
- Pb-Free Plus Anneal Available (RoHS Compliant) (See Ordering Info)
- Pin Compatible with OKI MSM82C55A - No Bus Hold Devices on any Port Pins
- 24 Programmable I/O Pins
- Fully TTL Compatible
- High Speed, No “Wait State” Operation with 8MHz 80C86 and 80C88
- Direct Bit Set/Reset Capability
- Enhanced Control Word Read Capability
- L7 Process
- 2.5mA Drive Capability on All I/O Ports
Ordering Information
NUMBERS* (Note) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # CMP82C55AZ CMP82C55AZ 0 to 70 40 Ld PDIP** E40.6 CMS82C55AZ CMS82C55AZ 0 to 70 44 Ld PLCC N44.65 IMS82C55AZ IMS82C55AZ -40 to 85 CMQ82C55AZ CMQ82C55AZ 0 to 70 44 Ld MQFP Q44.10x10 IMQ82C55AZ IMQ82C55AZ -40 to 85 *Add “96” suffix to part number for tape and reel packaging. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
MS82C55A, MQ82C55A, MP82C55A FN6140 Rev 2.00 Page 2 of 26 June 15, 2006 Pinouts MS82C55A (PLCC) TOP VIEW MQ82C55A (MQFP) TOP VIEW CMP82C55A (PDIP) TOP VIEW CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 NC NC RESET V CC RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR NC PC2 NC 44 4342 41 40 2827 123456 262524232221201918 PC6 PC7 GND CS 12 13 14 15 16 17 PC5 PC4 PC0 PC1 PC2
2221201918 PB7
V CC 39 38 37 36 35 34 44 43 42 41 40 NC PA4 PA5 PA6 PA7 WR RESET RD PA0 PA1 PA2 PA3 NC PB3 PB4 PB5 PB6 NC NC PC3 PB0 PB1 PB2 PA3 PA2 PA1 PA0 RD CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PA4 PA5 PA6 PA7 WR RESET V CC PB7 PB6 PB5 PB4 PB3
VCC VCC: The +5V power supply pin. A 0.1F capacitor between VCC and GND is recommended for decoupling. D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-sta te pins connected to the system data bus. RESET I RESET: A high on this input cl ears the control register and all ports (A, B, C) are set to the input mode. RD I READ: Read is an active low input control signal used by the CP U to read status information or data via the data bus. WR I WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. PA0-PA7 I/O PORT A: 8-bit input and output port. PB0-PB7 I/O PORT B: 8-bit input and output port. PC0-PC7 I/O PORT C: 8-bit input and output port. FIGURE 1. FUNCTIONAL DIAGRAM
are also transferred through the data bus buffer. in turn, issues commands to both of the Control Groups. communication between the 82C55A and the CPU. essence, it allows the CPU to “read from” the 82C55A. data or control words into the 82C55A. selection of one of the three ports or the control word register. register to 9Bh and all ports (A, B, C) are set to the input mode. functional configuration of the 82C55A. proper commands to its associated ports. implies control word mode information. signal inputs in conjunction with ports A and B.
00010 P o r t A Data Bus
01010 P o r t B Data Bus
10010 P o r t C Data Bus
11010 C o n t r o l W o r d Data Bus
00100 D a t a B u s Port A
01100 D a t a B u s Port B
10100 D a t a B u s Port C
11100 D a t a B u s Control
FIGURE 2. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
set/reset function of port C. other device in the interrupt structure. to or read from a specific port.
- Two 8-bit ports and two 4-bit ports
- Any Port can be input or output
- Outputs are latched
- Inputs are not latched
- 16 different Input/Output configurations possible
FIGURE 5. BIT SET/RESET FORMAT
MS82C55A, MQ82C55A, MP82C55A FN6140 Rev 2.00 Page 7 of 26 June 15, 2006 Mode 0 (Basic Output) Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #2 CONTROL WORD #1 CONTROL WORD #3 CONTROL WORD #4 CONTROL WORD #8 tAW tWA tWB tWW tWDtDW WR D7-D0 CS, A1, A0 OUTPUT PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C
MS82C55A, MQ82C55A, MP82C55A FN6140 Rev 2.00 Page 8 of 26 June 15, 2006 CONTROL WORD #5 CONTROL WORD #9 CONTROL WORD #6 CONTROL WORD #10 CONTROL WORD #7 CONTROL WORD #11 CONTROL WORD #12 CONTROL WORD #14 Mode 0 Configurations (Continued) PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C
MS82C55A, MQ82C55A, MP82C55A FN6140 Rev 2.00 Page 9 of 26 June 15, 2006 Operating Modes Mode 1 - (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “hand shaking” signals. In mode 1, port A and port B use the lines on port C to generate or accept these “hand shaking” signals. Mode 1 Basic Function Definitions:
- Two Groups (Group A and Group B)
- Each group contains one 8-bit port and one 4-bit control/data port
- The 8-bit data port can be either input or output. Both inputs and outputs are latched.
- The 4-bit port is used for control and status of the 8-bit port. Input Control Signal Definition (Figures 6 and 7) STB (Strobe Input) A “low” on this input loads data into the input latch. IBF (Input Buffer Full F/F) A “high” on this output indicates that the data has been loaded into the input latch: in essence, an acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input. INTR (Interrupt Request) A “high” on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the condition: STB is a “one”, IBF is a “one” and INTE is a “one”. It is reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into the port. INTE A Controlled by bit set/reset of PC4. INTE B Controlled by bit set/reset of PC2. Output Control Signal Definition (Figure 8 and 9) OBF - (Output Buffer Full F/F). The OBF output will go “low” to indicate that the CPU has written data out to the specified port. This does not mean valid data is sent out of the port at this time since OBF can go true before data is available. Data is guaranteed valid at the rising edge of OBF, (See Note 1). The OBF F/F will be set by the rising edge of the WR input and reset by ACK input being low. CONTROL WORD #13 CONTROL WORD #15 Mode 0 Configurations (Continued) PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C
FIGURE 14. MODE 2 COMBINATIONS
FIGURE 23. BASIC FLOPPY DISC INTERFACE FIGURE 24. MACHINE TOOL CON TROLLER INTERFACE
MS82C55A, MQ82C55A, MP82C55A FN6140 Rev 2.00 Page 18 of 26 June 15, 2006 Absolute Maximum Ratings TA = 25°C Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Typical, Note 1) JA (°C/W) Maximum Junction Temperature (Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications VCC = 5.0V 10%; TA = Operating Temperature Range SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIH Logical One Input Voltage 2.0 2.2 -- V VIL Logical Zero Input Voltage - - 0.8 V VOH Logical One Output Voltage I OH = -2.5mA, IOH = -100A 3.0 VCC -0.4 -- V VOL Logical Zero Output Voltage I OL +2.5mA - - 0.4 V II Input Leakage Current V IN = VCC or GND, RD, CS, A1, A0, RESET, WR -1.0 - +1.0 A IO I/O Pin Leakage Current VO = V CC or GND, D0 - D7 -10 - +10 A IDAR Darlington Drive Current Ports A, B, C. Test Condition 3 -2.5 - Notes 2, 4 mA ICCSB Standby Power Supply Current V CC = 5.5V, VIN = VCC or GND. Output Open - - 10 A ICCOP Operating Power Supply Current T A = +25°C, VCC = 5.0V, Typical (See Note 3) - 1 - mA/MHz NOTES: 3. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current. 4. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0s I/O Read/Write cycle time = 1mA). 5. Tested as VOH at -2.5mA. Capacitance TA = 25°C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 10 pF FREQ = 1MHz, All Measurements are refer enced to device GNDCI/O I/O Capacitance 20 pF
MS82C55A, MQ82C55A, MP82C55A FN6140 Rev 2.00 Page 19 of 26 June 15, 2006 SYMBOL PARAMETER TEST CONDITIONS 82C55A UNITSMIN MAX READ TIMING (1) tAR Address Stable Before RD 0- n s (2) tRA Address Stable After RD 0- n s (3) tRR RD Pulse Width 150 - ns (4) tRD Data Valid From RD 1 - 120 ns (5) tDF Data Float After RD 21 0 7 5 n s (6) tRV Time Between RD s and/or WRs 300 - ns WRITE TIMING (7) tAW Address Stable Before WR 0- n s (8) tWA Address Stable After WR 20 - ns (9) tWW WR Pulse Width 100 - ns (10) tDW Data Valid to WR High 100 - ns (11) tWD Data Valid After WR High 30 - ns OTHER TIMING (12) tWB WR = 1 to Output 1 - 350 ns (13) tIR Peripheral Data Before RD 0- n s (14) tHR Peripheral Data After RD 0- n s (15) tAK ACK Pulse Width 200 - ns (16) tST STB Pulse Width 100 - ns (17) tPS Peripheral Data Before STB High 20 - ns (18) tPH Peripheral Data After STB High 50 - ns (19) tAD ACK = 0 to Output 1 - 175 ns (20) tKD ACK = 1 to Output Float 2 20 250 ns (21) tWOB WR = 1 to OBF = 0 1 - 150 ns (22) tAOB ACK = 0 to OBF = 1 1 - 150 ns (23) tSIB STB = 0 to IBF = 1 1 - 150 ns (24) tRIB RD = 1 to IBF = 0 1 - 150 ns (25) tRIT RD = 0 to INTR = 0 1 - 200 ns (26) tSIT STB = 1 to INTR = 1 1 - 150 ns (27) tAIT ACK = 1 to INTR = 1 1 - 150 ns (28) tWIT WR = 0 to INTR = 0 1 - 200 ns (29) tRES Reset Pulse Width 1, (Note) 500 - ns NOTE: Period of initial Reset pulse after power-on must be at least 50sec. Subsequent Reset pulses may be 500ns minimum.
FIGURE 30. WRITE TIMING FIGURE 31. READ TIMING and FALL times are driven at 1ns/V.
MS82C55A, MQ82C55A, MP82C55A FN6140 Rev 2.00 Page 23 of 26 June 15, 2006 Die Characteristics METALLIZATION: Type: Silicon - Aluminum Thickness: 11kÅ 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ 1kÅ Metallization Mask Layout 82C55A RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 V CC RESET
MS82C55A, MQ82C55A, MP82C55A FN6140 Rev 2.00 Page 24 of 26 June 15, 2006 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E40.6 (JEDEC MS-011-AC ISSUE B)
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.980 2.095 50.3 53.2 5 D1 0.005 - 0.13 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N4 0 4 0 9 Rev. 0 12/93
MS82C55A, MQ82C55A, MP82C55A FN6140 Rev 2.00 Page 25 of 26 June 15, 2006 Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N44.65 (JEDEC MS-018AC ISSUE A)
44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N4 4 4 4 6 Rev. 2 11/97
FN6140 Rev 2.00 Page 26 of 26 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Metric Plastic Quad Flatpack Packages (MQFP) D E E1 -A- PIN 1 A2 A1 A 12o-16o 12o-16o 0o-7o 0.40
0.016 MIN
L 0o MIN PLANE b 0.005/0.009 0.13/0.23WITH PLATING BASE METAL SEATING 0.005/0.007 0.13/0.17 -B- e 0.008
0.20 A-B SD SCM
0.076 0.003 -C- -D- -H- Q44.10x10 (JEDEC MS-022AB ISSUE B)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
A - 0.096 - 2.45 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - D 0.515 0.524 13.08 13.32 3 D1 0.389 0.399 9.88 10.12 4, 5 E 0.516 0.523 13.10 13.30 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.029 0.040 0.73 1.03 - N4 4 4 47 e 0.032 BSC 0.80 BSC - Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. -C- -H-