MS82C55A INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Pb-Free Plus Anneal Available (RoHS Compliant) (See Ordering Info)
  • Pin Compatible with OKI MSM82C55A - No Bus Hold Devices on any Port Pins
  • 24 Programmable I/O Pins
  • Fully TTL Compatible
  • High Speed, No “Wait State” Operation with 8MHz 80C86 and 80C88
  • Direct Bit Set/Reset Capability
  • Enhanced Control Word Read Capability
  • L7 Process
  • 2.5mA Drive Capability on All I/O Ports

Ordering Information

NUMBERS* TEMP. RANGE (°C) PACKAGE PKG. DWG. # CMS82C55AZ (Note) 0 to 70 44 Ld PLCC (Pb-free) N44.65 IMS82C55AZ (Note) -40 to 85 CMQ82C55AZ (Note) 0 to 70 44 Ld MQFP (Pb-free) Q44.10x10 IMQ82C55AZ (Note) -40 to 85 *Add “96” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet June 28, 2005

2 FN6140.1 June 28, 2005 Pinouts MS82C55A (PLCC) TOP VIEW MQ82C55A (MQFP) TOP VIEW CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 NC NC RESET V CC RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR NC PC2 NC 44 43 42 41 40 2827 123456 262524232221201918 PC6 PC7 GND CS 12 13 14 15 16 17 PC5 PC4 PC0 PC1 PC2

2221201918 PB7

V CC 39 38 37 36 35 34 44 43 42 41 40 NC PA4 PA5 PA6 PA7 WR RESET RD PA0 PA1 PA2 PA3 NC PB3 PB4 PB5 PB6 NC NC PC3 PB0 PB1 PB2 Pin Description SYMBOL TYPE DESCRIPTION VCC VCC: The +5V power supply pin. A 0.1 µF capacitor between VCC and GND is recommended for decoupling. GND GROUND D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET I RESET: A high on this input clears the control regist er and all ports (A, B, C) are set to the input mode. CS I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. RD I READ: Read is an active low input control signal used by th e CPU to read status information or data via the data bus. WR I WRITE: Write is an active low input c ontrol signal used by the CPU to load control words and data into the 82C55A. A0-A1 I ADDRESS: These input signal s, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1. PA0-PA7 I/O PORT A: 8-bit input and output port. PB0-PB7 I/O PORT B: 8-bit input and output port. PC0-PC7 I/O PORT C: 8-bit input and output port. MS82C55A, MQ82C55A

information are also transferred through the data bus buffer. external transfers of both Data and Control or Status words. and in turn, issues commands to both of the Control Groups. communication between the 82C55A and the CPU. essence, it allows the CPU to “read from” the 82C55A. write data or control words into the 82C55A. bits of the address bus (A0 and A1). FIGURE 1. FUNCTIONAL DIAGRAM

00010 P o r t A → Data Bus

01010 P o r t B → Data Bus

10010 P o r t C → Data Bus

11010 C o n t r o l W o r d → Data Bus

00100 D a t a B u s → Port A

01100 D a t a B u s → Port B

10100 D a t a B u s → Port C

11100 D a t a B u s → Control

6 FN6140.1 June 28, 2005 MODE 0 PORT DEFINITION AB G R O U P A GROUP B D4 D3 D1 D0 PORT A PORT C (Upper) PORT B PORT C (Lower) 0 0 0 0 Output Output 0 Output Output 0 0 0 1 Output Output 1 Output Input 0 0 1 0 Output Output 2 Input Output 0 0 1 1 Output Output 3 Input Input 0 1 0 0 Output Input 4 Output Output 0 1 0 1 Output Input 5 Output Input 0 1 1 0 Output Input 6 Input Output 0 1 1 1 Output Input 7 Input Input 1 0 0 0 Input Output 8 Output Output 1 0 0 1 Input Output 9 Output Input 1 0 1 0 Input Output 10 Input Output 1 0 1 1 Input Output 11 Input Input 1 1 0 0 Input Input 12 Output Output 1 1 0 1 Input Input 13 Output Input 1 1 1 0 Input Input 14 Input Output 1 1 1 1 Input Input 15 Input Input MODE 0 PORT DEFINITION A B GROUP A GROUP B D4 D3 D1 D0 PORT A PORT C (Upper) PORT B PORT C (Lower) Mode 0 (Basic Input) Mode 0 (Basic Output) tRA tHR tRR tIR tAR tRD tDF RD INPUT CS, A1, A0 D7-D0 tAW tWA tWB tWW tWDtDW WR D7-D0 CS, A1, A0 OUTPUT MS82C55A, MQ82C55A

7 FN6140.1 June 28, 2005 Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #2 CONTROL WORD #1 CONTROL WORD #3 CONTROL WORD #4 CONTROL WORD #8 CONTROL WORD #5 CONTROL WORD #9 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C MS82C55A, MQ82C55A

8 FN6140.1 June 28, 2005 CONTROL WORD #6 CONTROL WORD #10 CONTROL WORD #7 CONTROL WORD #11 CONTROL WORD #12 CONTROL WORD #14 CONTROL WORD #13 CONTROL WORD #15 Mode 0 Configurations (Continued) PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C MS82C55A, MQ82C55A

generation and enable/disable functions are also available.

  • Used in Group A only
  • One 8-bit, bidirectional bus Port (Port A) and a 5-bit control Port (Port C)
  • Both inputs and outputs are latched
  • The 5-bit control port (Port C) is used for control and status for the 8-bit, bidirectional bus port (Port A) Bidirectional Bus I/O Control Signal Definition (Figures 11, 12, 13, 14) INTR - (Interrupt Request). A high on this output can be used to interrupt the CPU for both input or output operations. Output Operations OBF - (Output Buffer Full). The OBF output will go “low” to indicate that the CPU has written data out to port A. ACK - (Acknowledge). A “low” on this input enables the three- state output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 - (The INTE flip-flop associated with OBF Controlled by bit set/reset of PC4. Input Operations STB - (Strobe Input). A “low” on this input loads data into the input latch. IBF - (Input Buffer Full F/F). A “high” on this output indicates that data has been loaded into the input latch. INTE 2 - (The INTE flip-flop associated with IBF). Controlled by bit set/reset of PC4.

FIGURE 11. MODE CONTROL WORD FIGURE 12. MODE 2

FIGURE 14. MODE 2 COMBINATIONS (Continued)

17 FN6140.1 June 28, 2005 Absolute Maximum Ratings TA = 25°C Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Typical, Note 1) θ JA (°C/W) Maximum Junction Temperature (Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VCC = 5.0V± 10%; TA = Operating Temperature Range SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIH Logical One Input Voltage 2.0 2.2 -- V VIL Logical Zero Input Voltage - - 0.8 V VOH Logical One Output Voltage I OH = -2.5mA, IOH = -100µA 3.0 VCC -0.4 -- V VOL Logical Zero Output Voltage I OL +2.5mA - - 0.4 V II Input Leakage Current V IN = VCC or GND, RD, CS, A1, A0, RESET, WR -1.0 - +1.0 µA IO I/O Pin Leakage Current VO = V CC or GND, D0 - D7 -10 - +10 µA IDAR Darlington Drive Current Ports A, B, C. Test Condition 3 -2.5 - Notes 2, 4 mA ICCSB Standby Power Supply Current V CC = 5.5V, VIN = VCC or GND. Output Open - - 10 µA ICCOP Operating Power Supply Current T A = +25°C, VCC = 5.0V, Typical (See Note 3) - 1 - mA/MHz NOTES: 2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current. 3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0 µs I/O Read/Write cycle time = 1mA). 4. Tested as VOH at -2.5mA. Capacitance TA = 25°C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 10 pF FREQ = 1MHz, All Measurements are referenced to device GNDCI/O I/O Capacitance 20 pF MS82C55A, MQ82C55A

18 FN6140.1 June 28, 2005 SYMBOL PARAMETER TEST CONDITIONS 82C55A UNITSMIN MAX READ TIMING (1) tAR Address Stable Before RD 0- n s (2) tRA Address Stable After RD 0- n s (3) tRR RD Pulse Width 150 - ns (4) tRD Data Valid From RD 1 - 120 ns (5) tDF Data Float After RD 21 0 7 5 n s (6) tRV Time Between RD s and/or WRs 300 - ns WRITE TIMING (7) tAW Address Stable Before WR 0- n s (8) tWA Address Stable After WR 20 - ns (9) tWW WR Pulse Width 100 - ns (10) tDW Data Valid to WR High 100 - ns (11) tWD Data Valid After WR High 30 - ns OTHER TIMING (12) tWB WR = 1 to Output 1 - 350 ns (13) tIR Peripheral Data Before RD 0- n s (14) tHR Peripheral Data After RD 0- n s (15) tAK ACK Pulse Width 200 - ns (16) tST STB Pulse Width 100 - ns (17) tPS Peripheral Data Before STB High 20 - ns (18) tPH Peripheral Data After STB High 50 - ns (19) tAD ACK = 0 to Output 1 - 175 ns (20) tKD ACK = 1 to Output Float 2 20 250 ns (21) tWOB WR = 1 to OBF = 0 1 - 150 ns (22) tAOB ACK = 0 to OBF = 1 1 - 150 ns (23) tSIB STB = 0 to IBF = 1 1 - 150 ns (24) tRIB RD = 1 to IBF = 0 1 - 150 ns (25) tRIT RD = 0 to INTR = 0 1 - 200 ns (26) tSIT STB = 1 to INTR = 1 1 - 150 ns (27) tAIT ACK = 1 to INTR = 1 1 - 150 ns (28) tWIT WR = 0 to INTR = 0 1 - 200 ns (29) tRES Reset Pulse Width 1, (Note) 500 - ns NOTE: Period of initial Reset pulse after power-on must be at least 50 µsec. Subsequent Reset pulses may be 500ns minimum. MS82C55A, MQ82C55A

FIGURE 30. WRITE TIMING FIGURE 31. READ TIMING and FALL times are driven at 1ns/V.

22 FN6140.1 June 28, 2005 Die Characteristics METALLIZATION: Type: Silicon - Aluminum Thickness: 11kÅ ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ Metallization Mask Layout 82C55A RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 V CC RESET MS82C55A, MQ82C55A

23 FN6140.1 June 28, 2005 MS82C55A, MQ82C55A Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N44.65 (JEDEC MS-018AC ISSUE A)

44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N4 4 4 4 6 Rev. 2 11/97

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6140.1 June 28, 2005 MS82C55A, MQ82C55A Metric Plastic Quad Flatpack Packages (MQFP) D E E1 -A- PIN 1 A2 A1 A 12o-16o 12o-16o 0o-7o 0.40

0.016 MIN

L 0o MIN PLANE b 0.005/0.009 0.13/0.23WITH PLATING BASE METAL SEATING 0.005/0.007 0.13/0.17 -B- e 0.008

0.20 A-B SD SCM

0.076 0.003 -C- -D- -H- Q44.10x10 (JEDEC MS-022AB ISSUE B)

44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

A - 0.096 - 2.45 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - D 0.515 0.524 13.08 13.32 3 D1 0.389 0.399 9.88 10.12 4, 5 E 0.516 0.523 13.10 13.30 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.029 0.040 0.73 1.03 - N4 4 4 47 e 0.032 BSC 0.80 BSC - Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and toleranc es per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. -C- -H-